[squeak-dev] [RE] seL4 Microkernel: How small can the shim be?

Liam Proven lproven at gmail.com
Tue Mar 2 01:30:10 UTC 2021


On Sun, 28 Feb 2021 at 17:16, <ken.dickey at whidbey.com> wrote:
>
> I think you have specified a null set.

I know. It sounds unlikely. However, Oberon is real, it has users,
there are native versions for x86 and RISC5 (note, *not* RISC-V) and
hosted versions on Windows, macOS and both x86 & ARM Linux (and
formerly for DOS).

>
> Alan Kay said: "The best way to predict the future is to invent it."
>
> You have described the world you want to move into.

I tried to, certainly.

> My only suggestion here is to look at OSs which are easily ported.  I
> would look at RISC-V because the kind of solution you are looking for
> will probably appear there first.

TBH I am not convinced it's mature enough just yet. I could be wrong.

> Within "type-strict", you might consider a Rust or Haskell oSs.

I am aware of some but they do seem _very_ niche.

> [I
> think Smalltalk is "type-safe", every object knows its class and trying
> to access element 41 of a 10 element array gives DNU, but I suspect this
> is not your definition].

Close enough for government work. :-)

> For small, FreeRTOS and PharOS
> (https://sourceforge.net/projects/rtospharos/) look interesting.

They do indeed. I will do some more reading.

>  From Wikipedia entry on RISC-V:
[...]
> Note also OSDev.org.

Indeed.

There is an experimental RISC-V implementation:
https://github.com/solbjorg/oberon-riscv

Of course, this is doomed to lead to horrible confusion, since
Oberon's "native" platform is Professor Wirth's own RISC5 CPU, now
implemented on several FPGA devices.

https://people.inf.ethz.ch/wirth/ProjectOberon/RISC5.Update.pdf

I have heard a rumour it was done partly because Prof W was irked that
the main extant native versions were on x86.

RISC-V (pronounced "risk five" as opposed to RISC5 (pronounced "risk
five", I think, or I suppose "risk funf")? What could possibly go
wrong?

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