[Vm-dev] [commit][2727] commit some Raspberry Pi/Raspbian changes; note that unix/ config/confgure[.ac] has -msse commented out and this needs to be done more neatly

commits at squeakvm.org commits at squeakvm.org
Fri Apr 26 23:56:20 UTC 2013


Revision: 2727
Author:   rowledge
Date:     2013-04-26 16:56:18 -0700 (Fri, 26 Apr 2013)
Log Message:
-----------
commit some Raspberry Pi/Raspbian changes; note that unix/config/confgure[.ac] has -msse commented out and this needs to be done more neatly

Modified Paths:
--------------
    branches/Cog/platforms/Cross/vm/sqAtomicOps.h
    branches/Cog/platforms/Cross/vm/sqMemoryFence.h
    branches/Cog/platforms/unix/config/configure
    branches/Cog/platforms/unix/config/configure.ac
    branches/Cog/platforms/unix/vm/sqUnixITimerHeartbeat.c

Modified: branches/Cog/platforms/Cross/vm/sqAtomicOps.h
===================================================================
--- branches/Cog/platforms/Cross/vm/sqAtomicOps.h	2013-04-25 18:38:59 UTC (rev 2726)
+++ branches/Cog/platforms/Cross/vm/sqAtomicOps.h	2013-04-26 23:56:18 UTC (rev 2727)
@@ -1,11 +1,12 @@
 /****************************************************************************
 *   PROJECT: Atomic operations for multi-threading.
 *			 Atomic reads and writes of 64-bit values (e.g. for 64-bit clock).
-*			 Atomic 32-bit increment (e.g. for signalSemaphoreWithIndex:).
 *				get64(sqLong variable)
 *				set64(sqLong variable, sqLong value)
+*			 Atomic 32-bit increment (e.g. for signalSemaphoreWithIndex:).
 *				sqAtomicAddConst(var,n)
 *				sqCompareAndSwap(var,old,new)
+*				sqCompareAndSwapRes(var,old,new,res)
 *   FILE:    sqAtomicOps.h
 *
 *   AUTHOR:  Eliot Miranda
@@ -29,6 +30,8 @@
  * we can make a good guess that __LONG_MAX__ implies 32-bits or 64-bits.
  */
 
+// tpr; Raspbian does not define ILP32 or LP32, therefore LP32 is #def'd below
+
 #if defined(__LONG_MAX__) && !defined(LP32) && !defined(ILP32) \
        && !defined(LP64) && !defined(ILP64) && !defined(LLP64)
 # if __LONG_MAX__ > 0xFFFFFFFF
@@ -44,6 +47,8 @@
 # define set64(variable,value) (variable = value)
 
 #elif LP32 || ILP32
+
+
 # if TARGET_OS_IS_IPHONE
 static inline void
 AtomicSet(uint64_t *target, uint64_t new_value)
@@ -131,13 +136,24 @@
 							: "memory", "eax", "ebx", "ecx", "edx", "cc")
 #  endif /* __SSE2__ */
 # else /* TARGET_OS_IS_IPHONE elif x86 variants etc */
+
+#if defined(__arm__) && defined(__ARM_ARCH_6__)
+/* tpr - this is code intended for the Raspberry Pi Raspbian OS 
+ * We'll experimentally trust in our MMU to keep 64bit accesses atomic */
+#define get64(var)  \
+	(var)
+#define set64(var,value) \
+		(var) = (value)
+
+#else
 /* Dear implementor, you have choices.  For example consider defining get64 &
  * set64 thusly
- * #define get64(var) read64(&(var))
+ * #define get64(var)  read64(&(var))
  * #define set64(var,val) write64(&(var),val)
  * and get the JIT to generate read64 & write64 above atomic 64-bit read/write.
  */
 #	error atomic access of 64-bit variables not yet defined for this platform
+#endif
 # endif
 
 #else /* LP32 || ILP32 else LP64 || ILP64 || LLP64 */
@@ -159,13 +175,20 @@
 # define sqAtomicAddConst(var,n) \
 	asm volatile ("lock addl %1, %0" : "=m" (var) : "i" (n), "m" (var))
 #endif
+#elif defined TARGET_OS_IS_IPHONE
+#define sqAtomicAddConst(var,n) OSAtomicAdd32(n,&var)
+#elif  defined(__arm__) && defined(__ARM_ARCH_6__)
+/* tpr - this is code intended for the Raspberry Pi Raspbian OS */
+/* We'll experimentally use the gcc inbuilt functions detailed in
+ * http://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html
+ */
+#define sqAtomicAddConst(var,n) \
+	__sync_fetch_and_add((int *)&var, n)
 #else
-#ifdef TARGET_OS_IS_IPHONE
-#define sqAtomicAddConst(var,n) OSAtomicAdd32(n,&var)
-#endif
 /* Dear implementor, you have choices.  Google atomic increment and you will
  * find a number of implementations for other architectures.
  */
+#	error atomic increment of 32-bit variables not yet defined for this platfom
 #endif
 
 
@@ -197,19 +220,29 @@
 					: "g"(old), "r"(new), "m"(var)\
 					: "memory", "%eax")
 
-# define sqCompareAndSwapRes(var,old,new,res) \
+# define sqCompareAndSwapRes(var,old,new,res) \/tmp/ccf1WMiY.s:
 	asm volatile ("movl %2, %%eax; lock cmpxchg %3, %0; movl %%eax, %1" \
 					: "=m"(var), "=g"(res) \
 					: "g"(old), "r"(new), "m"(var) \
 					: "memory", "%eax")
 #endif
-#else
-#if TARGET_OS_IS_IPHONE
+#elif defined TARGET_OS_IS_IPHONE
 # define sqCompareAndSwap(var,old,new) OSAtomicCompareAndSwap32(old, new, &var) 
 # define sqCompareAndSwapRes(var,old,new,res) res = var; OSAtomicCompareAndSwap32(old, new, &var) 
 
-#endif
+#elif  defined(__arm__) && defined(__ARM_ARCH_6__)
+/* tpr - this is code intended for the Raspberry Pi Raspbian OS */
+/* We'll experimentally use the gcc inbuilt functions detailed in
+ * http://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html */
+# define sqCompareAndSwap(var,old,new) \
+	__sync_bool_compare_and_swap(&(var), (old), (new))
+
+# define sqCompareAndSwapRes(var,old,new,res) \
+	__sync_val_compare_and_swap(&(var), (old), (new))
+
+#else
 /* Dear implementor, you have choices.  Google atomic increment and you will
  * find a number of implementations for other architectures.
  */
+#	error atomic compare/swap of 32-bit variables not yet defined for this platfom
 #endif

Modified: branches/Cog/platforms/Cross/vm/sqMemoryFence.h
===================================================================
--- branches/Cog/platforms/Cross/vm/sqMemoryFence.h	2013-04-25 18:38:59 UTC (rev 2726)
+++ branches/Cog/platforms/Cross/vm/sqMemoryFence.h	2013-04-26 23:56:18 UTC (rev 2727)
@@ -47,7 +47,7 @@
 #	define sqLowLevelMFence() asm volatile ("mfence")
 # endif
 #else
-# if defined(TARGET_OS_IS_IPHONE)
+# if defined(TARGET_OS_IS_IPHONE) || (defined(__arm__) && defined(__ARM_ARCH_6__))
 #	define sqLowLevelMFence() __sync_synchronize()
 # elif !defined(sqLowLevelMFence)
 extern void sqLowLevelMFence(void);

Modified: branches/Cog/platforms/unix/config/configure
===================================================================
--- branches/Cog/platforms/unix/config/configure	2013-04-25 18:38:59 UTC (rev 2726)
+++ branches/Cog/platforms/unix/config/configure	2013-04-26 23:56:18 UTC (rev 2727)
@@ -23833,7 +23833,8 @@
 echo "$as_me:$LINENO: result: $CFLAGS_32" >&5
 echo "${ECHO_T}$CFLAGS_32" >&6
 
-CFLAGS="$CFLAGS_32 $CFLAGS -msse"
+# CFLAGS="$CFLAGS_32 $CFLAGS -msse"
+CFLAGS="$CFLAGS_32 $CFLAGS"
 
 echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
 echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6

Modified: branches/Cog/platforms/unix/config/configure.ac
===================================================================
--- branches/Cog/platforms/unix/config/configure.ac	2013-04-25 18:38:59 UTC (rev 2726)
+++ branches/Cog/platforms/unix/config/configure.ac	2013-04-26 23:56:18 UTC (rev 2727)
@@ -265,8 +265,10 @@
 AC_MODULE_LIB_PREFIX
 AC_64BIT_ARCH
 
-CFLAGS="$CFLAGS_32 $CFLAGS -msse"
+# tpr - try to keep msse out of it for Pi CFLAGS="$CFLAGS_32 $CFLAGS -msse"
+CFLAGS="$CFLAGS_32 $CFLAGS"
 
+
 AC_C_BYTEORDER
 AC_C_DOUBLE_ALIGNMENT
 

Modified: branches/Cog/platforms/unix/vm/sqUnixITimerHeartbeat.c
===================================================================
--- branches/Cog/platforms/unix/vm/sqUnixITimerHeartbeat.c	2013-04-25 18:38:59 UTC (rev 2726)
+++ branches/Cog/platforms/unix/vm/sqUnixITimerHeartbeat.c	2013-04-26 23:56:18 UTC (rev 2727)
@@ -164,6 +164,8 @@
 			|| defined(i486) || defined(__i486) || defined (__i486__) \
 			|| defined(intel) || defined(x86) || defined(i86pc) )
     __asm__ __volatile__ ("rdtsc" : "=A"(value));
+#elif defined(__arm__) && defined(__ARM_ARCH_6__)
+	/* tpr - do nothing for now; needs input from eliot to decide further */
 #else
 # error "no high res clock defined"
 #endif



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