[Vm-dev] VM Maker: VMMaker.oscog-eem.773.mcz

commits at source.squeak.org commits at source.squeak.org
Sat Jun 14 16:00:14 UTC 2014


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.773.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.773
Author: eem
Time: 14 June 2014, 8:57:30.345 am
UUID: 49d493b4-bfc6-4012-ad2c-8995602e7feb
Ancestors: VMMaker.oscog-eem.772

Fix a couple of unicode formatting issues that may be
corruptions that have crept in in older buggy Spur versions.

=============== Diff against VMMaker.oscog-eem.772 ===============

Item was changed:
  CogAbstractInstruction subclass: #CogIA32Compiler
  	instanceVariableNames: ''
  	classVariableNames: 'CDQ CMPXCHGAwR CMPXCHGMwrR CPUID EAX EBP EBX ECX EDI EDX ESI ESP IDIVR IMULRR LFENCE LOCK MFENCE ModReg ModRegInd ModRegIndDisp32 ModRegIndSIB ModRegRegDisp32 ModRegRegDisp8 SFENCE SIB1 SIB2 SIB4 SIB8 XCHGAwR XCHGMwrR XCHGRR XMM0H XMM0L XMM1H XMM1L XMM2H XMM2L XMM3H XMM3L XMM4H XMM4L XMM5H XMM5L XMM6H XMM6L XMM7H XMM7L'
  	poolDictionaries: ''
  	category: 'VMMaker-JIT'!
  
+ !CogIA32Compiler commentStamp: 'eem 6/14/2014 08:52' prior: 0!
- !CogIA32Compiler commentStamp: '<historical>' prior: 0!
  I generate IA32 (x86) instructions from CogAbstractInstructions.  For reference see
+ 1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
+ 2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
- 1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
- 2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
  	http://www.intel.com/products/processor/manuals/
+ (® is supposed to be the Unicode "registered  sign".
- (® is supposed to be the Unicode "registered  sign".
  
  This class does not take any special action to flush the instruction cache on instruction-modification, trusting that Intel and AMD processors correctly invalidate the instruction cache via snooping.  According to the manuals, this will work on systems where code and data have the same virtual address.  The CogICacheFlushingIA32Compiler subclass exists to use the CPUID instruction to serialize instruction-modification for systems with code and data at different virtual addresses.!

Item was changed:
  ----- Method: SpurMemoryManager>>followForwarded: (in category 'forwarding') -----
  followForwarded: objOop
  	"Follow a forwarding pointer.  Alas we cannot prevent forwarders to forwarders
  	 being created by lazy become.  Consider the following example by Igor Stasenko:
  		array := { a. b. c }.
+ 		- array at: 1 points to a. array at: 2 points to b. array at: 3 points to c
- 		- array at: 1 points to &a. array at: 2 points to &b. array at: 3 points to &c Ó
  		a becomeForward: b
+ 		- array at: 1 still points to a. array at: 2 still points to b. array at: 3 still points to c
- 		- array at: 1 still points to &a. array at: 2 still points to &b. array at: 3 still points to &c
  		b becomeForward: c.
+ 		- array at: 1 still points to a. array at: 2 still points to b. array at: 3 still points to c
- 		- array at: 1 still points to &a. array at: 2 still points to &b. array at: 3 still points to &c
  		- when accessing array first one has to follow a forwarding chain:
+ 		a -> b -> c"
- 		&a -> &b -> c"
  	<api>
  	| referent |
  	self assert: (self isForwarded: objOop).
  	referent := self fetchPointer: 0 ofMaybeForwardedObject: objOop.
  	[(self isOopForwarded: referent)] whileTrue:
  		[referent := self fetchPointer: 0 ofMaybeForwardedObject: referent].
  	^referent!



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