[Vm-dev] VM Maker: VMMaker.oscog-eem.1180.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1180.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1180
Author: eem
Time: 10 April 2015, 3:59:26.259 pm
UUID: 7b05983e-40dd-497e-9b91-91c188ecc133
Ancestors: VMMaker.oscog-eem.1179

Do register allocation in the right place in
genUnaryInlinePrimitive:.

Fix overflow slot access in genGetNumSlotsOf:into:
et al.

=============== Diff against VMMaker.oscog-eem.1179 ===============

Item was changed:
  ----- Method: CogObjectRepresentationFor32BitSpur>>genGetNumBytesOf:into: (in category 'compile abstract instructions') -----
  genGetNumBytesOf: srcReg into: destReg
  	"Get the size in byte-sized slots of the object in srcReg into destReg.
  	 srcReg may equal destReg.
  	 destReg <- numSlots << self shiftForWord - (fmt bitAnd: 3).
  	 Assumes the object in srcReg has a byte format, i.e. 16 to 23 or 24 to 31 "
  	<var: #jmp type: #'AbstractInstruction *'>
  	| jmp |
  	self genGetRawSlotSizeOfNonImm: srcReg into: TempReg.
  	cogit CmpCq: objectMemory numSlotsMask R: TempReg.
  	jmp := cogit JumpLess: 0.
+ 	self genGetOverflowSlotsOf: srcReg into: destReg.
- 	cogit MoveMw: objectMemory wordSize negated r: srcReg R: destReg.
  	jmp jmpTarget: (cogit LogicalShiftLeftCq: objectMemory shiftForWord R: destReg). 
  	"Now: destReg = numSlots << shiftForWord"
  	cogit MoveMw: 0 r: srcReg R: TempReg.
  	cogit LogicalShiftRightCq: objectMemory formatShift R: TempReg.
  	cogit AndCq: objectMemory wordSize - 1 R: TempReg.
  	"Now: fmt bitAnd: 3 in TempReg"
  	cogit SubR: TempReg R: destReg.
  	^0!

Item was changed:
  ----- Method: CogObjectRepresentationFor32BitSpur>>genGetNumSlotsOf:into: (in category 'compile abstract instructions') -----
  genGetNumSlotsOf: srcReg into: destReg
  	"Get the size in word-sized slots of the object in srcReg into destReg.
  	 srcReg may equal destReg."
  	<var: #jmp type: #'AbstractInstruction *'>
  	| jmp |
+ 	self assert: srcReg ~= destReg.
+ 	self genGetRawSlotSizeOfNonImm: srcReg into: destReg.
+ 	cogit CmpCq: objectMemory numSlotsMask R: destReg.
- 	self genGetRawSlotSizeOfNonImm: srcReg into: TempReg.
- 	cogit CmpCq: objectMemory numSlotsMask R: TempReg.
  	jmp := cogit JumpLess: 0.
+ 	self genGetOverflowSlotsOf: srcReg into: destReg.
+ 	jmp jmpTarget: cogit Label.
- 	cogit MoveMw: objectMemory wordSize negated r: srcReg R: TempReg.
- 	jmp jmpTarget: (cogit MoveR: TempReg R: destReg).
  	^0!

Item was added:
+ ----- Method: CogObjectRepresentationFor32BitSpur>>genGetOverflowSlotsOf:into: (in category 'compile abstract instructions') -----
+ genGetOverflowSlotsOf: srcReg into: destReg
+ 	cogit MoveMw: objectMemory baseHeaderSize negated r: srcReg R: destReg.
+ 	^0!

Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genGetOverflowSlotsOf:into: (in category 'compile abstract instructions') -----
+ genGetOverflowSlotsOf: srcReg into: destReg
+ 	self subclassResponsibility!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genUnaryInlinePrimitive: (in category 'inline primitive generators') -----
  genUnaryInlinePrimitive: prim
  	"Unary inline primitives."
  	"SistaV1: 248		11111000 	iiiiiiii		mjjjjjjj		Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  	 See EncoderForSistaV1's class comment and StackInterpreter>>#unaryInlinePrimitive:"
  	| rcvrReg resultReg |
  	self ssTop type = SSRegister
  		ifTrue: [rcvrReg := self ssTop register]
  		ifFalse:
  			[(rcvrReg := backEnd availableRegisterOrNilFor: self liveRegisters) ifNil:
  				[self ssAllocateRequiredReg:
  					(rcvrReg := optStatus isReceiverResultRegLive
  							ifTrue: [Arg0Reg]
  							ifFalse: [ReceiverResultReg])]].
- 	self ssTop popToReg: rcvrReg.
- 	self ssPop: 1.
  	(resultReg := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: (self registerMaskFor: rcvrReg))) ifNil:
  		[self ssAllocateRequiredReg: (resultReg := Arg1Reg)].
+ 	self ssTop popToReg: rcvrReg.
+ 	self ssPop: 1.
  	prim
  		caseOf: {
+ 					"00		unchecked class"
  			[1] ->	"01		unchecked pointer numSlots"
  				[objectRepresentation
  					genGetNumSlotsOf: rcvrReg into: resultReg;
  					genConvertIntegerToSmallIntegerInReg: resultReg].
+ 					"02		unchecked pointer basicSize"
+ 			[3] ->	"03		unchecked byte numBytes"
- 			[3] ->	"03 unchecked byte numBytes"
  				[objectRepresentation
  					genGetNumBytesOf: rcvrReg into: resultReg;
  					genConvertIntegerToSmallIntegerInReg: resultReg].
+ 					"04		unchecked short16Type format numShorts"
+ 					"05		unchecked word32Type format numWords"
+ 					"06		unchecked doubleWord64Type format numDoubleWords"
  				  }
  		otherwise:
  			[^EncounteredUnknownBytecode]..
  	self ssPushRegister: resultReg.
  	^0!