[Vm-dev] VM Maker: VMMaker.oscog-eem.1193.mcz

commits at source.squeak.org commits at source.squeak.org
Tue Apr 14 18:12:29 UTC 2015 

Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1193.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1193
Author: eem
Time: 14 April 2015, 11:10:47.632 am
UUID: 0b243ced-57fc-4dee-a6da-ec553b55eb40
Ancestors: VMMaker.oscog-eem.1192

Correct in-line primitive SmallInteger = ~=
missed in the last commit.

Fix slip in genGetNumBytesOf:into:.  And notice
that genGetFormatOf:into:baseHeaderIntoScratch:
et al can use byte access to get at format, as
intended in the Spur header design.

=============== Diff against VMMaker.oscog-eem.1192 ===============

Item was changed:
  ----- Method: CogObjectRepresentationFor32BitSpur>>genGetNumBytesOf:into: (in category 'compile abstract instructions') -----
  genGetNumBytesOf: srcReg into: destReg
  	"Get the size in byte-sized slots of the object in srcReg into destReg.
  	 srcReg may equal destReg.
  	 destReg <- numSlots << self shiftForWord - (fmt bitAnd: 3).
  	 Assumes the object in srcReg has a byte format, i.e. 16 to 23 or 24 to 31 "
  	<var: #jmp type: #'AbstractInstruction *'>
  	| jmp |
+ 	self genGetRawSlotSizeOfNonImm: srcReg into: destReg.
+ 	cogit CmpCq: objectMemory numSlotsMask R: destReg.
- 	self genGetRawSlotSizeOfNonImm: srcReg into: TempReg.
- 	cogit CmpCq: objectMemory numSlotsMask R: TempReg.
  	jmp := cogit JumpLess: 0.
  	self genGetOverflowSlotsOf: srcReg into: destReg.
  	jmp jmpTarget: (cogit LogicalShiftLeftCq: objectMemory shiftForWord R: destReg). 
+ 	self genGetFormatOf: srcReg into: TempReg baseHeaderIntoScratch: nil.
- 	"Now: destReg = numSlots << shiftForWord"
- 	cogit MoveMw: 0 r: srcReg R: TempReg.
- 	cogit LogicalShiftRightCq: objectMemory formatShift R: TempReg.
- 	cogit AndCq: objectMemory wordSize - 1 R: TempReg.
  	"Now: fmt bitAnd: 3 in TempReg"
  	cogit SubR: TempReg R: destReg.
  	^0!

Item was changed:
  ----- Method: CogObjectRepresentationForSpur>>genGetFormatOf:into:baseHeaderIntoScratch: (in category 'compile abstract instructions') -----
  genGetFormatOf: sourceReg into: destReg baseHeaderIntoScratch: scratchReg
+ 	scratchReg
+ 		ifNil:
+ 			[self flag: #endianness.
+ 			 cogit MoveMb: 3 r: sourceReg R: destReg]
+ 		ifNotNil:
+ 			[cogit MoveMw: 0 r: sourceReg R: destReg.
+ 			 cogit MoveR: destReg R: scratchReg. "destReg := (at least) least significant half of self baseHeader: receiver"
+ 			 cogit LogicalShiftRightCq: objectMemory formatShift R: destReg].
- 	cogit MoveMw: 0 r: sourceReg R: destReg.
- 	scratchReg ifNotNil:
- 		[cogit MoveR: destReg R: scratchReg]. "destReg := (at least) least significant half of self baseHeader: receiver"
- 	cogit LogicalShiftRightCq: objectMemory formatShift R: destReg.
  	cogit AndCq: objectMemory formatMask R: destReg.	"formatReg := self formatOfHeader: destReg"
  	^0!

Item was changed:
  ----- Method: CogObjectRepresentationForSpur>>genGetFormatOf:into:leastSignificantHalfOfBaseHeaderIntoScratch: (in category 'compile abstract instructions') -----
  genGetFormatOf: sourceReg into: destReg leastSignificantHalfOfBaseHeaderIntoScratch: scratchRegOrNil
  	"Get the format of the object in sourceReg into destReg.  If scratchRegOrNil
  	 is not nil, load at least the least significant 32-bits (64-bits in 64-bits) of the
  	 header word, which contains the format, into scratchRegOrNil."
+ 	scratchRegOrNil
+ 		ifNil:
+ 			[self flag: #endianness.
+ 			 cogit MoveMb: 3 r: sourceReg R: destReg]
+ 		ifNotNil:
+ 			[cogit MoveMw: 0 r: sourceReg R: destReg.
+ 			 cogit MoveR: destReg R: scratchRegOrNil. "destReg := (at least) least significant half of self baseHeader: receiver"
+ 			 cogit LogicalShiftRightCq: objectMemory formatShift R: destReg].
- 	cogit MoveMw: 0 r: sourceReg R: destReg.
- 	scratchRegOrNil ifNotNil:
- 		[cogit MoveR: destReg R: scratchRegOrNil]. "destReg := (at least) least significant half of self baseHeader: receiver"
- 	cogit LogicalShiftRightCq: objectMemory formatShift R: destReg.
  	cogit AndCq: objectMemory formatMask R: destReg.	"formatReg := self formatOfHeader: destReg"
  	^0!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genBinaryConstOpVarInlinePrimitive: (in category 'inline primitive generators') -----
  genBinaryConstOpVarInlinePrimitive: prim
  	"Const op var version of binary inline primitives."
  	"SistaV1: 248		11111000 	iiiiiiii		mjjjjjjj		Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  	 See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:"
  	| ra val untaggedVal adjust |
  	ra := self allocateOneRegister.
  	self ssTop popToReg: ra.
  	self ssPop: 1.
  	val := self ssTop constant.
  	self ssPop: 1.
  	untaggedVal := val - objectMemory smallIntegerTag.
  	prim caseOf: {
  		"0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  		[0]	->	[self AddCq: untaggedVal R: ra].
  		[1]	->	[self MoveCq: val R: TempReg.
  				 self SubR: ra R: TempReg.
  				 objectRepresentation genAddSmallIntegerTagsTo: TempReg.
  				 self MoveR: TempReg R: ra].
  		[2]	->	[objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ra.
  				 self MoveCq: (objectMemory integerValueOf: val) R: TempReg.
  				 self MulR: TempReg R: ra.
  				 objectRepresentation genAddSmallIntegerTagsTo: ra].
  
  		"2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  
  		"2032	through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)"
  		"CmpCqR is SubRCq so everything is reversed, but because no CmpRCq things are reversed again and we invert the sense of the jumps."
  		[32] -> [ self CmpCq: val R: ra.
  				self genBinaryInlineComparison: JumpLessOrEqual opFalse: JumpGreater destReg: ra ].
  		[33] -> [ self CmpCq: val R: ra.
  				self genBinaryInlineComparison: JumpGreaterOrEqual opFalse: JumpLess destReg: ra ].
  		[34] -> [ self CmpCq: val R: ra.
  				self genBinaryInlineComparison: JumpLess opFalse: JumpGreaterOrEqual destReg: ra ].
  		[35] -> [ self CmpCq: val R: ra.
  				self genBinaryInlineComparison: JumpGreater opFalse: JumpLessOrEqual destReg: ra ].
  		[36] -> [ self CmpCq: val R: ra.
- 				self genBinaryInlineComparison: JumpNonZero opFalse: JumpZero destReg: ra ].
- 		[37] -> [ self CmpCq: val R: ra.
  				self genBinaryInlineComparison: JumpZero opFalse: JumpNonZero destReg: ra ].
+ 		[37] -> [ self CmpCq: val R: ra.
+ 				self genBinaryInlineComparison: JumpNonZero opFalse: JumpZero destReg: ra ].
  
  		"2064	through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop"
  		[64] ->	[objectRepresentation genConvertSmallIntegerToIntegerInReg: ra.
  				adjust := (objectMemory baseHeaderSize >> objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative"
  				adjust ~= 0 ifTrue: [ self AddCq: adjust R: ra. ]. 
  				self annotate: (self MoveCw: val R: TempReg) objRef: val.
  				self MoveXwr: ra R: TempReg R: ra].
  		[65] ->	[objectRepresentation genConvertSmallIntegerToIntegerInReg: ra.
  				adjust := objectMemory baseHeaderSize - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative"
  				self AddCq: adjust R: ra.
  				self annotate: (self MoveCw: val R: TempReg) objRef: val.
  				self MoveXbr: ra R: TempReg R: ra.
  				objectRepresentation genConvertIntegerToSmallIntegerInReg: ra]
  	}
  	otherwise: [^EncounteredUnknownBytecode].
  	self ssPushRegister: ra.
  	^0!

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