[Vm-dev] VM Maker: VMMaker.oscog-eem.1606.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1606.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1606
Author: eem
Time: 17 December 2015, 12:08:45.954 am
UUID: 1efb5990-cfe7-420e-ae74-f40197a68c68
Ancestors: VMMaker.oscog-rmacnak.1605

x86 Cogit: Fix order of cmp in ArithCwR.
Extend var base range to 1Mb

=============== Diff against VMMaker.oscog-rmacnak.1605 ===============

Item was changed:
  ----- Method: CogInLineLiteralsX64Compiler>>concretizeArithCwR: (in category 'generate machine code') -----
  concretizeArithCwR: x64opcode
+ 	| value reg reverse |
- 	| value reg |
  	value := operands at: 0.
  	reg := self concreteRegister: (operands at: 1).
+ 	reverse := x64opcode = 16r85 or: [x64opcode = 16r39]. "Tst & Cmp; backwards"
  	machineCode
  		at:  0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg);
  		at:  1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7);
  		at:  2 put: (value bitAnd: 16rFF);
  		at:  3 put: (value >> 8 bitAnd: 16rFF);
  		at:  4 put: (value >> 16 bitAnd: 16rFF);
  		at:  5 put: (value >> 24 bitAnd: 16rFF);
  		at:  6 put: (value >> 32 bitAnd: 16rFF);
  		at:  7 put: (value >> 40 bitAnd: 16rFF);
  		at:  8 put: (value >> 48 bitAnd: 16rFF);
  		at:  9 put: (value >> 56 bitAnd: 16rFF);
+ 		at: 10 put: (reverse
- 		at: 10 put: (x64opcode = 16r85 "Tst; backwards"
  					ifTrue: [self rexR: ConcreteRISCTempReg x: 0 b: reg]
  					ifFalse: [self rexR: reg x: 0 b: ConcreteRISCTempReg]);
  		at: 11 put: x64opcode;
+ 		at: 12 put: (reverse
- 		at: 12 put: (x64opcode = 16r85 "Tst; backwards"
  					ifTrue: [self mod: ModReg RM: reg RO: ConcreteRISCTempReg]
  					ifFalse: [self mod: ModReg RM: ConcreteRISCTempReg RO: reg]).
  	^machineCodeSize := 13!

Item was changed:
  ----- Method: CogX64Compiler>>concretizeArithCqRWithRO:raxOpcode: (in category 'generate machine code') -----
  concretizeArithCqRWithRO: regOpcode raxOpcode: raxOpcode
  	"Will get inlined into concretizeAt: switch."
  	<inline: false>
  	| value reg |
  	value := operands at: 0.
  	reg := self concreteRegister: (operands at: 1).
  	machineCode
  		at: 0 put: (self rexR: 0 x: 0 b: reg).
  	(self isQuick: value) ifTrue:
  		[machineCode
  			at: 1 put: 16r83;
  			at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
  			at: 3 put: (value bitAnd: 16rFF).
  		 ^machineCodeSize := 4].
  	(self isSignExtendedFourByteValue: value) ifTrue:
  		[reg = RAX ifTrue:
  			[machineCode
  				at: 1 put: raxOpcode;
  				at: 2 put: (value bitAnd: 16rFF);
  				at: 3 put: (value >> 8 bitAnd: 16rFF);
  				at: 4 put: (value >> 16 bitAnd: 16rFF);
  				at: 5 put: (value >> 24 bitAnd: 16rFF).
  			 ^machineCodeSize := 6].
  		machineCode
  			at: 1 put: 16r81;
  			at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
  			at: 3 put: (value bitAnd: 16rFF);
  			at: 4 put: (value >> 8 bitAnd: 16rFF);
  			at: 5 put: (value >> 16 bitAnd: 16rFF);
  			at: 6 put: (value >> 24 bitAnd: 16rFF).
  		 ^machineCodeSize := 7].
+ 	^self concretizeArithCwR: (raxOpcode = 16r3D "Cmp" ifTrue: [16r39] ifFalse: [raxOpcode - 2])!
- 	^self concretizeArithCwR: (raxOpcode = 16r3D ifTrue: [16r39] ifFalse: [raxOpcode - 2])!

Item was changed:
  ----- Method: CogX64Compiler>>isAddressRelativeToVarBase: (in category 'testing') -----
  isAddressRelativeToVarBase: varAddress
  	<inline: true>
  	<var: #varAddress type: #usqInt>
+ 	"Support for addressing variables off the dedicated VarBaseReg.  Allow for 1Mb of variables.
- 	"Support for addressing variables off the dedicated VarBaseReg.  Allow for 16k of variables.
  	 The x64 supports 32-bit offsets, but we choose not to address everything from VarBaseReg."
  	^varAddress notNil
  	  and: [varAddress >= cogit varBaseAddress
+ 	  and: [varAddress - cogit varBaseAddress < (1 << 20)]]!
- 	  and: [varAddress - cogit varBaseAddress < (1 << 14)]]!