[Vm-dev] VM Maker: VMMaker.oscog-tpr.1092.mcz
commits at source.squeak.org
commits at source.squeak.org
Fri Mar 13 17:20:39 UTC 2015
tim Rowledge uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1092.mcz
==================== Summary ====================
Name: VMMaker.oscog-tpr.1092
Author: tpr
Time: 13 March 2015, 10:19:11.654 am
UUID: ff3802c0-8550-4a16-baef-1a4b359ef4b1
Ancestors: VMMaker.oscog-tpr.1091
Small improvements to some code and mostly comment improvements so there is some hope of making sense of this later on
=============== Diff against VMMaker.oscog-tpr.1091 ===============
Item was changed:
CogAbstractInstruction subclass: #CogARMCompiler
instanceVariableNames: ''
+ classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI NE OrOpcode PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RISCTempReg RsbOpcode SP STMFD SubOpcode VC VS XorOpcode'
- classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI NE OrOpcode PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RISCTempReg SP STMFD SubOpcode VC VS XorOpcode'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0!
I generate ARM instructions from CogAbstractInstructions. For reference see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html
The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw).
This class does not take any special action to flush the instruction cache on instruction-modification.!
Item was changed:
----- Method: CogARMCompiler class>>initialize (in category 'class initialization') -----
initialize
"Initialize various ARM instruction-related constants."
"CogARMCompiler initialize"
| specificOpcodes refs |
super initialize.
self ~~ CogARMCompiler ifTrue: [^self].
R0 := 0.
R1 := 1.
R2 := 2.
R3 := 3.
R4 := 4.
R5 := 5.
R6 := 6.
R7 := 7.
R8 := 8.
R9 := 9.
R10 := 10.
R11 := 11.
R12 := 12..
SP := 13..
LR := 14.
PC := 15.
CArg0Reg := 0.
CArg1Reg := 1.
CArg2Reg := 2.
CArg3Reg := 3.
RISCTempReg := R10.
"Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1"
EQ := 0.
NE := 1.
CS := 2.
CC := 3.
MI := 4.
PL := 5.
VS := 6.
VC := 7.
HI := 8.
LS := 9.
GE := 10.
LT := 11.
GT := 12.
LE := 13.
AL := 14.
AddOpcode := 4.
AndOpcode := 0.
BicOpcode := 16rE.
CmpOpcode := 10.
OrOpcode := 16rC.
+ RsbOpcode := 3.
SubOpcode := 2.
XorOpcode := 1.
"Specific instructions"
LastRTLCode isNil ifTrue:
[CogRTLOpcodes initialize].
specificOpcodes := #(LDMFD STMFD BICCqR).
refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
[:ea| ea key].
(classPool keys reject: [:k| (specificOpcodes includes: k) or: [refs includes: k]]) do:
[:k|
Undeclared declare: k from: classPool].
specificOpcodes withIndexDo:
[:classVarName :value|
self classPool
declare: classVarName from: Undeclared;
at: classVarName put: value + LastRTLCode - 1]!
Item was changed:
----- Method: CogARMCompiler>>add:rn:imm:ror: (in category 'ARM convenience instructions') -----
add: destReg rn: srcReg imm: immediate ror: rot
+ "Remember the ROR is doubled by the cpu so use 30>>1 etc.
+ ADD destReg, srcReg, #immediate ROR #rot"
- "return an ADD destReg, srcReg, immediat ROR rot instruction. Remember the ROR is doubled by the cpu so use 30>>1 etc"
+ ^self type: 1 op: AddOpcode set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
- ^self type: 1 op: 4 set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
Item was changed:
----- Method: CogARMCompiler>>add:rn:rm: (in category 'ARM convenience instructions') -----
add: destReg rn: srcReg rm: addReg
+ "return an ADD destReg, srcReg, addReg instruction
+ ADD destReg, srcReg, addReg"
- "return an ADD destReg, srcReg, addReg instruction"
+ ^self type: 0 op: AddOpcode set: 0 rn: srcReg rd: destReg shifterOperand: addReg!
- ^self type: 0 op: 4 set: 0 rn: srcReg rd: destReg shifterOperand: addReg!
Item was changed:
----- Method: CogARMCompiler>>adds:rn:imm:ror: (in category 'ARM convenience instructions') -----
adds: destReg rn: srcReg imm: immediate ror: rot
+ "Remember the ROR is doubled by the cpu so use 30>>1 etc
+ ADDS destReg, srcREg, #immediate ROR #rot"
- "return an ADDS destReg, srcReg, immediat ROR rot instruction. Remember the ROR is doubled by the cpu so use 30>>1 etc"
+ ^self type: 1 op: AddOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
- ^self type: 1 op: 4 set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
Item was changed:
----- Method: CogARMCompiler>>and:rn:imm:ror: (in category 'ARM convenience instructions') -----
and: destReg rn: srcReg imm: immediate ror: rot
+ "Remember the ROR is doubled by the cpu so use 30>>1 etc
+ AND destReg, srcReg, #immediate ROR #rot"
- "return an AND destReg, srcReg, immediat ROR rot instruction. Remember the ROR is doubled by the cpu so use 30>>1 etc"
+ ^self type: 1 op: AndOpcode set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
- ^self type: 1 op: 0 set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
Item was changed:
----- Method: CogARMCompiler>>ands:rn:imm:ror: (in category 'ARM convenience instructions') -----
ands: destReg rn: srcReg imm: immediate ror: rot
+ "Remember the ROR is doubled by the cpu so use 30>>1 etc
+ ANDS destReg, srcReg, #immediate ROR #rot"
- "return an ANDS destReg, srcReg, immediat ROR rot instruction. Remember the ROR is doubled by the cpu so use 30>>1 etc"
+ ^self type: 1 op: AndOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
- ^self type: 1 op: 0 set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
Item was changed:
----- Method: CogARMCompiler>>b: (in category 'ARM convenience instructions') -----
b: offset
+ "return a B offset instruction; offset is signed 24bits of WORD offset, so +_32Mbyte range
+ B offset"
- "return a B offset instruction"
^self cond: AL br: 0 offset: offset
!
Item was changed:
----- Method: CogARMCompiler>>bics:rn:imm:ror: (in category 'ARM convenience instructions') -----
bics: destReg rn: srcReg imm: immediate ror: rot
+ "Remember the ROR is doubled by the cpu so use 30>>1 etc
+ BICS destReg, srcReg, #immediate ROR #rot"
- "return a BICS destReg, srcReg, immediat ROR rot instruction. Remember the ROR is doubled by the cpu so use 30>>1 etc"
^self type: 1 op: 14 set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
Item was changed:
----- Method: CogARMCompiler>>bl: (in category 'ARM convenience instructions') -----
bl: offset
+ "return a BL offset instruction; offset is signed 24bits of WORD offset, so +_32Mbyte range. Return address is in LR
+ BL offset"
- "return a BL offset instruction"
^self cond: AL br: 1 offset: offset
!
Item was changed:
----- Method: CogARMCompiler>>blx: (in category 'ARM convenience instructions') -----
blx: targetReg
+ "Branch&link to the address in targetReg. Return address is in LR
+ BX targetReg"
- "return a BX targetReg instruction"
^self cond: AL bx: 1 target: targetReg
!
Item was changed:
----- Method: CogARMCompiler>>bx: (in category 'ARM convenience instructions') -----
bx: targetReg
+ "Branch to address in targetReg.
+ BX targetReg"
- "return a BX targetReg instruction"
^self cond: AL bx: 0 target: targetReg
!
Item was changed:
----- Method: CogARMCompiler>>callTargetFromReturnAddress: (in category 'inline cacheing') -----
callTargetFromReturnAddress: callSiteReturnAddress
+ "Answer the address that the call immediately preceeding callSiteReturnAddress will jump to."
+ "this is also used by #jumpLongTargetBeforeFollowingAddress: and so we check for both call and jump related instructions; later on we can use simpler tests once it feels safe to assume we get here always with a call/jump in the proper place"
- "Answer the address the call immediately preceeding callSiteReturnAddress will jump to."
- "this is also used by #jumpLongTargetBeforeFOllowingAddress: and so we check for both call and jump related instructions; later on we can use simpler tests once it feels safe to assume we get here always with a call/jump in the proper place"
| callDistance call |
call := self instructionBeforeAddress: callSiteReturnAddress.
self assert: call ~= 0. "andeq r0, r0 will not be generated, not even as nops"
((self instructionIsB: call) or:[self instructionIsBL: call])
ifTrue: [ "a short call/jump" callDistance := self extractOffsetFromBL: call.
^callSiteReturnAddress + 4 + callDistance signedIntFromLong].
((self instructionIsBX: call) or:[self instructionIsBLX: call])
ifTrue:["A Long Call/Jump. Extract the value saved to RISCTempReg from all the instructions before."
^self extractOffsetFromBXAt: callSiteReturnAddress - 4].
self halt
!
Item was changed:
----- Method: CogARMCompiler>>concretizeCall (in category 'generate machine code - concretize') -----
concretizeCall
"Will get inlined into concretizeAt: switch."
<inline: true>
+ "build either a
+ BL offset
+ or
+ {move offset to offsetReg}
+ BLX offsetReg
+ instruction sequence. In production VMs we expect never to have long calls within generated code"
| offset |
self assert: (operands at: 0) ~= 0.
self assert: (operands at: 0) \\ 4 = 0.
offset := (operands at: 0) signedIntFromLong - (address + 8 "normal pc offset") signedIntFromLong.
(self isQuick: offset)
ifTrue: [
self machineCodeAt: 0 put: (self bl: offset). "BL offset"
^machineCodeSize := 4]
ifFalse: [
"self error: 'While we know how to generate a long distance call, we can''t update such a send site yet. Please restart with smaller cache size'."
^self concretizeLongCall]!
Item was added:
+ ----- Method: CogARMCompiler>>concretizeMoveM16rR (in category 'generate machine code - concretize') -----
+ concretizeMoveM16rR
+ "Will get inlined into concretizeAt: switch."
+ "ldrh destReg, [srcReg, #immediate],
+ or
+ move offset to RISCTempReg
+ ldrh destReg, [srcReg, RISCTempReg]"
+ <inline: true>
+ | srcReg offset destReg instrOffset|
+ offset := operands at: 0.
+ srcReg := self concreteRegister: (operands at: 1).
+ destReg := self concreteRegister: (operands at: 2).
+ self is8BitValue: offset
+ ifTrue: [ :u :immediate |
+ self machineCodeAt: 0
+ "ldrh destReg, [srcReg, #immediate]"
+ put: (self ldrh: destReg rn: srcReg plus: u imm: immediate).
+ ^machineCodeSize := 4]
+ ifFalse: [
+ instrOffset := self at: 0 moveCw: offset intoR: RISCTempReg.
+ "ldrh destReg, [srcReg, RISCTempReg]"
+ self machineCodeAt: instrOffset put: (self ldrh: destReg rn: srcReg rm: RISCTempReg).
+ ^machineCodeSize := instrOffset + 4 ]!
Item was changed:
----- Method: CogARMCompiler>>concretizeNegateR (in category 'generate machine code - concretize') -----
concretizeNegateR
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
reg := self concreteRegister: (operands at: 0).
+ "RSB destReg, srcReg, #0"
+ self machineCodeAt: 0 put: (self type: 1 op: RsbOpcode set: 0 rn: reg rd: reg).
- "rsb r?, r?, #0"
- self machineCodeAt: 0 put: (self type: 1 op: 3 set: 0 rn: reg rd: reg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>cond:type:op:set: (in category 'encoding') -----
cond: c type: t op: o set: s
"c : 4 bit, t: 3 bit, o: 4 bit, s: 1bit"
+ "cccctttoooos + oxFFFFF - the leftmost 12bits of (most) ARM instruction. The other 20 bits get built elsewhere"
- "cccctttoooos + oxFFFFF - the leftmost 12bit of (most) ARM instruction"
<inline: true>
^ c << 28 bitOr: ((t << 25) bitOr: ((o << 21) bitOr: (s << 20)))!
Item was changed:
----- Method: CogARMCompiler>>cond:type:op:set:rn:rd:shifterOperand: (in category 'encoding') -----
cond: conditionCode type: type op: flagsOrOpcode set: doUpdateStatusRegister rn: sourceRegister rd: targetRegister shifterOperand: so
+ "build an instruction - cccctttoooo + source + target + shifter op"
<inline: true>
^(self cond: conditionCode type: type op: flagsOrOpcode set: doUpdateStatusRegister rn: sourceRegister rd: targetRegister) bitOr: (so bitAnd: 16rFFF)!
Item was changed:
----- Method: CogARMCompiler>>genGetLeafCallStackPointerFunction (in category 'assertions') -----
genGetLeafCallStackPointerFunction
+ "create a tiny leaf function that just returns the SP in r0 "
- "create a tiny leaf function that just returns the SP in r0; doesn't seem to actually get used. "
cogit MoveR: SP R: R0.
cogit RetN: 0!
Item was changed:
----- Method: CogARMCompiler>>instructionBeforeAddress: (in category 'inline cacheing') -----
instructionBeforeAddress: followingAddress
"Answer the instruction immediately preceeding followingAddress."
+ ^objectMemory longAt: followingAddress -4!
- ^objectMemory longAt: followingAddress -4
-
- " old version - ^ ((objectMemory byteAt: followingAddress - 1 235) << 24)
- + ((objectMemory byteAt: followingAddress - 2) << 16)
- + ((objectMemory byteAt: followingAddress - 3) << 8)
- + (objectMemory byteAt: followingAddress - 4)"
- !
Item was added:
+ ----- Method: CogARMCompiler>>is8BitValue:ifTrue:ifFalse: (in category 'testing') -----
+ is8BitValue: constant ifTrue: trueAlternativeBlock ifFalse: falseAlternativeBlock
+ "For extended LDR and STR for half & double, there is an instruction allowing for one instruction encoding if the offset is encodable in 8 bit."
+ constant abs <= 255 "(2 raisedTo: 8)-1"
+ ifTrue: [
+ constant >= 0
+ ifTrue: [trueAlternativeBlock value: 1 value: constant]
+ ifFalse: [trueAlternativeBlock value: 0 value: constant abs]]
+ ifFalse: falseAlternativeBlock!
Item was changed:
----- Method: CogARMCompiler>>ldr:rn:plus:imm: (in category 'ARM convenience instructions') -----
ldr: destReg rn: baseReg plus: u imm: immediate12bitValue
+ " LDR destReg, [baseReg, immediate12bitValue] u=0 -> subtract imm; =1 -> add imm "
- "return a LDR destReg, [baseReg, 'u' immediate12bitValue]"
^self memMxr: AL reg: destReg base: baseReg u: u b: 0 l: 1 imm: immediate12bitValue!
Item was changed:
----- Method: CogARMCompiler>>ldr:rn:plusImm: (in category 'ARM convenience instructions') -----
ldr: destReg rn: baseReg plusImm: immediate12bitValue
+ " LDR destReg, [baseReg, +immediate12bitValue]"
- "return a LDR destReg, [baseReg, +immediate12bitValue]"
^self memMxr: AL reg: destReg base: baseReg u: 1 b: 0 l: 1 imm: immediate12bitValue!
Item was changed:
----- Method: CogARMCompiler>>ldr:rn:rm: (in category 'ARM convenience instructions') -----
ldr: destReg rn: baseReg rm: offsetReg
+ " LDR destReg, [baseReg, + offsetReg]
+ The contents of offsetReg are assumed to be correctly signed"
- "return a LDR destReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed"
^self memMxr: AL reg: destReg base: baseReg p: 1 u: 1 b: 0 w: 0 l: 1 rm: offsetReg!
Item was changed:
----- Method: CogARMCompiler>>ldrb:rn:plus:imm: (in category 'ARM convenience instructions') -----
ldrb: destReg rn: baseReg plus: u imm: immediate12bitValue
+ " LDRB destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm "
- "return a LDRB destReg, [baseReg, 'u' immediate12bitValue]"
^self memMxr: AL reg: destReg base: baseReg u: u b: 1 l: 1 imm: immediate12bitValue!
Item was changed:
----- Method: CogARMCompiler>>ldrb:rn:rm: (in category 'ARM convenience instructions') -----
ldrb: destReg rn: baseReg rm: offsetReg
+ " LDR destReg, [baseReg, + offsetReg]
+ The contents of offsetReg are assumed to be correctly signed"
- "return a LDR destReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed"
^self memMxr: AL reg: destReg base: baseReg p: 1 u: 1 b: 1 w: 0 l: 1 rm: offsetReg!
Item was added:
+ ----- Method: CogARMCompiler>>ldrh:rn:plus:imm: (in category 'ARM convenience instructions') -----
+ ldrh: destReg rn: baseReg plus: u imm: immediate8bitValue
+ " LDRH destReg, [baseReg, 'u' immediate8bitValue] u=0 -> subtract imm; =1 -> add imm "
+ ^self memM16xr: AL reg: destReg base: baseReg p: 1 u: u w: 0 l: 1 offset: immediate8bitValue!
Item was added:
+ ----- Method: CogARMCompiler>>ldrh:rn:rm: (in category 'ARM convenience instructions') -----
+ ldrh: destReg rn: baseReg rm: offsetReg
+ " LDRH destReg, [baseReg, +offsetReg]
+ The contents of offsetReg are assumed to be correctly signed"
+ ^self memM16xr: AL reg: destReg base: baseReg p: 1 u: 1 w: 0 l: 1 rm: offsetReg!
Item was added:
+ ----- Method: CogARMCompiler>>memM16xr:reg:base:p:u:w:l:offset: (in category 'encoding') -----
+ memM16xr: cond reg: destReg base: baseReg p: postpreoffset u: updown w: weirdstuff l: loadstore offset: offset8
+ "build an ARM [base +/- offset8] half-word memory instruction
+ p -> pre-index (1) or post-index (0) the offset. Combines with W to do some odd things.
+ u -> up (1) or down (0) ie + or - for the offset
+ b -> byte(1) or word (0)
+ w -> write-back (1) if pre-indexing.
+ l -> load (1) or store (0)"
+ ^ cond << 28
+ bitOr: (0 << 25
+ bitOr: (postpreoffset << 24
+ bitOr: (updown << 23
+ bitOr: (1 << 22
+ bitOr: (weirdstuff << 21
+ bitOr: (loadstore << 20
+ bitOr: (baseReg << 16
+ bitOr: (destReg << 12
+ bitOr: ((offset8 bitAnd: 16rF0) << 4
+ bitOr: (11 << 4
+ bitOr: (offset8 bitAnd: 16rF)))))))))))!
Item was added:
+ ----- Method: CogARMCompiler>>memM16xr:reg:base:p:u:w:l:rm: (in category 'encoding') -----
+ memM16xr: cond reg: destReg base: baseReg p: postpreoffset u: updown w: weirdstuff l: loadstore rm: offsetReg
+ "build an ARM [base +/- offsetReg] memory instruction
+ p -> pre-index (1) or post-index (0) the offset. Combines with W to do some odd things.
+ u -> up (1) or down (0) ie + or - for the offset
+ b -> byte(1) or word (0)
+ w -> write-back (1) if pre-indexing.
+ l -> load (1) or store (0)"
+ ^ cond << 28
+ bitOr: (0 << 25
+ bitOr: (postpreoffset << 24
+ bitOr: (updown << 23
+ bitOr: (0 << 22
+ bitOr: (weirdstuff << 21
+ bitOr: (loadstore << 20
+ bitOr: (baseReg << 16
+ bitOr: (destReg << 12
+ bitOr: (16rB0
+ bitOr: offsetReg)))))))))!
Item was removed:
- ----- Method: CogARMCompiler>>minimalRightRingRotationFor:initialRotation: (in category 'encoding') -----
- minimalRightRingRotationFor: constant initialRotation: iniRightRingRotation
- "Given a constant and some initial rotation, tries to minimize that rotation in an effort to encode the according byte in constant. This is used, to encode the last 12bit of many operations, for which a 8bit immediate rotated by (2*)4bit is available. That immediate need be encoded with minimal rotation."
- | byte rightRingRotation |
- rightRingRotation := iniRightRingRotation.
- "Counter rotation to get the according byte. Because Smalltalk does not have left ring shift, shift further right."
- rightRingRotation ~= 0 ifTrue: [
- byte := constant >> (-2 * rightRingRotation + 32) bitAnd: 16rFF.
- "For 0, the shift has to be 0. For other immediates, the encoding with minimal rightRingRotation should be choosen."
- byte = 0
- ifTrue: [ rightRingRotation := 0]
- ifFalse: [
- 0 to: 2 do: [ :j |
- (byte bitAnd: 16r03) = 0
- ifTrue: [ rightRingRotation := rightRingRotation - 1.
- byte := byte >> 2 ]]]]
- ifFalse: [ byte := constant bitAnd: 16rFF].
- ^{rightRingRotation. byte}!
Item was changed:
----- Method: CogARMCompiler>>mov:imm:ror: (in category 'ARM convenience instructions') -----
+ mov: destReg imm: immediate8bitValue ror: rot
+ "Remember the ROR is doubled by the cpu so use 30>>1 etc.
+ MOV destReg, #immediate8BitValue ROR rot"
+ ^self type: 1 op: 16rD set: 0 rn: 0 rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)!
- mov: destReg imm: immediate8bitValue ror: rotateRightBy
- "return the ARM instruction MOV destReg, #immediate8BitValue ROR rotateRightBy"
- ^self type: 1 op: 16rD set: 0 rn: 0 rd: destReg shifterOperand: ((rotateRightBy>>1) <<8 bitOr: immediate8bitValue)!
Item was changed:
----- Method: CogARMCompiler>>mov:rn: (in category 'ARM convenience instructions') -----
mov: destReg rn: srcReg
+ " MOV destReg, srcReg"
- "return a MOV destReg, srcReg instruction"
^self type: 0 op: 16rD set: 0 rn: 0 rd: destReg shifterOperand: srcReg!
Item was changed:
----- Method: CogARMCompiler>>movs:rn: (in category 'ARM convenience instructions') -----
movs: destReg rn: srcReg
+ " MOVS destReg, srcReg"
- "return a MOV destReg, srcReg instruction"
^self type: 0 op: 16rD set: 1 rn: 0 rd: destReg shifterOperand: srcReg!
Item was changed:
----- Method: CogARMCompiler>>orr:imm:ror: (in category 'ARM convenience instructions') -----
+ orr: destReg imm: immediate8bitValue ror: rot
+ "Remember the ROR is doubled by the cpu so use 30>>1 etc.
+ ORR destReg, #immediate8BitValue ROR rot"
+ ^self type: 1 op: 16rC set: 0 rn: destReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)!
- orr: destReg imm: immediate8bitValue ror: rotateRightBy
- "return the ARM instruction ORR destReg, #immediate8BitValue ROR rotateRightBy"
- ^self type: 1 op: 16rC set: 0 rn: destReg rd: destReg shifterOperand: ((rotateRightBy>>1) <<8 bitOr: immediate8bitValue)!
Item was changed:
----- Method: CogARMCompiler>>popR: (in category 'ARM convenience instructions') -----
popR: dstReg
+ " pop word off TOS
+ LDR srcReg, [sp] #4"
- "return a pop - LDR srcReg, [sp] #4"
^self memMxr: AL reg: dstReg base: SP p: 0 u: 1 b: 0 w: 0 l: 1 imm: 4!
Item was changed:
----- Method: CogARMCompiler>>pushR: (in category 'ARM convenience instructions') -----
pushR: srcReg
+ " push word to TOS
+ STR srcReg, [sp, #-4]!!"
- "return a push - STR srcReg, [sp, #-4]!!"
^self memMxr: AL reg: srcReg base: SP p: 1 u: 0 b: 0 w: 1l: 0 imm: 4!
Item was changed:
----- Method: CogARMCompiler>>str:rn:plus:imm: (in category 'ARM convenience instructions') -----
str: destReg rn: baseReg plus: u imm: immediate12bitValue
+ " STR destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm "
- "return a STR destReg, [baseReg, 'u' immediate12bitValue]"
^self memMxr: AL reg: destReg base: baseReg u: u b: 0 l: 0 imm: immediate12bitValue!
Item was changed:
----- Method: CogARMCompiler>>str:rn:plusImm: (in category 'ARM convenience instructions') -----
str: srcReg rn: baseReg plusImm: immediate12bitValue
+ " STR srcReg, [baseReg, +immediate12bitValue]"
- "return a STR srcReg, [baseReg, +immediate12bitValue]"
^self memMxr: AL reg: srcReg base: baseReg u: 1 b: 0 l: 0 imm: immediate12bitValue!
Item was changed:
----- Method: CogARMCompiler>>str:rn:rm: (in category 'ARM convenience instructions') -----
str: srcReg rn: baseReg rm: offsetReg
+ " STR srcReg, [baseReg, + offsetReg]
+ The contents of offsetReg are assumed to be correctly signed"
- "return a STR srcReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed"
^self memMxr: AL reg: srcReg base: baseReg p: 1 u: 1 b: 0 w: 0 l: 0 rm: offsetReg!
Item was changed:
----- Method: CogARMCompiler>>strb:rn:plus:imm: (in category 'ARM convenience instructions') -----
strb: destReg rn: baseReg plus: u imm: immediate12bitValue
+ " STRB destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm "
- "return a STRB destReg, [baseReg, 'u' immediate12bitValue]"
^self memMxr: AL reg: destReg base: baseReg u: u b: 1 l: 0 imm: immediate12bitValue!
Item was changed:
----- Method: CogARMCompiler>>strb:rn:rm: (in category 'ARM convenience instructions') -----
strb: srcReg rn: baseReg rm: offsetReg
+ " STRB srcReg, [baseReg, + offsetReg]
+ The contents of offsetReg are assumed to be correctly signed"
- "return a STRB srcReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed"
^self memMxr: AL reg: srcReg base: baseReg p: 1 u: 1 b: 1 w: 0 l: 0 rm: offsetReg!
Item was changed:
----- Method: CogARMCompiler>>subs:rn:imm:ror: (in category 'ARM convenience instructions') -----
subs: destReg rn: srcReg imm: immediate ror: rot
+ " Remember the ROR is doubled by the cpu so use 30>>1 etc
+ SUBS destReg, srcReg, #immediate ROR rot"
- "return a SUBDS destReg, srcReg, immediat ROR rot instruction. Remember the ROR is doubled by the cpu so use 30>>1 etc"
^self type: 1 op: 2 set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
Item was changed:
----- Method: CogARMCompiler>>tst:rn:imm:ror: (in category 'ARM convenience instructions') -----
tst: ignored rn: srcReg imm: immediate ror: rot
+ " Remember the ROR is doubled by the cpu so use 30>>1 etc"
+ "also note that TST has no destReg
+ TST srcReg, #immediate ROR rot"
- "return a TST srcReg, immediat ROR rot instruction. Remember the ROR is doubled by the cpu so use 30>>1 etc"
- "also note that TST has no destREg"
^self type: 1 op: 8 set: 1 rn: srcReg rd: 0 shifterOperand: ((rot>>1) <<8 bitOr: immediate)!
More information about the Vm-dev
mailing list