[Vm-dev] VM Maker: VMMaker.oscog-eem.1097.mcz

commits at source.squeak.org commits at source.squeak.org
Wed Mar 18 20:01:19 UTC 2015


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1097.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1097
Author: eem
Time: 18 March 2015, 12:59:01.849 pm
UUID: 2d5d2313-de19-4642-9963-5e97ad1c7da8
Ancestors: VMMaker.oscog-eem.1096

Add a MoveOpcode to CogARMCompiler and use it.
Provide class side access to OrOpcode for GdbARMAlien's
disassembly code.

=============== Diff against VMMaker.oscog-eem.1096 ===============

Item was changed:
  CogAbstractInstruction subclass: #CogARMCompiler
  	instanceVariableNames: ''
+ 	classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI MoveOpcode NE OrOpcode PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RISCTempReg RsbOpcode SP STMFD SubOpcode VC VS XorOpcode'
- 	classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI NE OrOpcode PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RISCTempReg RsbOpcode SP STMFD SubOpcode VC VS XorOpcode'
  	poolDictionaries: ''
  	category: 'VMMaker-JIT'!
  
  !CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0!
  I generate ARM instructions from CogAbstractInstructions.  For reference see
  http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html
  
  The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw).
  
  This class does not take any special action to flush the instruction cache on instruction-modification.!

Item was changed:
  ----- Method: CogARMCompiler class>>initialize (in category 'class initialization') -----
  initialize
  	
  	"Initialize various ARM instruction-related constants."
  	"CogARMCompiler initialize"
  	
  	| specificOpcodes refs |
  	super initialize.
  	self ~~ CogARMCompiler ifTrue: [^self].
  	
  	R0 := 0.
  	R1 := 1.
  	R2 := 2.
  	R3 := 3.
  	R4 := 4.
  	R5 := 5.
  	R6 := 6.
  	R7 := 7.
  	R8 := 8.
  	R9 := 9.
  	R10 := 10.
  	R11 := 11.
  	R12 := 12..
  	SP := 13..
  	LR := 14.
  	PC := 15.
  	
  	CArg0Reg := 0.
  	CArg1Reg := 1.
  	CArg2Reg := 2.
  	CArg3Reg := 3.
  	
  	RISCTempReg := R10.
  	
  	"Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1"
  	EQ := 0.
  	NE := 1.
  	CS := 2.
  	CC := 3.
  	MI := 4.
  	PL := 5.
  	VS := 6.
  	VC := 7.
  	HI := 8.
  	LS := 9.
  	GE := 10.
  	LT := 11.
  	GT := 12.
  	LE := 13.
  	AL := 14.
  
  	AddOpcode := 	4.
  	AndOpcode := 0.
+ 	BicOpcode := 14.
- 	BicOpcode := 16rE.
  	CmpOpcode := 10.
+ 	MoveOpcode := 13.
+ 	OrOpcode := 12.
- 	OrOpcode := 16rC.
  	RsbOpcode := 3.
  	SubOpcode := 2.
  	XorOpcode := 1.
  	"Specific instructions"
  	LastRTLCode isNil ifTrue:
  		[CogRTLOpcodes initialize].
  	specificOpcodes := #(LDMFD STMFD BICCqR).
  	refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
  				[:ea| ea key].
  	(classPool keys reject: [:k| (specificOpcodes includes: k) or: [refs includes: k]]) do:
  		[:k|
  		Undeclared declare: k from: classPool].
  	specificOpcodes withIndexDo:
  		[:classVarName :value|
  		self classPool
  			declare: classVarName from: Undeclared;
  			at: classVarName put: value + LastRTLCode - 1]!

Item was added:
+ ----- Method: CogARMCompiler class>>orOpcode (in category 'accessing') -----
+ orOpcode
+ 	^OrOpcode!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeArithmeticShiftRightCqR (in category 'generate machine code - concretize') -----
  concretizeArithmeticShiftRightCqR
  	"Will get inlined into concretizeAt: switch."
  	"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction. 
  	Handle for now with a MOV reg, reg, ASR #distance"
  	<inline: true>
  	| distance reg |
  	distance := (operands at: 0) min: 31.
  	reg := self concreteRegister: (operands at: 1).
  	"cond 000 1101 0 0000 dest dist -100 srcR"
+ 	self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 0 rn: 0 rd: reg 
- 	self machineCodeAt: 0 put: (self type: 0 op: 16rD set: 0 rn: 0 rd: reg 
  									shifterOperand: (distance << 7 bitOr: (64 "flag for arithmetic" bitOr: reg))).
  	^machineCodeSize := 4!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeArithmeticShiftRightRR (in category 'generate machine code - concretize') -----
  concretizeArithmeticShiftRightRR
  	"Will get inlined into concretizeAt: switch."
  	"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction. 
  	Handle for now with a MOV reg, reg, ASR distReg"
  	<inline: true>
  	| destReg distReg |
  	distReg := self concreteRegister: (operands at: 0).
  	destReg := self concreteRegister: (operands at: 1).
  	"cond 000 1101 0 0000 destR distR 0101 srcR"
+ 	self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 0 rn: 0 rd: destReg 
- 	self machineCodeAt: 0 put: (self type: 0 op: 16rD set: 0 rn: 0 rd: destReg 
  									shifterOperand: (distReg << 8 bitOr: (80 bitOr: destReg))).
  	^machineCodeSize := 4!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeLogicalShiftLeftCqR (in category 'generate machine code - concretize') -----
  concretizeLogicalShiftLeftCqR
  	"Will get inlined into concretizeAt: switch."
  	"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction. 
  	Handle for now with a MOV reg, reg, LSL #distance"
  	<inline: true>
  	| distance reg |
  	distance := (operands at: 0) min: 31.
  	reg := self concreteRegister: (operands at: 1).
  	"cond 000 1101 0 0000 dest dista 000 srcR"
+ 	self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 0 rn: 0 rd: reg shifterOperand: (distance << 7 bitOr: reg)).
- 	self machineCodeAt: 0 put: (self type: 0 op: 16rD set: 0 rn: 0 rd: reg shifterOperand: (distance << 7 bitOr: reg)).
  	^machineCodeSize := 4!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeLogicalShiftLeftRR (in category 'generate machine code - concretize') -----
  concretizeLogicalShiftLeftRR
  	"Will get inlined into concretizeAt: switch."
  	"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction. 
  	Handle for now with a MOV reg, reg, LSL distReg"
  	<inline: true>
  	| destReg distReg |
  	distReg := self concreteRegister: (operands at: 0).
  	destReg := self concreteRegister: (operands at: 1).
  	"cond 000 1101 0 0000 dest dist 0001 srcR"
+ 	self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 0 rn: 0 rd: destReg 
- 	self machineCodeAt: 0 put: (self type: 0 op: 16rD set: 0 rn: 0 rd: destReg 
  									shifterOperand: (distReg << 8 bitOr: (16 bitOr: destReg))).
  	^machineCodeSize := 4!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeLogicalShiftRightCqR (in category 'generate machine code - concretize') -----
  concretizeLogicalShiftRightCqR
  	"Will get inlined into concretizeAt: switch."
  	"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction. 
  	Handle for now with a MOV reg, reg, LSR #distance"
  	<inline: true>
  	| distance reg |
  	distance := (operands at: 0) min: 31.
  	reg := self concreteRegister: (operands at: 1).
  	"cond 000 1101 0 0000 dest dist -010 srcR"
+ 	self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 0 rn: 0 rd: reg 
- 	self machineCodeAt: 0 put: (self type: 0 op: 16rD set: 0 rn: 0 rd: reg 
  									shifterOperand: (distance << 7 bitOr: (32 bitOr: reg))).
  	^machineCodeSize := 4!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeLogicalShiftRightRR (in category 'generate machine code - concretize') -----
  concretizeLogicalShiftRightRR
  	"Will get inlined into concretizeAt: switch."
  	"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction. 
  	Handle for now with a MOV reg, reg, LSR distReg"
  	<inline: true>
  	| destReg distReg |
  	distReg := self concreteRegister: (operands at: 0).
  	destReg := self concreteRegister: (operands at: 1).
  	"cond 000 1101 0 0000 dest dist 0011 srcR"
+ 	self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 0 rn: 0 rd: destReg 
- 	self machineCodeAt: 0 put: (self type: 0 op: 16rD set: 0 rn: 0 rd: destReg 
  									shifterOperand: (distReg << 8 bitOr: (48 bitOr: destReg))).
  	^machineCodeSize := 4!

Item was added:
+ ----- Method: CogARMCompiler>>instructionIsAnyB: (in category 'testing') -----
+ instructionIsAnyB: instr
+ 	"is this any of the B BX BL or BLX <offset> instructions?"
+ 	^(instr >> 25 bitAnd: 7) = 5!

Item was changed:
  ----- Method: CogARMCompiler>>mov:imm:ror: (in category 'ARM convenience instructions') -----
  mov: destReg imm: immediate8bitValue ror: rot
  	"Remember the ROR is doubled by the cpu so use 30>>1 etc.
  	MOV destReg, #immediate8BitValue ROR rot"
+ 	^self type: 1 op: MoveOpcode set: 0 rn: 0 rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)!
- 	^self type: 1 op: 16rD set: 0 rn: 0 rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)!

Item was changed:
  ----- Method: CogARMCompiler>>mov:rn: (in category 'ARM convenience instructions') -----
  mov: destReg rn: srcReg
  "	MOV destReg, srcReg"
  
+ 	^self type: 0 op: MoveOpcode set: 0 rn: 0 rd: destReg shifterOperand: srcReg!
- 	^self type: 0 op: 16rD set: 0 rn: 0 rd: destReg shifterOperand: srcReg!

Item was changed:
  ----- Method: CogARMCompiler>>movs:rn: (in category 'ARM convenience instructions') -----
  movs: destReg rn: srcReg
  "	MOVS destReg, srcReg"
  
+ 	^self type: 0 op: MoveOpcode set: 1 rn: 0 rd: destReg shifterOperand: srcReg!
- 	^self type: 0 op: 16rD set: 1 rn: 0 rd: destReg shifterOperand: srcReg!

Item was changed:
  ----- Method: CogARMCompiler>>rotateable8bitImmediate:ifTrue:ifFalse: (in category 'testing') -----
  rotateable8bitImmediate: constant ifTrue: trueAlternativeBlock ifFalse: falseAlternativeBlock
  	<inline: true>
  	"For data processing operands, there is the immediate shifter_operand variant, 
+ 	 where an 8 bit value is ring shifted _right_ by i.
+ 	 This is only suitable for quick constants(Cq), which won't change."
- 	where an 8 bit value is ring shifted _right_ by 2*i.
- 	This is only suitable for quick constant(Cq), which don't change."
  	
+ 	(constant bitAnd: 16rFF) = constant ifTrue:
+ 		[^trueAlternativeBlock value: 0 value: constant].
+ 	1 to: 30 do:
+ 		[:i |
+ 		(constant bitAnd: 16rFF << i) = constant ifTrue:
+ 			[^trueAlternativeBlock value: 32 - i value: constant >> i]].
- 	(constant bitAnd: 16rFF) = constant ifTrue: [ ^trueAlternativeBlock value: 0 value: constant].
- 	2 to: 30 do: [:i |
- 		(constant bitAnd: 16rFF << i) = constant 
- 			ifTrue: [ ^trueAlternativeBlock value: 32 - i value: constant >> i ]].
  	^falseAlternativeBlock value!



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