[Vm-dev] VM Maker: VMMaker.oscog-tpr.1107.mcz
commits at source.squeak.org
commits at source.squeak.org
Fri Mar 20 19:42:21 UTC 2015
tim Rowledge uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1107.mcz
==================== Summary ====================
Name: VMMaker.oscog-tpr.1107
Author: tpr
Time: 20 March 2015, 12:40:18.01 pm
UUID: befb7aea-840f-4950-ae37-b19889979997
Ancestors: VMMaker.oscog-eem.1106
Rescind unneeded redundantly unneccesary class vars that are unneccesarily redundant
=============== Diff against VMMaker.oscog-eem.1106 ===============
Item was changed:
CogAbstractInstruction subclass: #CogARMCompiler
instanceVariableNames: 'cond'
+ classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode'
- classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode CondHI CondLS EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0!
I generate ARM instructions from CogAbstractInstructions. For reference see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html
The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw).
This class does not take any special action to flush the instruction cache on instruction-modification.!
Item was changed:
----- Method: CogARMCompiler class>>initialize (in category 'class initialization') -----
initialize
"Initialize various ARM instruction-related constants."
"CogARMCompiler initialize"
| specificOpcodes refs |
super initialize.
self ~~ CogARMCompiler ifTrue: [^self].
R0 := 0.
R1 := 1.
R2 := 2.
R3 := 3.
R4 := 4.
R5 := 5.
R6 := 6.
R7 := 7.
R8 := 8.
R9 := 9.
R10 := 10.
R11 := 11.
R12 := 12..
SP := 13..
LR := 14.
PC := 15.
CArg0Reg := 0.
CArg1Reg := 1.
CArg2Reg := 2.
CArg3Reg := 3.
RISCTempReg := R10.
"Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1"
EQ := 0.
NE := 1.
CS := 2.
CC := 3.
MI := 4.
PL := 5.
VS := 6.
VC := 7.
HI := 8.
LS := 9.
GE := 10.
LT := 11.
GT := 12.
LE := 13.
AL := 14.
AddOpcode := 4.
AndOpcode := 0.
BicOpcode := 14.
CmpOpcode := 10.
MoveOpcode := 13.
OrOpcode := 12.
RsbOpcode := 3.
SubOpcode := 2.
XorOpcode := 1.
SMLALOpcode := 7.
- CondHI := 8.
- CondLS := 9.
CPSRReg := 16.
OverflowFlag := 1 << 28.
"Specific instructions"
LastRTLCode isNil ifTrue:
[CogRTLOpcodes initialize].
specificOpcodes := #(SMULL MSR MRS LDMFD STMFD BICCqR).
refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
[:ea| ea key].
(classPool keys reject: [:k| (specificOpcodes includes: k) or: [refs includes: k]]) do:
[:k|
Undeclared declare: k from: classPool].
specificOpcodes withIndexDo:
[:classVarName :value|
self classPool
declare: classVarName from: Undeclared;
at: classVarName put: value + LastRTLCode - 1]!
Item was changed:
----- Method: CogVMSimulator>>stackLimitFromMachineCode (in category 'I/O primitives support') -----
stackLimitFromMachineCode
"Intercept accesses to the stackLimit from machine code to
increment byteCount so that ioMSecs/ioMicroseconds does
somethng reasonable when we're purely in machine code."
(byteCount := byteCount + 1) - lastPollCount >= 100 ifTrue:
[lastPollCount := byteCount.
+ ("Sensor peekEvent notNil" false
- (Sensor peekEvent notNil
or: [nextProfileTick > 0
and: [nextProfileTick <= self ioUTCMicroseconds]]) ifTrue:
[suppressHeartbeatFlag "gets set by selector breakpoints"
ifTrue: [self forceInterruptCheck]
ifFalse: [self forceInterruptCheckFromHeartbeat]]].
^stackLimit!
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