[Vm-dev] a question about building ARM support code in processors

[tim Rowledge]

> On 18-10-2015, at 9:06 AM, Tim Olson <tim.olson.mail at gmail.com> wrote:
> 
> You can then try running with the ARM simulator instead of the IA32 simulator by uncommenting it and commenting the ISA IA32 back again.  However, you won’t get as far, as there are still problems with ARM simulation and Cog ARM code generation.

The sim is the biggest problem right now, but once some fixes from TimO get into the main svn tree that ought to improve. The actual code generation is pretty good - has to be or we wouldn’t be running a production Cog Spur VM on several million Raspbery Pis! - though we did spot an interesting bug in CPICs a week or so ago. I’m working on it with Eliot and I think we have a work-around fix and a better but more complex way to make CPICs better and simpler. Or something like that.


tim
--
tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
The generation of random numbers is too important to be left to chance.