[Vm-dev] Exploring the simulator (was Re: REPL image for simulation)

[Ben Coman]

Is their some method I can call in the Image to cause the simulator to
break into a debugger?  I want to do this right before the end block
bracket, so I can trace the termination of a forked block without
needing to trace over the block's statements.

cheers -ben

On Tue, May 31, 2016 at 1:27 AM, tim Rowledge <tim at rowledge.org> wrote:
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>> On 30-05-2016, at 10:09 AM, Ben Coman <btc at openinworld.com> wrote:
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>> On Mon, May 30, 2016 at 11:35 PM, Clément Bera <bera.clement at gmail.com> wrote:
>>>
>>> I did a post out of this thread:
>>>
>>> https://clementbera.wordpress.com/2016/05/30/simulating-the-cog-vm/
>>
>> Nice article Clement, thanks.
>> One thing though, I can't think what the "dis" means in genAndDis: ?
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> Ooh, ooh - I can answer that one! "generate and disassemble” as in generate the code and then disassemble it and display the nicely formatted string result so you can see where it all went horribly wrong.
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> tim
> --
> tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
> The less time planning, the more time programming.
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>