[Vm-dev] Exploring the simulator (was Re: REPL image for simulation)

[Clément Bera]

Well you can call a method with a specific selector name and use the [break
selector] feature in the simulator. Alternatively you call a specific
primitive and put a halt in it in the simulator.

On Fri, Jun 3, 2016 at 3:45 PM, Ben Coman <btc at openinworld.com> wrote:

>
> Is their some method I can call in the Image to cause the simulator to
> break into a debugger?  I want to do this right before the end block
> bracket, so I can trace the termination of a forked block without
> needing to trace over the block's statements.
>
> cheers -ben
>
> On Tue, May 31, 2016 at 1:27 AM, tim Rowledge <tim at rowledge.org> wrote:
> >
> >
> >> On 30-05-2016, at 10:09 AM, Ben Coman <btc at openinworld.com> wrote:
> >>
> >>
> >> On Mon, May 30, 2016 at 11:35 PM, Clément Bera <bera.clement at gmail.com>
> wrote:
> >>>
> >>> I did a post out of this thread:
> >>>
> >>> https://clementbera.wordpress.com/2016/05/30/simulating-the-cog-vm/
> >>
> >> Nice article Clement, thanks.
> >> One thing though, I can't think what the "dis" means in genAndDis: ?
> >
> > Ooh, ooh - I can answer that one! "generate and disassemble” as in
> generate the code and then disassemble it and display the nicely formatted
> string result so you can see where it all went horribly wrong.
> >
> >
> > tim
> > --
> > tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
> > The less time planning, the more time programming.
> >
> >
>
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