[Vm-dev] VM Maker: Cog-eem.318.mcz
commits at source.squeak.org
commits at source.squeak.org
Tue May 10 05:46:40 UTC 2016
Eliot Miranda uploaded a new version of Cog to project VM Maker:
http://source.squeak.org/VMMaker/Cog-eem.318.mcz
==================== Summary ====================
Name: Cog-eem.318
Author: eem
Time: 9 May 2016, 10:46:11.557606 pm
UUID: 089a0b72-a28d-4fda-8f87-7008a889773a
Ancestors: Cog-eem.317
Add incomplete support for emulating floating point operations in the GdbARMAlien
=============== Diff against Cog-eem.317 ===============
Item was changed:
----- Method: GdbARMAlien>>handleExecutionPrimitiveFailureIn:minimumAddress: (in category 'error handling') -----
handleExecutionPrimitiveFailureIn: memoryArray "<Bitmap|ByteArray>" minimumAddress: minimumAddress "<Integer>"
"Handle an execution primitive failure. Convert out-of-range call and absolute
memory read into register instructions into ProcessorSimulationTrap signals."
"self printRegistersOn: Transcript"
| pcOnEntry pc instr |
+ pc := pcOnEntry := self pc.
- pcOnEntry := self pc.
self endCondition = InstructionPrefetchError ifTrue:
+ [pc := self pc: self priorPc].
- [self pc: self priorPc].
+ (pc between: minimumAddress and: memoryArray byteSize - 1) ifTrue:
- ((pc := self pc) between: minimumAddress and: memoryArray byteSize - 1) ifTrue:
[instr := memoryArray unsignedLongAt: pc + 1 bigEndian: false.
(self endCondition = InstructionPrefetchError) ifTrue:
[^self handleFailingBranch: instr to: pcOnEntry at: pc].
(self instructionIsAnyLoadStore: instr) ifTrue:
[^self handleFailingLoadStore: instr at: pc].
+ (self instructionIsAnyFPArithmetic: instr) ifTrue:
+ [^self handleFailingFPArithmetic: instr at: pc].
+
^self handleExecutionPrimitiveFailureAt: pc in: memoryArray].
^self reportPrimitiveFailure!
Item was added:
+ ----- Method: GdbARMAlien>>handleFailingFPArithmetic:at: (in category 'error handling') -----
+ handleFailingFPArithmetic: instr at: pc
+ | oneRegTransferMask twoRegTransferMask |
+ oneRegTransferMask := 16rF000F00.
+ (instr bitAnd: oneRegTransferMask) = 16rE000B00 ifTrue:
+ [^self handleOneRegTransferDoubleArithmetic: instr at: pc].
+ (instr bitAnd: oneRegTransferMask) = 16rE000A00 ifTrue:
+ [^self handleOneRegTransferSingleArithmetic: instr at: pc].
+ twoRegTransferMask := 16rFE00FC0.
+ (instr bitAnd: twoRegTransferMask) = 16rC400B00 ifTrue:
+ [^self handleTwoRegTransferDoubleArithmetic: instr at: pc].
+ (instr bitAnd: twoRegTransferMask) = 16rC400A00 ifTrue:
+ [^self handleTwoRegTransferSingleArithmetic: instr at: pc].
+ ^self reportPrimitiveFailure!
Item was added:
+ ----- Method: GdbARMAlien>>handleOneRegTransferDoubleArithmetic:at: (in category 'floating-point emulation') -----
+ handleOneRegTransferDoubleArithmetic: instr at: pc
+ "Emulate a one-register transfer VFP instruction."
+ | rn rd rm vn vm |
+ rn := instr >> 16 bitAnd: 15.
+ rd := instr >> 12 bitAnd: 15.
+ rm := instr bitAnd: 15.
+ vn := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs"
+ vm := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs"
+ (instr >> 18 bitAnd: 31)
+ caseOf: {
+ [8 "FMULD"] ->
+ [| r |
+ r := vn * vm.
+ self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].
+ [12"FADDD/FSUBD"] ->
+ [self shouldBeImplemented].
+ [32"FDIVD"] ->
+ [self shouldBeImplemented].
+ [45"FCMPD"] ->
+ [self shouldBeImplemented]. }
+ otherwise: [self reportPrimitiveFailure]!
Item was added:
+ ----- Method: GdbARMAlien>>instructionIsAnyFPArithmetic: (in category 'testing') -----
+ instructionIsAnyFPArithmetic: instr
+ "Identify single register transfer and double register transfer VFP instructions.
+ See C3.3 & C3.4 in the ARM ARM."
+ | oneRegTransferMask twoRegTransferMask |
+ oneRegTransferMask := 16rF000F00.
+ (instr bitAnd: oneRegTransferMask) = 16rE000A00 ifTrue:
+ [^true].
+ (instr bitAnd: oneRegTransferMask) = 16rE000B00 ifTrue:
+ [^true].
+ twoRegTransferMask := 16rFE00FC0.
+ (instr bitAnd: twoRegTransferMask) = 16rC400A00 ifTrue:
+ [^true].
+ (instr bitAnd: twoRegTransferMask) = 16rC400B00 ifTrue:
+ [^true].
+ ^false!
Item was changed:
----- Method: GdbARMAlien>>registerStateGetters (in category 'accessing-abstract') -----
registerStateGetters
+ ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 sp lr pc eflags
+ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15)!
- ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 sp lr pc eflags)!
Item was changed:
----- Method: GdbARMAlien>>registerStateSetters (in category 'accessing-abstract') -----
registerStateSetters
+ ^#( r0: r1: r2: r3: r4: r5: r6: r7: r8: r9: sl: fp: r12: sp: lr: pc: eflags:
+ d0: d1: d2: d3: d4: d5: d6: d7: d8: d9: d10: d11: d12: d13: d14: d15:)!
- "a list of register setting messages used to initialise or reset registers"
- ^#( r0: r1: r2: r3: r4: r5: r6: r7: r8: r9: sl: fp: r12: sp: lr: pc: eflags:)!
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