[Vm-dev] VM Maker: VMMaker.oscog-eem.1938.mcz
commits at source.squeak.org
commits at source.squeak.org
Mon Sep 5 13:35:28 UTC 2016
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1938.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1938
Author: eem
Time: 5 September 2016, 3:32:52.115785 pm
UUID: 6a812714-7058-45ab-8429-2adf42078387
Ancestors: VMMaker.oscog-eem.1937
Fix Slang bug that mistranslated genGetActiveContextNumArgs:large:inBlock:.
Pass address of block start created in StackToRegisterMappingCogit>>compileFullBlockMethodFrameBuild:
=============== Diff against VMMaker.oscog-eem.1937 ===============
Item was changed:
----- Method: StackToRegisterMappingCogit>>compileFullBlockMethodFrameBuild: (in category 'compile abstract instructions') -----
compileFullBlockMethodFrameBuild: numCopied
<option: #SistaV1BytecodeSet>
| blockStart |
<var: 'blockStart' type: #CogBlockStart>
needsFrame ifFalse:
[self cCode: [] inSmalltalk: [blockStart := CogBlockStart new].
blockStart
startpc: initialPC;
numArgs: methodOrBlockNumArgs;
numCopied: numCopied;
numInitialNils: 0.
+ self compileBlockFramelessEntry: (self addressOf: blockStart).
- self compileBlockFramelessEntry: blockStart.
^self].
super compileFullBlockMethodFrameBuild: numCopied.
self initSimStackForFramefulMethod: initialPC!
Item was changed:
----- Method: TMethod>>isConditionalToBeTransformedForAssignment:in: (in category 'inlining') -----
isConditionalToBeTransformedForAssignment: aSend in: aCodeGen
"Answer if a send is of the form
e1
ifTrue: [e2 ifTrue: [self m1] ifFalse: [self m2]]
ifFalse: [self m3]
such that at least one of the sends mN may be inlined.."
^(#(ifTrue:ifFalse: ifFalse:ifTrue:) includes: aSend selector)
and: [aSend args anySatisfy:
[:arg| | stmt |
self assert: arg isStmtList.
arg statements size > 1
+ or: [(stmt := arg statements first) isSwitch
+ or: [stmt isSend
- or: [(stmt := arg statements first) isSend
and: [(aCodeGen mayInline: stmt selector)
+ or: [self isConditionalToBeTransformedForAssignment: stmt in: aCodeGen]]]]]]!
- or: [self isConditionalToBeTransformedForAssignment: stmt in: aCodeGen]]]]]!
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