[Vm-dev] VM Maker: VMMaker.oscog-rsf.1951.mcz
commits at source.squeak.org
commits at source.squeak.org
Thu Sep 8 16:55:47 UTC 2016
Ronie Salgado Faila uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-rsf.1951.mcz
==================== Summary ====================
Name: VMMaker.oscog-rsf.1951
Author: rsf
Time: 8 September 2016, 6:52:41.871669 pm
UUID: c714858a-7f63-47bd-a9ec-4bc1350eead2
Ancestors: VMMaker.oscog-rsf.1915, VMMaker.oscog-eem.1950
Integration of Lowcode.
Lowcode is an extended bytecode set that is encoded using the inline primitive facility from the SistaV1 bytecode set.
Building a VM with Lowcode requires the following VMMaker options:
SistaVM true
LowcodeVM true
MULTIPLEBYTECODESETS true
bytecodeTableInitializer initializeBytecodeTableForSqueakV3PlusClosuresSistaV1Hybrid
IWST Slides:
http://www.slideshare.net/esug/lowcode-extending-smalltalk-with-c-types-to-improve-performance
In addition to these huge changes in the VM, Lowcode has some dependencies in some C headers with the inline FFI callout glue, and additional sqMemoryAccess.h macros. I will send a patch for inclusion into the OpenSmalltalk VM C sources.
=============== Diff against VMMaker.oscog-eem.1950 ===============
Item was changed:
----- Method: CCodeGenerator>>computeKernelReturnTypes (in category 'public') -----
computeKernelReturnTypes
| dictionary |
dictionary := Dictionary newFromPairs:
#(oopAt: #sqInt oopAt:put: #sqInt
oopAtPointer: #sqInt oopAtPointer:put: #sqInt
byteAt: #sqInt byteAt:put: #sqInt
byteAtPointer: #sqInt byteAtPointer:put: #sqInt
shortAt: #sqInt shortAt:put: #sqInt
shortAtPointer: #sqInt shortAtPointer:put: #sqInt
intAt: #sqInt intAt:put: #sqInt
intAtPointer: #sqInt intAtPointer:put: #sqInt
longAt: #sqInt longAt:put: #sqInt
longAtPointer: #sqInt longAtPointer:put: #sqInt
long32At: #int long32At:put: #int
unalignedLongAt: #sqInt unalignedLongAt:put: #sqInt
unalignedLong32At: #int unalignedLong32At:put: #int
long64At: #sqLong long64At:put: #sqLong
+ long64AtPointer: #sqLong long64AtPointer:put: #sqLong
+
+ singleFloatAtPointer: #float singleFloatAtPointerPut: #float
+ floatAtPointer: #double floatAtPointerPut: #double
+
-
fetchFloatAt:into: #void storeFloatAt:from: #void
fetchFloatAtPointer:into: #void storeFloatAtPointer:from: #void
fetchSingleFloatAt:into: #void storeSingleFloatAt:from: #void
fetchSingleFloatAtPointer:into: #void storeSingleFloatAtPointer:from: #void
pointerForOop: #'char *' oopForPointer: #sqInt
baseHeaderSize #sqInt wordSize #sqInt bytesPerOop #sqInt).
+ BytesPerWord = 8 ifTrue:
+ [#(long32At: long32At:put: unalignedLong32At: unalignedLong32At:put:) do:
+ [:accessor|
+ dictionary at: accessor put: #int]].
^dictionary!
Item was changed:
----- Method: CoInterpreter>>commonCallerReturn (in category 'return bytecodes') -----
commonCallerReturn
"Return to the previous context/frame (sender for method activations, caller for block activations)."
<sharedCodeNamed: 'commonCallerReturn' inCase: #returnTopFromBlock>
+ | callersFPOrNull doWeHaveANativeFrame |
- | callersFPOrNull |
<var: #callersFPOrNull type: #'char *'>
+ "TODO: Store/restore the nativeSP more properly, when it exists"
+ self cppIf: LowcodeVM ifTrue: [
+ doWeHaveANativeFrame := self frameHasNativeFrame: localFP.
+ doWeHaveANativeFrame ifTrue: [
+ nativeStackPointer := (self nativePreviousStackPointerIn: localFP) - 1.
+ nativeSP := 0.
+ self setFrameHasNotNativeFrame: localFP.
+ ].
+ ].
+
callersFPOrNull := self frameCallerFP: localFP.
callersFPOrNull == 0 "baseFrame" ifTrue:
[self assert: localFP = stackPage baseFP.
^self baseFrameReturn].
localIP := self frameCallerSavedIP: localFP.
localSP := localFP + (self frameStackedReceiverOffset: localFP).
localFP := callersFPOrNull.
localIP asUnsignedInteger < objectMemory startOfMemory ifTrue:
[localIP asUnsignedInteger ~= cogit ceReturnToInterpreterPC ifTrue:
["localIP in the cog method zone indicates a return to machine code."
^self returnToMachineCodeFrame].
localIP := self pointerForOop: (self iframeSavedIP: localFP)].
self setMethod: (self iframeMethod: localFP).
self fetchNextBytecode.
self internalStackTopPut: localReturnValue!
Item was added:
+ ----- Method: CoInterpreter>>defaultNativeStackFrameSize (in category 'stack pages') -----
+ defaultNativeStackFrameSize
+ <api>
+ ^ super defaultNativeStackFrameSize!
Item was changed:
----- Method: CoInterpreter>>internalizeIPandSP (in category 'utilities') -----
internalizeIPandSP
"Copy the instruction, stack and frame pointers to local variables for rapid access within the interpret loop."
self assert: instructionPointer ~= cogit ceReturnToInterpreterPC.
localIP := self pointerForOop: instructionPointer.
localSP := self pointerForOop: stackPointer.
+ localFP := self pointerForOop: framePointer.
+ self cppIf: LowcodeVM ifTrue: [ nativeSP := 0. ]!
- localFP := self pointerForOop: framePointer!
Item was added:
+ ----- Method: CoInterpreter>>nativeFramePointerIn: (in category 'internal interpreter access') -----
+ nativeFramePointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*3) ]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*3) ]!
Item was added:
+ ----- Method: CoInterpreter>>nativeFramePointerIn:put: (in category 'internal interpreter access') -----
+ nativeFramePointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char*'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*3) put: valueOopPointer]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*3) put: valueOopPointer]!
Item was added:
+ ----- Method: CoInterpreter>>nativePreviousStackPointerIn: (in category 'internal interpreter access') -----
+ nativePreviousStackPointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*2)]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*2)]!
Item was added:
+ ----- Method: CoInterpreter>>nativePreviousStackPointerIn:put: (in category 'internal interpreter access') -----
+ nativePreviousStackPointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char *'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*2) put: valueOopPointer]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*2) put: valueOopPointer]!
Item was added:
+ ----- Method: CoInterpreter>>nativeStackPointerAddress (in category 'trampoline support') -----
+ nativeStackPointerAddress
+ <option: #LowcodeVM>
+ <api>
+ <returnTypeC: #usqInt>
+ ^self cCode: [(self addressOf: nativeStackPointer) asUnsignedInteger]
+ inSmalltalk: [cogit simulatedReadWriteVariableAddress: #nativeStackPointer in: self]!
Item was added:
+ ----- Method: CoInterpreter>>nativeStackPointerIn: (in category 'internal interpreter access') -----
+ nativeStackPointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*4)]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*4)]!
Item was added:
+ ----- Method: CoInterpreter>>nativeStackPointerIn:put: (in category 'internal interpreter access') -----
+ nativeStackPointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char *'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*4) put: valueOopPointer]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*4) put: valueOopPointer]!
Item was added:
+ ----- Method: CoInterpreter>>positive32BitValueOf: (in category 'trampolines') -----
+ positive32BitValueOf: oop
+ <api>
+ ^super positive32BitValueOf: oop!
Item was added:
+ ----- Method: CoInterpreter>>positive64BitIntegerFor: (in category 'trampolines') -----
+ positive64BitIntegerFor: integerValue
+ <api>
+ ^super positive64BitIntegerFor: integerValue!
Item was added:
+ ----- Method: CoInterpreter>>positive64BitValueOf: (in category 'trampolines') -----
+ positive64BitValueOf: oop
+ <api>
+ ^super positive64BitValueOf: oop!
Item was added:
+ ----- Method: CoInterpreter>>shadowCallStackAddress (in category 'trampoline support') -----
+ shadowCallStackAddress
+ <option: #LowcodeVM>
+ <api>
+ <returnTypeC: #usqInt>
+ ^self cCode: [(self addressOf: shadowCallStackPointer) asUnsignedInteger]
+ inSmalltalk: [cogit simulatedReadWriteVariableAddress: #shadowCallStackPointer in: self]!
Item was added:
+ ----- Method: CoInterpreter>>shadowCallStackPointerIn: (in category 'internal interpreter access') -----
+ shadowCallStackPointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*5)]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*5)]!
Item was added:
+ ----- Method: CoInterpreter>>shadowCallStackPointerIn:put: (in category 'internal interpreter access') -----
+ shadowCallStackPointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char *'>
+ ^(self isMachineCodeFrame: theFP)
+ ifTrue:
+ [stackPages pointerAtPointer: theFP + FoxMFReceiver - (BytesPerWord*5) put: valueOopPointer]
+ ifFalse:
+ [stackPages pointerAtPointer: theFP + FoxIFReceiver - (BytesPerWord*5) put: valueOopPointer]!
Item was added:
+ ----- Method: CoInterpreter>>signed32BitIntegerFor: (in category 'trampolines') -----
+ signed32BitIntegerFor: integerValue
+ <api>
+ ^super signed32BitIntegerFor: integerValue!
Item was added:
+ ----- Method: CoInterpreter>>signed32BitValueOf: (in category 'trampolines') -----
+ signed32BitValueOf: oop
+ <api>
+ ^super signed32BitValueOf: oop!
Item was added:
+ ----- Method: CoInterpreter>>signed64BitIntegerFor: (in category 'trampolines') -----
+ signed64BitIntegerFor: integerValue
+ <api>
+ ^super signed64BitIntegerFor: integerValue!
Item was added:
+ ----- Method: CoInterpreter>>signed64BitValueOf: (in category 'trampolines') -----
+ signed64BitValueOf: oop
+ <api>
+ ^super signed64BitValueOf: oop!
Item was added:
+ ----- Method: CogAbstractInstruction>>availableFloatRegisterOrNoneFor: (in category 'register allocation') -----
+ availableFloatRegisterOrNoneFor: liveRegsMask
+ "Answer an unused abstract register in the liveRegMask.
+ Subclasses with more registers can override to answer them."
+ <returnTypeC: #sqInt>
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg0)) ifFalse:
+ [^DPFPReg0].
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg1)) ifFalse:
+ [^DPFPReg1].
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg2)) ifFalse:
+ [^DPFPReg2].
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg3)) ifFalse:
+ [^DPFPReg3].
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg4)) ifFalse:
+ [^DPFPReg4].
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg5)) ifFalse:
+ [^DPFPReg5].
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg6)) ifFalse:
+ [^DPFPReg6].
+ (liveRegsMask anyMask: (cogit registerMaskFor: DPFPReg7)) ifFalse:
+ [^DPFPReg7].
+
+ ^ NoReg!
Item was added:
+ ----- Method: CogAbstractInstruction>>genMarshallNArgs:floatArg:floatArg:floatArg:floatArg: (in category 'abi') -----
+ genMarshallNArgs: numArgs floatArg: regOrConst0 floatArg: regOrConst1 floatArg: regOrConst2 floatArg: regOrConst3
+ "Generate the code to pass up to four arguments in a C run-time call. Hack: each argument is
+ either a negative number, which encodes a constant, or a non-negative number, that of a register.
+
+ Run-time calls have no more than four arguments, so chosen so that on ARM, where in its C ABI the
+ first four integer arguments are passed in registers, all arguments can be passed in registers. We
+ defer to the back end to generate this code not so much that the back end knows whether it uses
+ the stack or registers to pass arguments (it does, but...). In fact we defer for an extremely evil reason.
+ Doing so allows the x64 (where up to 6 args are passed) to assign the register arguments in an order
+ that allows some of the argument registers to be used for specific abstract registers, specifically
+ ReceiverResultReg and ClassReg. This is evil, evil, evil, but also it's really nice to keep using the old
+ register assignments the original author has grown accustomed to."
+ <inline: true>
+ ^self subclassResponsibility!
Item was added:
+ ----- Method: CogAbstractInstruction>>genWriteCSecondResultIntoReg: (in category 'abi') -----
+ genWriteCSecondResultIntoReg: abstractRegister
+ | cResultReg |
+ cResultReg := self cResultRegisterHigh.
+ abstractRegister ~= cResultReg ifTrue:
+ [cogit gen: MoveRR operand: cResultReg operand: abstractRegister]!
Item was changed:
VMStructType subclass: #CogBytecodeDescriptor
+ instanceVariableNames: 'generator spanFunction needsFrameFunction stackDelta opcode numBytes isBranchTrue isBranchFalse isReturn isBlockCreation isMapped isMappedInBlock isExtension isInstVarRef is1ByteInstVarStore hasIRC isCallPrimitive'
- instanceVariableNames: 'generator spanFunction needsFrameFunction stackDelta opcode numBytes isBranchTrue isBranchFalse isReturn isBlockCreation isMapped isMappedInBlock isExtension isInstVarRef is1ByteInstVarStore hasIRC'
classVariableNames: ''
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogBytecodeDescriptor commentStamp: 'eem 11/18/2010 06:32' prior: 0!
I am an entry in the Cogit's dispatch table for bytecodes. I hold the routine to call to generate code for the partcular bytecode I represent and the number of bytes the bytecode has. For eliminating temps in frameless blocks I maintain a stack delta for bytecodes that are valid in a frameless block. The order of my instance variables is chosen for compact struct packing.!
Item was added:
+ ----- Method: CogBytecodeDescriptor>>isCallPrimitive (in category 'accessing') -----
+ isCallPrimitive
+ "Answer the value of isCallPrimitive"
+
+ ^ isCallPrimitive!
Item was added:
+ ----- Method: CogBytecodeDescriptor>>isCallPrimitive: (in category 'accessing') -----
+ isCallPrimitive: anObject
+ "Set the value of isCallPrimitive"
+
+ ^isCallPrimitive := anObject!
Item was changed:
SharedPool subclass: #CogCompilationConstants
instanceVariableNames: ''
+ classVariableNames: 'BadRegisterSet CogCompilerClass InFullBlock InVanillaBlock NumSendTrampolines SSBaseOffset SSConstant SSConstantFloat32 SSConstantFloat64 SSConstantInt32 SSConstantInt64 SSConstantNativePointer SSIllegal SSNativeRegister SSRegister SSRegisterDoubleFloat SSRegisterPair SSRegisterSingleFloat SSSpill SSSpillFloat32 SSSpillFloat64 SSSpillInt64 SSSpillNative UnimplementedOperation'
- classVariableNames: 'BadRegisterSet CogCompilerClass InFullBlock InVanillaBlock NumSendTrampolines SSBaseOffset SSConstant SSIllegal SSRegister SSSpill UnimplementedOperation'
poolDictionaries: ''
category: 'VMMaker-JIT'!
Item was changed:
CogAbstractInstruction subclass: #CogIA32Compiler
instanceVariableNames: ''
+ classVariableNames: 'CDQ CLD CMPXCHGAwR CMPXCHGMwrR CPUID EAX EBP EBX ECX EDI EDX ESI ESP FSTPD FSTPS IDIVR IMULRR LFENCE LOCK MFENCE MOVSB MOVSD ModReg ModRegInd ModRegIndDisp32 ModRegIndSIB ModRegRegDisp32 ModRegRegDisp8 REP SFENCE SIB1 SIB2 SIB4 SIB8 XCHGAwR XCHGMwrR XCHGRR XMM0L XMM1L XMM2L XMM3L XMM4L XMM5L XMM6L XMM7L'
- classVariableNames: 'CDQ CMPXCHGAwR CMPXCHGMwrR CPUID EAX EBP EBX ECX EDI EDX ESI ESP IDIVR IMULRR LFENCE LOCK MFENCE ModReg ModRegInd ModRegIndDisp32 ModRegIndSIB ModRegRegDisp32 ModRegRegDisp8 SFENCE SIB1 SIB2 SIB4 SIB8 XCHGAwR XCHGMwrR XCHGRR XMM0L XMM1L XMM2L XMM3L XMM4L XMM5L XMM6L XMM7L'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogIA32Compiler commentStamp: 'eem 9/14/2015 17:13' prior: 0!
I generate IA32 (x86) instructions from CogAbstractInstructions. For reference see
1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
http://www.intel.com/products/processor/manuals/
(® is supposed to be the Unicode "registered sign".
This class does not take any special action to flush the instruction cache on instruction-modification, trusting that Intel and AMD processors correctly invalidate the instruction cache via snooping. According to the manuals, this will work on systems where code and data have the same virtual address. The CogICacheFlushingIA32Compiler subclass exists to use the CPUID instruction to serialize instruction-modification for systems with code and data at different virtual addresses.!
Item was changed:
----- Method: CogIA32Compiler class>>initialize (in category 'class initialization') -----
initialize
"Initialize various IA32/x86 instruction-related constants.
[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M"
"CogIA32Compiler initialize"
self ~~ CogIA32Compiler ifTrue: [^self].
"N.B. EAX ECX and EDX are caller-save (scratch) registers.
EBX ESI and EDI are callee-save; see concreteRegisterFor:"
EAX := 0.
ECX := 1. "Were they completely mad or simply sadistic?"
EDX := 2.
EBX := 3.
ESP := 4.
EBP := 5.
ESI := 6.
EDI := 7.
XMM0L := 0.
XMM1L := 1.
XMM2L := 2.
XMM3L := 3.
XMM4L := 4.
XMM5L := 5.
XMM6L := 6.
XMM7L := 7.
"Mod R/M Mod fields. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-2"
ModRegInd := 0.
ModRegIndSIB := 4.
ModRegIndDisp32 := 5.
ModRegRegDisp8 := 1.
ModRegRegDisp32 := 2.
ModReg := 3.
"SIB Scaled Index modes. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-3"
SIB1 := 0.
SIB2 := 1.
SIB4 := 2.
SIB8 := 3.
"Specific instructions"
self
+ initializeSpecificOpcodes: #(CDQ IDIVR IMULRR CPUID LFENCE MFENCE SFENCE LOCK CMPXCHGAwR CMPXCHGMwrR XCHGAwR XCHGMwrR XCHGRR FSTPS FSTPD CLD REP MOVSB MOVSD)
- initializeSpecificOpcodes: #(CDQ IDIVR IMULRR CPUID LFENCE MFENCE SFENCE LOCK CMPXCHGAwR CMPXCHGMwrR XCHGAwR XCHGMwrR XCHGRR)
in: thisContext method!
Item was added:
+ ----- Method: CogIA32Compiler>>cFloatResultToRd: (in category 'abi') -----
+ cFloatResultToRd: reg
+ cogit gen: FSTPD operand: -8 operand: SPReg .
+ cogit MoveM64: -8 r: SPReg Rd: reg!
Item was added:
+ ----- Method: CogIA32Compiler>>cFloatResultToRs: (in category 'abi') -----
+ cFloatResultToRs: reg
+ cogit gen: FSTPS operand: -4 operand: SPReg.
+ cogit MoveM32: -4 r: SPReg Rs: reg!
Item was added:
+ ----- Method: CogIA32Compiler>>cResultRegisterHigh (in category 'accessing') -----
+ cResultRegisterHigh
+ "Answer the abstract register for the C result register.
+ Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
+ ^ EDX!
Item was added:
+ ----- Method: CogIA32Compiler>>cResultRegisterLow (in category 'accessing') -----
+ cResultRegisterLow
+ "Answer the abstract register for the C result register.
+ Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
+ ^ EAX!
Item was changed:
----- Method: CogIA32Compiler>>computeMaximumSize (in category 'generate machine code') -----
computeMaximumSize
"Compute the maximum size for each opcode. This allows jump offsets to
be determined, provided that all backward branches are long branches."
"N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^0].
[AlignmentNops] -> [^(operands at: 0) - 1].
[Fill32] -> [^4].
[Nop] -> [^1].
"Specific Control/Data Movement"
+ [REP] -> [^1].
+ [CLD] -> [^1].
+ [MOVSB] -> [^1].
+ [MOVSD] -> [^1].
[CDQ] -> [^1].
[IDIVR] -> [^2].
[IMULRR] -> [^3].
[CPUID] -> [^2].
[CMPXCHGAwR] -> [^7].
[CMPXCHGMwrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[LFENCE] -> [^3].
[MFENCE] -> [^3].
[SFENCE] -> [^3].
[LOCK] -> [^1].
[XCHGAwR] -> [^6].
[XCHGMwrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [6]]].
[XCHGRR] -> [^((operands at: 0) = EAX
or: [(operands at: 1) = EAX])
ifTrue: [1]
ifFalse: [2]].
+ [FSTPS] -> [^7].
+ [FSTPD] -> [^7].
+
"Control"
[CallFull] -> [^5].
[Call] -> [^5].
+ [CallR] -> [^2].
[JumpR] -> [^2].
[JumpFull] -> [self resolveJumpTarget. ^5].
[JumpLong] -> [self resolveJumpTarget. ^5].
[Jump] -> [self resolveJumpTarget. ^5].
[JumpZero] -> [self resolveJumpTarget. ^6].
[JumpNonZero] -> [self resolveJumpTarget. ^6].
[JumpNegative] -> [self resolveJumpTarget. ^6].
[JumpNonNegative] -> [self resolveJumpTarget. ^6].
[JumpOverflow] -> [self resolveJumpTarget. ^6].
[JumpNoOverflow] -> [self resolveJumpTarget. ^6].
[JumpCarry] -> [self resolveJumpTarget. ^6].
[JumpNoCarry] -> [self resolveJumpTarget. ^6].
[JumpLess] -> [self resolveJumpTarget. ^6].
[JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpGreater] -> [self resolveJumpTarget. ^6].
[JumpLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpBelow] -> [self resolveJumpTarget. ^6].
[JumpAboveOrEqual] -> [self resolveJumpTarget. ^6].
[JumpAbove] -> [self resolveJumpTarget. ^6].
[JumpBelowOrEqual] -> [self resolveJumpTarget. ^6].
[JumpLongZero] -> [self resolveJumpTarget. ^6].
[JumpLongNonZero] -> [self resolveJumpTarget. ^6].
[JumpFPEqual] -> [self resolveJumpTarget. ^6].
[JumpFPNotEqual] -> [self resolveJumpTarget. ^6].
[JumpFPLess] -> [self resolveJumpTarget. ^6].
[JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPGreater] -> [self resolveJumpTarget. ^6].
[JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPOrdered] -> [self resolveJumpTarget. ^6].
[JumpFPUnordered] -> [self resolveJumpTarget. ^6].
[RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]].
[Stop] -> [^1].
"Arithmetic"
[AddCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
+ [AddcCqR] -> [^(self isQuick: (operands at: 0))
+ ifTrue: [3]
+ ifFalse: [(operands at: 1) = EAX
+ ifTrue: [5]
+ ifFalse: [6]]].
[AndCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[CmpCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[OrCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[SubCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[TstCqR] -> [^((self isQuick: (operands at: 0)) and: [(operands at: 1) < 4])
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AddCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[AndCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[CmpCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[OrCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[SubCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[XorCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[AddRR] -> [^2].
[AndRR] -> [^2].
[CmpRR] -> [^2].
[OrRR] -> [^2].
[XorRR] -> [^2].
[SubRR] -> [^2].
[NegateR] -> [^2].
+ [NotR] -> [^2].
[LoadEffectiveAddressMwrR]
-> [^((self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftLeftRR] -> [^self computeShiftRRSize].
[LogicalShiftRightRR] -> [^self computeShiftRRSize].
[ArithmeticShiftRightRR] -> [^self computeShiftRRSize].
[AddRdRd] -> [^4].
[CmpRdRd] -> [^4].
[SubRdRd] -> [^4].
[MulRdRd] -> [^4].
[DivRdRd] -> [^4].
[SqrtRd] -> [^4].
+ [XorRdRd] -> [^4].
+
+ [AddRsRs] -> [^4].
+ [CmpRsRs] -> [^3].
+ [SubRsRs] -> [^4].
+ [MulRsRs] -> [^4].
+ [DivRsRs] -> [^4].
+ [SqrtRs] -> [^4].
+ [XorRsRs] -> [^3].
+
"Data Movement"
[MoveCqR] -> [^(operands at: 0) = 0 ifTrue: [2] ifFalse: [5]].
[MoveCwR] -> [^5].
[MoveRR] -> [^2].
[MoveRdRd] -> [^4].
+ [MoveRsRs] -> [^4].
[MoveAwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[MoveRAw] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
[MoveAbR] -> [^7].
[MoveRAb] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
+ [MoveRM32r] -> [^((self isQuick: (operands at: 1))
+ ifTrue: [((operands at: 1) = 0
+ and: [(operands at: 2) ~= EBP])
+ ifTrue: [2]
+ ifFalse: [3]]
+ ifFalse: [6])
+ + ((operands at: 2) = ESP
+ ifTrue: [1]
+ ifFalse: [0])].
[MoveRMwr] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [(operands at: 2) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRdM64r] -> [^((self isQuick: (operands at: 1))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
+ [MoveRsM32r] -> [^((self isQuick: (operands at: 1))
+ ifTrue: [5]
+ ifFalse: [8])
+ + ((operands at: 2) = ESP
+ ifTrue: [1]
+ ifFalse: [0])].
[MoveMbrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRMbr] -> [^(operands at: 2) = ESP
ifTrue: [7]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].
+ [MoveM8rR] -> [^(operands at: 1) = ESP
+ ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
+ ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
+ [MoveRM8r] -> [^(operands at: 2) = ESP
+ ifTrue: [7]
+ ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].
[MoveM16rR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRM16r] -> [^(operands at: 2) = ESP
ifTrue: [8]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [4] ifFalse: [7]]].
[MoveM64rRd] -> [^((self isQuick: (operands at: 0))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
+ [MoveM32rRs] -> [^((self isQuick: (operands at: 0))
+ ifTrue: [5]
+ ifFalse: [8])
+ + ((operands at: 1) = ESP
+ ifTrue: [1]
+ ifFalse: [0])].
+ [MoveM32rR] -> [^((self isQuick: (operands at: 0))
+ ifTrue: [((operands at: 0) = 0
+ and: [(operands at: 1) ~= EBP])
+ ifTrue: [2]
+ ifFalse: [3]]
+ ifFalse: [6])
+ + ((operands at: 1) = ESP
+ ifTrue: [1]
+ ifFalse: [0])].
[MoveMwrR] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [(operands at: 1) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveXbrRR] -> [self assert: (operands at: 0) ~= ESP.
^(operands at: 1) = EBP
ifTrue: [5]
ifFalse: [4]].
[MoveRXbrR] -> [self assert: (operands at: 1) ~= ESP.
^((operands at: 2) = EBP
ifTrue: [4]
ifFalse: [3])
+ ((operands at: 0) >= 4
ifTrue: [2]
ifFalse: [0])].
[MoveXwrRR] -> [self assert: (operands at: 0) ~= ESP.
^(operands at: 1) = EBP
ifTrue: [4]
ifFalse: [3]].
[MoveRXwrR] -> [self assert: (operands at: 1) ~= ESP.
^(operands at: 2) = EBP
ifTrue: [4]
ifFalse: [3]].
[PopR] -> [^1].
[PushR] -> [^1].
[PushCq] -> [^(self isQuick: (operands at: 0)) ifTrue: [2] ifFalse: [5]].
[PushCw] -> [^5].
[PrefetchAw] -> [^self hasSSEInstructions ifTrue: [7] ifFalse: [0]].
"Conversion"
+ [ConvertRRd] -> [^4].
+ [ConvertRdR] -> [^4].
+
+ [ConvertRsRd] -> [^4].
+ [ConvertRdRs] -> [^4].
+ [ConvertRsR] -> [^4].
+ [ConvertRRs] -> [^4].
+
+ [SignExtend8RR] -> [^3].
+ [SignExtend16RR] -> [^3].
+ [ZeroExtend8RR] -> [^3].
+ [ZeroExtend16RR] -> [^3]. }.
- [ConvertRRd] -> [^4] }.
^0 "to keep C compiler quiet"!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeAddcCqR (in category 'generate machine code') -----
+ concretizeAddcCqR
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | value reg |
+ value := operands at: 0.
+ reg := operands at: 1.
+ (self isQuick: value) ifTrue:
+ [machineCode
+ at: 0 put: 16r83;
+ at: 1 put: (self mod: ModReg RM: reg RO: 2);
+ at: 2 put: (value bitAnd: 16rFF).
+ ^machineCodeSize := 3].
+ reg = EAX ifTrue:
+ [machineCode
+ at: 0 put: 16r15;
+ at: 1 put: (value bitAnd: 16rFF);
+ at: 2 put: (value >> 8 bitAnd: 16rFF);
+ at: 3 put: (value >> 16 bitAnd: 16rFF);
+ at: 4 put: (value >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 5].
+ machineCode
+ at: 0 put: 16r81;
+ at: 1 put: (self mod: ModReg RM: reg RO: 2);
+ at: 2 put: (value bitAnd: 16rFF);
+ at: 3 put: (value >> 8 bitAnd: 16rFF);
+ at: 4 put: (value >> 16 bitAnd: 16rFF);
+ at: 5 put: (value >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 6!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeAddcRR (in category 'generate machine code') -----
+ concretizeAddcRR
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ "Assemble the ADC instruction"
+ | regLHS regRHS |
+ regLHS := operands at: 0.
+ regRHS := operands at: 1.
+ machineCode
+ at: 0 put: 16r13;
+ at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
+ ^machineCodeSize := 2!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeCLD (in category 'generate machine code') -----
+ concretizeCLD
+ <inline: true>
+ machineCode at: 0 put: 16rFC.
+ ^machineCodeSize := 1!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeCallR (in category 'generate machine code') -----
+ concretizeCallR
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | reg |
+ "CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
+ reg := operands at: 0.
+ machineCode
+ at: 0 put: 16rFF;
+ at: 1 put: (self mod: ModReg RM: reg RO: 2).
+ ^machineCodeSize := 2!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeCmpRsRs (in category 'generate machine code') -----
+ concretizeCmpRsRs
+ "Will get inlined into concretizeAt: switch.
+ We use UCOMISS (see p 4-260 [2])"
+ <inline: true>
+ | regLHS regRHS |
+ "CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16r2E;
+ at: 2 put: (self mod: ModReg RM: regRHS RO: regLHS).
+ ^machineCodeSize := 3!
Item was changed:
----- Method: CogIA32Compiler>>concretizeConvertRRd (in category 'generate machine code') -----
concretizeConvertRRd
"Will get inlined into concretizeAt: switch."
+ "CVTSI2D"
<inline: true>
| srcReg destReg |
+ srcReg := operands at: 0.
- srcReg := operands at:0.
destReg := operands at: 1.
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r2A;
at: 3 put: (self mod: ModReg RM: srcReg RO: destReg).
^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeConvertRRs (in category 'generate machine code') -----
+ concretizeConvertRRs
+ "Will get inlined into concretizeAt: switch."
+ "CVTSI2SS"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r2A;
+ at: 3 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeConvertRdR (in category 'generate machine code') -----
+ concretizeConvertRdR
+ "Will get inlined into concretizeAt: switch."
+ "CVTSD2SI"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at:0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16rF2;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r2D;
+ at: 3 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeConvertRdRs (in category 'generate machine code') -----
+ concretizeConvertRdRs
+ "Will get inlined into concretizeAt: switch."
+ "CVTSD2SS"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16rF2;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r5A;
+ at: 3 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeConvertRsR (in category 'generate machine code') -----
+ concretizeConvertRsR
+ "Will get inlined into concretizeAt: switch."
+ "CVTSS2SI"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r2D;
+ at: 3 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeConvertRsRd (in category 'generate machine code') -----
+ concretizeConvertRsRd
+ "Will get inlined into concretizeAt: switch."
+ "CVTSS2SD"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r5A;
+ at: 3 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeFSTPD (in category 'generate machine code') -----
+ concretizeFSTPD
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | srcReg offset destReg |
+ srcReg := 3.
+ offset := operands at: 0.
+ destReg := operands at: 1.
+ destReg ~= ESP ifTrue:
+ [(self isQuick: offset) ifTrue:
+ "FSTP dest"
+ [machineCode
+ at: 0 put: 16rDD;
+ at: 1 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ at: 2 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 3].
+ "FSTP dest"
+ machineCode
+ at: 0 put: 16rDD;
+ at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
+ at: 2 put: (offset bitAnd: 16rFF);
+ at: 3 put: (offset >> 8 bitAnd: 16rFF);
+ at: 4 put: (offset >> 16 bitAnd: 16rFF);
+ at: 5 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 6].
+ "ESP:"
+ (self isQuick: offset) ifTrue:
+ [machineCode
+ at: 0 put: 16rDD;
+ at: 1 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ at: 2 put: (self s: SIB1 i: 4 b: destReg);
+ at: 3 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 4].
+ machineCode
+ at: 0 put: 16rDD;
+ at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
+ at: 2 put: (self s: SIB1 i: 4 b: destReg);
+ at: 3 put: (offset bitAnd: 16rFF);
+ at: 4 put: (offset >> 8 bitAnd: 16rFF);
+ at: 5 put: (offset >> 16 bitAnd: 16rFF);
+ at: 6 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 7!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeFSTPS (in category 'generate machine code') -----
+ concretizeFSTPS
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | srcReg offset destReg |
+ srcReg := 3.
+ offset := operands at: 0.
+ destReg := operands at: 1.
+ destReg ~= ESP ifTrue:
+ [(self isQuick: offset) ifTrue:
+ "FSTP dest"
+ [machineCode
+ at: 0 put: 16rD9;
+ at: 1 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ at: 2 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 3].
+ "FSTP dest"
+ machineCode
+ at: 0 put: 16rD9;
+ at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
+ at: 2 put: (offset bitAnd: 16rFF);
+ at: 3 put: (offset >> 8 bitAnd: 16rFF);
+ at: 4 put: (offset >> 16 bitAnd: 16rFF);
+ at: 5 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 6].
+ "ESP:"
+ (self isQuick: offset) ifTrue:
+ [machineCode
+ at: 0 put: 16rD9;
+ at: 1 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ at: 2 put: (self s: SIB1 i: 4 b: destReg);
+ at: 3 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 4].
+ machineCode
+ at: 0 put: 16rD9;
+ at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
+ at: 2 put: (self s: SIB1 i: 4 b: destReg);
+ at: 3 put: (offset bitAnd: 16rFF);
+ at: 4 put: (offset >> 8 bitAnd: 16rFF);
+ at: 5 put: (offset >> 16 bitAnd: 16rFF);
+ at: 6 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 7!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeMOVSB (in category 'generate machine code') -----
+ concretizeMOVSB
+ <inline: true>
+ machineCode at: 0 put: 16rA4.
+ ^machineCodeSize := 1!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeMOVSD (in category 'generate machine code') -----
+ concretizeMOVSD
+ <inline: true>
+ machineCode at: 0 put: 16rA5.
+ ^machineCodeSize := 1!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeMoveM32rRs (in category 'generate machine code') -----
+ concretizeMoveM32rRs
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | srcReg offset destReg |
+ offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
+ srcReg ~= ESP ifTrue:
+ [(self isQuick: offset) ifTrue:
+ [machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r10;
+ at: 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
+ at: 4 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 5].
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r10;
+ at: 3 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
+ at: 4 put: (offset bitAnd: 16rFF);
+ at: 5 put: (offset >> 8 bitAnd: 16rFF);
+ at: 6 put: (offset >> 16 bitAnd: 16rFF);
+ at: 7 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 8].
+ "ESP:"
+ (self isQuick: offset) ifTrue:
+ [machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r10;
+ at: 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
+ at: 4 put: (self s: SIB1 i: 4 b: srcReg);
+ at: 5 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 6].
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r10;
+ at: 3 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
+ at: 4 put: (self s: SIB1 i: 4 b: srcReg);
+ at: 5 put: (offset bitAnd: 16rFF);
+ at: 6 put: (offset >> 8 bitAnd: 16rFF);
+ at: 7 put: (offset >> 16 bitAnd: 16rFF);
+ at: 8 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 9!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeMoveM8rR (in category 'generate machine code') -----
+ concretizeMoveM8rR
+ "Will get inlined into concretizeAt: switch."
+ "movzwl"
+ <inline: true>
+ | srcReg offset destReg |
+ offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
+ srcReg ~= ESP ifTrue:
+ [(self isQuick: offset) ifTrue:
+ [machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rB6;
+ at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
+ at: 3 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 4].
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rB6;
+ at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
+ at: 3 put: (offset bitAnd: 16rFF);
+ at: 4 put: (offset >> 8 bitAnd: 16rFF);
+ at: 5 put: (offset >> 16 bitAnd: 16rFF);
+ at: 6 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 7].
+ "ESP:"
+ (self isQuick: offset) ifTrue:
+ [machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rB6;
+ at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
+ at: 3 put: (self s: SIB1 i: 4 b: srcReg);
+ at: 4 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 5].
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rB6;
+ at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
+ at: 3 put: (self s: SIB1 i: 4 b: srcReg);
+ at: 4 put: (offset bitAnd: 16rFF);
+ at: 5 put: (offset >> 8 bitAnd: 16rFF);
+ at: 6 put: (offset >> 16 bitAnd: 16rFF);
+ at: 7 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 8!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeMoveRdRd (in category 'generate machine code') -----
+ concretizeMoveRdRd
+ "Will get inlined into concretizeAt: switch."
+ "MOVSD"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16rF2;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r11;
+ at: 3 put: (self mod: ModReg RM: destReg RO: srcReg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeMoveRsM32r (in category 'generate machine code') -----
+ concretizeMoveRsM32r
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | srcReg offset destReg |
+ srcReg := operands at: 0.
+ offset := operands at: 1.
+ destReg := operands at: 2.
+ destReg ~= ESP ifTrue:
+ [(self isQuick: offset) ifTrue:
+ "MOVSD destReg, srcReg"
+ [machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r11;
+ at: 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ at: 4 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 5].
+ "MOVSD destReg, srcReg"
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r11;
+ at: 3 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
+ at: 4 put: (offset bitAnd: 16rFF);
+ at: 5 put: (offset >> 8 bitAnd: 16rFF);
+ at: 6 put: (offset >> 16 bitAnd: 16rFF);
+ at: 7 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 8].
+ "ESP:"
+ (self isQuick: offset) ifTrue:
+ [machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r11;
+ at: 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ at: 4 put: (self s: SIB1 i: 4 b: destReg);
+ at: 5 put: (offset bitAnd: 16rFF).
+ ^machineCodeSize := 6].
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r11;
+ at: 3 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
+ at: 4 put: (self s: SIB1 i: 4 b: destReg);
+ at: 5 put: (offset bitAnd: 16rFF);
+ at: 6 put: (offset >> 8 bitAnd: 16rFF);
+ at: 7 put: (offset >> 16 bitAnd: 16rFF);
+ at: 8 put: (offset >> 24 bitAnd: 16rFF).
+ ^machineCodeSize := 9!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeMoveRsRs (in category 'generate machine code') -----
+ concretizeMoveRsRs
+ "Will get inlined into concretizeAt: switch."
+ "MOVSS"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r11;
+ at: 3 put: (self mod: ModReg RM: destReg RO: srcReg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeNotR (in category 'generate machine code') -----
+ concretizeNotR
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | reg |
+ reg := operands at: 0.
+ machineCode
+ at: 0 put: 16rF7;
+ at: 1 put: (self mod: ModReg RM: reg RO: 2).
+ ^machineCodeSize := 2!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeREP (in category 'generate machine code') -----
+ concretizeREP
+ <inline: true>
+ machineCode at: 0 put: 16rF3.
+ ^machineCodeSize := 1!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeSEEOpRsRs: (in category 'generate machine code') -----
+ concretizeSEEOpRsRs: opCode
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | regLHS regRHS |
+ regRHS := self operands at: 0.
+ regLHS := self operands at: 1.
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: opCode;
+ at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeSignExtend16RR (in category 'generate machine code') -----
+ concretizeSignExtend16RR
+ "Will get inlined into concretizeAt: switch."
+ "movswl"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rBF;
+ at: 2 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^ machineCodeSize := 3!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeSignExtend8RR (in category 'generate machine code') -----
+ concretizeSignExtend8RR
+ "Will get inlined into concretizeAt: switch."
+ "movsbl"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rBE;
+ at: 2 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^ machineCodeSize := 3!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeSqrtRs (in category 'generate machine code') -----
+ concretizeSqrtRs
+ "Will get inlined into concretizeAt: switch."
+ "SRTSS"
+ <inline: true>
+ | reg |
+ reg := operands at: 0.
+ machineCode
+ at: 0 put: 16rF3;
+ at: 1 put: 16r0F;
+ at: 2 put: 16r51;
+ at: 3 put: (self mod: ModReg RM: reg RO: reg).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeSubbRR (in category 'generate machine code') -----
+ concretizeSubbRR
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ "Assemble the SBB instruction"
+ | regLHS regRHS |
+ regLHS := operands at: 0.
+ regRHS := operands at: 1.
+ machineCode
+ at: 0 put: 16r1B;
+ at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
+ ^machineCodeSize := 2!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeXorRdRd (in category 'generate machine code') -----
+ concretizeXorRdRd
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | regLHS regRHS |
+ regRHS := self operands at: 0.
+ regLHS := self operands at: 1.
+ machineCode
+ at: 0 put: 16r66;
+ at: 1 put: 16r0f;
+ at: 2 put: 16r57;
+ at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
+ ^machineCodeSize := 4!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeXorRsRs (in category 'generate machine code') -----
+ concretizeXorRsRs
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | regLHS regRHS |
+ regRHS := self operands at: 0.
+ regLHS := self operands at: 1.
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16r57;
+ at: 2 put: (self mod: ModReg RM: regRHS RO: regLHS).
+ ^machineCodeSize := 3!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeZeroExtend16RR (in category 'generate machine code') -----
+ concretizeZeroExtend16RR
+ "Will get inlined into concretizeAt: switch."
+ "movzwl"
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rB7;
+ at: 2 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^ machineCodeSize := 3!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeZeroExtend8RR (in category 'generate machine code') -----
+ concretizeZeroExtend8RR
+ "Will get inlined into concretizeAt: switch."
+ "movzbl"
+ <inline: true>
+ | srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
+ machineCode
+ at: 0 put: 16r0F;
+ at: 1 put: 16rB6;
+ at: 2 put: (self mod: ModReg RM: srcReg RO: destReg).
+ ^ machineCodeSize := 3!
Item was changed:
----- Method: CogIA32Compiler>>dispatchConcretize (in category 'generate machine code') -----
dispatchConcretize
"Attempt to generate concrete machine code for the instruction at address.
This is the inner dispatch of concretizeAt: actualAddress which exists only
to get around the branch size limits in the SqueakV3 (blue book derived)
bytecode set."
<returnTypeC: #void>
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^self concretizeLabel].
[AlignmentNops] -> [^self concretizeAlignmentNops].
[Fill32] -> [^self concretizeFill32].
[Nop] -> [^self concretizeNop].
"Specific Control/Data Movement"
[CDQ] -> [^self concretizeCDQ].
[IDIVR] -> [^self concretizeIDIVR].
[IMULRR] -> [^self concretizeMulRR].
[CPUID] -> [^self concretizeCPUID].
[CMPXCHGAwR] -> [^self concretizeCMPXCHGAwR].
[CMPXCHGMwrR] -> [^self concretizeCMPXCHGMwrR].
[LFENCE] -> [^self concretizeFENCE: 5].
[MFENCE] -> [^self concretizeFENCE: 6].
[SFENCE] -> [^self concretizeFENCE: 7].
[LOCK] -> [^self concretizeLOCK].
[XCHGAwR] -> [^self concretizeXCHGAwR].
[XCHGMwrR] -> [^self concretizeXCHGMwrR].
[XCHGRR] -> [^self concretizeXCHGRR].
+ [FSTPS] -> [^self concretizeFSTPS].
+ [FSTPD] -> [^self concretizeFSTPD].
"Control"
[Call] -> [^self concretizeCall].
+ [CallR] -> [^self concretizeCallR].
[CallFull] -> [^self concretizeCall].
[JumpR] -> [^self concretizeJumpR].
[JumpFull] -> [^self concretizeJumpLong].
[JumpLong] -> [^self concretizeJumpLong].
[JumpLongZero] -> [^self concretizeConditionalJump: 16r4].
[JumpLongNonZero] -> [^self concretizeConditionalJump: 16r5].
[Jump] -> [^self concretizeJump].
"Table B-1 Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture"
[JumpZero] -> [^self concretizeConditionalJump: 16r4].
[JumpNonZero] -> [^self concretizeConditionalJump: 16r5].
[JumpNegative] -> [^self concretizeConditionalJump: 16r8].
[JumpNonNegative] -> [^self concretizeConditionalJump: 16r9].
[JumpOverflow] -> [^self concretizeConditionalJump: 16r0].
[JumpNoOverflow] -> [^self concretizeConditionalJump: 16r1].
[JumpCarry] -> [^self concretizeConditionalJump: 16r2].
[JumpNoCarry] -> [^self concretizeConditionalJump: 16r3].
[JumpLess] -> [^self concretizeConditionalJump: 16rC].
[JumpGreaterOrEqual] -> [^self concretizeConditionalJump: 16rD].
[JumpGreater] -> [^self concretizeConditionalJump: 16rF].
[JumpLessOrEqual] -> [^self concretizeConditionalJump: 16rE].
[JumpBelow] -> [^self concretizeConditionalJump: 16r2].
[JumpAboveOrEqual] -> [^self concretizeConditionalJump: 16r3].
[JumpAbove] -> [^self concretizeConditionalJump: 16r7].
[JumpBelowOrEqual] -> [^self concretizeConditionalJump: 16r6].
[JumpFPEqual] -> [^self concretizeConditionalJump: 16r4].
[JumpFPNotEqual] -> [^self concretizeConditionalJump: 16r5].
[JumpFPLess] -> [^self concretizeConditionalJump: 16r2].
[JumpFPGreaterOrEqual] -> [^self concretizeConditionalJump: 16r3].
[JumpFPGreater] -> [^self concretizeConditionalJump: 16r7].
[JumpFPLessOrEqual] -> [^self concretizeConditionalJump: 16r6].
[JumpFPOrdered] -> [^self concretizeConditionalJump: 16rB].
[JumpFPUnordered] -> [^self concretizeConditionalJump: 16rA].
[RetN] -> [^self concretizeRetN].
[Stop] -> [^self concretizeStop].
"Arithmetic"
[AddCqR] -> [^self concretizeAddCqR].
[AddCwR] -> [^self concretizeAddCwR].
[AddRR] -> [^self concretizeOpRR: 16r03].
+ [AddcRR] -> [^self concretizeAddcRR].
+ [AddcCqR] -> [^self concretizeAddcCqR].
[AddRdRd] -> [^self concretizeSEE2OpRdRd: 16r58].
+ [AddRsRs] -> [^self concretizeSEEOpRsRs: 16r58].
[AndCqR] -> [^self concretizeAndCqR].
[AndCwR] -> [^self concretizeAndCwR].
[AndRR] -> [^self concretizeOpRR: 16r23].
[TstCqR] -> [^self concretizeTstCqR].
[CmpCqR] -> [^self concretizeCmpCqR].
[CmpCwR] -> [^self concretizeCmpCwR].
[CmpRR] -> [^self concretizeReverseOpRR: 16r39].
[CmpRdRd] -> [^self concretizeCmpRdRd].
+ [CmpRsRs] -> [^self concretizeCmpRsRs].
[DivRdRd] -> [^self concretizeSEE2OpRdRd: 16r5E].
+ [DivRsRs] -> [^self concretizeSEEOpRsRs: 16r5E].
[MulRdRd] -> [^self concretizeSEE2OpRdRd: 16r59].
+ [MulRsRs] -> [^self concretizeSEEOpRsRs: 16r59].
[OrCqR] -> [^self concretizeOrCqR].
[OrCwR] -> [^self concretizeOrCwR].
[OrRR] -> [^self concretizeOpRR: 16r0B].
[SubCqR] -> [^self concretizeSubCqR].
[SubCwR] -> [^self concretizeSubCwR].
[SubRR] -> [^self concretizeOpRR: 16r2B].
+ [SubbRR] -> [^self concretizeSubbRR].
[SubRdRd] -> [^self concretizeSEE2OpRdRd: 16r5C].
+ [SubRsRs] -> [^self concretizeSEEOpRsRs: 16r5C].
[SqrtRd] -> [^self concretizeSqrtRd].
+ [SqrtRs] -> [^self concretizeSqrtRs].
[XorCwR] -> [^self concretizeXorCwR].
[XorRR] -> [^self concretizeOpRR: 16r33].
[NegateR] -> [^self concretizeNegateR].
+ [NotR] -> [^self concretizeNotR].
[LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR].
[ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR].
[LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR].
[LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR].
[ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR].
[LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR].
"Data Movement"
[MoveCqR] -> [^self concretizeMoveCqR].
[MoveCwR] -> [^self concretizeMoveCwR].
[MoveRR] -> [^self concretizeReverseOpRR: 16r89].
+ [MoveRdRd] -> [^self concretizeMoveRdRd].
+ [MoveRsRs] -> [^self concretizeMoveRsRs].
[MoveAwR] -> [^self concretizeMoveAwR].
[MoveRAw] -> [^self concretizeMoveRAw].
[MoveAbR] -> [^self concretizeMoveAbR].
[MoveRAb] -> [^self concretizeMoveRAb].
[MoveMbrR] -> [^self concretizeMoveMbrR].
[MoveRMbr] -> [^self concretizeMoveRMbr].
+ [MoveRM8r] -> [^self concretizeMoveRMbr].
+ [MoveM8rR] -> [^self concretizeMoveM8rR].
[MoveM16rR] -> [^self concretizeMoveM16rR].
[MoveRM16r] -> [^self concretizeMoveRM16r].
+ [MoveM32rR] -> [^self concretizeMoveMwrR].
+ [MoveRM32r] -> [^self concretizeMoveRMwr].
+ [MoveM32rRs] -> [^self concretizeMoveM32rRs].
[MoveM64rRd] -> [^self concretizeMoveM64rRd].
[MoveMwrR] -> [^self concretizeMoveMwrR].
[MoveXbrRR] -> [^self concretizeMoveXbrRR].
[MoveRXbrR] -> [^self concretizeMoveRXbrR].
[MoveXwrRR] -> [^self concretizeMoveXwrRR].
[MoveRXwrR] -> [^self concretizeMoveRXwrR].
[MoveRMwr] -> [^self concretizeMoveRMwr].
[MoveRdM64r] -> [^self concretizeMoveRdM64r].
+ [MoveRsM32r] -> [^self concretizeMoveRsM32r].
[PopR] -> [^self concretizePopR].
[PushR] -> [^self concretizePushR].
[PushCq] -> [^self concretizePushCq].
[PushCw] -> [^self concretizePushCw].
[PrefetchAw] -> [^self concretizePrefetchAw].
"Conversion"
+ [ConvertRRd] -> [^self concretizeConvertRRd].
+ [ConvertRdR] -> [^self concretizeConvertRdR].
+
+ [ConvertRsRd] -> [^self concretizeConvertRsRd].
+ [ConvertRdRs] -> [^self concretizeConvertRdRs].
+ [ConvertRsR] -> [^self concretizeConvertRsR].
+ [ConvertRRs] -> [^self concretizeConvertRRs].
+
+ [SignExtend8RR] -> [^ self concretizeSignExtend8RR].
+ [SignExtend16RR] -> [^ self concretizeSignExtend16RR].
+ [ZeroExtend8RR] -> [^ self concretizeZeroExtend8RR].
+ [ZeroExtend16RR] -> [^ self concretizeZeroExtend16RR].
+ } otherwise: [^ self dispatchConcretize2].!
- [ConvertRRd] -> [^self concretizeConvertRRd] }!
Item was added:
+ ----- Method: CogIA32Compiler>>dispatchConcretize2 (in category 'generate machine code') -----
+ dispatchConcretize2
+ "Attempt to generate concrete machine code for the instruction at address.
+ This is the inner dispatch of concretizeAt: actualAddress which exists only
+ to get around the branch size limits in the SqueakV3 (blue book derived)
+ bytecode set."
+ <returnTypeC: #void>
+ opcode caseOf: {
+ [XorRsRs] -> [^self concretizeXorRsRs].
+ [XorRdRd] -> [^self concretizeXorRdRd].
+ [REP] -> [^self concretizeREP].
+ [CLD] -> [^self concretizeCLD].
+ [MOVSB] -> [^self concretizeMOVSB].
+ [MOVSD] -> [^self concretizeMOVSD].
+ }.!
Item was added:
+ ----- Method: CogIA32Compiler>>genMarshallNArgs:floatArg:floatArg:floatArg:floatArg: (in category 'abi') -----
+ genMarshallNArgs: numArgs floatArg: regOrConst0 floatArg: regOrConst1 floatArg: regOrConst2 floatArg: regOrConst3
+ "Generate the code to pass up to four arguments in a C run-time call. Hack: each argument is
+ either a negative number, which encodes a constant, or a non-negative number, that of a register.
+
+ Run-time calls have no more than four arguments, so chosen so that on ARM, where in its C ABI the
+ first four integer arguments are passed in registers, all arguments can be passed in registers. We
+ defer to the back end to generate this code not so much that the back end knows whether it uses
+ the stack or registers to pass arguments (it does, but...). In fact we defer for an extremely evil reason.
+ Doing so allows the x64 (where up to 6 args are passed) to assign the register arguments in an order
+ that allows some of the argument registers to be used for specific abstract registers, specifically
+ ReceiverResultReg and ClassReg. This is evil, evil, evil, but also it's really nice to keep using the old
+ register assignments the original author has grown accustomed to."
+ <inline: true>
+ numArgs = 0 ifTrue:
+ [^self].
+ numArgs > 1 ifTrue:
+ [numArgs > 2 ifTrue:
+ [numArgs > 3 ifTrue:
+ [(cogit isTrampolineArgConstant: regOrConst3)
+ ifFalse: [cogit PushRd: regOrConst3]
+ ifTrue: [cogit PushC64: (cogit trampolineArgValue: regOrConst3)]].
+ (cogit isTrampolineArgConstant: regOrConst2)
+ ifFalse: [cogit PushRd: regOrConst2]
+ ifTrue: [cogit PushC64: (cogit trampolineArgValue: regOrConst2)]].
+ (cogit isTrampolineArgConstant: regOrConst1)
+ ifFalse: [cogit PushRd: regOrConst1]
+ ifTrue: [cogit PushC64: (cogit trampolineArgValue: regOrConst1)]].
+ (cogit isTrampolineArgConstant: regOrConst0)
+ ifFalse: [cogit PushRd: regOrConst0]
+ ifTrue: [cogit PushC64: (cogit trampolineArgValue: regOrConst0)]!
Item was added:
+ ----- Method: CogIA32Compiler>>genMemCopy:to:constantSize: (in category 'abstract instructions') -----
+ genMemCopy: originalSourceReg to: originalDestReg constantSize: size
+ | numbytes numwords sourceReg destReg countReg inst |
+
+ "Get the abstract registers for ECX, EDI and ESI"
+ sourceReg := ESI.
+ destReg := EDI.
+ countReg := ECX.
+
+ "Put the source in ESI and the dest in EDI"
+ inst := cogit Label.
+ originalSourceReg ~= sourceReg ifTrue: [
+ originalDestReg = sourceReg ifTrue: [
+ cogit MoveR: originalDestReg R: TempReg.
+ ].
+ cogit MoveR: originalSourceReg R: sourceReg.
+ ].
+
+ originalDestReg ~= destReg ifTrue: [
+ originalDestReg = sourceReg ifTrue: [
+ cogit MoveR: TempReg R: destReg.
+ ] ifFalse: [
+ cogit MoveR: originalDestReg R: destReg.
+ ]
+ ].
+
+ "Store the count and clear the direction"
+ cogit gen: CLD.
+
+ "First copy the bytes"
+ numbytes := size bitAnd: 16r03.
+ numbytes > 0 ifTrue: [
+ cogit MoveCq: numbytes R: countReg.
+ cogit gen: REP.
+ cogit gen: MOVSB.
+ ].
+
+ "Now copy the words"
+ numwords := size // 4.
+ cogit MoveCq: numwords R: countReg.
+ cogit gen: REP.
+ cogit gen: MOVSD.
+
+ !
Item was added:
+ ----- Method: CogIA32Compiler>>genMemCopy:to:size: (in category 'abstract instructions') -----
+ genMemCopy: originalSourceReg to: originalDestReg size: originalSize
+ | spilledSize size sourceReg destReg countReg inst |
+
+ "Get the abstract registers for ECX, EDI and ESI"
+ sourceReg := ESI.
+ destReg := EDI.
+ countReg := ECX.
+
+ "TODO: Avoid spilling"
+ spilledSize := false.
+ (originalSize = sourceReg or: [originalSize = destReg]) ifTrue: [
+ cogit PushR: originalSize.
+ spilledSize := true.
+ ].
+
+ "Put the source in ESI and the dest in EDI"
+ inst := cogit Label.
+ originalSourceReg ~= sourceReg ifTrue: [
+ originalDestReg = sourceReg ifTrue: [
+ cogit MoveR: originalDestReg R: TempReg.
+ ].
+ cogit MoveR: originalSourceReg R: sourceReg.
+ ].
+
+ originalDestReg ~= destReg ifTrue: [
+ originalDestReg = sourceReg ifTrue: [
+ cogit MoveR: TempReg R: destReg.
+ ] ifFalse: [
+ cogit MoveR: originalDestReg R: destReg.
+ ]
+ ].
+
+ "Put the original size register in somewhere different than ECX"
+ spilledSize ifTrue: [
+ cogit PopR: TempReg.
+ size := TempReg.
+ ] ifFalse: [
+ originalSize = countReg ifTrue: [
+ cogit MoveR: originalSize R: TempReg.
+ size := TempReg.
+ ] ifFalse: [
+ size := originalSize.
+ ]
+ ].
+
+ cogit gen: CLD.
+
+ "First copy the bytes"
+ cogit MoveR: size R: countReg.
+ cogit AndCq: 16r03 R: countReg.
+ cogit gen: REP.
+ cogit gen: MOVSB.
+
+ "Now copy the words"
+ cogit MoveR: size R: countReg.
+ cogit LogicalShiftRightCq: 2 R: countReg.
+ cogit gen: REP.
+ cogit gen: MOVSD.
+
+ !
Item was added:
+ ----- Method: CogIA32Compiler>>genMoveCf32:Rs: (in category 'abstract instructions') -----
+ genMoveCf32: constantFloat32 Rs: register
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ <var: #constantFloat32 type: #float>
+ | inst |
+ inst := cogit PushCw: constantFloat32 asIEEE32BitWord.
+ cogit PopRs: register.
+ ^ inst!
Item was added:
+ ----- Method: CogIA32Compiler>>genMoveCf64:Rd: (in category 'abstract instructions') -----
+ genMoveCf64: constantFloat64 Rd: register
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ <var: #constantFloat64 type: #double>
+ | inst |
+ inst := cogit PushC64: constantFloat64 asIEEE64BitWord.
+ cogit PopRd: register.
+ ^ inst!
Item was added:
+ ----- Method: CogIA32Compiler>>genPopRd: (in category 'abstract instructions') -----
+ genPopRd: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ | inst |
+ inst := cogit MoveM64: 0 r: SPReg Rd: reg .
+ cogit AddCq: 8 R: SPReg.
+ ^ inst!
Item was added:
+ ----- Method: CogIA32Compiler>>genPopRs: (in category 'abstract instructions') -----
+ genPopRs: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ | inst |
+ inst := cogit MoveM32: 0 r: SPReg Rs: reg .
+ cogit AddCq: 4 R: SPReg.
+ ^ inst!
Item was added:
+ ----- Method: CogIA32Compiler>>genPushC64: (in category 'abstract instructions') -----
+ genPushC64: constant64Bits
+ <inline: true>
+ <var: #constant64Bits type: #sqLong>
+ <returnTypeC: #'AbstractInstruction *'>
+ | inst highPart |
+ BytesPerWord == 4 ifTrue: [
+ highPart := self cCode: '(constant64Bits >> 32ll)' inSmalltalk: [ constant64Bits bitShift: -32 ].
+ inst :=cogit PushCw: highPart.
+ cogit PushCw: (constant64Bits bitAnd: 16rFFFFFFFF).
+ ^ inst
+ ] ifFalse: [
+ ^ cogit PushCw: constant64Bits.
+ ]!
Item was added:
+ ----- Method: CogIA32Compiler>>genPushRd: (in category 'abstract instructions') -----
+ genPushRd: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ | inst |
+ inst := cogit MoveRd: reg M64: -8 r: SPReg.
+ cogit SubCq: 8 R: SPReg.
+ ^ inst!
Item was added:
+ ----- Method: CogIA32Compiler>>genPushRs: (in category 'abstract instructions') -----
+ genPushRs: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ | inst |
+ inst := cogit MoveRs: reg M32: -4 r: SPReg.
+ cogit SubCq: 4 R: SPReg.
+ ^ inst!
Item was added:
+ ----- Method: CogIA32Compiler>>genRemoveNFloatArgsFromStack: (in category 'abi') -----
+ genRemoveNFloatArgsFromStack: n
+ cogit AddCq: n * 8 R: ESP.
+ ^0!
Item was changed:
CogClass subclass: #CogObjectRepresentation
+ instanceVariableNames: 'cogit methodZone objectMemory coInterpreter ceStoreCheckTrampoline ceByteSizeOfTrampoline ceInstantiateClassTrampoline ceInstantiateClassIndexableSizeTrampoline ceFloatObjectOfTrampoline ceFloatValueOfTrampoline ceSigned64BitIntegerTrampoline ceSigned64BitValueOfTrampoline cePositive64BitIntegerTrampoline cePositive64BitValueOfTrampoline'
- instanceVariableNames: 'cogit methodZone objectMemory coInterpreter ceStoreCheckTrampoline'
classVariableNames: ''
poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogMethodConstants CogRTLOpcodes VMBasicConstants VMObjectIndices VMSqueakClassIndices VMStackFrameOffsets'
category: 'VMMaker-JIT'!
!CogObjectRepresentation commentStamp: '<historical>' prior: 0!
I am an abstract superclass for object representations whose job it is to generate abstract instructions for accessing objects. It is hoped that this level of indirection between the Cogit code generator and object access makes it easier to adapt the code generator to different garbage collectors, object representations and languages.!
Item was changed:
----- Method: CogObjectRepresentation class>>numTrampolines (in category 'accessing') -----
numTrampolines
+ ^1 "ceStoreCheckTrampoline" + (LowcodeVM ifTrue: [ 9 ] ifFalse: [ 0 ])!
- ^1 "ceStoreCheckTrampoline"!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcByteSizeOf:to: (in category 'inline primitive support') -----
+ genLcByteSizeOf: oop to: resultRegister
+ <option: #LowcodeVM>
+ "TODO: Optimize this one avoiding the trampoline"
+ oop ~= ReceiverResultReg ifTrue: [cogit MoveR: oop R: ReceiverResultReg ].
+ cogit CallRT: ceByteSizeOfTrampoline.
+
+ cogit MoveR: TempReg R: resultRegister.
+ cogit ssPushNativeRegister: resultRegister.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcFloat32:toOop: (in category 'inline primitive support') -----
+ genLcFloat32: value toOop: object
+ <option: #LowcodeVM>
+ cogit ConvertRs: value Rd: DPFPReg0.
+ cogit CallRT: ceFloatObjectOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcFloat64:toOop: (in category 'inline primitive support') -----
+ genLcFloat64: value toOop: object
+ <option: #LowcodeVM>
+ value ~= DPFPReg0 ifTrue: [ cogit MoveRd: value Rd: DPFPReg0].
+ cogit CallRT: ceFloatObjectOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcInstantiateOop: (in category 'inline primitive support') -----
+ genLcInstantiateOop: classOop
+ <option: #LowcodeVM>
+ classOop ~= ReceiverResultReg ifTrue: [cogit MoveR: classOop R: ReceiverResultReg].
+ cogit CallRT: ceInstantiateClassTrampoline.
+
+ cogit MoveR: TempReg R: classOop.
+ cogit ssPushRegister: classOop.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcInstantiateOop:constantIndexableSize: (in category 'inline primitive support') -----
+ genLcInstantiateOop: classOop constantIndexableSize: indexableSize
+ <option: #LowcodeVM>
+ classOop ~= ReceiverResultReg ifTrue: [cogit MoveR: classOop R: ReceiverResultReg].
+ cogit MoveCq: indexableSize R: Arg0Reg.
+ cogit CallRT: ceInstantiateClassIndexableSizeTrampoline.
+
+ cogit MoveR: TempReg R: classOop.
+ cogit ssPushRegister: classOop.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcInstantiateOop:indexableSize: (in category 'inline primitive support') -----
+ genLcInstantiateOop: classOop indexableSize: indexableSize
+ <option: #LowcodeVM>
+ classOop ~= ReceiverResultReg ifTrue: [
+ indexableSize = ReceiverResultReg ifTrue: [
+ cogit MoveR: indexableSize R: TempReg.
+ ].
+ cogit MoveR: classOop R: ReceiverResultReg
+ ].
+
+ indexableSize ~= Arg0Reg ifTrue: [
+ indexableSize = ReceiverResultReg ifTrue: [
+ cogit MoveR: TempReg R: Arg0Reg.
+ ] ifFalse: [
+ cogit MoveR: indexableSize R: Arg0Reg.
+ ]
+ ].
+
+ cogit CallRT: ceInstantiateClassIndexableSizeTrampoline.
+
+ cogit MoveR: TempReg R: classOop.
+ cogit ssPushRegister: classOop.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcInt64ToOop: (in category 'inline primitive support') -----
+ genLcInt64ToOop: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: ceSigned64BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcInt64ToOop:highPart: (in category 'inline primitive support') -----
+ genLcInt64ToOop: valueLow highPart: valueHigh
+ <option: #LowcodeVM>
+ "Put the arguments in the correct registers"
+ valueLow ~= ReceiverResultReg ifTrue: [
+ valueHigh = ReceiverResultReg ifTrue: [
+ cogit MoveR: valueHigh R: TempReg.
+ ].
+ cogit MoveR: valueLow R: ReceiverResultReg.
+ ].
+
+ valueHigh ~= Arg0Reg ifTrue: [
+ valueHigh = ReceiverResultReg ifTrue: [
+ cogit MoveR: TempReg R: Arg0Reg.
+ ] ifFalse: [
+ cogit MoveR: valueHigh R: Arg0Reg.
+ ]
+ ].
+
+ "Call the trampoline"
+ cogit CallRT: ceSigned64BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcOop:toFloat32: (in category 'inline primitive support') -----
+ genLcOop: object toFloat32: value
+ <option: #LowcodeVM>
+ object ~= ReceiverResultReg ifTrue: [ cogit MoveR: object R: ReceiverResultReg].
+ cogit CallRT: ceFloatValueOfTrampoline.
+
+ cogit ConvertRd: DPFPReg0 Rs: value.
+ cogit ssPushNativeRegisterSingleFloat: value.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcOop:toFloat64: (in category 'inline primitive support') -----
+ genLcOop: object toFloat64: value
+ <option: #LowcodeVM>
+ object ~= ReceiverResultReg ifTrue: [ cogit MoveR: object R: ReceiverResultReg].
+ cogit CallRT: ceFloatValueOfTrampoline.
+
+ DPFPReg0 ~= value ifTrue: [cogit MoveRd: DPFPReg0 Rd: value.].
+ cogit ssPushNativeRegisterDoubleFloat: value.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcOop:toInt64:highPart: (in category 'inline primitive support') -----
+ genLcOop: object toInt64: valueLow highPart: valueHigh
+ <option: #LowcodeVM>
+ object ~= ReceiverResultReg ifTrue: [ cogit MoveR: object R: ReceiverResultReg.].
+ cogit CallRT: ceSigned64BitValueOfTrampoline.
+
+ Arg0Reg ~= valueHigh ifTrue: [cogit MoveR: Arg0Reg R: valueHigh].
+ cogit MoveR: TempReg R: valueLow.
+
+ cogit ssPushNativeRegister: valueLow secondRegister: valueHigh.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcOop:toUInt64:highPart: (in category 'inline primitive support') -----
+ genLcOop: object toUInt64: valueLow highPart: valueHigh
+ <option: #LowcodeVM>
+ object ~= ReceiverResultReg ifTrue: [ cogit MoveR: object R: ReceiverResultReg.].
+ cogit CallRT: cePositive64BitValueOfTrampoline.
+
+ Arg0Reg ~= valueHigh ifTrue: [cogit MoveR: Arg0Reg R: valueHigh].
+ cogit MoveR: TempReg R: valueLow.
+
+ cogit ssPushNativeRegister: valueLow secondRegister: valueHigh.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcOopToInt64: (in category 'inline primitive support') -----
+ genLcOopToInt64: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: ceSigned64BitValueOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushNativeRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcOopToPointer: (in category 'inline primitive support') -----
+ genLcOopToPointer: object
+ <option: #LowcodeVM>
+ "Assume this is always correct"
+ cogit MoveMw: BaseHeaderSize r: object R: object.
+ cogit ssPushNativeRegister: object.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcOopToUInt64: (in category 'inline primitive support') -----
+ genLcOopToUInt64: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: cePositive64BitValueOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushNativeRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcPointerToOop:class: (in category 'inline primitive support') -----
+ genLcPointerToOop: pointer class: pointerClass
+ <option: #LowcodeVM>
+ cogit PushR: pointer.
+ cogit annotate: (cogit MoveCw: pointerClass R: ReceiverResultReg) objRef: pointerClass.
+ cogit MoveCq: BytesPerOop R: Arg0Reg.
+ cogit CallRT: ceInstantiateClassIndexableSizeTrampoline.
+
+ cogit PopR: pointer.
+ cogit MoveR: pointer Mw: BaseHeaderSize r: TempReg.
+
+ cogit MoveR: TempReg R: pointer.
+ cogit ssPushRegister: pointer.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcUInt64ToOop: (in category 'inline primitive support') -----
+ genLcUInt64ToOop: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: cePositive64BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>genLcUInt64ToOop:highPart: (in category 'inline primitive support') -----
+ genLcUInt64ToOop: valueLow highPart: valueHigh
+ <option: #LowcodeVM>
+ "Put the arguments in the correct registers"
+ valueLow ~= ReceiverResultReg ifTrue: [
+ valueHigh = ReceiverResultReg ifTrue: [
+ cogit MoveR: valueHigh R: TempReg.
+ ].
+ cogit MoveR: valueLow R: ReceiverResultReg.
+ ].
+
+ valueHigh ~= Arg0Reg ifTrue: [
+ valueHigh = ReceiverResultReg ifTrue: [
+ cogit MoveR: TempReg R: Arg0Reg.
+ ] ifFalse: [
+ cogit MoveR: valueHigh R: Arg0Reg.
+ ]
+ ].
+
+ "Call the trampoline"
+ cogit CallRT: cePositive64BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentation>>generateLowcodeObjectTrampolines (in category 'initialization') -----
+ generateLowcodeObjectTrampolines
+ ceFloatObjectOfTrampoline := cogit genTrampolineFor: #floatObjectOf:
+ called: 'ceFloatObjectOfTrampoline'
+ floatArg: DPFPReg0
+ result: TempReg.
+ ceFloatValueOfTrampoline := cogit genTrampolineFor: #floatValueOf:
+ called: 'ceFloatValueOfTrampoline'
+ arg: ReceiverResultReg
+ floatResult: DPFPReg0.
+ ceInstantiateClassIndexableSizeTrampoline := cogit genTrampolineFor: #instantiateClass:indexableSize:
+ called: 'ceInstantiateClassIndexableSizeTrampoline'
+ arg: ReceiverResultReg
+ arg: Arg0Reg
+ result: TempReg.
+ ceInstantiateClassTrampoline := cogit genTrampolineFor: #instantiateClass:indexableSize:
+ called: 'ceInstantiateClassTrampoline'
+ arg: ReceiverResultReg
+ arg: 0
+ result: TempReg.
+ ceByteSizeOfTrampoline := cogit genTrampolineFor: #byteSizeOf:
+ called: 'ceByteSizeOfTrampoline'
+ arg: ReceiverResultReg
+ arg: Arg0Reg
+ result: TempReg.
+ BytesPerOop = 4 ifTrue: [
+ cePositive64BitIntegerTrampoline := cogit genTrampolineFor: #positive64BitIntegerFor:
+ called: 'cePositive64BitIntegerTrampoline'
+ arg: ReceiverResultReg
+ arg: Arg0Reg
+ result: TempReg.
+ cePositive64BitValueOfTrampoline := cogit genTrampolineFor: #positive64BitValueOf:
+ called: 'cePositive64BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg
+ result: Arg0Reg.
+ ceSigned64BitIntegerTrampoline := cogit genTrampolineFor: #signed64BitIntegerFor:
+ called: 'ceSigned64BitIntegerTrampoline'
+ arg: ReceiverResultReg
+ arg: Arg0Reg
+ result: TempReg.
+ ceSigned64BitValueOfTrampoline := cogit genTrampolineFor: #signed64BitValueOf:
+ called: 'ceSigned64BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg
+ result: Arg0Reg.
+ ] ifFalse: [
+ cePositive64BitIntegerTrampoline := cogit genTrampolineFor: #positive64BitIntegerFor:
+ called: 'cePositive64BitIntegerTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ cePositive64BitValueOfTrampoline := cogit genTrampolineFor: #positive64BitValueOf:
+ called: 'cePositive64BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ceSigned64BitIntegerTrampoline := cogit genTrampolineFor: #signed64BitIntegerFor:
+ called: 'ceSigned64BitIntegerTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ceSigned64BitValueOfTrampoline := cogit genTrampolineFor: #signed64BitValueOf:
+ called: 'ceSigned64BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ]!
Item was changed:
CogObjectRepresentationForSpur subclass: #CogObjectRepresentationFor32BitSpur
+ instanceVariableNames: 'ceSigned32BitIntegerTrampoline ceSigned32BitValueOfTrampoline cePositive32BitValueOfTrampoline cePositive32BitIntegerTrampoline'
- instanceVariableNames: ''
classVariableNames: ''
poolDictionaries: ''
category: 'VMMaker-JIT'!
Item was added:
+ ----- Method: CogObjectRepresentationFor32BitSpur class>>numTrampolines (in category 'accessing') -----
+ numTrampolines
+ ^ super numTrampolines + 4 "lowcode"!
Item was added:
+ ----- Method: CogObjectRepresentationFor32BitSpur>>genLcInt32ToOop: (in category 'inline primitive support') -----
+ genLcInt32ToOop: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: ceSigned32BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentationFor32BitSpur>>genLcOopToInt32: (in category 'inline primitive support') -----
+ genLcOopToInt32: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: ceSigned32BitValueOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushNativeRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentationFor32BitSpur>>genLcOopToUInt32: (in category 'inline primitive support') -----
+ genLcOopToUInt32: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: cePositive32BitValueOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushNativeRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentationFor32BitSpur>>genLcUInt32ToOop: (in category 'inline primitive support') -----
+ genLcUInt32ToOop: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: cePositive32BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentationFor32BitSpur>>generateLowcodeObjectTrampolines (in category 'initialization') -----
+ generateLowcodeObjectTrampolines
+ super generateLowcodeObjectTrampolines.
+ cePositive32BitIntegerTrampoline := cogit genTrampolineFor: #positive32BitIntegerFor:
+ called: 'cePositive32BitIntegerTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ cePositive32BitValueOfTrampoline := cogit genTrampolineFor: #positive32BitValueOf:
+ called: 'cePositive32BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ceSigned32BitIntegerTrampoline := cogit genTrampolineFor: #signed32BitIntegerFor:
+ called: 'ceSigned32BitIntegerTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ceSigned32BitValueOfTrampoline := cogit genTrampolineFor: #signed32BitValueOf:
+ called: 'ceSigned32BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcFirstFieldPointer: (in category 'inline primitive support') -----
+ genLcFirstFieldPointer: objectReg
+ <option: #LowcodeVM>
+ cogit AddCq: 8 R: objectReg.
+ cogit ssPushNativeRegister: objectReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcFirstIndexableFieldPointer: (in category 'inline primitive support') -----
+ genLcFirstIndexableFieldPointer: objectReg
+ <option: #LowcodeVM>
+ "TODO: Retrieve the number of fixed fields."
+ cogit AddCq: 8 R: objectReg.
+ cogit ssPushNativeRegister: objectReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcIsBytes:to: (in category 'inline primitive support') -----
+ genLcIsBytes: objectReg to: valueReg
+ <option: #LowcodeVM>
+
+ "Check for integer"
+ | isImmediate isNotBytes isCompiledMethod cont falseTarget |
+ cogit MoveR: objectReg R: valueReg.
+ cogit AndCq: objectMemory tagMask R: valueReg.
+ isImmediate := cogit JumpNonZero: 0.
+
+ "Get the format"
+ self genGetFormatOf: objectReg into: valueReg.
+
+ cogit CmpCq: objectMemory firstByteFormat R: valueReg.
+ isNotBytes := cogit JumpLess: 0.
+ cogit CmpCq: objectMemory firstCompiledMethodFormat R: valueReg.
+ isCompiledMethod := cogit JumpGreaterOrEqual: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isImmediate jmpTarget: falseTarget.
+ isNotBytes jmpTarget: falseTarget.
+ isCompiledMethod jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcIsFloatObject:to: (in category 'inline primitive support') -----
+ genLcIsFloatObject: objectReg to: valueReg
+ <option: #LowcodeVM>
+ "TODO: Implement this one"
+ cogit MoveCq: 1 R: valueReg.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcIsIndexable:to: (in category 'inline primitive support') -----
+ genLcIsIndexable: objectReg to: valueReg
+ <option: #LowcodeVM>
+ "TODO: Implement this one"
+ cogit MoveCq: 1 R: valueReg.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcIsIntegerObject:to: (in category 'inline primitive support') -----
+ genLcIsIntegerObject: objectReg to: valueReg
+ <option: #LowcodeVM>
+
+ "Check for the immediate case"
+ | isImmediate isLargePositiveInteger isLargeNegativeInteger falseResult trueResult cont |
+ cogit MoveR: objectReg R: valueReg.
+ cogit AndCq: objectMemory smallIntegerTag R: valueReg.
+ isImmediate := cogit JumpNonZero: 0.
+
+ "Check the non-immediate case"
+ self genGetClassIndexOfNonImm: objectReg into: TempReg.
+ cogit CmpCq: ClassLargePositiveInteger R: TempReg.
+ isLargePositiveInteger := cogit JumpNonZero: 0.
+ cogit CmpCq: ClassLargeNegativeInteger R: TempReg.
+ isLargeNegativeInteger := cogit JumpNonZero: 0.
+ cogit XorR: valueReg R: valueReg.
+ falseResult := cogit Jump: 0.
+
+ "True result"
+ trueResult := cogit Label.
+ isLargePositiveInteger jmpTarget: trueResult.
+ isLargeNegativeInteger jmpTarget: trueResult.
+ cogit MoveCq: 1 R: valueReg.
+
+ "Return"
+ cont := cogit Label.
+ falseResult jmpTarget: cont.
+ isImmediate jmpTarget: cont.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcIsPointers:to: (in category 'inline primitive support') -----
+ genLcIsPointers: objectReg to: valueReg
+ <option: #LowcodeVM>
+
+ "Check for immediate"
+ | isImmediate isNotPointers cont falseTarget |
+ cogit MoveR: objectReg R: valueReg.
+ cogit AndCq: objectMemory tagMask R: valueReg.
+ isImmediate := cogit JumpNonZero: 0.
+
+ "Get the format"
+ self genGetFormatOf: objectReg into: valueReg.
+
+ cogit CmpCq: 9 R: valueReg.
+ isNotPointers := cogit JumpGreaterOrEqual: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isImmediate jmpTarget: falseTarget.
+ isNotPointers jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcIsWords:to: (in category 'inline primitive support') -----
+ genLcIsWords: objectReg to: valueReg
+ <option: #LowcodeVM>
+
+ "Check for immediate"
+ | isImmediate isNotWords cont falseTarget isBelowRange isAboveRange |
+ cogit MoveR: objectReg R: valueReg.
+ cogit AndCq: objectMemory tagMask R: valueReg.
+ isImmediate := cogit JumpNonZero: 0.
+
+ "Get the format"
+ self genGetFormatOf: objectReg into: valueReg.
+
+ "Hack: consider a compiled method as bytes too."
+ BytesPerWord = 8 ifTrue: [
+ cogit CmpCq: objectMemory firstLongFormat firs R: valueReg.
+ isBelowRange := cogit JumpLess: 0.
+ cogit CmpCq: objectMemory firstShortFormat R: valueReg.
+ isAboveRange := cogit JumpGreaterOrEqual: 0.
+ ] ifFalse: [
+ cogit CmpCq: objectMemory firstLongFormat R: valueReg.
+ isNotWords := cogit JumpNonZero: 0.
+ ].
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isImmediate jmpTarget: falseTarget.
+ BytesPerWord = 4 ifTrue: [
+ isNotWords jmpTarget: falseTarget.
+ ] ifFalse: [
+ isBelowRange jmpTarget: falseTarget.
+ isAboveRange jmpTarget: falseTarget.
+ ].
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcIsWordsOrBytes:to: (in category 'inline primitive support') -----
+ genLcIsWordsOrBytes: objectReg to: valueReg
+ <option: #LowcodeVM>
+
+ "Check for immediate"
+ | isImmediate isNotBits isCompiledMethod cont falseTarget |
+ cogit MoveR: objectReg R: valueReg.
+ cogit AndCq: objectMemory tagMask R: valueReg.
+ isImmediate := cogit JumpNonZero: 0.
+
+ "Get the format"
+ self genGetFormatOf: objectReg into: valueReg.
+
+ cogit CmpCq: 9 R: valueReg.
+ isNotBits := cogit JumpLess: 0.
+ cogit CmpCq: 24 R: valueReg.
+ isCompiledMethod := cogit JumpGreaterOrEqual: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isImmediate jmpTarget: falseTarget.
+ isNotBits jmpTarget: falseTarget.
+ isCompiledMethod jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcLoadObject:at: (in category 'inline primitive support') -----
+ genLcLoadObject: object at: fieldIndex
+ <option: #LowcodeVM>
+ cogit AddCq: 8 R: object.
+ cogit MoveXwr: fieldIndex R: object R: object.
+ cogit ssPushRegister: object!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcLoadObject:field: (in category 'inline primitive support') -----
+ genLcLoadObject: object field: fieldIndex
+ <option: #LowcodeVM>
+ cogit MoveMw: 8 + (BytesPerOop*fieldIndex) r: object R: object.
+ cogit ssPushRegister: object!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcStore:object:at: (in category 'inline primitive support') -----
+ genLcStore: value object: object at: fieldIndex
+ <option: #LowcodeVM>
+ cogit AddCq: 8 R: object.
+ cogit MoveR: value Xwr: fieldIndex R: object.!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genLcStore:object:field: (in category 'inline primitive support') -----
+ genLcStore: value object: object field: fieldIndex
+ <option: #LowcodeVM>
+ cogit MoveR: value Mw: 8 + (fieldIndex * BytesPerOop) r: object.!
Item was changed:
----- Method: CogObjectRepresentationForSpur>>generateObjectRepresentationTrampolines (in category 'initialization') -----
generateObjectRepresentationTrampolines
"Do the store check. Answer the argument for the benefit of the code generator;
ReceiverResultReg may be caller-saved and hence smashed by this call. Answering
it allows the code generator to reload ReceiverResultReg cheaply.
In Spur the only thing we leave to the run-time is adding the receiver to the
remembered set and setting its isRemembered bit."
self
cppIf: IMMUTABILITY
ifTrue:
[self cCode: [] inSmalltalk:
[ceStoreTrampolines := CArrayAccessor on: (Array new: NumStoreTrampolines)].
0 to: NumStoreTrampolines - 1 do:
[:instVarIndex |
ceStoreTrampolines
at: instVarIndex
put: (self
genStoreTrampolineCalled: (cogit
trampolineName: 'ceStoreTrampoline'
numArgs: instVarIndex
limit: NumStoreTrampolines - 2)
instVarIndex: instVarIndex)]].
ceStoreCheckTrampoline := self genStoreCheckTrampoline.
ceStoreCheckContextReceiverTrampoline := self genStoreCheckContextReceiverTrampoline.
ceScheduleScavengeTrampoline := cogit
genTrampolineFor: #ceScheduleScavenge
called: 'ceScheduleScavengeTrampoline'
regsToSave: CallerSavedRegisterMask.
ceSmallActiveContextInMethodTrampoline := self genActiveContextTrampolineLarge: false inBlock: 0 called: 'ceSmallMethodContext'.
ceSmallActiveContextInBlockTrampoline := self genActiveContextTrampolineLarge: false inBlock: InVanillaBlock called: 'ceSmallBlockContext'.
SistaV1BytecodeSet ifTrue:
[ceSmallActiveContextInFullBlockTrampoline := self genActiveContextTrampolineLarge: false inBlock: InFullBlock called: 'ceSmallFullBlockContext'].
ceLargeActiveContextInMethodTrampoline := self genActiveContextTrampolineLarge: true inBlock: 0 called: 'ceLargeMethodContext'.
ceLargeActiveContextInBlockTrampoline := self genActiveContextTrampolineLarge: true inBlock: InVanillaBlock called: 'ceLargeBlockContext'.
SistaV1BytecodeSet ifTrue:
+ [ceLargeActiveContextInFullBlockTrampoline := self genActiveContextTrampolineLarge: true inBlock: InFullBlock called: 'ceLargeFullBlockContext'].
+
+ self cppIf: LowcodeVM ifTrue: [ self generateLowcodeObjectTrampolines ]!
- [ceLargeActiveContextInFullBlockTrampoline := self genActiveContextTrampolineLarge: true inBlock: InFullBlock called: 'ceLargeFullBlockContext']!
Item was changed:
CogObjectRepresentation subclass: #CogObjectRepresentationForSqueakV3
+ instanceVariableNames: 'ceCreateNewArrayTrampoline cePositive32BitIntegerTrampoline ceActiveContextTrampoline ceClosureCopyTrampoline ceSigned32BitIntegerTrampoline ceSigned32BitValueOfTrampoline cePositive32BitValueOfTrampoline'
- instanceVariableNames: 'ceCreateNewArrayTrampoline cePositive32BitIntegerTrampoline ceActiveContextTrampoline ceClosureCopyTrampoline'
classVariableNames: 'RootBitDigitLength'
poolDictionaries: 'VMSqueakClassIndices VMSqueakV3ObjectRepresentationConstants'
category: 'VMMaker-JIT'!
!CogObjectRepresentationForSqueakV3 commentStamp: '<historical>' prior: 0!
Read my superclass' class comment. I am a CogObjectRepresentation for the Squeak V3 object representation.!
Item was changed:
----- Method: CogObjectRepresentationForSqueakV3 class>>numTrampolines (in category 'accessing') -----
numTrampolines
+ ^super numTrampolines + 4 + (LowcodeVM ifTrue: [ 3 ] ifFalse: [ 0 ])!
- ^super numTrampolines + 4!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genGetNumSlotsOf:into: (in category 'compile abstract instructions') -----
+ genGetNumSlotsOf: srcRegister into: destRegister!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcFirstFieldPointer: (in category 'inline primitive support') -----
+ genLcFirstFieldPointer: objectReg
+ <option: #LowcodeVM>
+ cogit AddCq: 4 R: objectReg.
+ cogit ssPushNativeRegister: objectReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcFirstIndexableFieldPointer: (in category 'inline primitive support') -----
+ genLcFirstIndexableFieldPointer: objectReg
+ <option: #LowcodeVM>
+ "TODO: Fixme for fixed fields"
+ cogit AddCq: 4 R: objectReg.
+ cogit ssPushNativeRegister: objectReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcInt32ToOop: (in category 'inline primitive support') -----
+ genLcInt32ToOop: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: ceSigned32BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcIsBytes:to: (in category 'inline primitive support') -----
+ genLcIsBytes: objectReg to: valueReg
+ <option: #LowcodeVM>
+ | isInteger isNotBytes falseTarget cont |
+
+ "Check for integer"
+ cogit MoveR: objectReg R: TempReg.
+ cogit AndCq: 1 R: TempReg.
+ isInteger := cogit JumpNonZero: 0.
+
+ "Get the class format"
+ self genGetClassFormatOfNonInt: objectReg into: valueReg scratchReg: TempReg.
+
+ "Hack: consider a compiled method as bytes too."
+ cogit CmpCq: 8 R: valueReg.
+ isNotBytes := cogit JumpLess: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isInteger jmpTarget: falseTarget.
+ isNotBytes jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcIsFloatObject:to: (in category 'inline primitive support') -----
+ genLcIsFloatObject: objectReg to: valueReg
+ <option: #LowcodeVM>
+ "TODO: Implement this one"
+ cogit MoveCq: 1 R: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcIsIndexable:to: (in category 'inline primitive support') -----
+ genLcIsIndexable: objectReg to: valueReg
+ <option: #LowcodeVM>
+ | isInteger isNotIndexable falseTarget cont |
+
+ "Check for integer"
+ cogit MoveR: objectReg R: TempReg.
+ cogit AndCq: 1 R: TempReg.
+ isInteger := cogit JumpNonZero: 0.
+
+ "Get the class format"
+ self genGetClassFormatOfNonInt: objectReg into: valueReg scratchReg: TempReg.
+
+ "Hack: consider a compiled method as bytes too."
+ cogit CmpCq: 2 R: valueReg.
+ isNotIndexable := cogit JumpLess: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isInteger jmpTarget: falseTarget.
+ isNotIndexable jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcIsIntegerObject:to: (in category 'inline primitive support') -----
+ genLcIsIntegerObject: objectReg to: valueReg
+ <option: #LowcodeVM>
+ "TODO: Support larger integers"
+ cogit AndCq: 1 R: objectReg.
+ cogit ssPushNativeRegister: objectReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcIsPointers:to: (in category 'inline primitive support') -----
+ genLcIsPointers: objectReg to: valueReg
+ <option: #LowcodeVM>
+ | isInteger isNotIndexable falseTarget cont |
+
+ "Check for integer"
+ cogit MoveR: objectReg R: TempReg.
+ cogit AndCq: 1 R: TempReg.
+ isInteger := cogit JumpNonZero: 0.
+
+ "Get the class format"
+ self genGetClassFormatOfNonInt: objectReg into: valueReg scratchReg: TempReg.
+
+ "Hack: consider a compiled method as bytes too."
+ cogit CmpCq: 3 R: valueReg.
+ isNotIndexable := cogit JumpGreater: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isInteger jmpTarget: falseTarget.
+ isNotIndexable jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcIsWords:to: (in category 'inline primitive support') -----
+ genLcIsWords: objectReg to: valueReg
+ <option: #LowcodeVM>
+ | isInteger isNotWords falseTarget cont |
+
+ "Check for integer"
+ cogit MoveR: objectReg R: TempReg.
+ cogit AndCq: 1 R: TempReg.
+ isInteger := cogit JumpNonZero: 0.
+
+ "Get the class format"
+ self genGetClassFormatOfNonInt: objectReg into: valueReg scratchReg: TempReg.
+
+ "Check for the words format"
+ cogit CmpCq: 6 R: valueReg.
+ isNotWords := cogit JumpNonZero: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isInteger jmpTarget: falseTarget.
+ isNotWords jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcIsWordsOrBytes:to: (in category 'inline primitive support') -----
+ genLcIsWordsOrBytes: objectReg to: valueReg
+ <option: #LowcodeVM>
+ | isInteger isNotBytes falseTarget cont |
+
+ "Check for integer"
+ cogit MoveR: objectReg R: TempReg.
+ cogit AndCq: 1 R: TempReg.
+ isInteger := cogit JumpNonZero: 0.
+
+ "Get the class format"
+ self genGetClassFormatOfNonInt: objectReg into: valueReg scratchReg: TempReg.
+
+ "Hack: consider a compiled method as bytes too."
+ cogit CmpCq: 6 R: valueReg.
+ isNotBytes := cogit JumpLess: 0.
+
+ "True result"
+ cogit MoveCq: 1 R: valueReg.
+ cont := cogit Jump: 0.
+
+ "False result"
+ falseTarget := cogit Label.
+ isInteger jmpTarget: falseTarget.
+ isNotBytes jmpTarget: falseTarget.
+ cogit MoveCq: 0 R: valueReg.
+
+ "Return"
+ cont jmpTarget: cogit Label.
+ cogit ssPushNativeRegister: valueReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcLoadObject:at: (in category 'inline primitive support') -----
+ genLcLoadObject: object at: fieldIndex
+ <option: #LowcodeVM>
+ cogit AddCq: 1 R: fieldIndex.
+ cogit MoveXwr: fieldIndex R: object R: object.
+ cogit ssPushRegister: object!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcLoadObject:field: (in category 'inline primitive support') -----
+ genLcLoadObject: object field: fieldIndex
+ <option: #LowcodeVM>
+ cogit MoveMw: (fieldIndex+ 1) * BytesPerWord r: object R: object.
+ cogit ssPushRegister: object!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcOopToInt32: (in category 'inline primitive support') -----
+ genLcOopToInt32: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: ceSigned32BitValueOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushNativeRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcOopToUInt32: (in category 'inline primitive support') -----
+ genLcOopToUInt32: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: cePositive32BitValueOfTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushNativeRegister: ReceiverResultReg.!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcStore:object:at: (in category 'inline primitive support') -----
+ genLcStore: value object: object at: fieldIndex
+ <option: #LowcodeVM>
+ cogit AddCq: 1 R: fieldIndex.
+ cogit MoveR: value Xwr: fieldIndex R: object!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcStore:object:field: (in category 'inline primitive support') -----
+ genLcStore: value object: object field: fieldIndex
+ <option: #LowcodeVM>
+ cogit MoveR: value Mw: (fieldIndex+ 1) * BytesPerWord r: object!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genLcUInt32ToOop: (in category 'inline primitive support') -----
+ genLcUInt32ToOop: value
+ <option: #LowcodeVM>
+ value ~= ReceiverResultReg ifTrue: [ cogit MoveR: value R: ReceiverResultReg.].
+ cogit CallRT: cePositive32BitIntegerTrampoline.
+
+ cogit MoveR: TempReg R: ReceiverResultReg.
+ cogit ssPushRegister: ReceiverResultReg.!
Item was changed:
----- Method: CogObjectRepresentationForSqueakV3>>generateObjectRepresentationTrampolines (in category 'initialization') -----
generateObjectRepresentationTrampolines
"Do the store check. Answer the argument for the benefit of the code generator;
ReceiverResultReg may be caller-saved and hence smashed by this call. Answering
it allows the code generator to reload ReceiverResultReg cheaply."
ceStoreCheckTrampoline := cogit
genTrampolineFor: #ceStoreCheck:
called: 'ceStoreCheckTrampoline'
arg: ReceiverResultReg
regsToSave: (CallerSavedRegisterMask bitClear: (cogit registerMaskFor: ReceiverResultReg))
result: cogit returnRegForStoreCheck.
ceCreateNewArrayTrampoline := cogit genTrampolineFor: #ceNewArraySlotSize:
called: 'ceCreateNewArrayTrampoline'
arg: SendNumArgsReg
regsToSave: (CallerSavedRegisterMask bitClear: (cogit registerMaskFor: ReceiverResultReg))
result: ReceiverResultReg.
cePositive32BitIntegerTrampoline := cogit genTrampolineFor: #positive32BitIntegerFor:
called: 'cePositive32BitIntegerTrampoline'
arg: ReceiverResultReg
regsToSave: (CallerSavedRegisterMask bitClear: (cogit registerMaskFor: ReceiverResultReg))
result: TempReg.
ceActiveContextTrampoline := self genActiveContextTrampoline.
ceClosureCopyTrampoline := cogit genTrampolineFor: #ceClosureCopyDescriptor:
called: 'ceClosureCopyTrampoline'
arg: SendNumArgsReg
regsToSave: (CallerSavedRegisterMask bitClear: (cogit registerMaskFor: ReceiverResultReg))
+ result: ReceiverResultReg.
+
+ self cppIf: LowcodeVM ifTrue: [
+ cePositive32BitValueOfTrampoline := cogit genTrampolineFor: #positive32BitValueOf:
+ called: 'cePositive32BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ceSigned32BitIntegerTrampoline := cogit genTrampolineFor: #signed32BitIntegerFor:
+ called: 'ceSigned32BitIntegerTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ceSigned32BitValueOfTrampoline := cogit genTrampolineFor: #signed32BitValueOf:
+ called: 'ceSigned32BitValueOfTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+
+ self generateLowcodeObjectTrampolines
+ ]!
- result: ReceiverResultReg!
Item was changed:
SharedPool subclass: #CogRTLOpcodes
instanceVariableNames: ''
+ classVariableNames: 'AddCqR AddCwR AddRR AddRdRd AddRsRs AddcCqR AddcRR AlignmentNops AndCqR AndCqRR AndCwR AndRR ArithmeticShiftRightCqR ArithmeticShiftRightRR Call CallFull CallR CmpC32R CmpCqR CmpCwR CmpRR CmpRdRd CmpRsRs ConvertRRd ConvertRRs ConvertRdR ConvertRdRs ConvertRsR ConvertRsRd DivRdRd DivRsRs Fill32 FirstJump FirstShortJump Jump JumpAbove JumpAboveOrEqual JumpBelow JumpBelowOrEqual JumpCarry JumpFPEqual JumpFPGreater JumpFPGreaterOrEqual JumpFPLess JumpFPLessOrEqual JumpFPNotEqual JumpFPOrdered JumpFPUnordered JumpFull JumpGreater JumpGreaterOrEqual JumpLess JumpLessOrEqual JumpLong JumpLongNonZero JumpLongZero JumpNegative JumpNoCarry JumpNoOverflow JumpNonNegative JumpNonZero JumpOverflow JumpR JumpZero Label LastJump LastRTLCode Literal LoadEffectiveAddressMwrR LoadEffectiveAddressXowrR LogicalShiftLeftCqR LogicalShiftLeftRR LogicalShiftRightCqR LogicalShiftRightRR MoveA32R MoveAbR MoveAwR MoveC32R MoveC64R MoveCqR MoveCwR MoveM16rR MoveM32rR MoveM32rRs MoveM64rRd MoveM8rR MoveMbrR MoveMs8rR MoveMwrR MoveRA32 MoveRAb MoveRAw MoveRM16r MoveRM32r MoveRM8r MoveRMbr MoveRMwr MoveRR MoveRRd MoveRX16rR MoveRX32rR MoveRXbrR MoveRXowr MoveRXwrR MoveRdM64r MoveRdR MoveRdRd MoveRsM32r MoveRsRs MoveX16rRR MoveX32rRR MoveXbrRR MoveXowrR MoveXwrRR MulRdRd MulRsRs NegateR Nop NotR OrCqR OrCwR OrRR PopR PrefetchAw PushCq PushCw PushR RetN RotateLeftCqR RotateRightCqR SignExtend16RR SignExtend8RR SqrtRd SqrtRs Stop SubCqR SubCwR SubRR SubRdRd SubRsRs SubbRR TstCqR XorCqR XorCwR XorRR XorRdRd XorRsRs ZeroExtend16RR ZeroExtend8RR'
- classVariableNames: 'AddCqR AddCwR AddRR AddRdRd AlignmentNops AndCqR AndCqRR AndCwR AndRR ArithmeticShiftRightCqR ArithmeticShiftRightRR Call CallFull CmpC32R CmpCqR CmpCwR CmpRR CmpRdRd ConvertRRd DivRdRd Fill32 FirstJump FirstShortJump Jump JumpAbove JumpAboveOrEqual JumpBelow JumpBelowOrEqual JumpCarry JumpFPEqual JumpFPGreater JumpFPGreaterOrEqual JumpFPLess JumpFPLessOrEqual JumpFPNotEqual JumpFPOrdered JumpFPUnordered JumpFull JumpGreater JumpGreaterOrEqual JumpLess JumpLessOrEqual JumpLong JumpLongNonZero JumpLongZero JumpNegative JumpNoCarry JumpNoOverflow JumpNonNegative JumpNonZero JumpOverflow JumpR JumpZero Label LastJump LastRTLCode Literal LoadEffectiveAddressMwrR LoadEffectiveAddressXowrR LogicalShiftLeftCqR LogicalShiftLeftRR LogicalShiftRightCqR LogicalShiftRightRR MoveA32R MoveAbR MoveAwR MoveC32R MoveC64R MoveCqR MoveCwR MoveM16rR MoveM32rR MoveM64rRd MoveMbrR MoveMwrR MoveRA32 MoveRAb MoveRAw MoveRM16r MoveRM32r MoveRMbr MoveRMwr MoveRR MoveRRd MoveRX16rR MoveRX32rR MoveRXbrR MoveRXowr MoveRXwrR MoveRdM64r MoveRdR MoveRdRd MoveX16rRR MoveX32rRR MoveXbrRR MoveXowrR MoveXwrRR MulRdRd NegateR Nop OrCqR OrCwR OrRR PopR PrefetchAw PushCq PushCw PushR RetN RotateLeftCqR RotateRightCqR SqrtRd Stop SubCqR SubCwR SubRR SubRdRd TstCqR XorCqR XorCwR XorRR'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogRTLOpcodes commentStamp: 'eem 12/26/2015 14:00' prior: 0!
I am a pool for the Register-Transfer-Language to which Cog compiles. I define unique integer values for all RTL opcodes. See CogAbstractInstruction for instances of instructions with the opcodes that I define.!
Item was changed:
----- Method: CogRTLOpcodes class>>initialize (in category 'class initialization') -----
initialize
"Abstract opcodes are a compound of a one word operation specifier and zero or more operand type specifiers.
The assembler is in Cogit protocol abstract instructions and uses `at&t' syntax, assigning to the register on the
right. e.g. MoveRR is the Move opcode with two register operand specifiers and defines a move register to
register instruction from operand 0 to operand 1. The word and register size is assumed to be either 32-bits
on a 32-bit architecture or 64-bits on a 64-bit architecture. The abstract machine is mostly a 2 address machine
with the odd three address instruction added to better exploit RISCs.
(self initialize)
The operand specifiers are
R - general purpose register
+ Rs - single-precision floating-point register
Rd - double-precision floating-point register
Cq - a `quick' constant that can be encoded in the minimum space possible.
Cw - a constant with word size where word is the default operand size for the Smalltalk VM, 32-bits
for a 32-bit VM, 64-bits for a 64-bit VM. The generated constant must occupy the default number
of bits. This allows e.g. a garbage collector to update the value without invalidating the code.
C32 - a constant with 32 bit size. The generated constant must occupy 32 bits.
C64 - a constant with 64 bit size. The generated constant must occupy 64 bits.
Aw - memory word (32-bits for a 32-bit VM, 64-bits for a 64-bit VM) at an absolute address
Ab - memory byte at an absolute address
A32 - memory 32-bit halfword at an absolute address
Mwr - memory word whose address is at a constant offset from an address in a register
Mbr - memory byte whose address is at a constant offset from an address in a register (zero-extended on read)
M16r - memory 16-bit halfword whose address is at a constant offset from an address in a register
M32r - memory 32-bit halfword whose address is at a constant offset from an address in a register
M64r - memory 64-bit doubleword whose address is at a constant offset from an address in a register
Xbr - memory byte whose address is r * byte size away from an address in a register
X16r - memory 16-bit halfword whose address is r * (2 bytes size) away from an address in a register
X32r - memory 32-bit halfword whose address is r * (4 bytes size) away from an address in a register
Xwr - memory word whose address is r * word size away from an address in a register
Xowr - memory word whose address is o + (r * word size) away from an address in a register (scaled indexed)
An alternative would be to decouple opcodes from operands, e.g.
Move := 1. Add := 2. Sub := 3...
RegisterOperand := 1. ConstantQuickOperand := 2. ConstantWordOperand := 3...
But not all combinations make sense and even fewer are used so we stick with the simple compound approach.
The assumption is that comparison and arithmetic instructions set condition codes and that move instructions
leave the condition codes unaffected. In particular LoadEffectiveAddressMwrR does not set condition codes
although it can be used to do arithmetic. On processors such as MIPS this distinction is invalid; there are no
condition codes. So the backend is allowed to collapse operation, branch pairs to internal instruciton definitions
(see sender and implementors of noteFollowingConditionalBranch:).
Not all of the definitions in opcodeDefinitions below are implemented. In particular we do not implement the
XowrR scaled index addressing mode since it requires 4 operands.
Not all instructions make sense on all architectures. MoveRRd and MoveRdR aqre meaningful only on 64-bit machines.
Note that there are no generic division instructions defined, but a processor may define some.
Branch/Call ranges. Jump[Cond] can be generated as short as possible. Call/Jump[Cond]Long must be generated
in the same number of bytes irrespective of displacement since their targets may be updated, but they need only
span 16Mb, the maximum size of the code zone. This allows e.g. ARM to use single-word call and jump instructions
for most calls and jumps. CallFull/JumpFull must also be generated in the same number of bytes irrespective of
displacement for the same reason, but they must be able to span the full (32-bit or 64-bit) address space because
they are used to call code in the C runtime, which may be distant from the code zone. CallFull/JumpFull are allowed
to use the cResultRegister as a scratch if required (e.g. on x64 where there is no direct 64-bit call or jump).
Byte reads. If the concrete compiler class answers true to byteReadsZeroExtend then byte reads must zero-extend
the byte read into the destination register. If not, the other bits of the register should be left undisturbed and the
Cogit will add an instruction to zero the register as required. Under no circumstances should byte reads sign-extend.
16-bit (and on 64-bits, 32-bit) reads. These /are/ expected to always zero-extend."
| opcodeNames refs |
opcodeNames := #("Noops & Pseudo Ops"
Label
Literal "a word-sized literal"
AlignmentNops
Fill32 "output four byte's worth of bytes with operand 0"
Nop
"Control"
Call "call within the code zone"
CallFull "call anywhere within the full address space"
+ CallR
RetN
JumpR "Not a regular jump, i.e. not pc dependent."
Stop "Halt the processor"
"N.B. Jumps are contiguous. Long and Full jumps are contigiuous within them. See FirstJump et al below"
JumpFull "Jump anywhere within the address space"
JumpLong "Jump anywhere within the 16mb code zone."
JumpLongZero "a.k.a. JumpLongEqual"
JumpLongNonZero "a.k.a. JumpLongNotEqual"
Jump "short jumps; can be encoded in as few bytes as possible; will not be disturbed by GC or relocation."
JumpZero "a.k.a. JumpEqual"
JumpNonZero "a.k.a. JumpNotEqual"
JumpNegative
JumpNonNegative
JumpOverflow
JumpNoOverflow
JumpCarry
JumpNoCarry
JumpLess "signed"
JumpGreaterOrEqual
JumpGreater
JumpLessOrEqual
JumpBelow "unsigned"
JumpAboveOrEqual
JumpAbove
JumpBelowOrEqual
JumpFPEqual
JumpFPNotEqual
JumpFPLess
JumpFPLessOrEqual
JumpFPGreater
JumpFPGreaterOrEqual
JumpFPOrdered
JumpFPUnordered
"Data Movement; destination is always last operand"
MoveRR
MoveAwR MoveA32R
MoveRAw MoveRA32
MoveAbR
MoveRAb
MoveMwrR MoveRMwr MoveXwrRR MoveRXwrR MoveXowrR MoveRXowr
+ MoveM8rR MoveMs8rR MoveRM8r
MoveM16rR MoveRM16r MoveX16rRR MoveRX16rR
MoveM32rR MoveRM32r MoveX32rRR MoveRX32rR
MoveMbrR MoveRMbr MoveXbrRR MoveRXbrR
MoveCqR MoveCwR MoveC32R MoveC64R
MoveRRd MoveRdR MoveRdRd MoveM64rRd MoveRdM64r
+ MoveRsRs MoveM32rRs MoveRsM32r
PopR PushR PushCq PushCw
PrefetchAw
"Arithmetic; destination is always last operand except Cmp; CmpXR is SubRX with no update of result"
LoadEffectiveAddressMwrR LoadEffectiveAddressXowrR "Variants of add/multiply"
NegateR "2's complement negation"
+ NotR
ArithmeticShiftRightCqR ArithmeticShiftRightRR
LogicalShiftRightCqR LogicalShiftRightRR
LogicalShiftLeftCqR LogicalShiftLeftRR
RotateLeftCqR RotateRightCqR
CmpRR AddRR SubRR AndRR OrRR XorRR
CmpCqR AddCqR SubCqR AndCqR OrCqR TstCqR XorCqR
CmpCwR CmpC32R AddCwR SubCwR AndCwR OrCwR XorCwR
+ AddcRR AddcCqR SubbRR
AndCqRR "Three address ops for RISCs; feel free to add and extend"
+ CmpRdRd AddRdRd SubRdRd MulRdRd DivRdRd SqrtRd XorRdRd
+ CmpRsRs AddRsRs SubRsRs MulRsRs DivRsRs SqrtRs XorRsRs
- CmpRdRd AddRdRd SubRdRd MulRdRd DivRdRd SqrtRd
"Conversion"
+ ConvertRRd ConvertRdR
+ ConvertRsRd ConvertRdRs ConvertRsR ConvertRRs
- ConvertRRd
+ SignExtend8RR SignExtend16RR
+ ZeroExtend8RR ZeroExtend16RR
+
LastRTLCode).
"Magic auto declaration. Add to the classPool any new variables and nuke any obsolete ones, and assign values"
"Find the variables directly referenced by this method"
refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
[:ea| ea key].
"Move to Undeclared any opcodes in classPool not in opcodes or this method."
(classPool keys reject: [:k| (opcodeNames includes: k) or: [refs includes: k]]) do:
[:k|
Undeclared declare: k from: classPool].
"Declare as class variables and number elements of opcodeArray above"
opcodeNames withIndexDo:
[:classVarName :value|
self classPool
declare: classVarName from: Undeclared;
at: classVarName put: value].
"For CogAbstractInstruction>>isJump etc..."
FirstJump := JumpFull.
LastJump := JumpFPUnordered.
FirstShortJump := Jump.
"And now initialize the backends; they add their own opcodes and hence these must be reinitialized."
(Smalltalk classNamed: #CogAbstractInstruction) ifNotNil:
[:cogAbstractInstruction| cogAbstractInstruction allSubclasses do: [:sc| sc initialize]]!
Item was changed:
----- Method: CogRTLOpcodes class>>printFormatForOpcodeName: (in category 'debug printing') -----
printFormatForOpcodeName: opcodeName
"Answer a sequence of $r, $f or nil for the operands in the opcode, used for printing, where
r => integer register, f => floating point register, and nil => numeric or address operand."
| printFormat operands |
printFormat := OrderedCollection new.
operands := opcodeName.
[(#( ('Ab' nil) ('Aw' nil)
('Cw' nil) ('Cq' nil) ('C32' nil)
(Fill32 nil)
(Label nil) (Literal nil)
('Mb' nil) ('Mw' nil) ('M16' nil) ('M32' nil) ('M64' nil)
('Nops' nil)
+ ('R' $r) ('Rd' $f) ('Rs' $f)
- ('R' $r) ('Rd' $f)
('Xbr' $r) ('Xwr' $r) ('X16r' $r) ('X32r' $r) ('X64r' $r) ('X' $r) ('ow' nil)
('Greater' exit) ('Xor' exit) ('r' $r))
detect: [:pair| operands endsWith: pair first]
ifNone: [])
ifNil: [false]
ifNotNil:
[:match|
match last ~~ #exit
and: [operands := operands allButLast: match first size.
printFormat addFirst: match last.
true]]]
whileTrue.
(printFormat isEmpty and: [(operands beginsWith: 'Jump') or: [operands beginsWith: 'Call']]) ifTrue:
[printFormat addFirst: nil].
^printFormat
"classPool keys sort collect: [:k| { k. (self printFormatForOpcodeName: k) asArray}]"!
Item was changed:
CogBytecodeFixup subclass: #CogSSBytecodeFixup
+ instanceVariableNames: 'simStackPtr simNativeStackPtr simNativeStackSize'
- instanceVariableNames: 'simStackPtr'
classVariableNames: 'NeedsMergeFixupFlag NeedsNonMergeFixupFlag UnknownSimStackPtrFlag'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogSSBytecodeFixup commentStamp: 'eem 1/20/2011 13:03' prior: 0!
A CogSSBytecodeFixup extends CogBytecodeFixup with state to merge the stack at control-flow joins. At a join the code generator must ensure that the stack is spilled to the same point along both branches and that the simStackPtr is correct.
Instance Variables
simStackPtr: <Integer>
simStackPtr
- the simStackPtr at the jump to this fixup. It should either agree with the incoming fixup if control continues, or replace the simStackPtr if contrl doesn't continue (the incomming control flow ended with a return)!
Item was changed:
----- Method: CogSSBytecodeFixup>>reinitialize (in category 'accessing') -----
reinitialize
<inline: true>
targetInstruction := 0.
+ simStackPtr := 0.
+ self cppIf: LowcodeVM ifTrue: [
+ simNativeStackPtr := 0.
+ ]!
- simStackPtr := 0.!
Item was changed:
----- Method: CogSSBytecodeFixup>>setIsBackwardBranchFixup (in category 'accessing') -----
setIsBackwardBranchFixup
<inline: true>
+ simStackPtr := UnknownSimStackPtrFlag.
+ self cppIf: LowcodeVM ifTrue: [
+ simNativeStackPtr := UnknownSimStackPtrFlag.
+ simNativeStackSize := 0.
+ ]
+ !
- simStackPtr := UnknownSimStackPtrFlag!
Item was added:
+ ----- Method: CogSSBytecodeFixup>>simNativeStackPtr (in category 'accessing') -----
+ simNativeStackPtr
+ "Answer the value of simStackPtr"
+
+ ^ simNativeStackPtr!
Item was added:
+ ----- Method: CogSSBytecodeFixup>>simNativeStackPtr: (in category 'accessing') -----
+ simNativeStackPtr: anObject
+ "Set the value of simStackPtr"
+
+ ^simNativeStackPtr := anObject!
Item was added:
+ ----- Method: CogSSBytecodeFixup>>simNativeStackSize (in category 'accessing') -----
+ simNativeStackSize
+ "Answer the value of simStackPtr"
+
+ ^ simNativeStackSize!
Item was added:
+ ----- Method: CogSSBytecodeFixup>>simNativeStackSize: (in category 'accessing') -----
+ simNativeStackSize: anObject
+ "Set the value of simStackPtr"
+
+ ^simNativeStackSize := anObject!
Item was added:
+ ----- Method: CogSimStackEntry>>floatRegisterMask (in category 'accessing') -----
+ floatRegisterMask
+ ^ 0!
Item was added:
+ VMStructType subclass: #CogSimStackNativeEntry
+ instanceVariableNames: 'cogit objectRepresentation type spilled register registerSecond offset constant constantInt32 constantInt64 constantFloat32 constantFloat64 constantNativePointer bcptr'
+ classVariableNames: ''
+ poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogRTLOpcodes'
+ category: 'VMMaker-JIT'!
Item was added:
+ ----- Method: CogSimStackNativeEntry class>>instVarNamesAndTypesForTranslationDo: (in category 'translation') -----
+ instVarNamesAndTypesForTranslationDo: aBinaryBlock
+ "enumerate aBinaryBlock with the names and C type strings for the inst vars to include in a CogSimStackEntry struct."
+ "self printTypedefOn: Transcript"
+ self filteredInstVarNames do:
+ [:ivn|
+ aBinaryBlock
+ value: (ivn = 'register' ifTrue: ['registerr'] ifFalse: [ivn]) "avoid reservedWord conflict"
+ value: (ivn caseOf: {
+ ['constaintInt64'] -> [#sqLong].
+ ['constantFloat32'] -> [#float].
+ ['constantFloat64'] -> [#double].
+ ['type'] -> [#char].
+ ['spilled'] -> [#char].}
+ otherwise:
+ [#sqInt])]!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>bcptr (in category 'accessing') -----
+ bcptr
+ "Answer the value of bcptr"
+
+ ^ bcptr!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>bcptr: (in category 'accessing') -----
+ bcptr: anObject
+ "Set the value of bcptr"
+
+ ^bcptr := anObject!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>cogit (in category 'accessing') -----
+ cogit
+ "Answer the value of cogit"
+ <doNotGenerate>
+ ^cogit!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>cogit: (in category 'initialize-release') -----
+ cogit: aCogit
+ <doNotGenerate>
+ cogit := aCogit.
+ objectRepresentation := cogit objectRepresentation.
+ ^self!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantFloat32 (in category 'accessing') -----
+ constantFloat32
+ "Answer the value of constant float32"
+ self assert: type = SSConstantFloat32.
+ ^constantFloat32!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantFloat32: (in category 'accessing') -----
+ constantFloat32: aFloat32
+ "Set the value of constant float32"
+
+ ^constantFloat32 := aFloat32!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantFloat64 (in category 'accessing') -----
+ constantFloat64
+ "Answer the value of constant float64"
+ self assert: type = SSConstantFloat64.
+ ^constantFloat64!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantFloat64: (in category 'accessing') -----
+ constantFloat64: aFloat64
+ "Set the value of constant float64"
+
+ ^constantFloat64 := aFloat64!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantInt32 (in category 'accessing') -----
+ constantInt32
+ "Answer the value of constant int32"
+ self assert: type = SSConstantInt32.
+ ^constantInt32!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantInt32: (in category 'accessing') -----
+ constantInt32: anInteger
+ "Set the value of constant int32"
+
+ ^constantInt32 := anInteger!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantInt64 (in category 'accessing') -----
+ constantInt64
+ "Answer the value of constant int64"
+ self assert: type = SSConstantInt64.
+ ^constantInt64!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantInt64: (in category 'accessing') -----
+ constantInt64: anInteger
+ "Set the value of constant int64"
+
+ ^constantInt64 := anInteger!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantNativePointer (in category 'accessing') -----
+ constantNativePointer
+ "Answer the value of constant native pointer"
+ self assert: type = SSConstantNativePointer.
+ ^constantNativePointer!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>constantNativePointer: (in category 'accessing') -----
+ constantNativePointer: aNativePointer
+ "Set the value of constant int64"
+
+ ^constantNativePointer := aNativePointer!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>ensureIsMarkedAsSpilled (in category 'compile abstract instructions') -----
+ ensureIsMarkedAsSpilled
+ spilled ifFalse: [
+ type caseOf: {
+ [SSNativeRegister] -> [ type := SSSpillNative ].
+ [SSRegisterSingleFloat] -> [ type := SSSpillFloat32 ].
+ [SSRegisterDoubleFloat] -> [ type := SSSpillFloat64 ].
+ [SSConstantFloat32] -> [ type := SSSpillFloat32. ].
+ [SSConstantFloat64] -> [ type := SSSpillFloat64. ].
+ [SSConstantInt32] -> [ type := SSSpillNative. ].
+ [SSConstantNativePointer] -> [ type := SSSpillNative. ].
+ }
+ ].
+
+ spilled := true.
+ !
Item was added:
+ ----- Method: CogSimStackNativeEntry>>ensureSpilledSP:scratchRegister: (in category 'compile abstract instructions') -----
+ ensureSpilledSP: spRegister scratchRegister: scratchRegister
+ spilled ifFalse: [
+ type caseOf: {
+ [SSNativeRegister] -> [
+ cogit MoveR: register Mw: offset negated - 1 r: spRegister.
+ type := SSSpillNative.
+ ].
+ [SSRegisterSingleFloat] -> [
+ cogit MoveRs: register M32: offset negated - 1 r: spRegister.
+ type := SSSpillFloat32.
+ ].
+ [SSRegisterDoubleFloat] -> [
+ cogit MoveRd: register M64: offset negated - 1 r: spRegister.
+ type := SSSpillFloat64.
+ ].
+ [SSConstantFloat32] -> [
+ cogit MoveCw: constantFloat32 asIEEE32BitWord R: scratchRegister.
+ cogit MoveR: scratchRegister M32: offset negated - 1 r: spRegister.
+ type := SSSpillFloat32.
+ ].
+ [SSConstantFloat64] -> [
+ BytesPerWord == 4 ifTrue: [
+ cogit MoveCw: (constantFloat64 asIEEE64BitWord bitAnd: 16rFFFFFFFF) R: scratchRegister.
+ cogit MoveR: scratchRegister M32: offset negated - 1 r: spRegister.
+ cogit MoveCw: (constantFloat64 asIEEE64BitWord bitShift: (self cCoerce: -32 to: #'sqLong')) R: scratchRegister.
+ cogit MoveR: scratchRegister M32: offset negated - 1 + 4 r: spRegister.
+ ] ifFalse: [
+ cogit MoveCw: constantFloat32 asIEEE64BitWord R: scratchRegister.
+ cogit MoveR: scratchRegister Mw: offset negated - 1 r: spRegister.
+ ].
+ type := SSSpillFloat64.
+ ].
+ [SSConstantInt32] -> [
+ cogit MoveCq: constantInt32 R: scratchRegister.
+ cogit MoveR: scratchRegister Mw: offset negated - 1 r: spRegister.
+ type := SSSpillNative.
+ ].
+ [SSConstantNativePointer] -> [
+ cogit MoveCw: constantNativePointer R: scratchRegister.
+ cogit MoveR: scratchRegister Mw: offset negated - 1 r: spRegister.
+ type := SSSpillNative.
+ ].
+ }
+ ].
+
+ spilled := true.
+
+ !
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeFloatRegisterMask (in category 'accessing') -----
+ nativeFloatRegisterMask
+ "Answer a bit mask for the receiver's register, if any."
+ ^ (type = SSRegisterSingleFloat or: [type = SSRegisterDoubleFloat])
+ ifTrue: [cogit registerMaskFor: register]
+ ifFalse: [0]!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeFloatRegisterOrNone (in category 'accessing') -----
+ nativeFloatRegisterOrNone
+ ^ ([type = SSRegisterSingleFloat] or: [type = SSRegisterDoubleFloat])
+ ifTrue: [register]
+ ifFalse: [NoReg]!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativePopToReg: (in category 'compile abstract instructions') -----
+ nativePopToReg: reg
+ spilled ifTrue: [
+ cogit loadNativeFramePointerInto: TempReg.
+
+ type caseOf: {
+ [SSSpillNative] -> [cogit MoveMw: offset negated - 1 r: TempReg R: reg].
+ [SSSpillFloat32] -> [cogit MoveM32: offset negated - 1 r: TempReg Rs: reg.].
+ [SSSpillFloat64] -> [cogit MoveM64: offset negated - 1 r: TempReg Rd: reg.].}
+ ] ifFalse: [
+ type caseOf: {
+ [SSNativeRegister] -> [reg ~= register
+ ifTrue: [cogit MoveR: register R: reg]].
+ [SSRegisterSingleFloat] -> [reg ~= register
+ ifTrue: [cogit MoveRs: register Rs: reg]].
+ [SSRegisterDoubleFloat] -> [reg ~= register
+ ifTrue: [cogit MoveRd: register Rd: reg]].
+
+ [SSConstantInt32] -> [cogit MoveCq: constantInt32 R: reg].
+ [SSConstantNativePointer] -> [cogit MoveCw: constantNativePointer R: reg].
+ [SSConstantFloat32] -> [ cogit MoveCf32: constantFloat32 Rs: reg. ].
+ [SSConstantFloat64] -> [ cogit MoveCf64: constantFloat64 Rd: reg. ].
+ }
+ ].
+ !
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativePopToReg:secondReg: (in category 'compile abstract instructions') -----
+ nativePopToReg: reg secondReg: secondReg
+ self assert: BytesPerWord = 4.
+ spilled ifTrue: [
+ cogit PopR: reg; PopR: secondReg
+ ]
+ ifFalse: [
+ type caseOf: {
+ [SSConstantInt64] -> [
+ cogit MoveCq: (constantInt64 bitAnd: 16rFFFFFFFF) R: reg.
+ cogit MoveCq: ((constantInt64 >> 32) bitAnd: 16rFFFFFFFF) R: secondReg.
+ ].
+ [SSRegisterPair] -> [
+ cogit Label.
+ reg ~= register ifTrue: [
+ registerSecond = reg ifTrue: [
+ cogit MoveR: registerSecond R: TempReg.
+ ].
+ cogit MoveR: register R: reg
+ ].
+
+ registerSecond ~= secondReg ifTrue: [
+ registerSecond = reg ifTrue: [
+ cogit MoveR: TempReg R: secondReg.
+ ] ifFalse: [
+ cogit MoveR: registerSecond R: secondReg.
+ ]
+ ].
+ ].
+ }
+ ].
+ !
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeRegisterMask (in category 'accessing') -----
+ nativeRegisterMask
+ "Answer a bit mask for the receiver's register, if any."
+ ^(((type = SSBaseOffset
+ or: [type = SSNativeRegister])
+ or: [type = SSRegisterSingleFloat])
+ or: [type = SSRegisterDoubleFloat])
+ ifTrue: [cogit registerMaskFor: register]
+ ifFalse: [
+ type = SSRegisterPair ifTrue: [(cogit registerMaskFor: register) bitOr: (cogit registerMaskFor: registerSecond)]
+ ifFalse: [0]]!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeRegisterOrNone (in category 'accessing') -----
+ nativeRegisterOrNone
+ ^(type = SSRegister or: [type = SSRegisterPair])
+ ifTrue: [register]
+ ifFalse: [NoReg]!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeStackPopToReg: (in category 'compile abstract instructions') -----
+ nativeStackPopToReg: reg
+ self assert: spilled.
+
+ type caseOf: {
+ [SSSpillNative] -> [cogit MoveMw: offset negated r: FPReg R: reg].
+ [SSSpillFloat32] -> [cogit MoveM32: offset negated r: FPReg Rs: reg.].
+ [SSSpillFloat64] -> [cogit MoveM64: offset negated r: FPReg Rd: reg.].
+ }!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeStackPopToReg:secondReg: (in category 'compile abstract instructions') -----
+ nativeStackPopToReg: reg secondReg: secondReg
+ self assert: spilled.
+
+ type caseOf: {
+ [SSSpillInt64] -> [cogit MoveMw: offset negated + 4 r: FPReg R: reg.
+ cogit MoveMw: offset negated r: FPReg R: secondReg].
+ }!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeStoreToReg: (in category 'compile abstract instructions') -----
+ nativeStoreToReg: reg
+ "FIXME: Duplicated code with popToReg:"
+ spilled ifTrue: [cogit loadNativeFramePointerInto: TempReg.].
+
+ type caseOf: {
+ [SSSpillNative] -> [cogit MoveMw: offset negated - 1 r: TempReg R: reg].
+ [SSSpillFloat32] -> [cogit MoveM32: offset negated - 1 r: TempReg Rs: reg.].
+ [SSSpillFloat64] -> [cogit MoveM64: offset negated - 1 r: TempReg Rd: reg.].
+ [SSNativeRegister] -> [reg ~= register
+ ifTrue: [cogit MoveR: register R: reg]
+ ifFalse: [cogit Label]].
+ [SSRegisterSingleFloat] -> [reg ~= register
+ ifTrue: [cogit MoveRs: register Rs: reg]
+ ifFalse: [cogit Label]].
+ [SSRegisterDoubleFloat] -> [reg ~= register
+ ifTrue: [cogit MoveRd: register Rd: reg]
+ ifFalse: [cogit Label]].
+
+ [SSConstantInt32] -> [cogit MoveCw: constantInt32 R: reg].
+ [SSConstantNativePointer] -> [cogit MoveCw: constantNativePointer R: reg].
+ [SSConstantFloat32] -> [ cogit MoveCf32: constantFloat32 Rs: reg. ].
+ [SSConstantFloat64] -> [ cogit MoveCf64: constantFloat64 Rd: reg. ].
+ }.!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeStoreToReg:secondReg: (in category 'compile abstract instructions') -----
+ nativeStoreToReg: reg secondReg: secondReg
+ self assert: BytesPerWord = 4.
+ "FIXME: Duplicated code with popToReg:secondReg:"
+ type caseOf: {
+ [SSBaseOffset] -> [
+ cogit MoveMw: offset r: register R: reg.
+ cogit MoveMw: offset + 4 r: register R: secondReg.
+ ].
+ [SSSpillInt64] -> [
+ cogit MoveMw: offset r: register R: reg.
+ cogit MoveMw: offset + 4 r: registerSecond R: secondReg
+ ].
+ [SSRegisterPair] -> [
+ cogit Label.
+ reg ~= register ifTrue: [
+ registerSecond = reg ifTrue: [
+ cogit MoveR: registerSecond R: TempReg.
+ ].
+ cogit MoveR: register R: reg
+ ].
+
+ registerSecond ~= secondReg ifTrue: [
+ registerSecond = reg ifTrue: [
+ cogit MoveR: TempReg R: secondReg.
+ ] ifFalse: [
+ cogit MoveR: registerSecond R: secondReg.
+ ]
+ ].
+ ].
+ [SSConstantInt64] -> [
+ self MoveCq: (constantInt64 bitAnd: 16rFFFFFFFF) R: reg.
+ self MoveCq: ((constantInt64 >> 32) bitAnd: 16rFFFFFFFF) R: secondReg.
+ ].
+ }.
+ !
Item was added:
+ ----- Method: CogSimStackNativeEntry>>offset (in category 'accessing') -----
+ offset
+ <doNotGenerate>
+ "Answer the value of offset"
+ ^offset!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>offset: (in category 'accessing') -----
+ offset: anObject
+ <doNotGenerate>
+ "Set the value of offset"
+
+ ^offset := anObject!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>printStateOn: (in category 'printing') -----
+ printStateOn: aStream
+ <doNotGenerate> "Smalltalk-side only"
+ type isInteger ifFalse: [^self].
+ aStream nextPut: $(.
+ type caseOf: {
+ [SSNativeRegister] -> [aStream
+ nextPutAll: 'reg ';
+ nextPutAll: (CogRTLOpcodes nameForRegister: register)].
+ [SSRegisterPair] -> [aStream
+ nextPutAll: 'reg ';
+ nextPutAll: (CogRTLOpcodes nameForRegister: register);
+ nextPutAll: '+';
+ nextPutAll: (CogRTLOpcodes nameForRegister: registerSecond).].
+ [SSRegisterSingleFloat] -> [aStream
+ nextPutAll: 'regFloat32 ';
+ nextPutAll: (CogRTLOpcodes nameForRegister: register)].
+ [SSRegisterDoubleFloat] -> [aStream
+ nextPutAll: 'regFloat64 ';
+ nextPutAll: (CogRTLOpcodes nameForRegister: register)].
+
+ [SSSpillNative] -> [aStream
+ nextPutAll: 'spillNative @ '.
+ offset negative ifFalse: [aStream nextPut: $+].
+ aStream print: offset].
+ [SSSpillInt64] -> [aStream
+ nextPutAll: 'spillInt64 @ '.
+ offset negative ifFalse: [aStream nextPut: $+].
+ aStream print: offset].
+ [SSSpillFloat32] -> [aStream
+ nextPutAll: 'spillFloat32 @ '.
+ offset negative ifFalse: [aStream nextPut: $+].
+ aStream print: offset].
+ [SSSpillFloat64] -> [aStream
+ nextPutAll: 'spillFloat64 @ '.
+ offset negative ifFalse: [aStream nextPut: $+].
+ aStream print: offset].
+
+ [SSConstantInt32] -> [aStream
+ nextPutAll: 'constInt32 ';
+ print: constantInt32].
+ [SSConstantInt64] -> [aStream
+ nextPutAll: 'constInt64 ';
+ print: constantInt64].
+ [SSConstantFloat32] -> [aStream
+ nextPutAll: 'constFloat32 ';
+ print: constantFloat32].
+ [SSConstantFloat64] -> [aStream
+ nextPutAll: 'constFloat64 ';
+ print: constantFloat64].
+ [SSConstantNativePointer] -> [aStream
+ nextPutAll: 'constNativePointer ';
+ print: constantNativePointer]
+ }.
+ spilled ifTrue:
+ [aStream nextPutAll: ' (spilled)'].
+ bcptr ifNotNil:
+ [aStream space; nextPut: ${; print: bcptr; nextPut: $}].
+ aStream nextPut: $)!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>register (in category 'accessing') -----
+ register
+ <doNotGenerate>
+ "Answer the value of register"
+ self assert: ((([type = SSNativeRegister] or: [type = SSRegisterPair]) or: [type = SSRegisterSingleFloat]) or: [type = SSRegisterDoubleFloat]).
+ ^register!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>register: (in category 'accessing') -----
+ register: anObject
+ <doNotGenerate>
+ "Set the value of register"
+
+ ^register := anObject!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>registerSecond (in category 'accessing') -----
+ registerSecond
+ "Answer the value of register"
+ self assert: type = SSRegisterPair.
+ ^ registerSecond!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>registerSecond: (in category 'accessing') -----
+ registerSecond: anObject
+ "Set the value of register"
+
+ ^registerSecond := anObject!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>registerSecondOrNil (in category 'accessing') -----
+ registerSecondOrNil
+ ^ type SSRegisterPair ifTrue: [registerSecond]!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>spilled (in category 'accessing') -----
+ spilled
+ "Answer the value of spilled"
+
+ ^ spilled!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>spilled: (in category 'accessing') -----
+ spilled: anObject
+ "Set the value of spilled"
+
+ ^spilled := anObject!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>spillingNeedsScratchRegister (in category 'compile abstract instructions') -----
+ spillingNeedsScratchRegister
+ spilled ifFalse: [
+ type caseOf: {
+ [SSConstantInt32] -> [ ^ true ].
+ [SSConstantInt64] -> [ ^ true ].
+ [SSConstantFloat32] -> [ ^ true ].
+ [SSConstantFloat64] -> [ ^ true ].
+ [SSConstantNativePointer] -> [ ^ true ].
+ }
+ otherwise: [^ false]
+ ].
+
+ ^ false.
+ !
Item was added:
+ ----- Method: CogSimStackNativeEntry>>stackSpillSize (in category 'accessing') -----
+ stackSpillSize
+ <returnTypeC: #sqInt>
+ type caseOf: {
+ [SSConstantInt64] -> [ ^ 8 ].
+ [SSConstantFloat64] -> [ ^ 8 ].
+ [SSRegisterDoubleFloat] -> [ ^ 8 ].
+ [SSRegisterPair] -> [ ^ 8 ].
+ [SSSpillFloat64] -> [ ^ 8 ].
+ [SSSpillInt64] -> [ ^ 8 ].
+ } otherwise: [^ BytesPerOop ]!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>type (in category 'accessing') -----
+ type
+ "Answer the value of type"
+
+ ^ type!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>type: (in category 'accessing') -----
+ type: anObject
+ "Set the value of type"
+
+ ^type := anObject!
Item was changed:
----- Method: CogVMSimulator>>extBBytecode (in category 'miscellaneous bytecodes') -----
extBBytecode
"225 11100001 sbbbbbbb Extend B (Ext B = Ext B prev * 256 + Ext B)"
+ (extA = 0 and: [extB = 0 and: [extBFirstZero not]]) ifTrue:
- (extA = 0 and: [extB = 0]) ifTrue:
[lastExtPC := localIP].
^super extBBytecode!
Item was changed:
CogClass subclass: #Cogit
+ instanceVariableNames: 'coInterpreter objectMemory objectRepresentation processor threadManager methodZone methodZoneBase codeBase minValidCallAddress lastNInstructions simulatedAddresses simulatedTrampolines simulatedVariableGetters simulatedVariableSetters printRegisters printInstructions compilationTrace clickConfirm breakPC breakBlock singleStep guardPageSize traceFlags traceStores breakMethod methodObj enumeratingCogMethod methodHeader initialPC endPC methodOrBlockNumArgs inBlock needsFrame hasYoungReferent primitiveIndex backEnd literalsManager postCompileHook methodLabel stackCheckLabel blockEntryLabel blockEntryNoContextSwitch blockNoContextSwitchOffset stackOverflowCall sendMiss missOffset entryPointMask checkedEntryAlignment uncheckedEntryAlignment cmEntryOffset entry cmNoCheckEntryOffset noCheckEntry fullBlockEntry cbEntryOffset fullBlockNoContextSwitchEntry cbNoSwitchEntryOffset picMNUAbort picInterpretAbort endCPICCase0 endCPICCase1 firstCPICCaseOffset cPICCaseSize cPICEndSize closedPICSize openPICSize fixups abstractOpcodes generatorTable byte0 byte1 byte2 byte3 bytecodePC bytecodeSetOffset opcodeIndex numAbstractOpcodes blockStarts blockCount labelCounter cStackAlignment expectedSPAlignment expectedFPAlignment codeModified maxLitIndex ceMethodAbortTrampoline cePICAbortTrampoline ceCheckForInterruptTrampoline ceCPICMissTrampoline ceReturnToInterpreterTrampoline ceBaseFrameReturnTrampoline ceSendMustBeBooleanAddTrueTrampoline ceSendMustBeBooleanAddFalseTrampoline ceCannotResumeTrampoline ceEnterCogCodePopReceiverReg ceCallCogCodePopReceiverReg ceCallCogCodePopReceiverAndClassRegs cePrimReturnEnterCogCode cePrimReturnEnterCogCodeProfiling ceNonLocalReturnTrampoline ceFetchContextInstVarTrampoline ceStoreContextInstVarTrampoline ceEnclosingObjectTrampoline ceFlushICache ceCheckFeaturesFunction ceTraceLinkedSendTrampoline ceTraceBlockActivationTrampoline ceTraceStoreTrampoline ceGetFP ceGetSP ceCaptureCStackPointers ordinarySendTrampolines superSendTrampolines directedSuperSendTrampolines dynamicSuperSendTrampolines outerSendTrampolines selfSendTrampolines firstSend lastSend realCEEnterCogCodePopReceiverReg realCECallCogCodePopReceiverReg realCECallCogCodePopReceiverAndClassRegs trampolineTableIndex trampolineAddresses objectReferencesInRuntime runtimeObjectRefIndex cFramePointerInUse debugPrimCallStackOffset ceTryLockVMOwner ceUnlockVMOwner extA extB extBFirstZero tempOop numIRCs indexOfIRC theIRCs implicitReceiverSendTrampolines cogMethodSurrogateClass cogBlockMethodSurrogateClass nsSendCacheSurrogateClass CStackPointer CFramePointer cPICPrototype cPICEndOfCodeOffset cPICEndOfCodeLabel maxCPICCases debugBytecodePointers debugOpcodeIndices disassemblingMethod ceMallocTrampoline ceFreeTrampoline ceFFICalloutTrampoline'
- instanceVariableNames: 'coInterpreter objectMemory objectRepresentation processor threadManager methodZone methodZoneBase codeBase minValidCallAddress lastNInstructions simulatedAddresses simulatedTrampolines simulatedVariableGetters simulatedVariableSetters printRegisters printInstructions compilationTrace clickConfirm breakPC breakBlock singleStep guardPageSize traceFlags traceStores breakMethod methodObj enumeratingCogMethod methodHeader initialPC endPC methodOrBlockNumArgs inBlock needsFrame hasYoungReferent primitiveIndex backEnd literalsManager postCompileHook methodLabel stackCheckLabel blockEntryLabel blockEntryNoContextSwitch blockNoContextSwitchOffset stackOverflowCall sendMiss missOffset entryPointMask checkedEntryAlignment uncheckedEntryAlignment cmEntryOffset entry cmNoCheckEntryOffset noCheckEntry fullBlockEntry cbEntryOffset fullBlockNoContextSwitchEntry cbNoSwitchEntryOffset picMNUAbort picInterpretAbort endCPICCase0 endCPICCase1 firstCPICCaseOffset cPICCaseSize cPICEndSize closedPICSize openPICSize fixups abstractOpcodes generatorTable byte0 byte1 byte2 byte3 bytecodePC bytecodeSetOffset opcodeIndex numAbstractOpcodes blockStarts blockCount labelCounter cStackAlignment expectedSPAlignment expectedFPAlignment codeModified maxLitIndex ceMethodAbortTrampoline cePICAbortTrampoline ceCheckForInterruptTrampoline ceCPICMissTrampoline ceReturnToInterpreterTrampoline ceBaseFrameReturnTrampoline ceSendMustBeBooleanAddTrueTrampoline ceSendMustBeBooleanAddFalseTrampoline ceCannotResumeTrampoline ceEnterCogCodePopReceiverReg ceCallCogCodePopReceiverReg ceCallCogCodePopReceiverAndClassRegs cePrimReturnEnterCogCode cePrimReturnEnterCogCodeProfiling ceNonLocalReturnTrampoline ceFetchContextInstVarTrampoline ceStoreContextInstVarTrampoline ceEnclosingObjectTrampoline ceFlushICache ceCheckFeaturesFunction ceTraceLinkedSendTrampoline ceTraceBlockActivationTrampoline ceTraceStoreTrampoline ceGetFP ceGetSP ceCaptureCStackPointers ordinarySendTrampolines superSendTrampolines directedSuperSendTrampolines dynamicSuperSendTrampolines outerSendTrampolines selfSendTrampolines firstSend lastSend realCEEnterCogCodePopReceiverReg realCECallCogCodePopReceiverReg realCECallCogCodePopReceiverAndClassRegs trampolineTableIndex trampolineAddresses objectReferencesInRuntime runtimeObjectRefIndex cFramePointerInUse debugPrimCallStackOffset ceTryLockVMOwner ceUnlockVMOwner extA extB tempOop numIRCs indexOfIRC theIRCs implicitReceiverSendTrampolines cogMethodSurrogateClass cogBlockMethodSurrogateClass nsSendCacheSurrogateClass CStackPointer CFramePointer cPICPrototype cPICEndOfCodeOffset cPICEndOfCodeLabel debugBytecodePointers debugOpcodeIndices disassemblingMethod'
classVariableNames: 'AltBlockCreationBytecodeSize AltFirstSpecialSelector AltNSSendIsPCAnnotated AltNumSpecialSelectors AnnotationConstantNames AnnotationShift AnnotationsWithBytecodePCs BlockCreationBytecodeSize Debug DisplacementMask DisplacementX2N EagerInstructionDecoration FirstAnnotation FirstSpecialSelector HasBytecodePC IsAbsPCReference IsAnnotationExtension IsDirectedSuperSend IsDisplacementX2N IsNSDynamicSuperSend IsNSImplicitReceiverSend IsNSSelfSend IsNSSendCall IsObjectReference IsRelativeCall IsSendCall IsSuperSend MapEnd MaxCPICCases MaxCompiledPrimitiveIndex MaxStackAllocSize MaxX2NDisplacement NSCClassTagIndex NSCEnclosingObjectIndex NSCNumArgsIndex NSCSelectorIndex NSCTargetIndex NSSendIsPCAnnotated NeedsFixupFlag NumObjRefsInRuntime NumOopsPerNSC NumSpecialSelectors NumTrampolines ProcessorClass'
poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogMethodConstants CogRTLOpcodes VMBasicConstants VMBytecodeConstants VMObjectIndices VMStackFrameOffsets'
category: 'VMMaker-JIT'!
Cogit class
instanceVariableNames: 'generatorTable primitiveTable'!
!Cogit commentStamp: 'eem 4/6/2015 15:56' prior: 0!
I am the code generator for the Cog VM. My job is to produce machine code versions of methods for faster execution and to manage inline caches for faster send performance. I can be tested in the current image using my class-side in-image compilation facilities. e.g. try
StackToRegisterMappingCogit genAndDis: (Integer >> #benchFib)
I have concrete subclasses that implement different levels of optimization:
SimpleStackBasedCogit is the simplest code generator.
StackToRegisterMappingCogit is the current production code generator It defers pushing operands
to the stack until necessary and implements a register-based calling convention for low-arity sends.
StackToRegisterMappingCogit is an experimental code generator with support for counting
conditional branches, intended to support adaptive optimization.
coInterpreter <CoInterpreterSimulator>
the VM's interpreter with which I cooperate
methodZoneManager <CogMethodZoneManager>
the manager of the machine code zone
objectRepresentation <CogObjectRepresentation>
the object used to generate object accesses
processor <BochsIA32Alien|?>
the simulator that executes the IA32/x86 machine code I generate when simulating execution in Smalltalk
simulatedTrampolines <Dictionary of Integer -> MessageSend>
the dictionary mapping trap jump addresses to run-time routines used to warp from simulated machine code in to the Smalltalk run-time.
simulatedVariableGetters <Dictionary of Integer -> MessageSend>
the dictionary mapping trap read addresses to variables in run-time objects used to allow simulated machine code to read variables in the Smalltalk run-time.
simulatedVariableSetters <Dictionary of Integer -> MessageSend>
the dictionary mapping trap write addresses to variables in run-time objects used to allow simulated machine code to write variables in the Smalltalk run-time.
printRegisters printInstructions clickConfirm <Boolean>
flags controlling debug printing and code simulation
breakPC <Integer>
machine code pc breakpoint
cFramePointer cStackPointer <Integer>
the variables representing the C stack & frame pointers, which must change on FFI callback and return
selectorOop <sqInt>
the oop of the methodObj being compiled
methodObj <sqInt>
the bytecode method being compiled
initialPC endPC <Integer>
the start and end pcs of the methodObj being compiled
methodOrBlockNumArgs <Integer>
argument count of current method or block being compiled
needsFrame <Boolean>
whether methodObj or block needs a frame to execute
primitiveIndex <Integer>
primitive index of current method being compiled
methodLabel <CogAbstractOpcode>
label for the method header
blockEntryLabel <CogAbstractOpcode>
label for the start of the block dispatch code
stackOverflowCall <CogAbstractOpcode>
label for the call of ceStackOverflow in the method prolog
sendMissCall <CogAbstractOpcode>
label for the call of ceSICMiss in the method prolog
entryOffset <Integer>
offset of method entry code from start (header) of method
entry <CogAbstractOpcode>
label for the first instruction of the method entry code
noCheckEntryOffset <Integer>
offset of the start of a method proper (after the method entry code) from start (header) of method
noCheckEntry <CogAbstractOpcode>
label for the first instruction of start of a method proper
fixups <Array of <AbstractOpcode Label | nil>>
the labels for forward jumps that will be fixed up when reaching the relevant bytecode. fixup shas one element per byte in methodObj's bytecode
abstractOpcodes <Array of <AbstractOpcode>>
the code generated when compiling methodObj
byte0 byte1 byte2 byte3 <Integer>
individual bytes of current bytecode being compiled in methodObj
bytecodePointer <Integer>
bytecode pc (same as Smalltalk) of the current bytecode being compiled
opcodeIndex <Integer>
the index of the next free entry in abstractOpcodes (this code is translated into C where OrderedCollection et al do not exist)
numAbstractOpcodes <Integer>
the number of elements in abstractOpcocdes
blockStarts <Array of <BlockStart>>
the starts of blocks in the current method
blockCount
the index into blockStarts as they are being noted, and hence eventually the total number of blocks in the current method
labelCounter <Integer>
a nicety for numbering labels not needed in the production system but probably not expensive enough to worry about
ceStackOverflowTrampoline <Integer>
ceSend0ArgsTrampoline <Integer>
ceSend1ArgsTrampoline <Integer>
ceSend2ArgsTrampoline <Integer>
ceSendNArgsTrampoline <Integer>
ceSendSuper0ArgsTrampoline <Integer>
ceSendSuper1ArgsTrampoline <Integer>
ceSendSuper2ArgsTrampoline <Integer>
ceSendSuperNArgsTrampoline <Integer>
ceSICMissTrampoline <Integer>
ceCPICMissTrampoline <Integer>
ceStoreCheckTrampoline <Integer>
ceReturnToInterpreterTrampoline <Integer>
ceBaseFrameReturnTrampoline <Integer>
ceSendMustBeBooleanTrampoline <Integer>
ceClosureCopyTrampoline <Integer>
the various trampolines (system-call-like jumps from machine code to the run-time).
See Cogit>>generateTrampolines for the mapping from trampoline to run-time
routine and then read the run-time routine for a funcitonal description.
ceEnterCogCodePopReceiverReg <Integer>
the enilopmart (jump from run-time to machine-code)
methodZoneBase <Integer>
!
Cogit class
instanceVariableNames: 'generatorTable primitiveTable'!
Item was changed:
----- Method: Cogit class>>generatorTableFrom: (in category 'class initialization') -----
generatorTableFrom: anArray
| blockCreationBytecodeSize |
generatorTable := CArrayAccessor on: (Array new: 256).
anArray do:
[:tuple| | descriptor |
(descriptor := CogBytecodeDescriptor new)
numBytes: tuple first;
generator: tuple fourth;
isReturn: (tuple includes: #return);
isMapped: ((tuple includes: #isMappedIfImmutability)
ifTrue: [self bindingOf: #IMMUTABILITY]
ifFalse: [tuple includes: #isMapped]);
isMappedInBlock: (tuple includes: #isMappedInBlock);
isBlockCreation: (tuple includes: #block);
spanFunction: (((tuple includes: #block) or: [(tuple includes: #branch)]) ifTrue:
[tuple detect: [:thing| thing isSymbol and: [thing numArgs = 4]]]);
isBranchTrue: (tuple includes: #isBranchTrue);
isBranchFalse: (tuple includes: #isBranchFalse);
isExtension: (tuple includes: #extension);
isInstVarRef: (tuple includes: #isInstVarRef); "for Spur"
is1ByteInstVarStore: (tuple includes: #is1ByteInstVarStore); "for Spur"
+ isCallPrimitive: (tuple includes: #callPrimitive);
hasIRC: (tuple includes: #hasIRC); "for Newspeak"
yourself.
"As a hack to cut down on descriptor flags, use opcode to tag unusedBytecode for scanning.
Currently descriptors are exactly 16 bytes with all 8 flag bits used (in Newspeak at least 17 bytes,
9 flag bits). As another hack to eliminate a test in scanMethod mark unknowns as extensions."
descriptor generator == #unknownBytecode ifTrue:
[descriptor opcode: Nop; isExtension: true].
descriptor isBlockCreation ifTrue:
[blockCreationBytecodeSize
ifNil: [blockCreationBytecodeSize := descriptor numBytes]
ifNotNil: [self assert: blockCreationBytecodeSize = descriptor numBytes]].
tuple do:
[:thing|
thing isSymbol ifTrue:
[(thing beginsWith: #needsFrame) ifTrue:
[descriptor needsFrameFunction: thing].
(CogRTLOpcodes classPool at: thing ifAbsent: []) ifNotNil:
[:opcode| descriptor opcode: opcode]]].
tuple last isInteger
ifTrue: [descriptor stackDelta: tuple last]
ifFalse:
[descriptor needsFrameFunction ifNotNil:
[self error: 'frameless block bytecodes must specify a stack delta']].
tuple second to: tuple third do:
[:index|
generatorTable at: index put: descriptor]].
BlockCreationBytecodeSize := blockCreationBytecodeSize.
^generatorTable!
Item was changed:
----- Method: Cogit class>>numTrampolines (in category 'accessing') -----
numTrampolines
+ ^38 "30 + 4 each for self and super sends"
- ^35 "27 + 4 each for self and super sends"
"self withAllSubclasses collect: [:c| {c. (c instVarNames select: [:ea| ea beginsWith: 'ce']) size}]"!
Item was added:
+ ----- Method: Cogit>>AddRs:Rs: (in category 'abstract instructions') -----
+ AddRs: dpreg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: AddRsRs operand: dpreg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>AddcCq:R: (in category 'abstract instructions') -----
+ AddcCq: quickConstant R: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: AddcCqR quickConstant: quickConstant operand: reg!
Item was added:
+ ----- Method: Cogit>>AddcR:R: (in category 'abstract instructions') -----
+ AddcR: reg1 R: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: AddcRR operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>CallR: (in category 'abstract instructions') -----
+ CallR: callTarget
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: CallR operand: callTarget!
Item was added:
+ ----- Method: Cogit>>CmpRs:Rs: (in category 'abstract instructions') -----
+ CmpRs: dpreg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: CmpRsRs operand: dpreg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>ConvertR:Rs: (in category 'abstract instructions') -----
+ ConvertR: reg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: ConvertRRs operand: reg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>ConvertRd:R: (in category 'abstract instructions') -----
+ ConvertRd: reg1 R: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: ConvertRdR operand: reg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>ConvertRd:Rs: (in category 'abstract instructions') -----
+ ConvertRd: reg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: ConvertRdRs operand: reg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>ConvertRs:R: (in category 'abstract instructions') -----
+ ConvertRs: reg1 R: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: ConvertRsR operand: reg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>ConvertRs:Rd: (in category 'abstract instructions') -----
+ ConvertRs: reg1 Rd: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: ConvertRsRd operand: reg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>DivRs:Rs: (in category 'abstract instructions') -----
+ DivRs: dpreg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: DivRsRs operand: dpreg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>MoveCf32:Rs: (in category 'abstract instructions') -----
+ MoveCf32: constantFloat32 Rs: register
+ <inline: true>
+ <var: #constantFloat32 type: #float>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^ backEnd genMoveCf32: constantFloat32 Rs: register!
Item was added:
+ ----- Method: Cogit>>MoveCf64:Rd: (in category 'abstract instructions') -----
+ MoveCf64: constantFloat64 Rd: register
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ <var: #constantFloat64 type: #double>
+ ^ backEnd genMoveCf64: constantFloat64 Rd: register!
Item was added:
+ ----- Method: Cogit>>MoveM32:r:R: (in category 'abstract instructions') -----
+ MoveM32: offset r: baseReg R: destReg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MoveM32rR quickConstant: offset operand: baseReg operand: destReg!
Item was added:
+ ----- Method: Cogit>>MoveM32:r:Rs: (in category 'abstract instructions') -----
+ MoveM32: offset r: baseReg Rs: destDPReg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MoveM32rRs quickConstant: offset operand: baseReg operand: destDPReg!
Item was added:
+ ----- Method: Cogit>>MoveM8:r:R: (in category 'abstract instructions') -----
+ MoveM8: offset r: baseReg R: destReg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MoveM8rR quickConstant: offset operand: baseReg operand: destReg!
Item was added:
+ ----- Method: Cogit>>MoveR:M32:r: (in category 'abstract instructions') -----
+ MoveR: sourceReg M32: offset r: baseReg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MoveRM32r operand: sourceReg quickConstant: offset operand: baseReg!
Item was added:
+ ----- Method: Cogit>>MoveR:M8:r: (in category 'abstract instructions') -----
+ MoveR: sourceReg M8: offset r: baseReg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MoveRM8r operand: sourceReg quickConstant: offset operand: baseReg!
Item was added:
+ ----- Method: Cogit>>MoveRs:M32:r: (in category 'abstract instructions') -----
+ MoveRs: sourceDPReg M32: offset r: baseReg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MoveRsM32r operand: sourceDPReg quickConstant: offset operand: baseReg!
Item was added:
+ ----- Method: Cogit>>MoveRs:Rs: (in category 'abstract instructions') -----
+ MoveRs: dpreg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MoveRsRs operand: dpreg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>MulRs:Rs: (in category 'abstract instructions') -----
+ MulRs: dpreg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: MulRsRs operand: dpreg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>NotR: (in category 'abstract instructions') -----
+ NotR: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: NotR operand: reg!
Item was added:
+ ----- Method: Cogit>>PopRd: (in category 'abstract instructions') -----
+ PopRd: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^ backEnd genPopRd: reg!
Item was added:
+ ----- Method: Cogit>>PopRs: (in category 'abstract instructions') -----
+ PopRs: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^ backEnd genPopRs: reg!
Item was added:
+ ----- Method: Cogit>>PushC64: (in category 'abstract instructions') -----
+ PushC64: constant64Bits
+ <inline: true>
+ <var: #constant64Bits type: #sqLong>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^ backEnd genPushC64: constant64Bits!
Item was added:
+ ----- Method: Cogit>>PushRd: (in category 'abstract instructions') -----
+ PushRd: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^ backEnd genPushRd: reg!
Item was added:
+ ----- Method: Cogit>>PushRs: (in category 'abstract instructions') -----
+ PushRs: reg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^ backEnd genPushRs: reg!
Item was added:
+ ----- Method: Cogit>>SignExtend16R:R: (in category 'abstract instructions') -----
+ SignExtend16R: reg1 R: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: SignExtend16RR operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>SignExtend8R:R: (in category 'abstract instructions') -----
+ SignExtend8R: reg1 R: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: SignExtend8RR operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>SqrtRs: (in category 'abstract instructions') -----
+ SqrtRs: dpreg
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: SqrtRs operand: dpreg!
Item was added:
+ ----- Method: Cogit>>SubRs:Rs: (in category 'abstract instructions') -----
+ SubRs: dpreg1 Rs: dpreg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: SubRsRs operand: dpreg1 operand: dpreg2!
Item was added:
+ ----- Method: Cogit>>SubbR:R: (in category 'abstract instructions') -----
+ SubbR: reg1 R: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: SubbRR operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>XorRd:Rd: (in category 'abstract instructions') -----
+ XorRd: reg1 Rd: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: XorRdRd operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>XorRs:Rs: (in category 'abstract instructions') -----
+ XorRs: reg1 Rs: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: XorRsRs operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>ZeroExtend16R:R: (in category 'abstract instructions') -----
+ ZeroExtend16R: reg1 R: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: ZeroExtend16RR operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>ZeroExtend8R:R: (in category 'abstract instructions') -----
+ ZeroExtend8R: reg1 R: reg2
+ <inline: true>
+ <returnTypeC: #'AbstractInstruction *'>
+ ^self gen: ZeroExtend8RR operand: reg1 operand: reg2!
Item was added:
+ ----- Method: Cogit>>ceFree: (in category 'trampoline support') -----
+ ceFree: pointer
+ <api>
+ <var: #pointer type: #'void*'>
+ self free: pointer!
Item was added:
+ ----- Method: Cogit>>ceMalloc: (in category 'trampoline support') -----
+ ceMalloc: size
+ <api>
+ <var: #size type: #'size_t'>
+ <returnTypeC: #'void*'>
+ ^ self malloc: size!
Item was changed:
----- Method: Cogit>>collectMapEntry:address:into: (in category 'disassembly') -----
collectMapEntry: annotation address: mcpc into: aDictionary
<doNotGenerate>
aDictionary
at: mcpc
ifPresent:
[:extant|
aDictionary
at: mcpc
put: extant, ':\' withCRs, (self class annotationConstantNames at: annotation + 1)]
+ ifAbsent: [ aDictionary at: mcpc put: (self class annotationConstantNames at: annotation + 1)].
- ifAbsentPut: [self class annotationConstantNames at: annotation + 1].
^0!
Item was added:
+ ----- Method: Cogit>>compileCallFor:numArgs:arg:arg:arg:arg:floatResultReg:regsToSave: (in category 'initialization') -----
+ compileCallFor: aRoutine numArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 floatResultReg: resultRegOrNone regsToSave: regMask
+ "Generate a call to aRoutine with up to 4 arguments. If resultRegOrNone is not
+ NoReg assign the C result to resultRegOrNone. If saveRegs, save all registers.
+ Hack: a negative arg value indicates an abstract register, a non-negative value
+ indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <inline: false>
+ | regsToSave |
+ regsToSave := resultRegOrNone = NoReg
+ ifTrue: [regMask]
+ ifFalse: [regMask bitClear: (self registerMaskFor: resultRegOrNone)].
+ cStackAlignment > objectMemory wordSize ifTrue:
+ [backEnd
+ genAlignCStackSavingRegisters: regsToSave
+ numArgs: numArgs
+ wordAlignment: cStackAlignment / objectMemory wordSize].
+ backEnd
+ genSaveRegs: regsToSave;
+ genMarshallNArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3.
+ self CallFullRT: (self cCode: [aRoutine asUnsignedInteger]
+ inSmalltalk: [self simulatedTrampolineFor: aRoutine]).
+ resultRegOrNone ~= NoReg ifTrue:
+ [backEnd cFloatResultToRd: resultRegOrNone].
+ numArgs > 0 ifTrue:
+ [backEnd genRemoveNArgsFromStack: numArgs].
+ backEnd genRestoreRegs: regsToSave!
Item was added:
+ ----- Method: Cogit>>compileCallFor:numArgs:arg:arg:arg:arg:resultReg:resultReg:regsToSave: (in category 'initialization') -----
+ compileCallFor: aRoutine numArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 resultReg: resultRegOrNone resultReg: resultReg2OrNone regsToSave: regMask
+ "Generate a call to aRoutine with up to 4 arguments. If resultRegOrNone is not
+ NoReg assign the C result to resultRegOrNone. If saveRegs, save all registers.
+ Hack: a negative arg value indicates an abstract register, a non-negative value
+ indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <inline: false>
+ | regsToSave |
+ regsToSave := resultRegOrNone = NoReg
+ ifTrue: [regMask]
+ ifFalse: [regMask bitClear: (self registerMaskFor: resultRegOrNone)].
+ cStackAlignment > objectMemory wordSize ifTrue:
+ [backEnd
+ genAlignCStackSavingRegisters: regsToSave
+ numArgs: numArgs
+ wordAlignment: cStackAlignment / objectMemory wordSize].
+ backEnd
+ genSaveRegs: regsToSave;
+ genMarshallNArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3.
+ self CallFullRT: (self cCode: [aRoutine asUnsignedInteger]
+ inSmalltalk: [self simulatedTrampolineFor: aRoutine]).
+ resultRegOrNone ~= NoReg ifTrue:
+ [backEnd genWriteCResultIntoReg: resultRegOrNone].
+ resultReg2OrNone ~= NoReg ifTrue:
+ [backEnd genWriteCSecondResultIntoReg: resultReg2OrNone].
+ numArgs > 0 ifTrue:
+ [backEnd genRemoveNArgsFromStack: numArgs].
+ backEnd genRestoreRegs: regsToSave!
Item was added:
+ ----- Method: Cogit>>compileCallFor:numArgs:floatArg:floatArg:floatArg:floatArg:resultReg:regsToSave: (in category 'initialization') -----
+ compileCallFor: aRoutine numArgs: numArgs floatArg: regOrConst0 floatArg: regOrConst1 floatArg: regOrConst2 floatArg: regOrConst3 resultReg: resultRegOrNone regsToSave: regMask
+ "Generate a call to aRoutine with up to 4 arguments. If resultRegOrNone is not
+ NoReg assign the C result to resultRegOrNone. If saveRegs, save all registers.
+ Hack: a negative arg value indicates an abstract register, a non-negative value
+ indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <inline: false>
+ | regsToSave |
+ regsToSave := resultRegOrNone = NoReg
+ ifTrue: [regMask]
+ ifFalse: [regMask bitClear: (self registerMaskFor: resultRegOrNone)].
+ cStackAlignment > objectMemory wordSize ifTrue:
+ [backEnd
+ genAlignCStackSavingRegisters: regsToSave
+ numArgs: numArgs
+ wordAlignment: cStackAlignment / objectMemory wordSize].
+ backEnd
+ genSaveRegs: regsToSave;
+ genMarshallNArgs: numArgs floatArg: regOrConst0 floatArg: regOrConst1 floatArg: regOrConst2 floatArg: regOrConst3.
+ self CallFullRT: (self cCode: [aRoutine asUnsignedInteger]
+ inSmalltalk: [self simulatedTrampolineFor: aRoutine]).
+ resultRegOrNone ~= NoReg ifTrue:
+ [backEnd genWriteCResultIntoReg: resultRegOrNone].
+ numArgs > 0 ifTrue:
+ [backEnd genRemoveNFloatArgsFromStack: numArgs].
+ backEnd genRestoreRegs: regsToSave!
Item was added:
+ ----- Method: Cogit>>compileTrampolineFor:numArgs:arg:arg:arg:arg:regsToSave:pushLinkReg:floatResultReg: (in category 'initialization') -----
+ compileTrampolineFor: aRoutine numArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 regsToSave: regMask pushLinkReg: pushLinkReg floatResultReg: resultRegOrNone
+ "Generate a trampoline with up to four arguments. Generate either a call or a jump to aRoutine
+ as requested by callJumpBar. If generating a call and resultRegOrNone is not NoReg pass the C
+ result back in resultRegOrNone.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <inline: false>
+ self genSmalltalkToCStackSwitch: pushLinkReg.
+ self
+ compileCallFor: aRoutine
+ numArgs: numArgs
+ arg: regOrConst0
+ arg: regOrConst1
+ arg: regOrConst2
+ arg: regOrConst3
+ floatResultReg: resultRegOrNone
+ regsToSave: regMask.
+ backEnd genLoadStackPointers.
+ (pushLinkReg and: [backEnd hasLinkRegister])
+ ifTrue:
+ [backEnd hasPCRegister
+ ifTrue: [self PopR: PCReg]
+ ifFalse: [self PopR: LinkReg.
+ self RetN: 0]]
+ ifFalse: [self RetN: 0]!
Item was added:
+ ----- Method: Cogit>>compileTrampolineFor:numArgs:arg:arg:arg:arg:regsToSave:pushLinkReg:resultReg:resultReg: (in category 'initialization') -----
+ compileTrampolineFor: aRoutine numArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 regsToSave: regMask pushLinkReg: pushLinkReg resultReg: resultRegOrNone resultReg: resultReg2OrNone
+ "Generate a trampoline with up to four arguments. Generate either a call or a jump to aRoutine
+ as requested by callJumpBar. If generating a call and resultRegOrNone is not NoReg pass the C
+ result back in resultRegOrNone.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <inline: false>
+ self genSmalltalkToCStackSwitch: pushLinkReg.
+ self
+ compileCallFor: aRoutine
+ numArgs: numArgs
+ arg: regOrConst0
+ arg: regOrConst1
+ arg: regOrConst2
+ arg: regOrConst3
+ resultReg: resultRegOrNone
+ resultReg: resultReg2OrNone
+ regsToSave: regMask.
+ backEnd genLoadStackPointers.
+ (pushLinkReg and: [backEnd hasLinkRegister])
+ ifTrue:
+ [backEnd hasPCRegister
+ ifTrue: [self PopR: PCReg]
+ ifFalse: [self PopR: LinkReg.
+ self RetN: 0]]
+ ifFalse: [self RetN: 0]!
Item was added:
+ ----- Method: Cogit>>compileTrampolineFor:numArgs:floatArg:floatArg:floatArg:floatArg:regsToSave:pushLinkReg:resultReg: (in category 'initialization') -----
+ compileTrampolineFor: aRoutine numArgs: numArgs floatArg: regOrConst0 floatArg: regOrConst1 floatArg: regOrConst2 floatArg: regOrConst3 regsToSave: regMask pushLinkReg: pushLinkReg resultReg: resultRegOrNone
+ "Generate a trampoline with up to four arguments. Generate either a call or a jump to aRoutine
+ as requested by callJumpBar. If generating a call and resultRegOrNone is not NoReg pass the C
+ result back in resultRegOrNone.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <inline: false>
+ self genSmalltalkToCStackSwitch: pushLinkReg.
+ self
+ compileCallFor: aRoutine
+ numArgs: numArgs
+ floatArg: regOrConst0
+ floatArg: regOrConst1
+ floatArg: regOrConst2
+ floatArg: regOrConst3
+ resultReg: resultRegOrNone
+ regsToSave: regMask.
+ backEnd genLoadStackPointers.
+ (pushLinkReg and: [backEnd hasLinkRegister])
+ ifTrue:
+ [backEnd hasPCRegister
+ ifTrue: [self PopR: PCReg]
+ ifFalse: [self PopR: LinkReg.
+ self RetN: 0]]
+ ifFalse: [self RetN: 0]!
Item was changed:
----- Method: Cogit>>extBBytecode (in category 'bytecode generators') -----
extBBytecode
"225 11100001 sbbbbbbb Extend B (Ext B = Ext B prev * 256 + Ext B)"
+ extB := (extB = 0 and: [extBFirstZero not and: [byte1 > 127]])
- extB := (extB = 0 and: [byte1 > 127])
ifTrue: [byte1 - 256]
ifFalse: [(extB bitShift: 8) + byte1].
+ extBFirstZero := extB = 0.
^0!
Item was added:
+ ----- Method: Cogit>>genFFICalloutTrampoline (in category 'initialization') -----
+ genFFICalloutTrampoline
+ <option: #LowcodeVM>
+ | startAddress |
+ opcodeIndex := 0.
+ backEnd hasLinkRegister ifTrue: [
+ self MoveR: LinkReg Aw: coInterpreter instructionPointerAddress
+ ] ifFalse: [
+ self PopR: ClassReg.
+ self MoveR: ClassReg Aw: coInterpreter instructionPointerAddress
+ ].
+
+ self CallR: TempReg.
+
+ backEnd hasLinkRegister ifTrue: [
+ self MoveAw: coInterpreter instructionPointerAddress R: LinkReg
+ ] ifFalse: [
+ self MoveAw: coInterpreter instructionPointerAddress R: ClassReg.
+ self PushR: ClassReg.
+ ].
+
+ self RetN: 0.
+
+ startAddress := methodZoneBase.
+ self outputInstructionsForGeneratedRuntimeAt: startAddress.
+ self recordGeneratedRunTime: 'ceFFICalloutTrampoline' address: startAddress.
+ self recordRunTimeObjectReferences.
+ ^ startAddress
+ !
Item was added:
+ ----- Method: Cogit>>genTrampolineFor:called:arg:floatResult: (in category 'initialization') -----
+ genTrampolineFor: aRoutine called: aString arg: regOrConst0 floatResult: resultReg
+ "Generate a trampoline with one argument that answers a result.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <var: #aString type: #'char *'>
+ ^self
+ genTrampolineFor: aRoutine
+ called: aString
+ numArgs: 1
+ arg: regOrConst0
+ arg: nil
+ arg: nil
+ arg: nil
+ regsToSave: self emptyRegisterMask
+ pushLinkReg: true
+ floatResultReg: resultReg
+ appendOpcodes: false!
Item was added:
+ ----- Method: Cogit>>genTrampolineFor:called:arg:result:result: (in category 'initialization') -----
+ genTrampolineFor: aRoutine called: aString arg: regOrConst0 result: resultReg result: resultReg2
+ "Generate a trampoline with one argument that answers a result.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <var: #aString type: #'char *'>
+ ^self
+ genTrampolineFor: aRoutine
+ called: aString
+ numArgs: 1
+ arg: regOrConst0
+ arg: nil
+ arg: nil
+ arg: nil
+ regsToSave: self emptyRegisterMask
+ pushLinkReg: true
+ resultReg: resultReg
+ resultReg: resultReg2
+ appendOpcodes: false!
Item was added:
+ ----- Method: Cogit>>genTrampolineFor:called:floatArg:result: (in category 'initialization') -----
+ genTrampolineFor: aRoutine called: aString floatArg: regOrConst0 result: resultReg
+ "Generate a trampoline with one argument that answers a result.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <var: #aString type: #'char *'>
+ ^self
+ genTrampolineFor: aRoutine
+ called: aString
+ numArgs: 1
+ floatArg: regOrConst0
+ floatArg: nil
+ floatArg: nil
+ floatArg: nil
+ regsToSave: self emptyRegisterMask
+ pushLinkReg: true
+ resultReg: resultReg
+ appendOpcodes: false!
Item was added:
+ ----- Method: Cogit>>genTrampolineFor:called:numArgs:arg:arg:arg:arg:regsToSave:pushLinkReg:floatResultReg:appendOpcodes: (in category 'initialization') -----
+ genTrampolineFor: aRoutine called: trampolineName numArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 regsToSave: regMask pushLinkReg: pushLinkReg floatResultReg: resultRegOrNone appendOpcodes: appendBoolean
+ "Generate a trampoline with up to four arguments. Generate either a call or a jump to aRoutineOrNil
+ as requested by callJumpBar. If generating a call and resultRegOrNone is not NoReg pass the C result
+ back in resultRegOrNone.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <var: #trampolineName type: #'char *'>
+ | startAddress |
+ <inline: false>
+ startAddress := methodZoneBase.
+ appendBoolean ifFalse:
+ [self zeroOpcodeIndex].
+ self compileTrampolineFor: aRoutine
+ numArgs: numArgs
+ arg: regOrConst0
+ arg: regOrConst1
+ arg: regOrConst2
+ arg: regOrConst3
+ regsToSave: regMask
+ pushLinkReg: pushLinkReg
+ floatResultReg: resultRegOrNone.
+ self outputInstructionsForGeneratedRuntimeAt: startAddress.
+ self recordGeneratedRunTime: trampolineName address: startAddress.
+ self recordRunTimeObjectReferences.
+ ^startAddress!
Item was added:
+ ----- Method: Cogit>>genTrampolineFor:called:numArgs:arg:arg:arg:arg:regsToSave:pushLinkReg:resultReg:resultReg:appendOpcodes: (in category 'initialization') -----
+ genTrampolineFor: aRoutine called: trampolineName numArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 regsToSave: regMask pushLinkReg: pushLinkReg resultReg: resultRegOrNone resultReg: resultReg2OrNone appendOpcodes: appendBoolean
+ "Generate a trampoline with up to four arguments. Generate either a call or a jump to aRoutineOrNil
+ as requested by callJumpBar. If generating a call and resultRegOrNone is not NoReg pass the C result
+ back in resultRegOrNone.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <var: #trampolineName type: #'char *'>
+ | startAddress |
+ <inline: false>
+ startAddress := methodZoneBase.
+ appendBoolean ifFalse:
+ [self zeroOpcodeIndex].
+ self compileTrampolineFor: aRoutine
+ numArgs: numArgs
+ arg: regOrConst0
+ arg: regOrConst1
+ arg: regOrConst2
+ arg: regOrConst3
+ regsToSave: regMask
+ pushLinkReg: pushLinkReg
+ resultReg: resultRegOrNone
+ resultReg: resultReg2OrNone.
+ self outputInstructionsForGeneratedRuntimeAt: startAddress.
+ self recordGeneratedRunTime: trampolineName address: startAddress.
+ self recordRunTimeObjectReferences.
+ ^startAddress!
Item was added:
+ ----- Method: Cogit>>genTrampolineFor:called:numArgs:floatArg:floatArg:floatArg:floatArg:regsToSave:pushLinkReg:resultReg:appendOpcodes: (in category 'initialization') -----
+ genTrampolineFor: aRoutine called: trampolineName numArgs: numArgs floatArg: regOrConst0 floatArg: regOrConst1 floatArg: regOrConst2 floatArg: regOrConst3 regsToSave: regMask pushLinkReg: pushLinkReg resultReg: resultRegOrNone appendOpcodes: appendBoolean
+ "Generate a trampoline with up to four arguments. Generate either a call or a jump to aRoutineOrNil
+ as requested by callJumpBar. If generating a call and resultRegOrNone is not NoReg pass the C result
+ back in resultRegOrNone.
+ Hack: a negative value indicates an abstract register, a non-negative value indicates a constant."
+ <var: #aRoutine type: #'void *'>
+ <var: #trampolineName type: #'char *'>
+ | startAddress |
+ <inline: false>
+ startAddress := methodZoneBase.
+ appendBoolean ifFalse:
+ [self zeroOpcodeIndex].
+ self compileTrampolineFor: aRoutine
+ numArgs: numArgs
+ floatArg: regOrConst0
+ floatArg: regOrConst1
+ floatArg: regOrConst2
+ floatArg: regOrConst3
+ regsToSave: regMask
+ pushLinkReg: pushLinkReg
+ resultReg: resultRegOrNone.
+ self outputInstructionsForGeneratedRuntimeAt: startAddress.
+ self recordGeneratedRunTime: trampolineName address: startAddress.
+ self recordRunTimeObjectReferences.
+ ^startAddress!
Item was changed:
----- Method: Cogit>>generateRunTimeTrampolines (in category 'initialization') -----
generateRunTimeTrampolines
"Generate the run-time entries at the base of the native code zone and update the base."
ceSendMustBeBooleanAddFalseTrampoline := self genMustBeBooleanTrampolineFor: objectMemory falseObject
called: 'ceSendMustBeBooleanAddFalseTrampoline'.
ceSendMustBeBooleanAddTrueTrampoline := self genMustBeBooleanTrampolineFor: objectMemory trueObject
called: 'ceSendMustBeBooleanAddTrueTrampoline'.
ceNonLocalReturnTrampoline := self genNonLocalReturnTrampoline.
ceCheckForInterruptTrampoline := self genCheckForInterruptsTrampoline.
"Neither of the context inst var access trampolines save registers. Their operation could cause
arbitrary update of stack frames, so the assumption is that callers flush the stack before calling
the context inst var access trampolines, and that everything except the result is dead afterwards."
ceFetchContextInstVarTrampoline := self genTrampolineFor: #ceContext:instVar:
called: 'ceFetchContextInstVarTrampoline'
arg: ReceiverResultReg
arg: SendNumArgsReg
result: SendNumArgsReg.
ceStoreContextInstVarTrampoline := self genTrampolineFor: #ceContext:instVar:value:
called: 'ceStoreContextInstVarTrampoline'
arg: ReceiverResultReg
arg: SendNumArgsReg
arg: ClassReg
result: ReceiverResultReg. "to keep ReceiverResultReg live.".
ceCannotResumeTrampoline := self genTrampolineFor: #ceCannotResume
called: 'ceCannotResumeTrampoline'.
"These two are unusual; they are reached by return instructions."
ceBaseFrameReturnTrampoline := self genReturnTrampolineFor: #ceBaseFrameReturn:
called: 'ceBaseFrameReturnTrampoline'
arg: ReceiverResultReg.
ceReturnToInterpreterTrampoline := self
genReturnTrampolineFor: #ceReturnToInterpreter:
called: 'ceReturnToInterpreterTrampoline'
+ arg: ReceiverResultReg.
+ ceMallocTrampoline := self genTrampolineFor: #ceMalloc:
+ called: 'ceMallocTrampoline'
+ arg: ReceiverResultReg
+ result: TempReg.
+ ceFreeTrampoline := self genTrampolineFor: #ceFree:
+ called: 'ceFreeTrampoline'
+ arg: ReceiverResultReg.
+ self cppIf: LowcodeVM ifTrue: [
+ ceFFICalloutTrampoline := self genFFICalloutTrampoline.
+ ]!
- arg: ReceiverResultReg!
Item was changed:
----- Method: Cogit>>scanBlock: (in category 'compile abstract instructions') -----
scanBlock: blockStart
"Scan the block to determine if the block needs a frame or not"
| descriptor pc end framelessStackDelta nExts |
<var: #blockStart type: #'BlockStart *'>
<var: #descriptor type: #'BytecodeDescriptor *'>
needsFrame := false.
methodOrBlockNumArgs := blockStart numArgs.
inBlock := InVanillaBlock.
pc := blockStart startpc.
end := blockStart startpc + blockStart span.
framelessStackDelta := nExts := extA := extB := 0.
+ extBFirstZero := false.
[pc < end] whileTrue:
[byte0 := (objectMemory fetchByte: pc ofObject: methodObj) + bytecodeSetOffset.
descriptor := self generatorAt: byte0.
descriptor isExtension ifTrue:
[self loadSubsequentBytesForDescriptor: descriptor at: pc.
self perform: descriptor generator].
needsFrame ifFalse:
[(descriptor needsFrameFunction isNil
or: [self perform: descriptor needsFrameFunction with: framelessStackDelta])
ifTrue: [needsFrame := true]
ifFalse: [framelessStackDelta := framelessStackDelta + descriptor stackDelta]].
objectRepresentation maybeNoteDescriptor: descriptor blockStart: blockStart.
pc := self nextBytecodePCFor: descriptor at: pc exts: nExts in: methodObj.
descriptor isExtension
ifTrue: [nExts := nExts + 1]
ifFalse: [nExts := extA := extB := 0]].
needsFrame ifFalse:
[framelessStackDelta < 0 ifTrue:
[self error: 'negative stack delta in block; block contains bogus code or internal error'].
[framelessStackDelta > 0] whileTrue:
[descriptor := self generatorAt: (objectMemory fetchByte: blockStart startpc ofObject: methodObj) + bytecodeSetOffset.
descriptor generator ~~ #genPushConstantNilBytecode ifTrue:
[self error: 'frameless block doesn''t start with enough pushNils'].
blockStart
startpc: blockStart startpc + descriptor numBytes;
span: blockStart span - descriptor numBytes.
framelessStackDelta := framelessStackDelta - 1]].
^0!
Item was changed:
----- Method: Cogit>>scanMethod (in category 'compile abstract instructions') -----
scanMethod
"Scan the method (and all embedded blocks) to determine
- what the last bytecode is; extra bytes at the end of a method are used to encode things like source pointers or temp names
- if the method needs a frame or not
- what are the targets of any backward branches.
- how many blocks it creates
- if it contans an unknown bytecode
Answer the block count or on error a negative error code"
| latestContinuation nExts descriptor pc numBlocks distance targetPC framelessStackDelta |
<var: #descriptor type: #'BytecodeDescriptor *'>
needsFrame := false.
NewspeakVM ifTrue:
[numIRCs := 0].
(primitiveIndex > 0
and: [coInterpreter isQuickPrimitiveIndex: primitiveIndex]) ifTrue:
[^0].
pc := latestContinuation := initialPC.
numBlocks := framelessStackDelta := nExts := extA := extB := 0.
+ extBFirstZero := false.
[pc <= endPC] whileTrue:
[byte0 := (objectMemory fetchByte: pc ofObject: methodObj) + bytecodeSetOffset.
descriptor := self generatorAt: byte0.
descriptor isExtension ifTrue:
[descriptor opcode = Nop ifTrue: "unknown bytecode tag; see Cogit class>>#generatorTableFrom:"
[^EncounteredUnknownBytecode].
self loadSubsequentBytesForDescriptor: descriptor at: pc.
self perform: descriptor generator].
(descriptor isReturn
and: [pc >= latestContinuation]) ifTrue:
[endPC := pc].
needsFrame ifFalse:
[(descriptor needsFrameFunction isNil
or: [self perform: descriptor needsFrameFunction with: framelessStackDelta])
ifTrue: [needsFrame := true]
ifFalse: [framelessStackDelta := framelessStackDelta + descriptor stackDelta]].
descriptor isBranch ifTrue:
[distance := self spanFor: descriptor at: pc exts: nExts in: methodObj.
targetPC := pc + descriptor numBytes + distance.
(self isBackwardBranch: descriptor at: pc exts: nExts in: methodObj)
ifTrue: [self initializeFixupAt: targetPC - initialPC]
ifFalse: [latestContinuation := latestContinuation max: targetPC]].
descriptor isBlockCreation ifTrue:
[numBlocks := numBlocks + 1.
distance := self spanFor: descriptor at: pc exts: nExts in: methodObj.
targetPC := pc + descriptor numBytes + distance.
latestContinuation := latestContinuation max: targetPC].
self cppIf: NewspeakVM ifTrue:
[descriptor hasIRC ifTrue:
[numIRCs := numIRCs + 1]].
pc := pc + descriptor numBytes.
descriptor isExtension
ifTrue: [nExts := nExts + 1]
ifFalse: [nExts := extA := extB := 0]].
^numBlocks!
Item was changed:
----- Method: Cogit>>setInterpreter: (in category 'initialization') -----
setInterpreter: aCoInterpreter
"Initialization of the code generator in the simulator.
These objects already exist in the generated C VM
or are used only in the simulation."
<doNotGenerate>
coInterpreter := aCoInterpreter.
objectMemory := aCoInterpreter objectMemory.
threadManager := aCoInterpreter threadManager. "N.B. may be nil"
methodZone := CogMethodZone new.
objectRepresentation := objectMemory objectRepresentationClass
forCogit: self methodZone: methodZone.
methodZone setInterpreter: aCoInterpreter
objectRepresentation: objectRepresentation
cogit: self.
generatorTable := self class generatorTable.
processor := ProcessorClass new.
simulatedAddresses := Dictionary new.
simulatedTrampolines := Dictionary new.
simulatedVariableGetters := Dictionary new.
simulatedVariableSetters := Dictionary new.
traceStores := 0.
traceFlags := (self class initializationOptions at: #recordPrimTrace ifAbsent: [true])
ifTrue: [8] "record prim trace on by default (see Cogit class>>decareCVarsIn:)"
ifFalse: [0].
debugPrimCallStackOffset := 0.
singleStep := printRegisters := printInstructions := clickConfirm := false.
backEnd := CogCompilerClass for: self.
methodLabel := CogCompilerClass for: self.
(literalsManager := backEnd class literalsManagerClass new) cogit: self.
ordinarySendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
superSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
BytecodeSetHasDirectedSuperSend ifTrue:
[directedSuperSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines)].
NewspeakVM ifTrue:
[selfSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
dynamicSuperSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
implicitReceiverSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
outerSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines)].
"debug metadata"
objectReferencesInRuntime := CArrayAccessor on: (Array new: NumObjRefsInRuntime).
runtimeObjectRefIndex := 0.
"debug metadata"
trampolineAddresses := CArrayAccessor on: (Array new: NumTrampolines * 2).
trampolineTableIndex := 0.
extA := extB := 0.
+ extBFirstZero := false.
compilationTrace ifNil: [compilationTrace := self class initializationOptions at: #compilationTrace ifAbsent: [0]].
debugOpcodeIndices := self class initializationOptions at: #debugOpcodeIndices ifAbsent: [Set new].
debugBytecodePointers := self class initializationOptions at: #debugBytecodePointers ifAbsent: [Set new]!
Item was added:
+ ----- Method: CurrentImageCoInterpreterFacade>>nativeStackPointerAddress (in category 'accessing') -----
+ nativeStackPointerAddress
+ ^self addressForLabel: #nativeStackPointer!
Item was added:
+ ----- Method: CurrentImageCoInterpreterFacade>>shadowCallStackAddress (in category 'accessing') -----
+ shadowCallStackAddress
+ ^self addressForLabel: #shadowCallStackAddress!
Item was changed:
----- Method: CurrentImageCoInterpreterFacade>>splObj: (in category 'accessing') -----
splObj: splObjIndex
^splObjIndex caseOf: {
[ClassArray] -> [self oopForObject: Array].
[ClassCharacter] -> [self oopForObject: Character].
[ClassLargeNegativeInteger] -> [self oopForObject: LargeNegativeInteger].
[ClassLargePositiveInteger] -> [self oopForObject: LargePositiveInteger].
[ClassSmallInteger] -> [self oopForObject: SmallInteger].
+ [CompactClasses] -> [self oopForObject: Smalltalk compactClassesArray].
+ [LowcodeContextMark] -> [self oopForObject: (Smalltalk globals at: #LowcodeNativeContext ifPresent: [:cls | cls signalingObject ]) ]
- [CompactClasses] -> [self oopForObject: Smalltalk compactClassesArray]
}!
Item was added:
+ ----- Method: CurrentImageCoInterpreterFacadeForSpurObjectRepresentation>>defaultNativeStackFrameSize (in category 'accessing') -----
+ defaultNativeStackFrameSize
+ ^ coInterpreter defaultNativeStackFrameSize!
Item was changed:
----- Method: ObjectMemory class>>initializeSpecialObjectIndices (in category 'initialization') -----
initializeSpecialObjectIndices
"Initialize indices into specialObjects array."
NilObject := 0.
FalseObject := 1.
TrueObject := 2.
SchedulerAssociation := 3.
ClassBitmap := 4.
ClassSmallInteger := 5.
ClassByteString := ClassString := 6. "N.B. Actually class ByteString"
ClassArray := 7.
"SmalltalkDictionary := 8." "Do not delete!!"
ClassFloat := 9.
ClassMethodContext := 10.
ClassBlockContext := 11.
ClassPoint := 12.
ClassLargePositiveInteger := 13.
TheDisplay := 14.
ClassMessage := 15.
"ClassCompiledMethod := 16. unused by the VM"
TheLowSpaceSemaphore := 17.
ClassSemaphore := 18.
ClassCharacter := 19.
SelectorDoesNotUnderstand := 20.
SelectorCannotReturn := 21.
ProcessSignalingLowSpace := 22. "was TheInputSemaphore"
SpecialSelectors := 23.
CharacterTable := 24.
SelectorMustBeBoolean := 25.
ClassByteArray := 26.
"ClassProcess := 27. unused"
CompactClasses := 28.
TheTimerSemaphore := 29.
TheInterruptSemaphore := 30.
SelectorCannotInterpret := 34.
"Was MethodContextProto := 35."
ClassBlockClosure := 36.
ClassFullBlockClosure := 37. "Was BlockContextProto := 37."
ExternalObjectsArray := 38.
ClassMutex := 39.
"Was: ClassTranslatedMethod := 40."
ProcessInExternalCodeTag := 40.
TheFinalizationSemaphore := 41.
ClassLargeNegativeInteger := 42.
ClassExternalAddress := 43.
ClassExternalStructure := 44.
ClassExternalData := 45.
ClassExternalFunction := 46.
ClassExternalLibrary := 47.
SelectorAboutToReturn := 48.
SelectorRunWithIn := 49.
SelectorAttemptToAssign := 50.
"PrimErrTableIndex := 51. in VMClass class>>initializePrimitiveErrorCodes"
ClassAlien := 52.
SelectorInvokeCallback := 53.
ClassUnsafeAlien := 54.
ClassWeakFinalizer := 55.
ForeignCallbackProcess := 56.
SelectorUnknownBytecode := 57.
SelectorCounterTripped := 58.
+ SelectorSistaTrap := 59.
+
+ LowcodeContextMark := 60.
+ LowcodeNativeContextClass := 61.
- SelectorSistaTrap := 59
!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>frameOffsetOfNativeFrameMark (in category 'bytecode generator support') -----
+ frameOffsetOfNativeFrameMark
+ <option: #LowcodeVM>
+ ^ FoxMFReceiver - BytesPerWord!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>frameOffsetOfNativeFramePointer (in category 'bytecode generator support') -----
+ frameOffsetOfNativeFramePointer
+ <option: #LowcodeVM>
+ ^ FoxMFReceiver - (BytesPerWord*3)!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>frameOffsetOfNativeStackPointer (in category 'bytecode generator support') -----
+ frameOffsetOfNativeStackPointer
+ <option: #LowcodeVM>
+ ^ FoxMFReceiver - (BytesPerWord*4)!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>frameOffsetOfPreviousNativeStackPointer (in category 'bytecode generator support') -----
+ frameOffsetOfPreviousNativeStackPointer
+ <option: #LowcodeVM>
+ ^ FoxMFReceiver - (BytesPerWord*2)!
Item was changed:
----- Method: SimpleStackBasedCogit>>fullBlockEntryOffset (in category 'accessing') -----
fullBlockEntryOffset
<api>
- <cmacro>
^cbEntryOffset!
Item was changed:
----- Method: SimpleStackBasedCogit>>fullBlockNoContextSwitchEntryOffset (in category 'accessing') -----
fullBlockNoContextSwitchEntryOffset
<api>
- <cmacro>
^cbNoSwitchEntryOffset!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>loadNativeArgumentAddress:to: (in category 'bytecode generator support') -----
+ loadNativeArgumentAddress: baseOffset to: reg
+ <option: #LowcodeVM>
+ self MoveMw: self frameOffsetOfPreviousNativeStackPointer r: FPReg R: reg.
+ self AddCq: baseOffset - 1 R: reg.!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>loadNativeFramePointerInto: (in category 'bytecode generator support') -----
+ loadNativeFramePointerInto: reg
+ <option: #LowcodeVM>
+ self MoveMw: self frameOffsetOfNativeFramePointer r: FPReg R: reg!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>loadNativeLocalAddress:to: (in category 'bytecode generator support') -----
+ loadNativeLocalAddress: baseOffset to: reg
+ <option: #LowcodeVM>
+ self MoveMw: self frameOffsetOfNativeFramePointer r: FPReg R: reg.
+ self AddCq: baseOffset - 1 R: reg.!
Item was changed:
----- Method: Spur32BitMemoryManager>>floatObjectOf: (in category 'interpreter access') -----
floatObjectOf: aFloat
| newFloatObj |
<inline: false>
<var: #aFloat type: #double>
+ <api>
newFloatObj := self
eeInstantiateSmallClassIndex: ClassFloatCompactIndex
format: self firstLongFormat
numSlots: (self sizeof: #double) / self bytesPerOop.
self storeFloatAt: newFloatObj + self baseHeaderSize from: aFloat.
^newFloatObj!
Item was changed:
----- Method: Spur64BitMemoryManager>>floatObjectOf: (in category 'interpreter access') -----
floatObjectOf: aFloat
| newFloatObj |
<inline: false>
<var: #aFloat type: #double>
+ <api>
(self isSmallFloatValue: aFloat) ifTrue:
[^self smallFloatObjectOf: aFloat].
newFloatObj := self
eeInstantiateSmallClassIndex: ClassFloatCompactIndex
format: self firstLongFormat
numSlots: (self sizeof: #double) / self bytesPerOop.
self storeFloatAt: newFloatObj + self baseHeaderSize from: aFloat.
^newFloatObj!
Item was changed:
----- Method: SpurMemoryManager class>>initializeSpecialObjectIndices (in category 'class initialization') -----
initializeSpecialObjectIndices
"Initialize indices into specialObjects array."
NilObject := 0.
FalseObject := 1.
TrueObject := 2.
SchedulerAssociation := 3.
ClassBitmap := 4.
ClassSmallInteger := 5.
ClassByteString := ClassString := 6. "N.B. Actually class ByteString"
ClassArray := 7.
"SmalltalkDictionary := 8." "Do not delete!!"
ClassFloat := 9.
ClassMethodContext := 10.
"ClassBlockContext := 11. unused by the VM"
ClassPoint := 12.
ClassLargePositiveInteger := 13.
TheDisplay := 14.
ClassMessage := 15.
"ClassCompiledMethod := 16. unused by the VM"
TheLowSpaceSemaphore := 17.
ClassSemaphore := 18.
ClassCharacter := 19.
SelectorDoesNotUnderstand := 20.
SelectorCannotReturn := 21.
ProcessSignalingLowSpace := 22. "was TheInputSemaphore"
SpecialSelectors := 23.
CharacterTable := nil. "Must be unused by the VM"
SelectorMustBeBoolean := 25.
ClassByteArray := 26.
"ClassProcess := 27. unused"
CompactClasses := 28.
TheTimerSemaphore := 29.
TheInterruptSemaphore := 30.
SelectorCannotInterpret := 34.
"Was MethodContextProto := 35."
ClassBlockClosure := 36.
"Was BlockContextProto := 37."
ExternalObjectsArray := 38.
ClassMutex := 39.
"Was: ClassTranslatedMethod := 40."
ProcessInExternalCodeTag := 40.
TheFinalizationSemaphore := 41.
ClassLargeNegativeInteger := 42.
ClassExternalAddress := 43.
ClassExternalStructure := 44.
ClassExternalData := 45.
ClassExternalFunction := 46.
ClassExternalLibrary := 47.
SelectorAboutToReturn := 48.
SelectorRunWithIn := 49.
SelectorAttemptToAssign := 50.
"PrimErrTableIndex := 51. in VMClass class>>initializePrimitiveErrorCodes"
ClassAlien := 52.
SelectorInvokeCallback := 53.
ClassUnsafeAlien := 54.
ClassWeakFinalizer := 55.
ForeignCallbackProcess := 56.
SelectorUnknownBytecode := 57.
SelectorCounterTripped := 58.
+ SelectorSistaTrap := 59.
+
+ LowcodeContextMark := 60.
+ LowcodeNativeContextClass := 61.!
- SelectorSistaTrap := 59!
Item was changed:
----- Method: StackDepthFinder>>stackPointers (in category 'accessing') -----
stackPointers
"Collect the stack depth for each bytecode in the method.
For the convenience of clients, write the stack depth for extended bytecodes
to the bytecode pc, as well as the bytecocdes' extensions' pcs."
| method stackPointers end |
"endPC +1 because of full blocks that can end with NLR effectively mapping the pc right after the end PC"
stackPointers := Array new: (end := (method := self method) endPC) + 1.
encoderClass ifNil: [encoderClass := method encoderClass].
[pc <= end] whileTrue:
[stackPointers at: pc put: stackp.
encoderClass extensionsAt: pc in: method into:
[:extA :extB :delta|
+ 2 to: delta by: 2 do: [ :dlt |
+ stackPointers at: pc + dlt put: stackp]].
- delta > 0 ifTrue:
- [stackPointers at: pc + delta put: stackp]].
self interpretNextInstructionFor: self].
- stackPointers at: end + 1 put: (stackPointers at: end).
^stackPointers!
Item was changed:
InterpreterPrimitives subclass: #StackInterpreter
+ instanceVariableNames: 'currentBytecode bytecodeSetSelector localFP localIP localSP stackLimit stackPage stackPages method instructionPointer stackPointer framePointer localReturnValue localAbsentReceiver localAbsentReceiverOrZero extA extB extBFirstZero primitiveFunctionPointer methodCache nsMethodCache atCache lkupClassTag lkupClass methodDictLinearSearchLimit highestRunnableProcessPriority nextWakeupUsecs nextPollUsecs inIOProcessEvents interruptKeycode interruptPending savedWindowSize imageHeaderFlags fullScreenFlag deferDisplayUpdates pendingFinalizationSignals extraVMMemory interpreterProxy showSurfaceFn primitiveTable primitiveAccessorDepthTable externalPrimitiveTable externalPrimitiveTableFirstFreeIndex overflowedPage extraFramesToMoveOnOverflow globalSessionID jmpBuf jmpDepth suspendedCallbacks suspendedMethods numStackPages desiredNumStackPages desiredEdenBytes classNameIndex thisClassIndex metaclassNumSlots interruptCheckChain suppressHeartbeatFlag breakSelector breakSelectorLength longRunningPrimitiveCheckMethod longRunningPrimitiveCheckSemaphore longRunningPrimitiveStartUsecs longRunningPrimitiveStopUsecs longRunningPrimitiveGCUsecs longRunningPrimitiveCheckSequenceNumber longRunningPrimitiveSignalUndelivered checkAllocFiller tempOop tempOop2 tempOop3 theUnknownShort the2ndUnknownShort imageFloatsBigEndian maxExtSemTabSizeSet lastMethodCacheProbeWrite gcSemaphoreIndex classByteArrayCompactIndex checkedPluginName statForceInterruptCheck statStackOverflow statStackPageDivorce statCheckForEvents statProcessSwitch statIOProcessEvents statPendingFinalizationSignals nativeSP nativeStackPointer lowcodeCalloutState shadowCallStackPointer'
- instanceVariableNames: 'currentBytecode bytecodeSetSelector localFP localIP localSP stackLimit stackPage stackPages method instructionPointer stackPointer framePointer localReturnValue localAbsentReceiver localAbsentReceiverOrZero extA extB primitiveFunctionPointer methodCache nsMethodCache atCache lkupClassTag lkupClass methodDictLinearSearchLimit highestRunnableProcessPriority nextWakeupUsecs nextPollUsecs inIOProcessEvents interruptKeycode interruptPending savedWindowSize imageHeaderFlags fullScreenFlag deferDisplayUpdates pendingFinalizationSignals extraVMMemory interpreterProxy showSurfaceFn primitiveTable primitiveAccessorDepthTable externalPrimitiveTable externalPrimitiveTableFirstFreeIndex overflowedPage extraFramesToMoveOnOverflow globalSessionID jmpBuf jmpDepth suspendedCallbacks suspendedMethods numStackPages desiredNumStackPages desiredEdenBytes classNameIndex thisClassIndex metaclassNumSlots interruptCheckChain suppressHeartbeatFlag breakSelector breakSelectorLength longRunningPrimitiveCheckMethod longRunningPrimitiveCheckSemaphore longRunningPrimitiveStartUsecs longRunningPrimitiveStopUsecs longRunningPrimitiveGCUsecs longRunningPrimitiveCheckSequenceNumber longRunningPrimitiveSignalUndelivered checkAllocFiller tempOop tempOop2 tempOop3 theUnknownShort the2ndUnknownShort imageFloatsBigEndian maxExtSemTabSizeSet lastMethodCacheProbeWrite gcSemaphoreIndex classByteArrayCompactIndex checkedPluginName statForceInterruptCheck statStackOverflow statStackPageDivorce statCheckForEvents statProcessSwitch statIOProcessEvents statPendingFinalizationSignals'
classVariableNames: 'AccessModifierPrivate AccessModifierProtected AccessModifierPublic AltBytecodeEncoderClassName AltLongStoreBytecode AlternateHeaderHasPrimFlag AlternateHeaderIsOptimizedFlag AlternateHeaderNumLiteralsMask AtCacheFixedFields AtCacheFmt AtCacheMask AtCacheOop AtCacheSize AtCacheTotalSize AtPutBase BytecodeEncoderClassName BytecodeTable CacheProbeMax DirBadPath DirEntryFound DirNoMoreEntries DumpStackOnLowSpace EnclosingMixinIndex EnclosingObjectIndex EnforceAccessControl FailImbalancedPrimitives LongStoreBytecode MaxExternalPrimitiveTableSize MaxJumpBuf MaxPrimitiveIndex MaxQuickPrimitiveIndex MethodHeaderArgCountShift MethodHeaderFlagBitPosition MethodHeaderTempCountShift MixinIndex PrimNumberDoExternalCall PrimNumberExternalCall PrimNumberFFICall PrimitiveExternalCallIndex PrimitiveTable StackPageReachedButUntraced StackPageTraceInvalid StackPageTraced StackPageUnreached V3PrimitiveBitsMask'
poolDictionaries: 'VMBasicConstants VMBytecodeConstants VMMethodCacheConstants VMObjectIndices VMSpurObjectRepresentationConstants VMSqueakClassIndices VMStackFrameOffsets'
category: 'VMMaker-Interpreter'!
!StackInterpreter commentStamp: 'eem 12/5/2014 11:32' prior: 0!
This class is a complete implementation of the Smalltalk-80 virtual machine, derived originally from the Blue Book specification but quite different in some areas. This VM supports Closures but *not* old-style BlockContexts.
It has been modernized with 32-bit pointers, better management of Contexts (see next item), and attention to variable use that allows the CCodeGenerator (qv) to keep, eg, the instruction pointer and stack pointer in registers as well as keeping most simple variables in a global array that seems to improve performance for most platforms.
The VM does not use Contexts directly. Instead Contexts serve as proxies for a more conventional stack format that is invisible to the image. There is considerable explanation at http://www.mirandabanda.org/cogblog/2009/01/14/under-cover-contexts-and-the-big-frame-up. The VM maintains a fixed-size stack zone divided into pages, each page being capable of holding several method/block activations. A send establishes a new frame in the current stack page, a return returns to the previous frame. This eliminates allocation/deallocation of contexts and the moving of receiver and arguments from caller to callee on each send/return. Contexts are created lazily when an activation needs a context (creating a block, explicit use of thisContext, access to sender when sender is a frame, or linking of stack pages together). Contexts are either conventional and heap-resident ("single") or "married" and serve as proxies for their corresponding frame or "widowed", meaning that their spouse frame has been returned from (died). A married context is specially marked (more details in the code) and refers to its frame. Likewise a married frame is specially marked and refers to its context.
In addition to SmallInteger arithmetic and Floats, the VM supports logic on 32-bit PositiveLargeIntegers, thus allowing it to simulate itself much more effectively than would otherwise be the case.
StackInterpreter and subclasses support multiple memory managers. Currently there are two. NewMemoryManager is a slightly refined version of ObjectMemory, and is the memory manager and garbage collector for the original Squeak object representation as described in "Back to the Future The Story of Squeak, A Practical Smalltalk Written in Itself", see http://ftp.squeak.org/docs/OOPSLA.Squeak.html. Spur is a faster, more regular object representation that is designed for more performance and functionality, and to have a common header format for both 32-bit and 64-bit versions. You can read about it in SpurMemoryManager's class comment. There is also a video of a presentation at ESUG 2014 (https://www.youtube.com/watch?v=k0nBNS1aHZ4), along with slides (http://www.slideshare.net/esug/spur-a-new-object-representation-for-cog?related=1).!
Item was changed:
----- Method: StackInterpreter class>>declareCVarsIn: (in category 'translation') -----
declareCVarsIn: aCCodeGenerator
| vmClass |
self class == thisContext methodClass ifFalse: [^self]. "Don't duplicate decls in subclasses"
vmClass := aCCodeGenerator vmClass. "Generate primitiveTable etc based on vmClass, not just StackInterpreter"
aCCodeGenerator
addHeaderFile:'<stddef.h> /* for e.g. alloca */';
addHeaderFile:'<setjmp.h>';
addHeaderFile:'<wchar.h> /* for wint_t */';
addHeaderFile:'"vmCallback.h"';
addHeaderFile:'"sqMemoryFence.h"';
addHeaderFile:'"dispdbg.h"'.
+ LowcodeVM ifTrue: [ aCCodeGenerator addHeaderFile:'"sqLowcodeFFI.h"'].
+
vmClass declareInterpreterVersionIn: aCCodeGenerator defaultName: 'Stack'.
aCCodeGenerator
var: #interpreterProxy type: #'struct VirtualMachine*'.
aCCodeGenerator
declareVar: #sendTrace type: 'volatile int';
declareVar: #byteCount type: 'unsigned long'.
"These need to be pointers or unsigned."
self declareC: #(instructionPointer method newMethod)
as: #usqInt
in: aCCodeGenerator.
"These are all pointers; char * because Slang has no support for C pointer arithmetic."
+ self declareC: #(localIP localSP localFP nativeSP stackPointer framePointer stackLimit breakSelector nativeStackPointer nativeFramePointer shadowCallStack)
- self declareC: #(localIP localSP localFP stackPointer framePointer stackLimit breakSelector)
as: #'char *'
in: aCCodeGenerator.
aCCodeGenerator
var: #breakSelectorLength
declareC: 'sqInt breakSelectorLength = MinSmallInteger'.
self declareC: #(stackPage overflowedPage)
as: #'StackPage *'
in: aCCodeGenerator.
aCCodeGenerator removeVariable: 'stackPages'. "this is an implicit receiver in the translated code."
NewspeakVM ifFalse:
[aCCodeGenerator
removeVariable: 'localAbsentReceiver';
removeVariable: 'localAbsentReceiverOrZero';
removeVariable: 'nsMethodCache'].
"This defines bytecodeSetSelector as 0 if MULTIPLEBYTECODESETS
is not defined, for the benefit of the interpreter on slow machines."
aCCodeGenerator addConstantForBinding: (self bindingOf: #MULTIPLEBYTECODESETS).
MULTIPLEBYTECODESETS == false ifTrue:
[aCCodeGenerator
removeVariable: 'extA';
removeVariable: 'extB';
removeVariable: 'bytecodeSetSelector'].
aCCodeGenerator
var: #methodCache
declareC: 'long methodCache[MethodCacheSize + 1 /* ', (MethodCacheSize + 1) printString, ' */]'.
aCCodeGenerator
var: #nsMethodCache
declareC: 'long nsMethodCache[NSMethodCacheSize + 1 /* ', (NSMethodCacheSize + 1) printString, ' */]'.
AtCacheTotalSize isInteger ifTrue:
[aCCodeGenerator
var: #atCache
declareC: 'sqInt atCache[AtCacheTotalSize + 1 /* ', (AtCacheTotalSize + 1) printString, ' */]'].
aCCodeGenerator
var: #primitiveTable
declareC: 'void (*primitiveTable[MaxPrimitiveIndex + 2 /* ', (MaxPrimitiveIndex + 2) printString, ' */])(void) = ', vmClass primitiveTableString.
vmClass primitiveTable do:
[:symbolOrNot|
(symbolOrNot isSymbol
and: [symbolOrNot ~~ #primitiveFail]) ifTrue:
[(aCCodeGenerator methodNamed: symbolOrNot) ifNotNil:
[:tMethod| tMethod returnType: #void]]].
vmClass objectMemoryClass hasSpurMemoryManagerAPI
ifTrue:
[aCCodeGenerator
var: #primitiveAccessorDepthTable
type: 'signed char'
sizeString: 'MaxPrimitiveIndex + 2 /* ', (MaxPrimitiveIndex + 2) printString, ' */'
array: vmClass primitiveAccessorDepthTable]
ifFalse:
[aCCodeGenerator removeVariable: #primitiveAccessorDepthTable].
aCCodeGenerator
var: #primitiveFunctionPointer
declareC: 'void (*primitiveFunctionPointer)()'.
aCCodeGenerator
var: #externalPrimitiveTable
declareC: 'void (*externalPrimitiveTable[MaxExternalPrimitiveTableSize + 1 /* ', (MaxExternalPrimitiveTableSize + 1) printString, ' */])(void)'.
aCCodeGenerator var: #showSurfaceFn type: #'void *'.
aCCodeGenerator
var: #jmpBuf
declareC: 'jmp_buf jmpBuf[MaxJumpBuf + 1 /* ', (MaxJumpBuf + 1) printString, ' */]'.
aCCodeGenerator
var: #suspendedCallbacks
declareC: 'usqInt suspendedCallbacks[MaxJumpBuf + 1 /* ', (MaxJumpBuf + 1) printString, ' */]'.
aCCodeGenerator
var: #suspendedMethods
declareC: 'usqInt suspendedMethods[MaxJumpBuf + 1 /* ', (MaxJumpBuf + 1) printString, ' */]'.
aCCodeGenerator
var: #interruptCheckChain
declareC: 'void (*interruptCheckChain)(void) = 0'.
self declareCAsUSqLong: #(nextPollUsecs nextWakeupUsecs longRunningPrimitiveGCUsecs
longRunningPrimitiveStartUsecs longRunningPrimitiveStopUsecs
"these are high-frequency enough that they're overflowing quite quickly on modern hardware"
statProcessSwitch statIOProcessEvents statForceInterruptCheck
statCheckForEvents statStackOverflow statStackPageDivorce)
in: aCCodeGenerator.
+ aCCodeGenerator var: #nextProfileTick type: #sqLong.
+
+ LowcodeVM ifTrue: [
+ aCCodeGenerator
+ var: #shadowCallStackPointer
+ type: #'char*'.
+ aCCodeGenerator
+ var: #lowcodeCalloutState
+ type: #'sqLowcodeCalloutState*'
+ ].!
- aCCodeGenerator var: #nextProfileTick type: #sqLong!
Item was added:
+ ----- Method: StackInterpreter>>allocateLowcodeCalloutState (in category 'inline primitive ffi abi') -----
+ allocateLowcodeCalloutState
+ <option: #LowcodeVM>
+ | calloutStateSize |
+ calloutStateSize := self sizeof: #'sqLowcodeCalloutState'.
+ shadowCallStackPointer := self cCoerce: ((self cCoerce: shadowCallStackPointer - calloutStateSize to: 'size_t') bitAnd: -16) to: 'char*'.
+ lowcodeCalloutState := self cCoerce: shadowCallStackPointer to: #'sqLowcodeCalloutState*'.
+ !
Item was changed:
----- Method: StackInterpreter>>callPrimitiveBytecode (in category 'miscellaneous bytecodes') -----
callPrimitiveBytecode
"V4: 249 11111001 i i i i i i i i jjjjjjjj Call Primitive #iiiiiiii + (jjjjjjjj * 256)
SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
V3/Spur: 139 10001011 i i i i i i i i jjjjjjjj Call Primitive #iiiiiiii + (jjjjjjjj * 256)"
"Note that we simply skip a callPrimitiveBytecode at the start of a method
that contains a primitive. This because methods like Context(Part)>>reset
have to be updated to skip the callPrimtiive bytecode otherwise."
self cppIf: SistaVM
ifTrue:
+ [| byte1 byte2 prim primSet header |
- [| byte1 byte2 prim header |
byte1 := self fetchByte.
byte2 := self fetchByte.
self fetchNextBytecode.
byte2 < 128 ifTrue:
[header := objectMemory methodHeaderOf: method.
((self methodHeaderHasPrimitive: header)
and: [localIP asUnsignedInteger
= (self initialPCForHeader: header method: method) + (self sizeOfCallPrimitiveBytecode: header)]) ifTrue:
[^self].
localIP := localIP - 3.
^self respondToUnknownBytecode].
prim := byte2 - 128 << 8 + byte1.
+ primSet := prim >> 13 bitAnd: 3.
+ prim := prim bitAnd: 8191.
+ primSet = 0 ifTrue: [
+
+ prim < 1000 ifTrue:
+ [^self nullaryInlinePrimitive: prim].
- prim < 1000 ifTrue:
- [^self nullaryInlinePrimitive: prim].
+ prim < 2000 ifTrue:
+ [^self unaryInlinePrimitive: prim - 1000].
- prim < 2000 ifTrue:
- [^self unaryInlinePrimitive: prim - 1000].
+ prim < 3000 ifTrue:
+ [^self binaryInlinePrimitive: prim - 2000].
- prim < 3000 ifTrue:
- [^self binaryInlinePrimitive: prim - 2000].
+ prim < 4000 ifTrue:
+ [^self trinaryInlinePrimitive: prim - 3000].
+ ].
+
+ self cppIf: LowcodeVM
+ ifTrue: [
+ primSet = 1 ifTrue: [
+ prim < 1000 ifTrue:
+ [^self lowcodeNullaryInlinePrimitive: prim].
- prim < 4000 ifTrue:
- [^self trinaryInlinePrimitive: prim - 3000].
+ prim < 2000 ifTrue:
+ [^self lowcodeUnaryInlinePrimitive: prim - 1000].
+
+ prim < 3000 ifTrue:
+ [^self lowcodeBinaryInlinePrimitive: prim - 2000].
+
+ prim < 4000 ifTrue:
+ [^self lowcodeTrinaryInlinePrimitive: prim - 3000].
+ ].
+ ].
+
+ localIP := localIP - 3.
+ ^self respondToUnknownBytecode]
- localIP := localIP - 3.
- ^self respondToUnknownBytecode]
ifFalse:
[| header |
header := objectMemory methodHeaderOf: method.
((self methodHeaderHasPrimitive: header)
and: [localIP asInteger = (self initialPCForHeader: header method: method)])
ifTrue:
[localIP := localIP + (self sizeOfCallPrimitiveBytecode: header) - 1.
^self fetchNextBytecode]
ifFalse:
[^self respondToUnknownBytecode]]!
Item was changed:
----- Method: StackInterpreter>>commonCallerReturn (in category 'return bytecodes') -----
commonCallerReturn
"Return to the previous context/frame (sender for method activations, caller for block activations)."
<sharedCodeInCase: #returnTopFromBlock>
+ | callersFPOrNull doWeHaveANativeFrame |
- | callersFPOrNull |
<var: #callersFPOrNull type: #'char *'>
+ "TODO: Store/restore the nativeSP more properly, when it exists"
+ self cppIf: LowcodeVM ifTrue: [
+ doWeHaveANativeFrame := self frameHasNativeFrame: localFP.
+ doWeHaveANativeFrame ifTrue: [
+ nativeStackPointer := (self nativePreviousStackPointerIn: localFP) - 1.
+ nativeSP := 0.
+ self setFrameHasNotNativeFrame: localFP.
+ ].
+ ].
+
callersFPOrNull := self frameCallerFP: localFP.
callersFPOrNull == 0 "baseFrame" ifTrue:
[self assert: localFP = stackPage baseFP.
^self baseFrameReturn].
localIP := self frameCallerSavedIP: localFP.
localSP := localFP + (self frameStackedReceiverOffset: localFP).
localFP := callersFPOrNull.
self setMethod: (self frameMethod: localFP).
self fetchNextBytecode.
self internalStackTopPut: localReturnValue!
Item was added:
+ ----- Method: StackInterpreter>>defaultNativeStackFrameSize (in category 'stack pages') -----
+ defaultNativeStackFrameSize
+ "default native stack frame size"
+ ^ 256!
Item was changed:
----- Method: StackInterpreter>>extBBytecode (in category 'miscellaneous bytecodes') -----
extBBytecode
"225 11100001 sbbbbbbb Extend B (Ext B = Ext B prev * 256 + Ext B)"
| byte |
byte := self fetchByte.
self fetchNextBytecode.
+ extB := (extB = 0 and: [extBFirstZero not and: [ byte > 127 ]])
- extB := (extB = 0 and: [byte > 127])
ifTrue: [byte - 256]
+ ifFalse: [(extB bitShift: 8) + byte].
+ extBFirstZero := extB = 0.!
- ifFalse: [(extB bitShift: 8) + byte]!
Item was added:
+ ----- Method: StackInterpreter>>frameHasNativeFrame: (in category 'frame access') -----
+ frameHasNativeFrame: theFP
+ "See encodeFrameFieldHasContext:numArgs:"
+ <inline: true>
+ <option: #LowcodeVM>
+ <var: #theFP type: #'char *'>
+ | markObject |
+ markObject := self temporary: (self frameNumArgs: theFP) in: theFP.
+
+ ^ markObject ~= objectMemory nilObject and: [ markObject = (objectMemory splObj: LowcodeContextMark)]!
Item was added:
+ ----- Method: StackInterpreter>>framePointerOfNativeArgument:in: (in category 'internal interpreter access') -----
+ framePointerOfNativeArgument: offset in: theFP
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: 'char*'>
+ <var: #theFP type: #'char*'>
+ ^ (self nativePreviousStackPointerIn: theFP) + offset - 1!
Item was added:
+ ----- Method: StackInterpreter>>framePointerOfNativeLocal:in: (in category 'internal interpreter access') -----
+ framePointerOfNativeLocal: offset in: theFP
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: 'char*'>
+ <var: #theFP type: #'char*'>
+ ^ (self nativeFramePointerIn: theFP) + offset - 1!
Item was changed:
----- Method: StackInterpreter>>initExtensions (in category 'simulation support') -----
initExtensions
<inline: true>
+ self cppIf: MULTIPLEBYTECODESETS ifTrue: [extA := extB := 0. extBFirstZero := false]!
- self cppIf: MULTIPLEBYTECODESETS ifTrue: [extA := extB := 0]!
Item was changed:
----- Method: StackInterpreter>>initializeInterpreter: (in category 'initialization') -----
initializeInterpreter: bytesToShift
"Initialize Interpreter state before starting execution of a new image."
interpreterProxy := self sqGetInterpreterProxy.
self dummyReferToProxy.
objectMemory initializeObjectMemory: bytesToShift.
self checkAssumedCompactClasses.
self initializeExtraClassInstVarIndices.
method := newMethod := objectMemory nilObject.
self cCode: '' inSmalltalk:
[breakSelectorLength ifNil:
[breakSelectorLength := objectMemory minSmallInteger]].
methodDictLinearSearchLimit := 8.
self initialCleanup.
+ self cppIf: LowcodeVM ifTrue: [ self setupNativeStack ].
profileSemaphore := profileProcess := profileMethod := objectMemory nilObject.
interruptKeycode := 2094. "cmd-. as used for Mac but no other OS"
[globalSessionID = 0] whileTrue:
[globalSessionID := self
cCode: [(self time: #NULL) + self ioMSecs]
inSmalltalk: [(Random new next * SmallInteger maxVal) asInteger]]!
Item was added:
+ ----- Method: StackInterpreter>>internalPopStackFloat32 (in category 'internal interpreter access') -----
+ internalPopStackFloat32
+ <option: #LowcodeVM>
+ <returnTypeC: #float>
+ <var: #topSingle type: #float>
+ "In the StackInterpreter stacks grow down."
+ | topSingle |
+ nativeSP := self nativeStackPointerIn: localFP.
+ topSingle := stackPages singleFloatAtPointer: nativeSP - 1.
+ nativeSP := self nativeStackPointerIn: localFP put: nativeSP + 4.
+ ^topSingle!
Item was added:
+ ----- Method: StackInterpreter>>internalPopStackFloat64 (in category 'internal interpreter access') -----
+ internalPopStackFloat64
+ <option: #LowcodeVM>
+ <returnTypeC: #double>
+ <var: #topDouble type: #double>
+ "In the StackInterpreter stacks grow down."
+ | topDouble |
+ nativeSP := self nativeStackPointerIn: localFP.
+ topDouble := stackPages floatAtPointer: nativeSP - 1.
+ nativeSP := self nativeStackPointerIn: localFP put: nativeSP + 8.
+ ^topDouble!
Item was added:
+ ----- Method: StackInterpreter>>internalPopStackInt32 (in category 'internal interpreter access') -----
+ internalPopStackInt32
+ <option: #LowcodeVM>
+ "In the StackInterpreter stacks grow down."
+ | topInt32 |
+ nativeSP := self nativeStackPointerIn: localFP.
+ topInt32 := stackPages int32AtPointer: nativeSP - 1.
+ nativeSP := self nativeStackPointerIn: localFP put: nativeSP + BytesPerOop.
+ ^topInt32!
Item was added:
+ ----- Method: StackInterpreter>>internalPopStackInt64 (in category 'internal interpreter access') -----
+ internalPopStackInt64
+ <option: #LowcodeVM>
+ <returnTypeC: #sqLong>
+ <var: #topInt64 type: #sqLong>
+ "In the StackInterpreter stacks grow down."
+ | topInt64 |
+ nativeSP := self nativeStackPointerIn: localFP.
+ topInt64 := stackPages long64AtPointer: nativeSP - 1.
+ nativeSP := self nativeStackPointerIn: localFP put: nativeSP + 8.
+ ^topInt64!
Item was added:
+ ----- Method: StackInterpreter>>internalPopStackNativeSize: (in category 'as yet unclassified') -----
+ internalPopStackNativeSize: popSize
+ <option: #LowcodeVM>
+ "In the StackInterpreter stacks grow down."
+ nativeSP := self nativeStackPointerIn: localFP.
+ nativeSP := self nativeStackPointerIn: localFP put: nativeSP + popSize.!
Item was added:
+ ----- Method: StackInterpreter>>internalPopStackPointer (in category 'internal interpreter access') -----
+ internalPopStackPointer
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #topPointer type: #'char*'>
+ "In the StackInterpreter stacks grow down."
+ | topPointer |
+ nativeSP := self nativeStackPointerIn: localFP.
+ topPointer := stackPages pointerAtPointer: nativeSP - 1.
+ nativeSP := self nativeStackPointerIn: localFP put: nativeSP + BytesPerOop.
+ ^topPointer!
Item was added:
+ ----- Method: StackInterpreter>>internalPushFloat32: (in category 'internal interpreter access') -----
+ internalPushFloat32: singleFloatValue
+ <option: #LowcodeVM>
+ <var: #singleFloatValue type: #float >
+ "In the StackInterpreter stacks grow down."
+ nativeSP := (self nativeStackPointerIn: localFP) - 4.
+ self nativeStackPointerIn: localFP put: nativeSP.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages singleFloatAtPointer: (nativeSP - 1) put: singleFloatValue!
Item was added:
+ ----- Method: StackInterpreter>>internalPushFloat64: (in category 'internal interpreter access') -----
+ internalPushFloat64: floatValue
+ <option: #LowcodeVM>
+ <arg: #floatValue type: #double >
+ "In the StackInterpreter stacks grow down."
+ nativeSP := (self nativeStackPointerIn: localFP) - 8.
+ self nativeStackPointerIn: localFP put: nativeSP.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages floatAtPointer: (nativeSP - 1) put: floatValue
+ !
Item was added:
+ ----- Method: StackInterpreter>>internalPushInt32: (in category 'internal interpreter access') -----
+ internalPushInt32: int32Value
+ <option: #LowcodeVM>
+ "In the StackInterpreter stacks grow down."
+ nativeSP := (self nativeStackPointerIn: localFP) - 4.
+ self nativeStackPointerIn: localFP put: nativeSP.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages int32AtPointer: (nativeSP - 1) put: int32Value
+ !
Item was added:
+ ----- Method: StackInterpreter>>internalPushInt64: (in category 'internal interpreter access') -----
+ internalPushInt64: int64Value
+ <option: #LowcodeVM>
+ <arg: #int64Value type: #sqLong >
+ "In the StackInterpreter stacks grow down."
+ nativeSP := (self nativeStackPointerIn: localFP) - 8.
+ self nativeStackPointerIn: localFP put: nativeSP.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages long64AtPointer: (nativeSP - 1) put: int64Value
+ !
Item was added:
+ ----- Method: StackInterpreter>>internalPushPointer: (in category 'internal interpreter access') -----
+ internalPushPointer: pointerValue
+ <option: #LowcodeVM>
+ <var: #pointerValue type: #'char*' >
+ "In the StackInterpreter stacks grow down."
+ nativeSP := (self nativeStackPointerIn: localFP) - BytesPerOop.
+ self nativeStackPointerIn: localFP put: nativeSP.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages pointerAtPointer: (nativeSP - 1) put: pointerValue
+ !
Item was added:
+ ----- Method: StackInterpreter>>internalPushShadowCallStackFloat32: (in category 'internal interpreter access') -----
+ internalPushShadowCallStackFloat32: singleFloatValue
+ <option: #LowcodeVM>
+ <var: #singleFloatValue type: #float >
+ "In the StackInterpreter stacks grow down."
+ shadowCallStackPointer := shadowCallStackPointer - 4.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages singleFloatAtPointer: shadowCallStackPointer put: singleFloatValue!
Item was added:
+ ----- Method: StackInterpreter>>internalPushShadowCallStackFloat64: (in category 'internal interpreter access') -----
+ internalPushShadowCallStackFloat64: floatValue
+ <option: #LowcodeVM>
+ <var: #floatValue type: #double >
+ "In the StackInterpreter stacks grow down."
+ shadowCallStackPointer := shadowCallStackPointer - 8.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages singleFloatAtPointer: shadowCallStackPointer put: floatValue!
Item was added:
+ ----- Method: StackInterpreter>>internalPushShadowCallStackInt32: (in category 'internal interpreter access') -----
+ internalPushShadowCallStackInt32: int32Value
+ <option: #LowcodeVM>
+ "In the StackInterpreter stacks grow down."
+ shadowCallStackPointer := shadowCallStackPointer - 4.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages int32AtPointer: shadowCallStackPointer put: int32Value!
Item was added:
+ ----- Method: StackInterpreter>>internalPushShadowCallStackInt64: (in category 'internal interpreter access') -----
+ internalPushShadowCallStackInt64: int64Value
+ <option: #LowcodeVM>
+ <arg: #int64Value type: #sqLong >
+
+ "In the StackInterpreter stacks grow down."
+ shadowCallStackPointer := shadowCallStackPointer - 8.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages int64AtPointer: shadowCallStackPointer put: int64Value!
Item was added:
+ ----- Method: StackInterpreter>>internalPushShadowCallStackPointer: (in category 'internal interpreter access') -----
+ internalPushShadowCallStackPointer: pointerValue
+ <option: #LowcodeVM>
+ <var: #pointerValue type: #'char*' >
+ "In the StackInterpreter stacks grow down."
+ shadowCallStackPointer := shadowCallStackPointer - BytesPerOop.
+
+ "In the StackInterpreter stacks grow down."
+ stackPages pointerAtPointer: shadowCallStackPointer put: pointerValue!
Item was added:
+ ----- Method: StackInterpreter>>internalPushShadowCallStackSpace: (in category 'internal interpreter access') -----
+ internalPushShadowCallStackSpace: spaceSize
+ <option: #LowcodeVM>
+ "In the StackInterpreter stacks grow down."
+ shadowCallStackPointer := shadowCallStackPointer - spaceSize.!
Item was added:
+ ----- Method: StackInterpreter>>internalPushShadowCallStackStructure:size: (in category 'internal interpreter access') -----
+ internalPushShadowCallStackStructure: structurePointer size: size
+ <option: #LowcodeVM>
+ shadowCallStackPointer := shadowCallStackPointer - size.
+ self mem: shadowCallStackPointer cp: structurePointer y: size!
Item was changed:
----- Method: StackInterpreter>>internalizeIPandSP (in category 'utilities') -----
internalizeIPandSP
"Copy the instruction, stack and frame pointers to local variables for rapid access within the interpret loop."
localIP := self pointerForOop: instructionPointer.
localSP := self pointerForOop: stackPointer.
+ localFP := self pointerForOop: framePointer.
+ self cppIf: LowcodeVM ifTrue: [ nativeSP := 0. ]!
- localFP := self pointerForOop: framePointer!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeBinaryInlinePrimitive: (in category 'inline primitive dispatch generated code') -----
+ lowcodeBinaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self lowcodePrimitiveByteSizeOf ].
+ [1] -> [ ^ self lowcodePrimitiveFirstFieldPointer ].
+ [2] -> [ ^ self lowcodePrimitiveFirstIndexableFieldPointer ].
+ [3] -> [ ^ self lowcodePrimitiveIsBytes ].
+ [4] -> [ ^ self lowcodePrimitiveIsFloatObject ].
+ [5] -> [ ^ self lowcodePrimitiveIsIndexable ].
+ [6] -> [ ^ self lowcodePrimitiveIsIntegerObject ].
+ [7] -> [ ^ self lowcodePrimitiveIsPointers ].
+ [8] -> [ ^ self lowcodePrimitiveIsWords ].
+ [9] -> [ ^ self lowcodePrimitiveIsWordsOrBytes ].
+ [10] -> [ ^ self lowcodePrimitiveOopSmallIntegerToInt32 ].
+ [11] -> [ ^ self lowcodePrimitiveOopSmallIntegerToInt64 ].
+ [12] -> [ ^ self lowcodePrimitiveOopToBoolean32 ].
+ [13] -> [ ^ self lowcodePrimitiveOopToBoolean64 ].
+ [14] -> [ ^ self lowcodePrimitiveOopToFloat32 ].
+ [15] -> [ ^ self lowcodePrimitiveOopToFloat64 ].
+ [16] -> [ ^ self lowcodePrimitiveOopToInt32 ].
+ [17] -> [ ^ self lowcodePrimitiveOopToInt64 ].
+ [18] -> [ ^ self lowcodePrimitiveOopToPointer ].
+ [19] -> [ ^ self lowcodePrimitiveOopToPointerReinterpret ].
+ [20] -> [ ^ self lowcodePrimitiveOopToUInt32 ].
+ [21] -> [ ^ self lowcodePrimitiveOopToUInt64 ].
+ [22] -> [ ^ self lowcodePrimitivePin ].
+ [23] -> [ ^ self lowcodePrimitiveUnpin ].
+ }
+ otherwise: [
+ localIP := localIP - 3.
+ ^self respondToUnknownBytecode
+ ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCallout:structureResult: (in category 'inline primitive ffi abi') -----
+ lowcodeCallout: functionPointer structureResult: resultPointer
+ <option: #LowcodeVM>
+ <var: #functionPointer type: #'char*' >
+ <var: #resultPointer type: #'char*' >
+ self internalPushShadowCallStackPointer: resultPointer.
+ self externalizeIPandSP.
+ self lowcodeCalloutState: lowcodeCalloutState callFunction: functionPointer.
+ self internalizeIPandSP.
+ self reloadLowcodeStateAfterCallout.
+ ^ self lowcodeCalloutStateFetchResultStructure: lowcodeCalloutState!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutFloat32Result: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutFloat32Result: functionPointer
+ <option: #LowcodeVM>
+ <var: #functionPointer type: #'char*' >
+ self externalizeIPandSP.
+ self lowcodeCalloutState: lowcodeCalloutState callFunction: functionPointer.
+ self internalizeIPandSP.
+ self reloadLowcodeStateAfterCallout.
+ ^ self lowcodeCalloutStateFetchResultFloat32: lowcodeCalloutState!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutFloat64Result: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutFloat64Result: functionPointer
+ <option: #LowcodeVM>
+ <var: #functionPointer type: #'char*' >
+ self externalizeIPandSP.
+ self lowcodeCalloutState: lowcodeCalloutState callFunction: functionPointer.
+ self internalizeIPandSP.
+ self reloadLowcodeStateAfterCallout.
+ ^ self lowcodeCalloutStateFetchResultFloat64: lowcodeCalloutState!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutInt32Result: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutInt32Result: functionPointer
+ <option: #LowcodeVM>
+ <var: #functionPointer type: #'char*' >
+ self externalizeIPandSP.
+ self lowcodeCalloutState: lowcodeCalloutState callFunction: functionPointer.
+ self internalizeIPandSP.
+ self reloadLowcodeStateAfterCallout.
+ ^ self lowcodeCalloutStateFetchResultInt32: lowcodeCalloutState!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutInt64Result: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutInt64Result: functionPointer
+ <option: #LowcodeVM>
+ <var: #functionPointer type: #'char*' >
+ self externalizeIPandSP.
+ self lowcodeCalloutState: lowcodeCalloutState callFunction: functionPointer.
+ self internalizeIPandSP.
+ self reloadLowcodeStateAfterCallout.
+ ^ self lowcodeCalloutStateFetchResultInt64: lowcodeCalloutState!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutPointerResult: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutPointerResult: functionPointer
+ <option: #LowcodeVM>
+ <var: #functionPointer type: #'char*' >
+ self externalizeIPandSP.
+ self lowcodeCalloutState: lowcodeCalloutState callFunction: functionPointer.
+ self internalizeIPandSP.
+ self reloadLowcodeStateAfterCallout.
+ ^ self lowcodeCalloutStateFetchResultPointer: lowcodeCalloutState!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:callFunction: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState callFunction: functionPointer
+ <option: #LowcodeVM>
+ self lowcodeCalloutState: calloutState stackPointer: shadowCallStackPointer stackSize: (self cCoerce: lowcodeCalloutState to: #'char*') - shadowCallStackPointer callFunction: functionPointer
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:float32Register: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState float32Register: registerId
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:float32Register:value: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState float32Register: registerId value: value
+ "This is implemented as C macros in platform specific headers"
+ <var: #value type: #'float' >
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:float64Register: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState float64Register: registerId
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:float64Register:value: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState float64Register: registerId value: value
+ "This is implemented as C macros in platform specific headers"
+ <var: #value type: #'double' >
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:int32Register: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState int32Register: registerId
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:int32Register:value: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState int32Register: registerId value: value
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:int64Register: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState int64Register: registerId
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:int64Register:value: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState int64Register: registerId value: value
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:pointerRegister: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState pointerRegister: registerId
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:pointerRegister:value: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState pointerRegister: registerId value: value
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutState:stackPointer:stackSize:callFunction: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutState: calloutState stackPointer: calloutStackPointer stackSize: calloutStackSize callFunction: functionPointer
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutStateFetchResultFloat32: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutStateFetchResultFloat32: calloutState
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutStateFetchResultFloat64: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutStateFetchResultFloat64: calloutState
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutStateFetchResultInt32: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutStateFetchResultInt32: calloutState
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutStateFetchResultInt64: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutStateFetchResultInt64: calloutState
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutStateFetchResultPointer: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutStateFetchResultPointer: calloutState
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeCalloutStateFetchResultStructure: (in category 'inline primitive ffi abi') -----
+ lowcodeCalloutStateFetchResultStructure: calloutState
+ "This is implemented as C macros in platform specific headers"
+ <doNotGenerate>
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeNullaryInlinePrimitive: (in category 'inline primitive dispatch generated code') -----
+ lowcodeNullaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self lowcodePrimitiveBoolean32ToOop ].
+ [1] -> [ ^ self lowcodePrimitiveBoolean64ToOop ].
+ [2] -> [ ^ self lowcodePrimitiveFloat32ToOop ].
+ [3] -> [ ^ self lowcodePrimitiveFloat64ToOop ].
+ [4] -> [ ^ self lowcodePrimitiveInt32ToOop ].
+ [5] -> [ ^ self lowcodePrimitiveInt64ToOop ].
+ [6] -> [ ^ self lowcodePrimitivePointerToOop ].
+ [7] -> [ ^ self lowcodePrimitivePointerToOopReinterprer ].
+ [8] -> [ ^ self lowcodePrimitiveSmallInt32ToOop ].
+ [9] -> [ ^ self lowcodePrimitiveUint32ToOop ].
+ [10] -> [ ^ self lowcodePrimitiveUint64ToOop ].
+ }
+ otherwise: [
+ localIP := localIP - 3.
+ ^self respondToUnknownBytecode
+ ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveAdd32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveAdd32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first + second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveAdd64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveAdd64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first + second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveAlloca32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveAlloca32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer size |
+ <var: #pointer type: #'char*' >
+ <var: #size type: #'sqInt' >
+ size := self internalPopStackInt32.
+
+ nativeStackPointer := self cCoerce:
+ ((self cCoerce: nativeStackPointer - size to: 'size_t') bitAnd: -16)
+ to: 'char*'.
+ pointer := nativeStackPointer.
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveAlloca64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveAlloca64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer size |
+ <var: #pointer type: #'char*' >
+ <var: #size type: #'sqLong' >
+ size := self internalPopStackInt64.
+
+ nativeStackPointer := nativeStackPointer - size.
+ pointer := nativeStackPointer.
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveAnd32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveAnd32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first bitAnd: second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveAnd64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveAnd64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first bitAnd: second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveArithmeticRightShift32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveArithmeticRightShift32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount result |
+ <var: #value type: #'sqInt' >
+ <var: #shiftAmount type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ shiftAmount := self internalPopStackInt32.
+ value := self internalPopStackInt32.
+
+ result := value >> shiftAmount.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveArithmeticRightShift64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveArithmeticRightShift64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount result |
+ <var: #value type: #'sqLong' >
+ <var: #shiftAmount type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ shiftAmount := self internalPopStackInt64.
+ value := self internalPopStackInt64.
+
+ result := value >> shiftAmount.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveBeginCall (in category 'inline primitive generated code') -----
+ lowcodePrimitiveBeginCall
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | alignment |
+ alignment := extA.
+
+ "Store the shadow stack pointer"
+ self shadowCallStackPointerIn: localFP put: shadowCallStackPointer + 1.
+ "Allocate the callout state"
+ self allocateLowcodeCalloutState.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveBoolean32ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveBoolean32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ object := value ~= 0 ifTrue: [ objectMemory trueObject ] ifFalse: [objectMemory falseObject].
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveBoolean64ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveBoolean64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ object := value ~= 0 ifTrue: [ objectMemory trueObject ] ifFalse: [objectMemory falseObject].
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveByteSizeOf (in category 'inline primitive generated code') -----
+ lowcodePrimitiveByteSizeOf
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := self byteSizeOf: object.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallArgumentFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallArgumentFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | argumentValue |
+ <var: #argumentValue type: #'float' >
+ argumentValue := self internalPopStackFloat32.
+
+ self internalPushShadowCallStackFloat32: argumentValue.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallArgumentFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallArgumentFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | argumentValue |
+ <var: #argumentValue type: #'double' >
+ argumentValue := self internalPopStackFloat64.
+
+ self internalPushShadowCallStackFloat64: argumentValue.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallArgumentInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallArgumentInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+ <var: #value type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ self internalPushShadowCallStackInt32: value.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallArgumentInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallArgumentInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+ <var: #value type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ self internalPushShadowCallStackInt64: value.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallArgumentPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallArgumentPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerValue |
+ <var: #pointerValue type: #'char*' >
+ pointerValue := self internalPopStackPointer.
+
+ self internalPushShadowCallStackPointer: pointerValue.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallArgumentSpace (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallArgumentSpace
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | spaceSize |
+ spaceSize := extA.
+
+ self internalPushShadowCallStackSpace: spaceSize.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallArgumentStructure (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallArgumentStructure
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | structurePointer structureSize |
+ <var: #structurePointer type: #'char*' >
+ structureSize := extA.
+ structurePointer := self internalPopStackPointer.
+
+ self internalPushShadowCallStackStructure: structurePointer size: structureSize.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallInstruction (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallInstruction
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | function |
+ function := extA.
+
+ self abort.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCallPhysical (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCallPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID |
+ registerID := extA.
+
+ self abort.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCheckSessionIdentifier (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCheckSessionIdentifier
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | expectedSession value |
+ <var: #value type: #'sqInt' >
+ expectedSession := extA.
+
+ value := (expectedSession = self getThisSessionID) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveCompareAndSwap32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveCompareAndSwap32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | newValue check oldValue value |
+ <var: #newValue type: #'sqInt' >
+ <var: #check type: #'char*' >
+ <var: #oldValue type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ newValue := self internalPopStackInt32.
+ oldValue := self internalPopStackInt32.
+ check := self internalPopStackPointer.
+
+ self abort.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveDiv32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveDiv32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first // second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveDiv64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveDiv64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first // second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveDuplicateFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveDuplicateFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup1 dup2 |
+ <var: #value type: #'float' >
+ <var: #dup1 type: #'float' >
+ <var: #dup2 type: #'float' >
+ value := self internalPopStackFloat32.
+
+ dup1 := value.
+ dup2 := value.
+
+ self internalPushFloat32: dup1.
+ self internalPushFloat32: dup2.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveDuplicateFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveDuplicateFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup1 dup2 |
+ <var: #value type: #'double' >
+ <var: #dup1 type: #'double' >
+ <var: #dup2 type: #'double' >
+ value := self internalPopStackFloat64.
+
+ dup1 := value.
+ dup2 := value.
+
+ self internalPushFloat64: dup1.
+ self internalPushFloat64: dup2.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveDuplicateInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveDuplicateInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup1 dup2 |
+ <var: #value type: #'sqInt' >
+ <var: #dup1 type: #'sqInt' >
+ <var: #dup2 type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ dup1 := value.
+ dup2 := value.
+
+ self internalPushInt32: dup1.
+ self internalPushInt32: dup2.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveDuplicateInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveDuplicateInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup1 dup2 |
+ <var: #value type: #'sqLong' >
+ <var: #dup1 type: #'sqLong' >
+ <var: #dup2 type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ dup1 := value.
+ dup2 := value.
+
+ self internalPushInt64: dup1.
+ self internalPushInt64: dup2.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveDuplicatePointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveDuplicatePointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | dup2 dup1 pointerValue |
+ <var: #dup2 type: #'char*' >
+ <var: #dup1 type: #'char*' >
+ <var: #pointerValue type: #'char*' >
+ pointerValue := self internalPopStackPointer.
+
+ dup1 := pointerValue.
+ dup2 := pointerValue.
+
+ self internalPushPointer: dup1.
+ self internalPushPointer: dup2.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveEffectiveAddress32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveEffectiveAddress32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result offset base scale index |
+ <var: #result type: #'char*' >
+ <var: #offset type: #'sqInt' >
+ <var: #base type: #'char*' >
+ <var: #scale type: #'sqInt' >
+ <var: #index type: #'sqInt' >
+ offset := self internalPopStackInt32.
+ scale := self internalPopStackInt32.
+ index := self internalPopStackInt32.
+ base := self internalPopStackPointer.
+
+ result := base + (index*scale) + offset.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveEffectiveAddress64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveEffectiveAddress64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result offset base scale index |
+ <var: #result type: #'char*' >
+ <var: #offset type: #'sqLong' >
+ <var: #base type: #'char*' >
+ <var: #scale type: #'sqLong' >
+ <var: #index type: #'sqLong' >
+ offset := self internalPopStackInt64.
+ scale := self internalPopStackInt64.
+ index := self internalPopStackInt64.
+ base := self internalPopStackPointer.
+
+ result := base + (index*scale) + offset.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveEndCall (in category 'inline primitive generated code') -----
+ lowcodePrimitiveEndCall
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ "Restore the shadow stack pointer"
+ shadowCallStackPointer := (self shadowCallStackPointerIn: localFP) - 1.
+ self shadowCallStackPointerIn: localFP put: (self cCoerce: 1 to: #'char*').
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveEndCallNoCleanup (in category 'inline primitive generated code') -----
+ lowcodePrimitiveEndCallNoCleanup
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ "Restore the shadow stack pointer"
+ shadowCallStackPointer := (self shadowCallStackPointerIn: localFP) - 1.
+ self shadowCallStackPointerIn: localFP put: (self cCoerce: 1 to: #'char*').
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFirstFieldPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFirstFieldPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object pointer |
+ <var: #object type: #'sqInt' >
+ <var: #pointer type: #'char*' >
+ object := self internalPopStack.
+
+ pointer := objectMemory firstFixedField: object.
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFirstIndexableFieldPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFirstIndexableFieldPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object pointer |
+ <var: #object type: #'sqInt' >
+ <var: #pointer type: #'char*' >
+ object := self internalPopStack.
+
+ pointer := objectMemory firstIndexableField: object.
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Add (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Add
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'float' >
+ <var: #result type: #'float' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ result := first + second.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Div (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Div
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'float' >
+ <var: #result type: #'float' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ result := first / second.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Equal (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'float' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ value := first = second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Great (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'float' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ value := first > second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32GreatEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'float' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ value := first >= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Less (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'float' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ value := first < second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32LessEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'float' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ value := first <= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Mul (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Mul
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'float' >
+ <var: #result type: #'float' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ result := first * second.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Neg (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Neg
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'float' >
+ <var: #result type: #'float' >
+ value := self internalPopStackFloat32.
+
+ result := value negated.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32NotEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'float' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ value := first ~= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Sqrt (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Sqrt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'float' >
+ <var: #result type: #'float' >
+ value := self internalPopStackFloat32.
+
+ result := self sqrt: value.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32Sub (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32Sub
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'float' >
+ <var: #result type: #'float' >
+ <var: #first type: #'float' >
+ second := self internalPopStackFloat32.
+ first := self internalPopStackFloat32.
+
+ result := first - second.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32ToFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | singleFloatValue doubleResult |
+ <var: #singleFloatValue type: #'float' >
+ <var: #doubleResult type: #'double' >
+ singleFloatValue := self internalPopStackFloat32.
+
+ doubleResult := self cCoerce: singleFloatValue to: 'double'.
+
+ self internalPushFloat64: doubleResult.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32ToInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32ToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'float' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackFloat32.
+
+ result := self cCoerce: value to: 'sqInt'.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32ToInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32ToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'float' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackFloat32.
+
+ result := self cCoerce: value to: 'sqLong'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | singleFloatValue object |
+ <var: #singleFloatValue type: #'float' >
+ <var: #object type: #'sqInt' >
+ singleFloatValue := self internalPopStackFloat32.
+
+ object := objectMemory floatObjectOf: singleFloatValue.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32ToUInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32ToUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'float' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackFloat32.
+
+ result := self cCoerce: value to: 'uint32_t'.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat32ToUInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat32ToUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'float' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackFloat32.
+
+ result := self cCoerce: value to: 'uint64_t'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Add (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Add
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'double' >
+ <var: #result type: #'double' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ result := first + second.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Div (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Div
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'double' >
+ <var: #result type: #'double' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ result := first / second.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Equal (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'double' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ value := first = second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Great (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'double' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ value := first > second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64GreatEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'double' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ value := first >= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Less (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'double' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ value := first < second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64LessEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'double' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ value := first <= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Mul (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Mul
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'double' >
+ <var: #result type: #'double' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ result := first * second.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Neg (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Neg
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'double' >
+ <var: #result type: #'double' >
+ value := self internalPopStackFloat64.
+
+ result := value negated.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64NotEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'double' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ value := first ~= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Sqrt (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Sqrt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'double' >
+ <var: #result type: #'double' >
+ value := self internalPopStackFloat64.
+
+ result := self sqrt: value.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64Sub (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64Sub
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'double' >
+ <var: #result type: #'double' >
+ <var: #first type: #'double' >
+ second := self internalPopStackFloat64.
+ first := self internalPopStackFloat64.
+
+ result := first - second.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64ToFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue singleFloatResult |
+ <var: #floatValue type: #'double' >
+ <var: #singleFloatResult type: #'float' >
+ floatValue := self internalPopStackFloat64.
+
+ singleFloatResult := self cCoerce: floatValue to: 'float'.
+
+ self internalPushFloat32: singleFloatResult.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64ToInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64ToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int32Result |
+ <var: #floatValue type: #'double' >
+ <var: #int32Result type: #'sqInt' >
+ floatValue := self internalPopStackFloat64.
+
+ int32Result := self cCoerce: floatValue to: 'sqInt'.
+
+ self internalPushInt32: int32Result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64ToInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64ToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int64Result |
+ <var: #floatValue type: #'double' >
+ <var: #int64Result type: #'sqLong' >
+ floatValue := self internalPopStackFloat64.
+
+ int64Result := self cCoerce: floatValue to: 'sqLong'.
+
+ self internalPushInt64: int64Result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue object |
+ <var: #floatValue type: #'double' >
+ <var: #object type: #'sqInt' >
+ floatValue := self internalPopStackFloat64.
+
+ object := objectMemory floatObjectOf: floatValue.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64ToUInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64ToUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int64Result |
+ <var: #floatValue type: #'double' >
+ <var: #int64Result type: #'sqInt' >
+ floatValue := self internalPopStackFloat64.
+
+ int64Result := self cCoerce: floatValue to: 'uint32_t'.
+
+ self internalPushInt32: int64Result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFloat64ToUInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFloat64ToUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int64Result |
+ <var: #floatValue type: #'double' >
+ <var: #int64Result type: #'sqLong' >
+ floatValue := self internalPopStackFloat64.
+
+ int64Result := self cCoerce: floatValue to: 'uint64_t'.
+
+ self internalPushInt64: int64Result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveFree (in category 'inline primitive generated code') -----
+ lowcodePrimitiveFree
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer |
+ <var: #pointer type: #'char*' >
+ pointer := self internalPopStackPointer.
+
+ self free: pointer.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInstantiateIndexable32Oop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInstantiateIndexable32Oop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | indexableSize object classOop |
+ <var: #indexableSize type: #'sqInt' >
+ <var: #object type: #'sqInt' >
+ <var: #classOop type: #'sqInt' >
+ indexableSize := self internalPopStackInt32.
+ classOop := self internalPopStack.
+
+ object := objectMemory instantiateClass: classOop indexableSize: indexableSize.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInstantiateIndexableOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInstantiateIndexableOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | indexableSize object classOop |
+ <var: #object type: #'sqInt' >
+ <var: #classOop type: #'sqInt' >
+ indexableSize := extA.
+ classOop := self internalPopStack.
+
+ object := objectMemory instantiateClass: classOop indexableSize: indexableSize.
+
+ self internalPush: object.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInstantiateOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInstantiateOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object classOop |
+ <var: #object type: #'sqInt' >
+ <var: #classOop type: #'sqInt' >
+ classOop := self internalPopStack.
+
+ object := objectMemory instantiateClass: classOop indexableSize: 0.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32Equal (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := first = second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32Great (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := first > second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32GreatEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := first >= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32Less (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := first < second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32LessEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := first <= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32NotEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := first ~= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32ToFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'float' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'float'.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32ToFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'double' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'double'.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ object := objectMemory signed32BitIntegerFor: value.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt32ToPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt32ToPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'char*' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'uintptr_t'.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64Equal (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := first = second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64Great (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := first > second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64GreatEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := first >= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64Less (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := first < second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64LessEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := first <= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64NotEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := first ~= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64ToFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'double' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: value to: 'float'.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64ToFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'double' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: value to: 'double'.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ object := objectMemory signed64BitIntegerFor: value.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveInt64ToPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveInt64ToPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'char*' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce:
+ (self cCoerce: value to: 'intptr_t')
+ to: 'char*'.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveIsBytes (in category 'inline primitive generated code') -----
+ lowcodePrimitiveIsBytes
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := (objectMemory isBytes: object) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveIsFloatObject (in category 'inline primitive generated code') -----
+ lowcodePrimitiveIsFloatObject
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := (objectMemory isFloatObject: object) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveIsIndexable (in category 'inline primitive generated code') -----
+ lowcodePrimitiveIsIndexable
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := (objectMemory isIndexable: object) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveIsIntegerObject (in category 'inline primitive generated code') -----
+ lowcodePrimitiveIsIntegerObject
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := (objectMemory isIntegerObject: object) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveIsPointers (in category 'inline primitive generated code') -----
+ lowcodePrimitiveIsPointers
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := (objectMemory isPointers: object) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveIsWords (in category 'inline primitive generated code') -----
+ lowcodePrimitiveIsWords
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := (objectMemory isWords: object) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveIsWordsOrBytes (in category 'inline primitive generated code') -----
+ lowcodePrimitiveIsWordsOrBytes
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := (objectMemory isWordsOrBytes: object) ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLeftShift32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLeftShift32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount result |
+ <var: #value type: #'sqInt' >
+ <var: #shiftAmount type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ shiftAmount := self internalPopStackInt32.
+ value := self internalPopStackInt32.
+
+ result := value << shiftAmount.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLeftShift64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLeftShift64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount result |
+ <var: #value type: #'sqLong' >
+ <var: #shiftAmount type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ shiftAmount := self internalPopStackInt64.
+ value := self internalPopStackInt64.
+
+ result := value << shiftAmount.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentAddress (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentAddress
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer baseOffset |
+ <var: #pointer type: #'char*' >
+ baseOffset := extA.
+
+ pointer := self framePointerOfNativeArgument: baseOffset in: localFP.
+
+ self internalPushPointer: pointer.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue baseOffset |
+ <var: #floatValue type: #'float' >
+ baseOffset := extA.
+
+ floatValue := stackPages singleFloatAtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushFloat32: floatValue.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | doubleValue baseOffset |
+ <var: #doubleValue type: #'double' >
+ baseOffset := extA.
+
+ doubleValue := stackPages floatAtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushFloat64: doubleValue.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentInt16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages int16AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages int32AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqLong' >
+ baseOffset := extA.
+
+ value := stackPages int64AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt64: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentInt8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages int8AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerResult baseOffset |
+ <var: #pointerResult type: #'char*' >
+ baseOffset := extA.
+
+ pointerResult := stackPages pointerAtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushPointer: pointerResult.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentUInt16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentUInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages uint16AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentUInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages uint32AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentUInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqLong' >
+ baseOffset := extA.
+
+ value := stackPages uint64AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt64: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadArgumentUInt8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadArgumentUInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages uint8AtPointer: (self framePointerOfNativeArgument: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadFloat32FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadFloat32FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'float' >
+ pointer := self internalPopStackPointer.
+
+ value := self singleFloatAtPointer: pointer.
+
+ self internalPushFloat32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadFloat64FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadFloat64FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'double' >
+ pointer := self internalPopStackPointer.
+
+ value := self floatAtPointer: pointer.
+
+ self internalPushFloat64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadInt16FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadInt16FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ value := self int16AtPointer: pointer.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadInt32FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadInt32FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ value := self int32AtPointer: pointer.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadInt64FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadInt64FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqLong' >
+ pointer := self internalPopStackPointer.
+
+ value := self int64AtPointer: pointer.
+
+ self internalPushInt64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadInt8FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadInt8FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ value := self int8AtPointer: pointer.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalAddress (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalAddress
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer baseOffset |
+ <var: #pointer type: #'char*' >
+ baseOffset := extA.
+
+ pointer := self framePointerOfNativeLocal: baseOffset in: localFP.
+
+ self internalPushPointer: pointer.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue baseOffset |
+ <var: #floatValue type: #'float' >
+ baseOffset := extA.
+
+ floatValue := stackPages singleFloatAtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushFloat32: floatValue.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | doubleValue baseOffset |
+ <var: #doubleValue type: #'double' >
+ baseOffset := extA.
+
+ doubleValue := stackPages floatAtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushFloat64: doubleValue.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalInt16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages int16AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages int32AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqLong' >
+ baseOffset := extA.
+
+ value := stackPages int64AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt64: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalInt8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages int8AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerResult baseOffset |
+ <var: #pointerResult type: #'char*' >
+ baseOffset := extA.
+
+ pointerResult := stackPages pointerAtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushPointer: pointerResult.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalUInt16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalUInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages uint16AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalUInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages uint32AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalUInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqLong' >
+ baseOffset := extA.
+
+ value := stackPages uint64AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt64: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadLocalUInt8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadLocalUInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+
+ value := stackPages uint8AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP).
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadObjectAt (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadObjectAt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object fieldValue |
+ <var: #fieldIndex type: #'sqInt' >
+ <var: #object type: #'sqInt' >
+ <var: #fieldValue type: #'sqInt' >
+ fieldIndex := self internalPopStackInt32.
+ object := self internalPopStack.
+
+ fieldValue := objectMemory fetchPointer: fieldIndex ofObject: object.
+
+ self internalPush: fieldValue.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadObjectField (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadObjectField
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object fieldValue |
+ <var: #object type: #'sqInt' >
+ <var: #fieldValue type: #'sqInt' >
+ fieldIndex := extA.
+ object := self internalPopStack.
+
+ fieldValue := self fetchPointer: fieldIndex ofObject: object.
+
+ self internalPush: fieldValue.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadPointerFromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadPointerFromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerResult pointer |
+ <var: #pointerResult type: #'char*' >
+ <var: #pointer type: #'char*' >
+ pointer := self internalPopStackPointer.
+
+ pointerResult := self pointerAtPointer: pointer.
+
+ self internalPushPointer: pointerResult.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadUInt16FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadUInt16FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ value := self uint16AtPointer: pointer.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadUInt32FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadUInt32FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ value := self uint32AtPointer: pointer.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadUInt64FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadUInt64FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqLong' >
+ pointer := self internalPopStackPointer.
+
+ value := self uint64AtPointer: pointer.
+
+ self internalPushInt64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLoadUInt8FromMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLoadUInt8FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ value := self uint8AtPointer: pointer.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLocalFrameSize (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLocalFrameSize
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | size |
+ size := extA.
+
+ "Mark the frame"
+ self setFrameHasNativeFrame: localFP.
+ "Store the previous stack pointer"
+ self nativePreviousStackPointerIn: localFP put: nativeStackPointer + 1.
+ "Make the frame pointer"
+ nativeStackPointer := nativeStackPointer - size.
+ self nativeFramePointerIn: localFP put: nativeStackPointer + 1.
+ "Set the stack pointer"
+ nativeSP := nativeStackPointer + 1.
+ self nativeStackPointerIn: localFP put: nativeStackPointer + 1.
+ "Reserve space for the native stack"
+ nativeStackPointer := nativeStackPointer - self defaultNativeStackFrameSize.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLockRegisters (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLockRegisters
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self abort.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveLockVM (in category 'inline primitive generated code') -----
+ lowcodePrimitiveLockVM
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self abort.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMalloc32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMalloc32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer size |
+ <var: #pointer type: #'char*' >
+ <var: #size type: #'sqInt' >
+ size := self internalPopStackInt32.
+
+ pointer := self malloc: size.
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMalloc64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMalloc64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer size |
+ <var: #pointer type: #'char*' >
+ <var: #size type: #'sqLong' >
+ size := self internalPopStackInt64.
+
+ pointer := self malloc: size.
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMemcpy32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMemcpy32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | source dest size |
+ <var: #source type: #'char*' >
+ <var: #dest type: #'char*' >
+ <var: #size type: #'sqInt' >
+ size := self internalPopStackInt32.
+ source := self internalPopStackPointer.
+ dest := self internalPopStackPointer.
+
+ self mem: dest cp: source y: size.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMemcpy64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMemcpy64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | source dest size |
+ <var: #source type: #'char*' >
+ <var: #dest type: #'char*' >
+ <var: #size type: #'sqLong' >
+ size := self internalPopStackInt64.
+ source := self internalPopStackPointer.
+ dest := self internalPopStackPointer.
+
+ self mem: dest cp: source y: size.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMemcpyFixed (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMemcpyFixed
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | source size dest |
+ <var: #source type: #'char*' >
+ <var: #dest type: #'char*' >
+ size := extA.
+ source := self internalPopStackPointer.
+ dest := self internalPopStackPointer.
+
+ self mem: dest cp: source y: size.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMoveFloat32ToPhysical (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMoveFloat32ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'float' >
+ registerID := extA.
+ value := self internalPopStackFloat32.
+
+ self lowcodeCalloutState: lowcodeCalloutState float32Register: registerID value: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMoveFloat64ToPhysical (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMoveFloat64ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'double' >
+ registerID := extA.
+ value := self internalPopStackFloat64.
+
+ self lowcodeCalloutState: lowcodeCalloutState float64Register: registerID value: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMoveInt32ToPhysical (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMoveInt32ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'sqInt' >
+ registerID := extA.
+ value := self internalPopStackInt32.
+
+ self lowcodeCalloutState: lowcodeCalloutState int32Register: registerID value: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMoveInt64ToPhysical (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMoveInt64ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'sqLong' >
+ registerID := extA.
+ value := self internalPopStackInt64.
+
+ self lowcodeCalloutState: lowcodeCalloutState int64Register: registerID value: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMovePointerToPhysical (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMovePointerToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID pointerValue |
+ <var: #pointerValue type: #'char*' >
+ registerID := extA.
+ pointerValue := self internalPopStackPointer.
+
+ self lowcodeCalloutState: lowcodeCalloutState pointerRegister: registerID value: pointerValue.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMul32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMul32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first * second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveMul64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveMul64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first * second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveNeg32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveNeg32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := value negated.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveNeg64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveNeg64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ result := value negated.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveNot32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveNot32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := value bitXor: -1.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveNot64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveNot64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ result := value bitXor: -1.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStack.
+ first := self internalPopStack.
+
+ value := first = second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopNotEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopNotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStack.
+ first := self internalPopStack.
+
+ value := first ~= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopSmallIntegerToInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopSmallIntegerToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := objectMemory integerValueOf: object.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopSmallIntegerToInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopSmallIntegerToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqLong' >
+ object := self internalPopStack.
+
+ value := objectMemory integerValueOf: object.
+
+ self internalPushInt64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToBoolean32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToBoolean32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := self booleanValueOf: object.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToBoolean64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToBoolean64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqLong' >
+ object := self internalPopStack.
+
+ value := self booleanValueOf: object.
+
+ self internalPushInt64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'float' >
+ object := self internalPopStack.
+
+ value := objectMemory floatValueOf: object.
+
+ self internalPushFloat32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'double' >
+ object := self internalPopStack.
+
+ value := objectMemory floatValueOf: object.
+
+ self internalPushFloat64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := self signed32BitValueOf: object.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqLong' >
+ object := self internalPopStack.
+
+ value := self signed64BitValueOf: object.
+
+ self internalPushInt64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object pointer |
+ <var: #object type: #'sqInt' >
+ <var: #pointer type: #'char*' >
+ object := self internalPopStack.
+
+ pointer := self pointerAtPointer: (objectMemory firstIndexableField: object).
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToPointerReinterpret (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToPointerReinterpret
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object pointer |
+ <var: #object type: #'sqInt' >
+ <var: #pointer type: #'char*' >
+ object := self internalPopStack.
+
+ pointer := self cCoerce: object to: 'char*'.
+
+ self internalPushPointer: pointer.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToUInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ object := self internalPopStack.
+
+ value := self positive32BitValueOf: object.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOopToUInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOopToUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqLong' >
+ object := self internalPopStack.
+
+ value := self positive64BitValueOf: object.
+
+ self internalPushInt64: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOr32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOr32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first bitOr: second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveOr64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveOr64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first bitOr: second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'float' >
+ function := extA.
+
+ result := self lowcodeCalloutFloat32Result: (self cCoerce: function to: #'char*').
+
+ self internalPushFloat32: result.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'double' >
+ function := extA.
+
+ result := self lowcodeCalloutFloat64Result: (self cCoerce: function to: #'char*').
+
+ self internalPushFloat64: result.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallIndirectFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallIndirectFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'float' >
+ <var: #function type: #'char*' >
+ function := self internalPopStackPointer.
+
+ result := self lowcodeCalloutFloat32Result: function.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallIndirectFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallIndirectFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'double' >
+ <var: #function type: #'char*' >
+ function := self internalPopStackPointer.
+
+ result := self lowcodeCalloutFloat64Result: function.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallIndirectInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallIndirectInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'sqInt' >
+ <var: #function type: #'char*' >
+ function := self internalPopStackPointer.
+
+ result := self lowcodeCalloutInt32Result: function.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallIndirectInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallIndirectInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'sqLong' >
+ <var: #function type: #'char*' >
+ function := self internalPopStackPointer.
+
+ result := self lowcodeCalloutInt64Result: function.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallIndirectPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallIndirectPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'char*' >
+ <var: #function type: #'char*' >
+ function := self internalPopStackPointer.
+
+ result := self lowcodeCalloutPointerResult: function.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallIndirectStructure (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallIndirectStructure
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | resultPointer result function structureSize |
+ <var: #resultPointer type: #'char*' >
+ <var: #result type: #'char*' >
+ <var: #function type: #'char*' >
+ structureSize := extA.
+ result := self internalPopStackPointer.
+ function := self internalPopStackPointer.
+
+ resultPointer := self lowcodeCallout: function structureResult: result.
+
+ self internalPushPointer: resultPointer.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallIndirectVoid (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallIndirectVoid
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | function |
+ <var: #function type: #'char*' >
+ function := self internalPopStackPointer.
+
+ self lowcodeCalloutInt32Result: function.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'sqInt' >
+ function := extA.
+
+ result := self lowcodeCalloutInt32Result: (self cCoerce: function to: #'char*').
+
+ self internalPushInt32: result.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'sqLong' >
+ function := extA.
+
+ result := self lowcodeCalloutInt64Result: (self cCoerce: function to: #'char*').
+
+ self internalPushInt64: result.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result function |
+ <var: #result type: #'char*' >
+ function := extA.
+
+ result := self lowcodeCalloutPointerResult: (self cCoerce: function to: #'char*').
+
+ self internalPushPointer: result.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallStructure (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallStructure
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | resultPointer result function structureSize |
+ <var: #resultPointer type: #'char*' >
+ <var: #result type: #'char*' >
+ function := extA.
+ structureSize := extB.
+ result := self internalPopStackPointer.
+
+ self internalPushShadowCallStackPointer: result.
+ resultPointer := self lowcodeCalloutPointerResult: (self cCoerce: function to: #'char*').
+
+ self internalPushPointer: resultPointer.
+ extA := 0.
+ extB := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePerformCallVoid (in category 'inline primitive generated code') -----
+ lowcodePrimitivePerformCallVoid
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | function |
+ function := extA.
+
+ self lowcodeCalloutInt32Result: (self cCoerce: function to: #'char*').
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePin (in category 'inline primitive generated code') -----
+ lowcodePrimitivePin
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+ <var: #object type: #'sqInt' >
+ object := self internalPopStack.
+
+ objectMemory pinObject: object.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePlaftormCode (in category 'inline primitive generated code') -----
+ lowcodePrimitivePlaftormCode
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | code |
+ <var: #code type: #'sqInt' >
+
+ self abort.
+
+ self internalPushInt32: code.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerAddConstantOffset (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerAddConstantOffset
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | base offset result |
+ <var: #base type: #'char*' >
+ <var: #result type: #'char*' >
+ offset := extB.
+ base := self internalPopStackPointer.
+
+ result := base + offset.
+
+ self internalPushPointer: result.
+ extB := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerAddOffset32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerAddOffset32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | base offset result |
+ <var: #base type: #'char*' >
+ <var: #offset type: #'sqInt' >
+ <var: #result type: #'char*' >
+ offset := self internalPopStackInt32.
+ base := self internalPopStackPointer.
+
+ result := base + offset.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerAddOffset64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerAddOffset64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | base offset result |
+ <var: #base type: #'char*' >
+ <var: #offset type: #'sqLong' >
+ <var: #result type: #'char*' >
+ offset := self internalPopStackInt64.
+ base := self internalPopStackPointer.
+
+ result := base + offset.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'char*' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'char*' >
+ second := self internalPopStackPointer.
+ first := self internalPopStackPointer.
+
+ value := first = second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerNotEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerNotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'char*' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'char*' >
+ second := self internalPopStackPointer.
+ first := self internalPopStackPointer.
+
+ value := first ~= second ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerToInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer result |
+ <var: #pointer type: #'char*' >
+ <var: #result type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ result := self cCoerce: pointer to: 'uintptr_t'.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerToInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer result |
+ <var: #pointer type: #'char*' >
+ <var: #result type: #'sqLong' >
+ pointer := self internalPopStackPointer.
+
+ result := self cCoerce: pointer to: 'uintptr_t'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer object pointerClassLiteral |
+ <var: #pointer type: #'char*' >
+ <var: #object type: #'sqInt' >
+ pointerClassLiteral := self literal: extA.
+ pointer := self internalPopStackPointer.
+
+ object := objectMemory instantiateClass: pointerClassLiteral indexableSize: BytesPerWord.
+ self pointerAtPointer: (objectMemory firstIndexableField: object) put: pointer.
+
+ self internalPush: object.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePointerToOopReinterprer (in category 'inline primitive generated code') -----
+ lowcodePrimitivePointerToOopReinterprer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer object |
+ <var: #pointer type: #'char*' >
+ <var: #object type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+
+ object := self cCoerce: pointer to: 'sqInt'.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePopFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePopFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+ <var: #value type: #'float' >
+ value := self internalPopStackFloat32.
+
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePopFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePopFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+ <var: #value type: #'double' >
+ value := self internalPopStackFloat64.
+
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePopInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePopInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+ <var: #value type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePopInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePopInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+ <var: #value type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePopMultipleNative (in category 'inline primitive generated code') -----
+ lowcodePrimitivePopMultipleNative
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | popSize |
+ popSize := extA.
+
+ self internalPopStackNativeSize: popSize.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePopPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitivePopPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerValue |
+ <var: #pointerValue type: #'char*' >
+ pointerValue := self internalPopStackPointer.
+
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushConstantUInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushConstantUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result constant |
+ <var: #result type: #'sqInt' >
+ constant := extA.
+
+ result := constant.
+
+ self internalPushInt32: result.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushConstantUInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushConstantUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result constant |
+ <var: #result type: #'sqLong' >
+ constant := extA.
+
+ result := constant.
+
+ self internalPushInt64: result.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushNullPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushNullPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'char*' >
+
+ result := 0.
+
+ self internalPushPointer: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushOne32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushOne32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'sqInt' >
+
+ result := 1.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushOne64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushOne64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'sqLong' >
+
+ result := 1.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushOneFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushOneFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'float' >
+
+ result := 1.0.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushOneFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushOneFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'double' >
+
+ result := 1.0.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushPhysicalFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushPhysicalFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'float' >
+ registerID := extA.
+
+ value := self lowcodeCalloutState: lowcodeCalloutState float32Register: registerID.
+
+ self internalPushFloat32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushPhysicalFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushPhysicalFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'double' >
+ registerID := extA.
+
+ value := self lowcodeCalloutState: lowcodeCalloutState float64Register: registerID.
+
+ self internalPushFloat64: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushPhysicalInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushPhysicalInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'sqInt' >
+ registerID := extA.
+
+ value := self lowcodeCalloutState: lowcodeCalloutState int32Register: registerID.
+
+ self internalPushInt32: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushPhysicalInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushPhysicalInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ <var: #value type: #'sqLong' >
+ registerID := extA.
+
+ value := self lowcodeCalloutState: lowcodeCalloutState int64Register: registerID.
+
+ self internalPushInt64: value.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushPhysicalPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushPhysicalPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID pointerValue |
+ <var: #pointerValue type: #'char*' >
+ registerID := extA.
+
+ pointerValue := self lowcodeCalloutState: lowcodeCalloutState pointerRegister: registerID.
+
+ self internalPushPointer: pointerValue.
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushSessionIdentifier (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushSessionIdentifier
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+ <var: #value type: #'sqInt' >
+
+ value := self getThisSessionID.
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushZero32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushZero32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'sqInt' >
+
+ result := 0.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushZero64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushZero64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'sqLong' >
+
+ result := 0.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushZeroFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushZeroFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'float' >
+
+ result := 0.0.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitivePushZeroFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitivePushZeroFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | result |
+ <var: #result type: #'double' >
+
+ result := 0.0.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveRem32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveRem32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first \\ second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveRem64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveRem64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first \\ second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveRightShift32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveRightShift32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount result |
+ <var: #value type: #'sqInt' >
+ <var: #shiftAmount type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ shiftAmount := self internalPopStackInt32.
+ value := self internalPopStackInt32.
+
+ result := value >> shiftAmount.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveRightShift64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveRightShift64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount result |
+ <var: #value type: #'sqLong' >
+ <var: #shiftAmount type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ shiftAmount := self internalPopStackInt64.
+ value := self internalPopStackInt64.
+
+ result := value >> shiftAmount.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSignExtend32From16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSignExtend32From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'signed short'.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSignExtend32From8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSignExtend32From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'signed char'.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSignExtend64From16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSignExtend64From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: value to: 'int16_t'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSignExtend64From32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSignExtend64From32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'int32_t'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSignExtend64From8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSignExtend64From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: value to: 'signed char'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSmallInt32ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSmallInt32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ object := objectMemory integerObjectOf: value.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreFloat32ToMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreFloat32ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue pointer |
+ <var: #floatValue type: #'float' >
+ <var: #pointer type: #'char*' >
+ pointer := self internalPopStackPointer.
+ floatValue := self internalPopStackFloat32.
+
+ self singleFloatAtPointer: pointer put: floatValue.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreFloat64ToMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreFloat64ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | doubleValue pointer |
+ <var: #doubleValue type: #'double' >
+ <var: #pointer type: #'char*' >
+ pointer := self internalPopStackPointer.
+ doubleValue := self internalPopStackFloat64.
+
+ self floatAtPointer: pointer put: doubleValue.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreInt16ToMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreInt16ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+ value := self internalPopStackInt32.
+
+ self int16AtPointer: pointer put: value.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreInt32ToMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreInt32ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+ value := self internalPopStackInt32.
+
+ self int32AtPointer: pointer put: value.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreInt64ToMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreInt64ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqLong' >
+ pointer := self internalPopStackPointer.
+ value := self internalPopStackInt64.
+
+ self int64AtPointer: pointer put: value.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreInt8ToMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreInt8ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+ <var: #pointer type: #'char*' >
+ <var: #value type: #'sqInt' >
+ pointer := self internalPopStackPointer.
+ value := self internalPopStackInt32.
+
+ self int8AtPointer: pointer put: value.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreLocalFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreLocalFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'float' >
+ baseOffset := extA.
+ value := self internalPopStackFloat32.
+
+ stackPages singleFloatAtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP) put: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreLocalFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreLocalFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'double' >
+ baseOffset := extA.
+ value := self internalPopStackFloat64.
+
+ stackPages floatAtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP) put: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreLocalInt16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreLocalInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+ value := self internalPopStackInt32.
+
+ stackPages int16AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP) put: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreLocalInt32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreLocalInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+ value := self internalPopStackInt32.
+
+ stackPages int32AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP) put: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreLocalInt64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreLocalInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ <var: #valueInt64 type: #'sqLong'>
+ |valueInt64|
+ BytesPerWord = 4 ifTrue: [
+ self lowcodeStoreLocalInt64Workaround: extA in: localFP sp: localSP.
+ ] ifFalse: [
+ valueInt64 := self internalPopStackInt64.
+ stackPages int64AtPointer: (self framePointerOfNativeLocal: extA in: localFP) put: valueInt64.
+ ].
+ extA := 0.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreLocalInt8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreLocalInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ <var: #value type: #'sqInt' >
+ baseOffset := extA.
+ value := self internalPopStackInt32.
+
+ stackPages int8AtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP) put: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreLocalPointer (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreLocalPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerValue baseOffset |
+ <var: #pointerValue type: #'char*' >
+ baseOffset := extA.
+ pointerValue := self internalPopStackPointer.
+
+ stackPages pointerAtPointer: (self framePointerOfNativeLocal: baseOffset in: localFP) put: pointerValue.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreObjectField (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreObjectField
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ fieldIndex := extA.
+ value := self internalPopStack.
+ object := self internalPopStack.
+
+ objectMemory storePointer: fieldIndex ofObject: object withValue: value.
+
+ extA := 0.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStoreObjectFieldAt (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStoreObjectFieldAt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object value |
+ <var: #fieldIndex type: #'sqInt' >
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ value := self internalPopStack.
+ fieldIndex := self internalPopStackInt32.
+ object := self internalPopStack.
+
+ objectMemory storePointer: fieldIndex ofObject: object withValue: value.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveStorePointerToMemory (in category 'inline primitive generated code') -----
+ lowcodePrimitiveStorePointerToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | memoryPointer pointerValue |
+ <var: #memoryPointer type: #'char*' >
+ <var: #pointerValue type: #'char*' >
+ memoryPointer := self internalPopStackPointer.
+ pointerValue := self internalPopStackPointer.
+
+ self pointerAtPointer: memoryPointer put: pointerValue.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSub32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSub32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first - second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveSub64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveSub64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first - second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveTruncate32To16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveTruncate32To16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := value bitAnd: 16rFFFF.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveTruncate32To8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveTruncate32To8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := value bitAnd: 16rFF.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveTruncate64To16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveTruncate64To16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt64.
+
+ result := value bitAnd: 16rFFFF.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveTruncate64To32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveTruncate64To32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt64.
+
+ result := value bitAnd: 16rFFFFFFFF.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveTruncate64To8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveTruncate64To8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt64.
+
+ result := value bitAnd: 16rFF.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUdiv32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUdiv32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := (self cCoerce: first to: 'unsigned int') //
+ (self cCoerce: second to: 'unsigned int').
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUdiv64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUdiv64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := (self cCoerce: first to: 'uint64_t') //
+ (self cCoerce: second to: 'uint64_t').
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint32Great (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint32Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := (self cCoerce: first to: 'unsigned int') >
+ (self cCoerce: second to: 'unsigned int') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint32GreatEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint32GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := (self cCoerce: first to: 'unsigned int') >=
+ (self cCoerce: second to: 'unsigned int') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint32Less (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint32Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := (self cCoerce: first to: 'unsigned int') <
+ (self cCoerce: second to: 'unsigned int') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint32LessEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint32LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ value := (self cCoerce: first to: 'unsigned int') <=
+ (self cCoerce: second to: 'unsigned int') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint32ToFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint32ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'float' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: (self cCoerce: value to: 'unsigned int') to: 'float'.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint32ToFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint32ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'double' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: (self cCoerce: value to: 'unsigned int') to: 'double'.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint32ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ object := objectMemory positive32BitIntegerFor: value.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint64Great (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint64Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := (self cCoerce: first to: 'uint64_t') >
+ (self cCoerce: second to: 'uint64_t') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint64GreatEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint64GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := (self cCoerce: first to: 'uint64_t') >=
+ (self cCoerce: second to: 'uint64_t') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint64Less (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint64Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := (self cCoerce: first to: 'uint64_t') <
+ (self cCoerce: second to: 'uint64_t') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint64LessEqual (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint64LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second value first |
+ <var: #second type: #'sqLong' >
+ <var: #value type: #'sqInt' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ value := (self cCoerce: first to: 'uint64_t') <=
+ (self cCoerce: second to: 'uint64_t') ifTrue: [1] ifFalse: [0].
+
+ self internalPushInt32: value.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint64ToFloat32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint64ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'float' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: (self cCoerce: value to: 'uint64_t') to: 'float'.
+
+ self internalPushFloat32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint64ToFloat64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint64ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'double' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: (self cCoerce: value to: 'uint64_t') to: 'double'.
+
+ self internalPushFloat64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUint64ToOop (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUint64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+ <var: #object type: #'sqInt' >
+ <var: #value type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ object := self positive64BitIntegerFor: value.
+
+ self internalPush: object.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUmul32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUmul32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := (self cCoerce: first to: 'unsigned int') *
+ (self cCoerce: second to: 'unsigned int').
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUmul64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUmul64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := (self cCoerce: first to: 'uint64_t') *
+ (self cCoerce: second to: 'uint64_t').
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUnlockRegisters (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUnlockRegisters
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self abort.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUnlockVM (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUnlockVM
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self abort.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUnpin (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUnpin
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+ <var: #object type: #'sqInt' >
+ object := self internalPopStack.
+
+ objectMemory unpinObject: object.
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUrem32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUrem32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := (self cCoerce: first to: 'unsigned int') \\
+ (self cCoerce: second to: 'unsigned int').
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveUrem64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveUrem64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := (self cCoerce: first to: 'unsigned int') \\
+ (self cCoerce: second to: 'unsigned int').
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveXor32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveXor32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ <var: #first type: #'sqInt' >
+ second := self internalPopStackInt32.
+ first := self internalPopStackInt32.
+
+ result := first bitXor: second.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveXor64 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveXor64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+ <var: #second type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ <var: #first type: #'sqLong' >
+ second := self internalPopStackInt64.
+ first := self internalPopStackInt64.
+
+ result := first bitXor: second.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveZeroExtend32From16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveZeroExtend32From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'uint16_t'.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveZeroExtend32From8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveZeroExtend32From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqInt' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'uint8_t'.
+
+ self internalPushInt32: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveZeroExtend64From16 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveZeroExtend64From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: value to: 'uint16_t'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveZeroExtend64From32 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveZeroExtend64From32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqInt' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt32.
+
+ result := self cCoerce: value to: 'uint32_t'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodePrimitiveZeroExtend64From8 (in category 'inline primitive generated code') -----
+ lowcodePrimitiveZeroExtend64From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+ <var: #value type: #'sqLong' >
+ <var: #result type: #'sqLong' >
+ value := self internalPopStackInt64.
+
+ result := self cCoerce: value to: 'uint8_t'.
+
+ self internalPushInt64: result.
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeStoreLocalInt64Workaround:in:sp: (in category 'inline primitive support') -----
+ lowcodeStoreLocalInt64Workaround: baseOffset in: theFP sp: theSP
+ "This method is a workaround a GCC bug"
+ <inline: #never>
+ <option: #LowcodeVM>
+ <var: #theFP type: #'char*'>
+ <var: #theSP type: #'char*'>
+ <var: #value type: #'sqLong'>
+ | value workNativeSP|
+
+ "Fetch the value from the native tack"
+ workNativeSP := (self nativeStackPointerIn: theFP).
+ value := stackPages long64AtPointer: (workNativeSP - 1).
+ self nativeStackPointerIn: theFP put: workNativeSP + 8.
+
+ "Store the local"
+ self int64AtPointer: (self framePointerOfNativeLocal: baseOffset in: theFP) put: value.!
Item was added:
+ ----- Method: StackInterpreter>>lowcodeTrinaryInlinePrimitive: (in category 'inline primitive dispatch generated code') -----
+ lowcodeTrinaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self lowcodePrimitiveOopEqual ].
+ [1] -> [ ^ self lowcodePrimitiveOopNotEqual ].
+ [2] -> [ ^ self lowcodePrimitiveStoreObjectField ].
+ [3] -> [ ^ self lowcodePrimitiveStoreObjectFieldAt ].
+ }
+ otherwise: [
+ localIP := localIP - 3.
+ ^self respondToUnknownBytecode
+ ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeUnaryInlinePrimitive2: (in category 'inline primitive dispatch generated code') -----
+ lowcodeUnaryInlinePrimitive2: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [60] -> [ ^ self lowcodePrimitiveFloat64ToFloat32 ].
+ [61] -> [ ^ self lowcodePrimitiveFloat64ToInt32 ].
+ [62] -> [ ^ self lowcodePrimitiveFloat64ToInt64 ].
+ [63] -> [ ^ self lowcodePrimitiveFloat64ToUInt32 ].
+ [64] -> [ ^ self lowcodePrimitiveFloat64ToUInt64 ].
+ [65] -> [ ^ self lowcodePrimitiveFree ].
+ [66] -> [ ^ self lowcodePrimitiveInstantiateIndexable32Oop ].
+ [67] -> [ ^ self lowcodePrimitiveInstantiateIndexableOop ].
+ [68] -> [ ^ self lowcodePrimitiveInstantiateOop ].
+ [69] -> [ ^ self lowcodePrimitiveInt32Equal ].
+ [70] -> [ ^ self lowcodePrimitiveInt32Great ].
+ [71] -> [ ^ self lowcodePrimitiveInt32GreatEqual ].
+ [72] -> [ ^ self lowcodePrimitiveInt32Less ].
+ [73] -> [ ^ self lowcodePrimitiveInt32LessEqual ].
+ [74] -> [ ^ self lowcodePrimitiveInt32NotEqual ].
+ [75] -> [ ^ self lowcodePrimitiveInt32ToFloat32 ].
+ [76] -> [ ^ self lowcodePrimitiveInt32ToFloat64 ].
+ [77] -> [ ^ self lowcodePrimitiveInt32ToPointer ].
+ [78] -> [ ^ self lowcodePrimitiveInt64Equal ].
+ [79] -> [ ^ self lowcodePrimitiveInt64Great ].
+ [80] -> [ ^ self lowcodePrimitiveInt64GreatEqual ].
+ [81] -> [ ^ self lowcodePrimitiveInt64Less ].
+ [82] -> [ ^ self lowcodePrimitiveInt64LessEqual ].
+ [83] -> [ ^ self lowcodePrimitiveInt64NotEqual ].
+ [84] -> [ ^ self lowcodePrimitiveInt64ToFloat32 ].
+ [85] -> [ ^ self lowcodePrimitiveInt64ToFloat64 ].
+ [86] -> [ ^ self lowcodePrimitiveInt64ToPointer ].
+ [87] -> [ ^ self lowcodePrimitiveLeftShift32 ].
+ [88] -> [ ^ self lowcodePrimitiveLeftShift64 ].
+ [89] -> [ ^ self lowcodePrimitiveLoadArgumentAddress ].
+ [90] -> [ ^ self lowcodePrimitiveLoadArgumentFloat32 ].
+ [91] -> [ ^ self lowcodePrimitiveLoadArgumentFloat64 ].
+ [92] -> [ ^ self lowcodePrimitiveLoadArgumentInt16 ].
+ [93] -> [ ^ self lowcodePrimitiveLoadArgumentInt32 ].
+ [94] -> [ ^ self lowcodePrimitiveLoadArgumentInt64 ].
+ [95] -> [ ^ self lowcodePrimitiveLoadArgumentInt8 ].
+ [96] -> [ ^ self lowcodePrimitiveLoadArgumentPointer ].
+ [97] -> [ ^ self lowcodePrimitiveLoadArgumentUInt16 ].
+ [98] -> [ ^ self lowcodePrimitiveLoadArgumentUInt32 ].
+ [99] -> [ ^ self lowcodePrimitiveLoadArgumentUInt64 ].
+ [100] -> [ ^ self lowcodePrimitiveLoadArgumentUInt8 ].
+ [101] -> [ ^ self lowcodePrimitiveLoadFloat32FromMemory ].
+ [102] -> [ ^ self lowcodePrimitiveLoadFloat64FromMemory ].
+ [103] -> [ ^ self lowcodePrimitiveLoadInt16FromMemory ].
+ [104] -> [ ^ self lowcodePrimitiveLoadInt32FromMemory ].
+ [105] -> [ ^ self lowcodePrimitiveLoadInt64FromMemory ].
+ [106] -> [ ^ self lowcodePrimitiveLoadInt8FromMemory ].
+ [107] -> [ ^ self lowcodePrimitiveLoadLocalAddress ].
+ [108] -> [ ^ self lowcodePrimitiveLoadLocalFloat32 ].
+ [109] -> [ ^ self lowcodePrimitiveLoadLocalFloat64 ].
+ [110] -> [ ^ self lowcodePrimitiveLoadLocalInt16 ].
+ [111] -> [ ^ self lowcodePrimitiveLoadLocalInt32 ].
+ [112] -> [ ^ self lowcodePrimitiveLoadLocalInt64 ].
+ [113] -> [ ^ self lowcodePrimitiveLoadLocalInt8 ].
+ [114] -> [ ^ self lowcodePrimitiveLoadLocalPointer ].
+ [115] -> [ ^ self lowcodePrimitiveLoadLocalUInt16 ].
+ [116] -> [ ^ self lowcodePrimitiveLoadLocalUInt32 ].
+ [117] -> [ ^ self lowcodePrimitiveLoadLocalUInt64 ].
+ [118] -> [ ^ self lowcodePrimitiveLoadLocalUInt8 ].
+ [119] -> [ ^ self lowcodePrimitiveLoadObjectAt ].
+ }
+ otherwise: [ ^ self lowcodeUnaryInlinePrimitive3: prim ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeUnaryInlinePrimitive3: (in category 'inline primitive dispatch generated code') -----
+ lowcodeUnaryInlinePrimitive3: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [120] -> [ ^ self lowcodePrimitiveLoadObjectField ].
+ [121] -> [ ^ self lowcodePrimitiveLoadPointerFromMemory ].
+ [122] -> [ ^ self lowcodePrimitiveLoadUInt16FromMemory ].
+ [123] -> [ ^ self lowcodePrimitiveLoadUInt32FromMemory ].
+ [124] -> [ ^ self lowcodePrimitiveLoadUInt64FromMemory ].
+ [125] -> [ ^ self lowcodePrimitiveLoadUInt8FromMemory ].
+ [126] -> [ ^ self lowcodePrimitiveLocalFrameSize ].
+ [127] -> [ ^ self lowcodePrimitiveLockRegisters ].
+ [128] -> [ ^ self lowcodePrimitiveLockVM ].
+ [129] -> [ ^ self lowcodePrimitiveMalloc32 ].
+ [130] -> [ ^ self lowcodePrimitiveMalloc64 ].
+ [131] -> [ ^ self lowcodePrimitiveMemcpy32 ].
+ [132] -> [ ^ self lowcodePrimitiveMemcpy64 ].
+ [133] -> [ ^ self lowcodePrimitiveMemcpyFixed ].
+ [134] -> [ ^ self lowcodePrimitiveMoveFloat32ToPhysical ].
+ [135] -> [ ^ self lowcodePrimitiveMoveFloat64ToPhysical ].
+ [136] -> [ ^ self lowcodePrimitiveMoveInt32ToPhysical ].
+ [137] -> [ ^ self lowcodePrimitiveMoveInt64ToPhysical ].
+ [138] -> [ ^ self lowcodePrimitiveMovePointerToPhysical ].
+ [139] -> [ ^ self lowcodePrimitiveMul32 ].
+ [140] -> [ ^ self lowcodePrimitiveMul64 ].
+ [141] -> [ ^ self lowcodePrimitiveNeg32 ].
+ [142] -> [ ^ self lowcodePrimitiveNeg64 ].
+ [143] -> [ ^ self lowcodePrimitiveNot32 ].
+ [144] -> [ ^ self lowcodePrimitiveNot64 ].
+ [145] -> [ ^ self lowcodePrimitiveOr32 ].
+ [146] -> [ ^ self lowcodePrimitiveOr64 ].
+ [147] -> [ ^ self lowcodePrimitivePerformCallFloat32 ].
+ [148] -> [ ^ self lowcodePrimitivePerformCallFloat64 ].
+ [149] -> [ ^ self lowcodePrimitivePerformCallIndirectFloat32 ].
+ [150] -> [ ^ self lowcodePrimitivePerformCallIndirectFloat64 ].
+ [151] -> [ ^ self lowcodePrimitivePerformCallIndirectInt32 ].
+ [152] -> [ ^ self lowcodePrimitivePerformCallIndirectInt64 ].
+ [153] -> [ ^ self lowcodePrimitivePerformCallIndirectPointer ].
+ [154] -> [ ^ self lowcodePrimitivePerformCallIndirectStructure ].
+ [155] -> [ ^ self lowcodePrimitivePerformCallIndirectVoid ].
+ [156] -> [ ^ self lowcodePrimitivePerformCallInt32 ].
+ [157] -> [ ^ self lowcodePrimitivePerformCallInt64 ].
+ [158] -> [ ^ self lowcodePrimitivePerformCallPointer ].
+ [159] -> [ ^ self lowcodePrimitivePerformCallStructure ].
+ [160] -> [ ^ self lowcodePrimitivePerformCallVoid ].
+ [161] -> [ ^ self lowcodePrimitivePlaftormCode ].
+ [162] -> [ ^ self lowcodePrimitivePointerAddConstantOffset ].
+ [163] -> [ ^ self lowcodePrimitivePointerAddOffset32 ].
+ [164] -> [ ^ self lowcodePrimitivePointerAddOffset64 ].
+ [165] -> [ ^ self lowcodePrimitivePointerEqual ].
+ [166] -> [ ^ self lowcodePrimitivePointerNotEqual ].
+ [167] -> [ ^ self lowcodePrimitivePointerToInt32 ].
+ [168] -> [ ^ self lowcodePrimitivePointerToInt64 ].
+ [169] -> [ ^ self lowcodePrimitivePopFloat32 ].
+ [170] -> [ ^ self lowcodePrimitivePopFloat64 ].
+ [171] -> [ ^ self lowcodePrimitivePopInt32 ].
+ [172] -> [ ^ self lowcodePrimitivePopInt64 ].
+ [173] -> [ ^ self lowcodePrimitivePopMultipleNative ].
+ [174] -> [ ^ self lowcodePrimitivePopPointer ].
+ [175] -> [ ^ self lowcodePrimitivePushConstantUInt32 ].
+ [176] -> [ ^ self lowcodePrimitivePushConstantUInt64 ].
+ [177] -> [ ^ self lowcodePrimitivePushNullPointer ].
+ [178] -> [ ^ self lowcodePrimitivePushOne32 ].
+ [179] -> [ ^ self lowcodePrimitivePushOne64 ].
+ }
+ otherwise: [ ^ self lowcodeUnaryInlinePrimitive4: prim ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeUnaryInlinePrimitive4: (in category 'inline primitive dispatch generated code') -----
+ lowcodeUnaryInlinePrimitive4: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [180] -> [ ^ self lowcodePrimitivePushOneFloat32 ].
+ [181] -> [ ^ self lowcodePrimitivePushOneFloat64 ].
+ [182] -> [ ^ self lowcodePrimitivePushPhysicalFloat32 ].
+ [183] -> [ ^ self lowcodePrimitivePushPhysicalFloat64 ].
+ [184] -> [ ^ self lowcodePrimitivePushPhysicalInt32 ].
+ [185] -> [ ^ self lowcodePrimitivePushPhysicalInt64 ].
+ [186] -> [ ^ self lowcodePrimitivePushPhysicalPointer ].
+ [187] -> [ ^ self lowcodePrimitivePushSessionIdentifier ].
+ [188] -> [ ^ self lowcodePrimitivePushZero32 ].
+ [189] -> [ ^ self lowcodePrimitivePushZero64 ].
+ [190] -> [ ^ self lowcodePrimitivePushZeroFloat32 ].
+ [191] -> [ ^ self lowcodePrimitivePushZeroFloat64 ].
+ [192] -> [ ^ self lowcodePrimitiveRem32 ].
+ [193] -> [ ^ self lowcodePrimitiveRem64 ].
+ [194] -> [ ^ self lowcodePrimitiveRightShift32 ].
+ [195] -> [ ^ self lowcodePrimitiveRightShift64 ].
+ [196] -> [ ^ self lowcodePrimitiveSignExtend32From16 ].
+ [197] -> [ ^ self lowcodePrimitiveSignExtend32From8 ].
+ [198] -> [ ^ self lowcodePrimitiveSignExtend64From16 ].
+ [199] -> [ ^ self lowcodePrimitiveSignExtend64From32 ].
+ [200] -> [ ^ self lowcodePrimitiveSignExtend64From8 ].
+ [201] -> [ ^ self lowcodePrimitiveStoreFloat32ToMemory ].
+ [202] -> [ ^ self lowcodePrimitiveStoreFloat64ToMemory ].
+ [203] -> [ ^ self lowcodePrimitiveStoreInt16ToMemory ].
+ [204] -> [ ^ self lowcodePrimitiveStoreInt32ToMemory ].
+ [205] -> [ ^ self lowcodePrimitiveStoreInt64ToMemory ].
+ [206] -> [ ^ self lowcodePrimitiveStoreInt8ToMemory ].
+ [207] -> [ ^ self lowcodePrimitiveStoreLocalFloat32 ].
+ [208] -> [ ^ self lowcodePrimitiveStoreLocalFloat64 ].
+ [209] -> [ ^ self lowcodePrimitiveStoreLocalInt16 ].
+ [210] -> [ ^ self lowcodePrimitiveStoreLocalInt32 ].
+ [211] -> [ ^ self lowcodePrimitiveStoreLocalInt64 ].
+ [212] -> [ ^ self lowcodePrimitiveStoreLocalInt8 ].
+ [213] -> [ ^ self lowcodePrimitiveStoreLocalPointer ].
+ [214] -> [ ^ self lowcodePrimitiveStorePointerToMemory ].
+ [215] -> [ ^ self lowcodePrimitiveSub32 ].
+ [216] -> [ ^ self lowcodePrimitiveSub64 ].
+ [217] -> [ ^ self lowcodePrimitiveTruncate32To16 ].
+ [218] -> [ ^ self lowcodePrimitiveTruncate32To8 ].
+ [219] -> [ ^ self lowcodePrimitiveTruncate64To16 ].
+ [220] -> [ ^ self lowcodePrimitiveTruncate64To32 ].
+ [221] -> [ ^ self lowcodePrimitiveTruncate64To8 ].
+ [222] -> [ ^ self lowcodePrimitiveUdiv32 ].
+ [223] -> [ ^ self lowcodePrimitiveUdiv64 ].
+ [224] -> [ ^ self lowcodePrimitiveUint32Great ].
+ [225] -> [ ^ self lowcodePrimitiveUint32GreatEqual ].
+ [226] -> [ ^ self lowcodePrimitiveUint32Less ].
+ [227] -> [ ^ self lowcodePrimitiveUint32LessEqual ].
+ [228] -> [ ^ self lowcodePrimitiveUint32ToFloat32 ].
+ [229] -> [ ^ self lowcodePrimitiveUint32ToFloat64 ].
+ [230] -> [ ^ self lowcodePrimitiveUint64Great ].
+ [231] -> [ ^ self lowcodePrimitiveUint64GreatEqual ].
+ [232] -> [ ^ self lowcodePrimitiveUint64Less ].
+ [233] -> [ ^ self lowcodePrimitiveUint64LessEqual ].
+ [234] -> [ ^ self lowcodePrimitiveUint64ToFloat32 ].
+ [235] -> [ ^ self lowcodePrimitiveUint64ToFloat64 ].
+ [236] -> [ ^ self lowcodePrimitiveUmul32 ].
+ [237] -> [ ^ self lowcodePrimitiveUmul64 ].
+ [238] -> [ ^ self lowcodePrimitiveUnlockRegisters ].
+ [239] -> [ ^ self lowcodePrimitiveUnlockVM ].
+ }
+ otherwise: [ ^ self lowcodeUnaryInlinePrimitive5: prim ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeUnaryInlinePrimitive5: (in category 'inline primitive dispatch generated code') -----
+ lowcodeUnaryInlinePrimitive5: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [240] -> [ ^ self lowcodePrimitiveUrem32 ].
+ [241] -> [ ^ self lowcodePrimitiveUrem64 ].
+ [242] -> [ ^ self lowcodePrimitiveXor32 ].
+ [243] -> [ ^ self lowcodePrimitiveXor64 ].
+ [244] -> [ ^ self lowcodePrimitiveZeroExtend32From16 ].
+ [245] -> [ ^ self lowcodePrimitiveZeroExtend32From8 ].
+ [246] -> [ ^ self lowcodePrimitiveZeroExtend64From16 ].
+ [247] -> [ ^ self lowcodePrimitiveZeroExtend64From32 ].
+ [248] -> [ ^ self lowcodePrimitiveZeroExtend64From8 ].
+ }
+ otherwise: [
+ localIP := localIP - 3.
+ ^self respondToUnknownBytecode
+ ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>lowcodeUnaryInlinePrimitive: (in category 'inline primitive dispatch generated code') -----
+ lowcodeUnaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction interpreter dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self lowcodePrimitiveAdd32 ].
+ [1] -> [ ^ self lowcodePrimitiveAdd64 ].
+ [2] -> [ ^ self lowcodePrimitiveAlloca32 ].
+ [3] -> [ ^ self lowcodePrimitiveAlloca64 ].
+ [4] -> [ ^ self lowcodePrimitiveAnd32 ].
+ [5] -> [ ^ self lowcodePrimitiveAnd64 ].
+ [6] -> [ ^ self lowcodePrimitiveArithmeticRightShift32 ].
+ [7] -> [ ^ self lowcodePrimitiveArithmeticRightShift64 ].
+ [8] -> [ ^ self lowcodePrimitiveBeginCall ].
+ [9] -> [ ^ self lowcodePrimitiveCallArgumentFloat32 ].
+ [10] -> [ ^ self lowcodePrimitiveCallArgumentFloat64 ].
+ [11] -> [ ^ self lowcodePrimitiveCallArgumentInt32 ].
+ [12] -> [ ^ self lowcodePrimitiveCallArgumentInt64 ].
+ [13] -> [ ^ self lowcodePrimitiveCallArgumentPointer ].
+ [14] -> [ ^ self lowcodePrimitiveCallArgumentSpace ].
+ [15] -> [ ^ self lowcodePrimitiveCallArgumentStructure ].
+ [16] -> [ ^ self lowcodePrimitiveCallInstruction ].
+ [17] -> [ ^ self lowcodePrimitiveCallPhysical ].
+ [18] -> [ ^ self lowcodePrimitiveCheckSessionIdentifier ].
+ [19] -> [ ^ self lowcodePrimitiveCompareAndSwap32 ].
+ [20] -> [ ^ self lowcodePrimitiveDiv32 ].
+ [21] -> [ ^ self lowcodePrimitiveDiv64 ].
+ [22] -> [ ^ self lowcodePrimitiveDuplicateFloat32 ].
+ [23] -> [ ^ self lowcodePrimitiveDuplicateFloat64 ].
+ [24] -> [ ^ self lowcodePrimitiveDuplicateInt32 ].
+ [25] -> [ ^ self lowcodePrimitiveDuplicateInt64 ].
+ [26] -> [ ^ self lowcodePrimitiveDuplicatePointer ].
+ [27] -> [ ^ self lowcodePrimitiveEffectiveAddress32 ].
+ [28] -> [ ^ self lowcodePrimitiveEffectiveAddress64 ].
+ [29] -> [ ^ self lowcodePrimitiveEndCall ].
+ [30] -> [ ^ self lowcodePrimitiveEndCallNoCleanup ].
+ [31] -> [ ^ self lowcodePrimitiveFloat32Add ].
+ [32] -> [ ^ self lowcodePrimitiveFloat32Div ].
+ [33] -> [ ^ self lowcodePrimitiveFloat32Equal ].
+ [34] -> [ ^ self lowcodePrimitiveFloat32Great ].
+ [35] -> [ ^ self lowcodePrimitiveFloat32GreatEqual ].
+ [36] -> [ ^ self lowcodePrimitiveFloat32Less ].
+ [37] -> [ ^ self lowcodePrimitiveFloat32LessEqual ].
+ [38] -> [ ^ self lowcodePrimitiveFloat32Mul ].
+ [39] -> [ ^ self lowcodePrimitiveFloat32Neg ].
+ [40] -> [ ^ self lowcodePrimitiveFloat32NotEqual ].
+ [41] -> [ ^ self lowcodePrimitiveFloat32Sqrt ].
+ [42] -> [ ^ self lowcodePrimitiveFloat32Sub ].
+ [43] -> [ ^ self lowcodePrimitiveFloat32ToFloat64 ].
+ [44] -> [ ^ self lowcodePrimitiveFloat32ToInt32 ].
+ [45] -> [ ^ self lowcodePrimitiveFloat32ToInt64 ].
+ [46] -> [ ^ self lowcodePrimitiveFloat32ToUInt32 ].
+ [47] -> [ ^ self lowcodePrimitiveFloat32ToUInt64 ].
+ [48] -> [ ^ self lowcodePrimitiveFloat64Add ].
+ [49] -> [ ^ self lowcodePrimitiveFloat64Div ].
+ [50] -> [ ^ self lowcodePrimitiveFloat64Equal ].
+ [51] -> [ ^ self lowcodePrimitiveFloat64Great ].
+ [52] -> [ ^ self lowcodePrimitiveFloat64GreatEqual ].
+ [53] -> [ ^ self lowcodePrimitiveFloat64Less ].
+ [54] -> [ ^ self lowcodePrimitiveFloat64LessEqual ].
+ [55] -> [ ^ self lowcodePrimitiveFloat64Mul ].
+ [56] -> [ ^ self lowcodePrimitiveFloat64Neg ].
+ [57] -> [ ^ self lowcodePrimitiveFloat64NotEqual ].
+ [58] -> [ ^ self lowcodePrimitiveFloat64Sqrt ].
+ [59] -> [ ^ self lowcodePrimitiveFloat64Sub ].
+ }
+ otherwise: [ ^ self lowcodeUnaryInlinePrimitive2: prim ].
+
+
+ !
Item was added:
+ ----- Method: StackInterpreter>>nativeFramePointerIn: (in category 'internal interpreter access') -----
+ nativeFramePointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*3)!
Item was added:
+ ----- Method: StackInterpreter>>nativeFramePointerIn:put: (in category 'internal interpreter access') -----
+ nativeFramePointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char*'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*3) put: valueOopPointer!
Item was added:
+ ----- Method: StackInterpreter>>nativeFrameSignalObjectIn: (in category 'internal interpreter access') -----
+ nativeFrameSignalObjectIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <var: #theFP type: #'char *'>
+ ^ stackPages longAt: theFP + FoxReceiver - (BytesPerWord*3)!
Item was added:
+ ----- Method: StackInterpreter>>nativeFrameSignalObjectIn:put: (in category 'internal interpreter access') -----
+ nativeFrameSignalObjectIn: theFP put: oop
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <var: #theFP type: #'char *'>
+ ^ stackPages longAt: theFP + FoxReceiver - BytesPerWord put: oop!
Item was added:
+ ----- Method: StackInterpreter>>nativePreviousStackPointerIn: (in category 'internal interpreter access') -----
+ nativePreviousStackPointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*2)!
Item was added:
+ ----- Method: StackInterpreter>>nativePreviousStackPointerIn:put: (in category 'internal interpreter access') -----
+ nativePreviousStackPointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char*'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*2) put: valueOopPointer!
Item was added:
+ ----- Method: StackInterpreter>>nativeStackPointerIn: (in category 'internal interpreter access') -----
+ nativeStackPointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*4)!
Item was added:
+ ----- Method: StackInterpreter>>nativeStackPointerIn:put: (in category 'internal interpreter access') -----
+ nativeStackPointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <inline: false>
+ <option: #LowcodeVM>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char *'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*4) put: valueOopPointer!
Item was added:
+ ----- Method: StackInterpreter>>nativeStackSize (in category 'stack pages') -----
+ nativeStackSize
+ "4 MB native stack size"
+ ^ 4 *1024 * 1024!
Item was added:
+ ----- Method: StackInterpreter>>reloadLowcodeStateAfterCallout (in category 'inline primitive ffi abi') -----
+ reloadLowcodeStateAfterCallout
+ <option: #LowcodeVM>
+ <var: #initialShadowCallStackPointer type: #'char*' >
+
+ | calloutStateSize initialShadowCallStackPointer |
+ calloutStateSize := self sizeof: #'sqLowcodeCalloutState'.
+ initialShadowCallStackPointer := (self shadowCallStackPointerIn: localFP) - 1.
+
+ initialShadowCallStackPointer := self cCoerce: ((self cCoerce: initialShadowCallStackPointer - calloutStateSize to: 'size_t') bitAnd: -16) to: 'char*'.
+ lowcodeCalloutState := self cCoerce: initialShadowCallStackPointer to: #'sqLowcodeCalloutState*'.!
Item was changed:
----- Method: StackInterpreter>>returnAs:ThroughCallback:Context: (in category 'callback support') -----
returnAs: returnTypeOop ThroughCallback: vmCallbackContext Context: callbackMethodContext
"callbackMethodContext is an activation of invokeCallback:[stack:registers:jmpbuf:].
Its sender is the VM's state prior to the callback. Reestablish that state (via longjmp),
and mark callbackMethodContext as dead."
<export: true>
<var: #vmCallbackContext type: #'VMCallbackContext *'>
| calloutMethodContext theFP thePage |
<var: #theFP type: #'char *'>
<var: #thePage type: #'StackPage *'>
((self isIntegerObject: returnTypeOop)
and: [self isLiveContext: callbackMethodContext]) ifFalse:
[^false].
calloutMethodContext := self externalInstVar: SenderIndex ofContext: callbackMethodContext.
(self isLiveContext: calloutMethodContext) ifFalse:
[^false].
"We're about to leave this stack page; must save the current frame's instructionPointer."
self push: instructionPointer.
self externalWriteBackHeadFramePointers.
"Mark callbackMethodContext as dead; the common case is that it is the current frame.
We go the extra mile for the debugger."
(self isSingleContext: callbackMethodContext)
ifTrue: [self markContextAsDead: callbackMethodContext]
ifFalse:
[theFP := self frameOfMarriedContext: callbackMethodContext.
framePointer = theFP "common case"
ifTrue:
[(self isBaseFrame: theFP)
ifTrue: [stackPages freeStackPage: stackPage]
ifFalse: "calloutMethodContext is immediately below on the same page. Make it current."
[instructionPointer := (self frameCallerSavedIP: framePointer) asUnsignedInteger.
stackPointer := framePointer + (self frameStackedReceiverOffset: framePointer) + objectMemory wordSize.
framePointer := self frameCallerFP: framePointer.
self setMethod: (self frameMethodObject: framePointer).
self restoreCStackStateForCallbackContext: vmCallbackContext.
"N.B. siglongjmp is defines as _longjmp on non-win32 platforms.
This matches the use of _setjmp in ia32abicc.c."
self siglong: vmCallbackContext trampoline jmp: (self integerValueOf: returnTypeOop).
^true]]
ifFalse:
[self externalDivorceFrame: theFP andContext: callbackMethodContext.
self markContextAsDead: callbackMethodContext]].
"Make the calloutMethodContext the active frame. The case where calloutMethodContext
is immediately below callbackMethodContext on the same page is handled above."
(self isStillMarriedContext: calloutMethodContext)
ifTrue:
[theFP := self frameOfMarriedContext: calloutMethodContext.
thePage := stackPages stackPageFor: theFP.
"findSPOf:on: points to the word beneath the instructionPointer, but
there is no instructionPointer on the top frame of the current page."
self assert: thePage ~= stackPage.
stackPointer := (self findSPOf: theFP on: thePage) - objectMemory wordSize.
framePointer := theFP]
ifFalse:
[thePage := self makeBaseFrameFor: calloutMethodContext.
framePointer := thePage headFP.
stackPointer := thePage headSP].
instructionPointer := self popStack.
self setMethod: (objectMemory fetchPointer: MethodIndex ofObject: calloutMethodContext).
self setStackPageAndLimit: thePage.
self restoreCStackStateForCallbackContext: vmCallbackContext.
"N.B. siglongjmp is defines as _longjmp on non-win32 platforms.
This matches the use of _setjmp in ia32abicc.c."
self siglong: vmCallbackContext trampoline jmp: (self integerValueOf: returnTypeOop).
"NOTREACHED"
^true!
Item was added:
+ ----- Method: StackInterpreter>>setFrameHasNativeFrame: (in category 'frame access') -----
+ setFrameHasNativeFrame: theFP
+ <inline: true>
+ <var: #theFP type: #'char *'>
+ self temporary: (self frameNumArgs: theFP) in: theFP put: (objectMemory splObj: LowcodeContextMark)!
Item was added:
+ ----- Method: StackInterpreter>>setFrameHasNotNativeFrame: (in category 'frame access') -----
+ setFrameHasNotNativeFrame: theFP
+ <inline: true>
+ <option: #LowcodeVM>
+ <var: #theFP type: #'char *'>
+ self temporary: (self frameNumArgs: theFP) in: theFP put: (objectMemory nilObject)!
Item was added:
+ ----- Method: StackInterpreter>>setupNativeStack (in category 'initialization') -----
+ setupNativeStack
+ <option: #LowcodeVM>
+ <var: #theNativeStackMemory type: #'char*'>
+ <var: #theShadowCallStackMemory type: #'char*'>
+ <inline: false>
+ "This initializes an alternate stack that is used by the Lowcode instructions"
+ | nativeStackMemorySize theNativeStackMemory shadowCallStackMemorySize theShadowCallStackMemory|
+ nativeStackMemorySize := self nativeStackSize.
+ theNativeStackMemory := self
+ cCode: [self malloc: nativeStackMemorySize ]
+ inSmalltalk: [CArrayAccessor on: (ByteArray new: self nativeStackSize)].
+ nativeStackPointer := theNativeStackMemory + nativeStackMemorySize.
+
+ shadowCallStackMemorySize := self shadowCallStackSize.
+ theShadowCallStackMemory := self
+ cCode: [self malloc: shadowCallStackMemorySize ]
+ inSmalltalk: [CArrayAccessor on: (ByteArray new: self shadowCallStackSize)].
+ shadowCallStackPointer := theShadowCallStackMemory + shadowCallStackMemorySize.!
Item was added:
+ ----- Method: StackInterpreter>>shadowCallStackPointerIn: (in category 'internal interpreter access') -----
+ shadowCallStackPointerIn: theFP
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <inline: false>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*5)!
Item was added:
+ ----- Method: StackInterpreter>>shadowCallStackPointerIn:put: (in category 'internal interpreter access') -----
+ shadowCallStackPointerIn: theFP put: valueOopPointer
+ "See StackInterpreter class>>initializeFrameIndices"
+ <option: #LowcodeVM>
+ <inline: false>
+ <returnTypeC: #'char*'>
+ <var: #theFP type: #'char *'>
+ <var: #valueOopPointer type: #'char*'>
+ ^ stackPages pointerAtPointer: theFP + FoxReceiver - (BytesPerWord*5) put: valueOopPointer!
Item was added:
+ ----- Method: StackInterpreter>>shadowCallStackSize (in category 'stack pages') -----
+ shadowCallStackSize
+ "1 MB shadow call stack size"
+ ^ 1 *1024 * 1024!
Item was changed:
SimpleStackBasedCogit subclass: #StackToRegisterMappingCogit
+ instanceVariableNames: 'prevBCDescriptor numPushNilsFunction pushNilSizeFunction methodOrBlockNumTemps regArgsHaveBeenPushed simSelf simStack simStackPtr simSpillBase optStatus ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs methodAbortTrampolines picAbortTrampolines picMissTrampolines ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC debugStackPointers debugFixupBreaks realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs deadCode useTwoPaths currentCallCleanUpSize simNativeStack simNativeStackPtr simNativeSpillBase simNativeStackSize hasNativeFrame'
- instanceVariableNames: 'prevBCDescriptor numPushNilsFunction pushNilSizeFunction methodOrBlockNumTemps regArgsHaveBeenPushed simSelf simStack simStackPtr simSpillBase optStatus ceCallCogCodePopReceiverArg0Regs ceCallCogCodePopReceiverArg1Arg0Regs methodAbortTrampolines picAbortTrampolines picMissTrampolines ceCall0ArgsPIC ceCall1ArgsPIC ceCall2ArgsPIC debugStackPointers debugFixupBreaks realCECallCogCodePopReceiverArg0Regs realCECallCogCodePopReceiverArg1Arg0Regs deadCode useTwoPaths'
classVariableNames: 'NeedsMergeFixupFlag NeedsNonMergeFixupFlag'
poolDictionaries: 'CogCompilationConstants VMMethodCacheConstants VMObjectIndices VMStackFrameOffsets'
category: 'VMMaker-JIT'!
StackToRegisterMappingCogit class
instanceVariableNames: 'numPushNilsFunction pushNilSizeFunction'!
!StackToRegisterMappingCogit commentStamp: 'eem 6/1/2016 14:50' prior: 0!
StackToRegisterMappingCogit is an optimizing code generator that eliminates a lot of stack operations and inlines some special selector arithmetic. It does so by a simple stack-to-register mapping scheme based on deferring the generation of code to produce operands until operand-consuming operations. The operations that consume operands are sends, stores and returns.
See methods in the class-side documentation protocol for more detail.
Instance Variables
callerSavedRegMask: <Integer>
ceEnter0ArgsPIC: <Integer>
ceEnter1ArgsPIC: <Integer>
ceEnter2ArgsPIC: <Integer>
ceEnterCogCodePopReceiverArg0Regs: <Integer>
ceEnterCogCodePopReceiverArg1Arg0Regs: <Integer>
debugBytecodePointers: <Set of Integer>
debugFixupBreaks: <Set of Integer>
debugStackPointers: <CArrayAccessor of (Integer|nil)>
methodAbortTrampolines: <CArrayAccessor of Integer>
methodOrBlockNumTemps: <Integer>
optStatus: <Integer>
picAbortTrampolines: <CArrayAccessor of Integer>
picMissTrampolines: <CArrayAccessor of Integer>
realCEEnterCogCodePopReceiverArg0Regs: <Integer>
realCEEnterCogCodePopReceiverArg1Arg0Regs: <Integer>
regArgsHaveBeenPushed: <Boolean>
simSelf: <CogSimStackEntry>
simSpillBase: <Integer>
simStack: <CArrayAccessor of CogSimStackEntry>
simStackPtr: <Integer>
traceSimStack: <Integer>
useTwoPaths <Boolean>
callerSavedRegMask
- the bitmask of the ABI's caller-saved registers
ceEnter0ArgsPIC ceEnter1ArgsPIC ceEnter2ArgsPIC
- the trampoline for entering an N-arg PIC
ceEnterCogCodePopReceiverArg0Regs ceEnterCogCodePopReceiverArg1Arg0Regs
- teh trampoline for entering a method with N register args
debugBytecodePointers
- a Set of bytecode pcs for setting breakpoints (simulation only)
debugFixupBreaks
- a Set of fixup indices for setting breakpoints (simulation only)
debugStackPointers
- an Array of stack depths for each bytecode for code verification
methodAbortTrampolines
- a CArrayAccessor of abort trampolines for 0, 1, 2 and N args
methodOrBlockNumTemps
- the number of method or block temps (including args) in the current compilation unit (method or block)
optStatus
- the variable used to track the status of ReceiverResultReg for avoiding reloading that register with self between adjacent inst var accesses
picAbortTrampolines
- a CArrayAccessor of abort trampolines for 0, 1, 2 and N args
picMissTrampolines
- a CArrayAccessor of abort trampolines for 0, 1, 2 and N args
realCEEnterCogCodePopReceiverArg0Regs realCEEnterCogCodePopReceiverArg1Arg0Regs
- the real trampolines for ebtering machine code with N reg args when in the Debug regime
regArgsHaveBeenPushed
- whether the register args have been pushed before frame build (e.g. when an interpreter primitive is called)
simSelf
- the simulation stack entry representing self in the current compilation unit
simSpillBase
- the variable tracking how much of the simulation stack has been spilled to the real stack
simStack
- the simulation stack itself
simStackPtr
- the pointer to the top of the simulation stack
useTwoPaths
- a variable controlling whether to create two paths through a method based on the existence of inst var stores. With immutability this causes a frameless path to be generated if an otherwise frameless method is frameful simply because of inst var stores. In this case the test to take the first frameless path is if the receiver is not immutable. Without immutability, if a frameless method contains two or more inst var stores, the first path will be code with no store check, chosen by a single check for the receiver being in new space.
!
StackToRegisterMappingCogit class
instanceVariableNames: 'numPushNilsFunction pushNilSizeFunction'!
Item was changed:
----- Method: StackToRegisterMappingCogit class>>ancilliaryClasses: (in category 'translation') -----
ancilliaryClasses: options
^(super ancilliaryClasses: options),
+ { self basicNew simStackEntryClass. self basicNew bytecodeFixupClass. CogSSOptStatus } ,
+ (LowcodeVM ifTrue: [ { self basicNew simStackNativeEntryClass } ] ifFalse: [ #() ])!
- { self basicNew simStackEntryClass. self basicNew bytecodeFixupClass. CogSSOptStatus }!
Item was changed:
----- Method: StackToRegisterMappingCogit class>>declareCVarsIn: (in category 'translation') -----
declareCVarsIn: aCodeGen
aCodeGen
var: #methodAbortTrampolines
declareC: 'sqInt methodAbortTrampolines[4]';
var: #picAbortTrampolines
declareC: 'sqInt picAbortTrampolines[4]';
var: #picMissTrampolines
declareC: 'sqInt picMissTrampolines[4]';
var: 'ceCall0ArgsPIC'
declareC: 'void (*ceCall0ArgsPIC)(void)';
var: 'ceCall1ArgsPIC'
declareC: 'void (*ceCall1ArgsPIC)(void)';
var: 'ceCall2ArgsPIC'
declareC: 'void (*ceCall2ArgsPIC)(void)';
var: #ceCallCogCodePopReceiverArg0Regs
declareC: 'void (*ceCallCogCodePopReceiverArg0Regs)(void)';
var: #realCECallCogCodePopReceiverArg0Regs
declareC: 'void (*realCECallCogCodePopReceiverArg0Regs)(void)';
var: #ceCallCogCodePopReceiverArg1Arg0Regs
declareC: 'void (*ceCallCogCodePopReceiverArg1Arg0Regs)(void)';
var: #realCECallCogCodePopReceiverArg1Arg0Regs
declareC: 'void (*realCECallCogCodePopReceiverArg1Arg0Regs)(void)';
var: 'simStack'
declareC: 'SimStackEntry simStack[', self simStackSlots asString, ']';
var: 'simSelf'
type: #CogSimStackEntry;
var: #optStatus
type: #CogSSOptStatus;
var: 'prevBCDescriptor'
type: #'BytecodeDescriptor *'.
+ LowcodeVM ifTrue: [
+ aCodeGen var: 'simNativeStack'
+ declareC: 'CogSimStackNativeEntry simNativeStack[', ((CoInterpreter bindingOf: #LargeContextSlots) value * 5 / 4 // BytesPerWord) asString, ']'
+ ].
self numPushNilsFunction ifNotNil:
[aCodeGen
var: 'numPushNilsFunction'
declareC: 'sqInt (* const numPushNilsFunction)(struct _BytecodeDescriptor *,sqInt,sqInt,sqInt) = ', (aCodeGen cFunctionNameFor: self numPushNilsFunction);
var: 'pushNilSizeFunction'
declareC: 'sqInt (* const pushNilSizeFunction)(sqInt,sqInt) = ', (aCodeGen cFunctionNameFor: self pushNilSizeFunction)].
aCodeGen
addSelectorTranslation: #register to: (aCodeGen cFunctionNameFor: 'registerr');
addSelectorTranslation: #register: to: (aCodeGen cFunctionNameFor: 'registerr:')!
Item was changed:
----- Method: StackToRegisterMappingCogit class>>initializeSimStackConstants (in category 'class initialization') -----
initializeSimStackConstants
"The simulation stack is used to delay code generation until operands are consumed by
some operation, thereby avoiding pushing operands to the real stack and enabling
mapping stack contents to registers, and cheaply apply various peephole optimizations.
The simulation stack is an array of CogSimStackEntry structs. Each entry defines the
object on the virtual stack (Smalltalk context stack) as compilation proceeds. See
stackToRegisterMapping in this class for documentation."
SSIllegal := 0.
SSBaseOffset := 1.
SSConstant := 2.
SSRegister := 3.
+ SSSpill := 4.
+
+ " Native simulation stack"
+ SSNativeRegister := 5.
+ SSRegisterPair := 6.
+ SSRegisterDoubleFloat := 7.
+ SSRegisterSingleFloat := 8.
+
+ SSSpillNative := 9.
+ SSSpillInt64 := 10.
+ SSSpillFloat32 := 11.
+ SSSpillFloat64 := 12.
+
+ SSConstantInt32 := 13.
+ SSConstantInt64 := 14.
+ SSConstantFloat32 := 15.
+ SSConstantFloat64 := 16.
+ SSConstantNativePointer := 17.!
- SSSpill := 4!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>beginHighLevelCall: (in category 'inline ffi') -----
+ beginHighLevelCall: alignment
+ <option: #LowcodeVM>
+ | mask actualAlignment |
+
+ "Store the smalltalk pointers"
+ self ssFlushAll.
+ self MoveR: SPReg Aw: coInterpreter stackPointerAddress.
+ self MoveR: FPReg Aw: coInterpreter framePointerAddress.
+ backEnd hasLinkRegister ifTrue: [
+ self MoveAw: coInterpreter instructionPointerAddress R: LinkReg
+ ].
+
+ "Load the C pointers"
+ self MoveAw: self cStackPointerAddress R: SPReg.
+
+ "Load the native stack frame pointer"
+ self MoveMw: self frameOffsetOfNativeFramePointer r: FPReg R: FPReg.
+ self SubCq: 1 R: FPReg.
+
+ actualAlignment := (alignment max: BytesPerWord).
+ actualAlignment > BytesPerWord ifTrue: [
+ mask := actualAlignment negated.
+ self AndCq: mask R: SPReg.
+ ].
+ currentCallCleanUpSize := 0.!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>callSwitchToCStack (in category 'inline ffi') -----
+ callSwitchToCStack
+ <option: #LowcodeVM>
+ self MoveAw: self cFramePointerAddress R: FPReg.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>callSwitchToSmalltalkStack (in category 'inline ffi') -----
+ callSwitchToSmalltalkStack
+ <option: #LowcodeVM>
+ "Restore the link register"
+ backEnd hasLinkRegister ifTrue: [
+ self MoveAw: coInterpreter instructionPointerAddress R: LinkReg
+ ].
+ backEnd genLoadStackPointers.!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>endHighLevelCallWithCleanup (in category 'inline ffi') -----
+ endHighLevelCallWithCleanup
+ <option: #LowcodeVM>
+ currentCallCleanUpSize > 0 ifTrue: [
+ self AddCq: currentCallCleanUpSize R: SPReg
+ ].
+ self callSwitchToSmalltalkStack.
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>endHighLevelCallWithoutCleanup (in category 'inline ffi') -----
+ endHighLevelCallWithoutCleanup
+ <option: #LowcodeVM>
+ self callSwitchToSmalltalkStack.!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ensureFixupAt: (in category 'compile abstract instructions') -----
ensureFixupAt: targetIndex
"Make sure there's a flagged fixup at the targetIndex (pc relative to first pc) in fixups.
Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction."
<returnTypeC: #'BytecodeFixup *'>
| fixup |
<var: #fixup type: #'BytecodeFixup *'>
fixup := self fixupAt: targetIndex.
self traceFixup: fixup.
self cCode: '' inSmalltalk:
[self assert: simStackPtr = (self debugStackPointerFor: targetIndex + initialPC).
(fixup isMergeFixupOrIsFixedUp
and: [fixup isBackwardBranchFixup not]) ifTrue: "ignore backward branch targets"
[self assert: fixup simStackPtr = simStackPtr]].
fixup isNonMergeFixupOrNotAFixup
ifTrue: "convert a non-merge into a merge"
[fixup becomeMergeFixup.
+ fixup simStackPtr: simStackPtr.
+ self cppIf: LowcodeVM ifTrue: [
+ fixup simNativeStackPtr: simNativeStackPtr.
+ fixup simNativeStackSize: simNativeStackSize.]]
- fixup simStackPtr: simStackPtr]
ifFalse:
[fixup isBackwardBranchFixup
ifTrue: ["this is the target of a backward branch and
so doesn't have a simStackPtr assigned yet."
+ fixup simStackPtr: simStackPtr.
+ self cppIf: LowcodeVM ifTrue: [
+ fixup simNativeStackPtr: simNativeStackPtr.
+ fixup simNativeStackSize: simNativeStackSize.]]
+ ifFalse: [
+ self assert: fixup simStackPtr = simStackPtr.
+ self cppIf: LowcodeVM ifTrue: [
+ self assert: fixup simNativeStackPtr = simNativeStackPtr.
+ self assert: fixup simNativeStackSize = simNativeStackSize.]]].
- fixup simStackPtr: simStackPtr]
- ifFalse: [self assert: fixup simStackPtr = simStackPtr]].
^fixup!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genCallPrimitiveBytecode (in category 'bytecode generators') -----
+ genCallPrimitiveBytecode
+ "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
+ See EncoderForSistaV1's class comment and StackInterpreter>>#inlinePrimitiveBytecode:"
+ | prim primSet |
+ byte2 < 128 ifTrue:
+ [^bytecodePC = initialPC
+ ifTrue: [0]
+ ifFalse: [EncounteredUnknownBytecode]].
+ prim := byte2 - 128 << 8 + byte1.
+ primSet := prim >> 13 bitAnd: 3.
+ prim := prim bitAnd: 8191.
+ self cppIf: LowcodeVM
+ ifTrue:
+ [
+ primSet = 1 ifTrue: [
+ prim < 1000 ifTrue:
+ [^self genLowcodeNullaryInlinePrimitive: prim].
+
+ prim < 2000 ifTrue:
+ [^self genLowcodeUnaryInlinePrimitive: prim - 1000].
+
+ prim < 3000 ifTrue:
+ [^ self genLowcodeBinaryInlinePrimitive: prim - 2000].
+
+ prim < 4000 ifTrue:
+ [^self genLowcodeTrinaryInlinePrimitive: prim - 3000].
+ ]
+ ].
+
+ ^EncounteredUnknownBytecode!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode (in category 'bytecode generators') -----
+ genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode
+ "SistaV1: * 254 11111110 kkkkkkkk jjjjjjjj branch If Not Instance Of Behavior/Array Of Behavior kkkkkkkk (+ Extend A * 256, where Extend A >= 0) distance jjjjjjjj (+ Extend B * 256, where Extend B >= 0)"
+
+ | reg literal distance targetFixUp |
+
+ "We loose the information of in which register is stack top
+ when jitting the branch target so we need to flush everything.
+ We could use a fixed register here...."
+ reg := self allocateRegForStackEntryAt: 0.
+ self ssTop popToReg: reg.
+ self ssFlushTo: simStackPtr. "flushed but the value is still in reg"
+
+ literal := self getLiteral: (extA * 256 + byte1).
+ extA := 0.
+ distance := extB * 256 + byte2.
+ extB := 0.
+
+ targetFixUp := self cCoerceSimple: (self ensureFixupAt: bytecodePC + 3 + distance - initialPC) to: #'AbstractInstruction *'.
+
+ (objectMemory isArrayNonImm: literal)
+ ifTrue: [objectRepresentation branchIf: reg notInstanceOfBehaviors: literal target: targetFixUp]
+ ifFalse: [objectRepresentation branchIf: reg notInstanceOfBehavior: literal target: targetFixUp].
+
+ self genPopStackBytecode.
+
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeAdd32 (in category 'inline primitive generators generated code') -----
+ genLowcodeAdd32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self AddR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeAdd64 (in category 'inline primitive generators generated code') -----
+ genLowcodeAdd64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh first second firstHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (secondLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
+
+ (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
+
+ (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
+ (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
+ self ssNativePop: 1.
+
+ self AddR: secondLow R: firstLow.
+ self AddcR: secondHigh R: firstHigh.
+ self ssPushNativeRegister: firstLow secondRegister: firstHigh.
+
+ ] ifFalse: [
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self AddR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeAlloca32 (in category 'inline primitive generators generated code') -----
+ genLowcodeAlloca32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | size |
+
+ (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (size := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ size = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: size.
+ self ssNativePop: 1.
+
+ self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
+ self SubR: size R: TempReg.
+ self AndCq: -16 R: TempReg.
+ self MoveR: TempReg R: size.
+ self MoveR: size Aw: coInterpreter nativeStackPointerAddress.
+ self ssPushNativeRegister: size.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeAlloca64 (in category 'inline primitive generators generated code') -----
+ genLowcodeAlloca64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | sizeHigh size sizeLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (sizeLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (sizeLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (sizeHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: sizeLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (sizeHigh := Arg1Reg)].
+ (sizeLow = ReceiverResultReg or: [sizeHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: sizeLow secondReg: sizeHigh.
+ self ssNativePop: 1.
+
+ self SubR: sizeLow R: SPReg.
+ self MoveR: SPReg R: sizeLow.
+ self ssPushNativeRegister: sizeLow.
+
+ ] ifFalse: [
+
+ (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (size := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ size = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: size.
+ self ssNativePop: 1.
+
+ self SubR: size R: SPReg.
+ self MoveR: SPReg R: size.
+ self ssPushNativeRegister: size.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeAnd32 (in category 'inline primitive generators generated code') -----
+ genLowcodeAnd32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self AndR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeAnd64 (in category 'inline primitive generators generated code') -----
+ genLowcodeAnd64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh first second firstHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (secondLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
+
+ (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
+
+ (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
+ (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
+ self ssNativePop: 1.
+
+ self AndR: secondLow R: firstLow.
+ self AndR: secondHigh R: firstHigh.
+ self ssPushNativeRegister: firstLow secondRegister: firstHigh.
+
+ ] ifFalse: [
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self AndR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeArithmeticRightShift32 (in category 'inline primitive generators generated code') -----
+ genLowcodeArithmeticRightShift32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount |
+
+ (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (shiftAmount := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: shiftAmount.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ArithmeticShiftRightR: shiftAmount R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeArithmeticRightShift64 (in category 'inline primitive generators generated code') -----
+ genLowcodeArithmeticRightShift64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh |
+
+ (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (shiftAmount := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: shiftAmount.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeBeginCall (in category 'inline primitive generators generated code') -----
+ genLowcodeBeginCall
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | alignment |
+ alignment := extA.
+
+ self beginHighLevelCall: alignment.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeBinaryInlinePrimitive: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeBinaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self genLowcodeByteSizeOf ].
+ [1] -> [ ^ self genLowcodeFirstFieldPointer ].
+ [2] -> [ ^ self genLowcodeFirstIndexableFieldPointer ].
+ [3] -> [ ^ self genLowcodeIsBytes ].
+ [4] -> [ ^ self genLowcodeIsFloatObject ].
+ [5] -> [ ^ self genLowcodeIsIndexable ].
+ [6] -> [ ^ self genLowcodeIsIntegerObject ].
+ [7] -> [ ^ self genLowcodeIsPointers ].
+ [8] -> [ ^ self genLowcodeIsWords ].
+ [9] -> [ ^ self genLowcodeIsWordsOrBytes ].
+ [10] -> [ ^ self genLowcodeOopSmallIntegerToInt32 ].
+ [11] -> [ ^ self genLowcodeOopSmallIntegerToInt64 ].
+ [12] -> [ ^ self genLowcodeOopToBoolean32 ].
+ [13] -> [ ^ self genLowcodeOopToBoolean64 ].
+ [14] -> [ ^ self genLowcodeOopToFloat32 ].
+ [15] -> [ ^ self genLowcodeOopToFloat64 ].
+ [16] -> [ ^ self genLowcodeOopToInt32 ].
+ [17] -> [ ^ self genLowcodeOopToInt64 ].
+ [18] -> [ ^ self genLowcodeOopToPointer ].
+ [19] -> [ ^ self genLowcodeOopToPointerReinterpret ].
+ [20] -> [ ^ self genLowcodeOopToUInt32 ].
+ [21] -> [ ^ self genLowcodeOopToUInt64 ].
+ [22] -> [ ^ self genLowcodePin ].
+ [23] -> [ ^ self genLowcodeUnpin ].
+ }
+ otherwise: [ ^ EncounteredUnknownBytecode ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeBoolean32ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeBoolean32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value inst cont object trueJump |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := Arg1Reg)].
+ (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self CmpCq: 0 R: value.
+ trueJump := self JumpNonZero: 0.
+ "False"
+ self annotate: (self MoveCw: objectMemory falseObject R: value) objRef: objectMemory falseObject.
+ cont := self Jump: 0.
+ "True"
+ inst := self MoveCw: objectMemory trueObject R: value.
+ trueJump jmpTarget: inst.
+ self annotate: inst objRef: objectMemory trueObject.
+ cont jmpTarget: self Label.
+ self ssPushRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeBoolean64ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeBoolean64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value inst trueJump2 cont valueLow object trueJump valueHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+
+ (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
+ ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self OrR: valueLow R: valueHigh.
+ trueJump := self JumpNonZero: 0.
+ "False"
+ self annotate: (self MoveCw: objectMemory falseObject R: valueLow) objRef: objectMemory falseObject.
+ cont := self Jump: 0.
+ "True"
+ inst := self MoveCw: objectMemory trueObject R: valueLow.
+ trueJump jmpTarget: inst.
+ self annotate: inst objRef: objectMemory trueObject.
+ cont jmpTarget: self Label.
+ self ssPushRegister: valueLow.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := Arg1Reg)].
+ (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self CmpCq: 0 R: value.
+ trueJump := self JumpNonZero: 0.
+ "False"
+ self annotate: (self MoveCw: objectMemory falseObject R: value) objRef: objectMemory falseObject.
+ cont := self Jump: 0.
+ "True"
+ inst := self MoveCw: objectMemory trueObject R: value.
+ trueJump jmpTarget: inst.
+ self annotate: inst objRef: objectMemory trueObject.
+ cont jmpTarget: self Label.
+ self ssPushRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeByteSizeOf (in category 'inline primitive generators generated code') -----
+ genLowcodeByteSizeOf
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcByteSizeOf: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeCallArgumentFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: DPFPReg0.
+ self ssNativePop: 1.
+ self MoveRs: DPFPReg0 M32: BytesPerWord negated r: SPReg.
+ self SubCq: BytesPerWord R: SPReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeCallArgumentFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: DPFPReg0.
+ self ssNativePop: 1.
+ self MoveRd: DPFPReg0 M64: -8 r: SPReg.
+ self SubCq: 8 R: SPReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + 8.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeCallArgumentInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self PushR: TempReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeCallArgumentInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ BytesPerWord = 4 ifTrue: [
+ self ssNativeTop nativeStackPopToReg: TempReg secondReg: ReceiverResultReg.
+ self ssNativePop: 1.
+ self PushR: TempReg.
+ self PushR: ReceiverResultReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + 8.
+ ] ifFalse: [
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self PushR: TempReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
+ ].
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeCallArgumentPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self PushR: TempReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentSpace (in category 'inline primitive generators generated code') -----
+ genLowcodeCallArgumentSpace
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ "Allocate space"
+ self SubCq: extA R: SPReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + extA.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentStructure (in category 'inline primitive generators generated code') -----
+ genLowcodeCallArgumentStructure
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ "Fetch the pointer"
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ "Allocate space"
+ self SubCq: extA R: SPReg.
+ currentCallCleanUpSize := currentCallCleanUpSize + extA.
+ "Copy the structure"
+ backEnd genMemCopy: TempReg to: SPReg constantSize: extA.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallInstruction (in category 'inline primitive generators generated code') -----
+ genLowcodeCallInstruction
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | function |
+ function := extA.
+
+ self CallRT: function.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCallPhysical (in category 'inline primitive generators generated code') -----
+ genLowcodeCallPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID |
+ registerID := extA.
+
+ self CallR: registerID.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCheckSessionIdentifier (in category 'inline primitive generators generated code') -----
+ genLowcodeCheckSessionIdentifier
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | expectedSession |
+ expectedSession := extA.
+
+ self ssPushNativeConstantInt32: (expectedSession = coInterpreter getThisSessionID ifTrue: [1] ifFalse: [0]).
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeCompareAndSwap32 (in category 'inline primitive generators generated code') -----
+ genLowcodeCompareAndSwap32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | newValue check oldValue value |
+
+ (newValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (newValue := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (oldValue := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: newValue))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (oldValue := Arg1Reg)].
+
+ (check := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: newValue)) bitOr: (self registerMaskFor: oldValue))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (check := SendNumArgsReg)].
+
+ (value := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: newValue)) bitOr: (self registerMaskFor: oldValue)) bitOr: (self registerMaskFor: check))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := ClassReg)].
+ (((newValue = ReceiverResultReg or: [oldValue = ReceiverResultReg]) or: [check = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: newValue.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: oldValue.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: check.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeDiv32 (in category 'inline primitive generators generated code') -----
+ genLowcodeDiv32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self DivR: second R: first Quo: first Rem: second.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeDiv64 (in category 'inline primitive generators generated code') -----
+ genLowcodeDiv64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeDuplicateFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup2 |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (dup2 := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (dup2 := DPFPReg1)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveRs: value Rs: dup2.
+ self ssPushNativeRegisterSingleFloat: value;
+ ssPushNativeRegisterSingleFloat: dup2.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeDuplicateFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup2 |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (dup2 := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (dup2 := DPFPReg1)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveRd: value Rd: dup2.
+ self ssPushNativeRegisterDoubleFloat: value;
+ ssPushNativeRegisterDoubleFloat: dup2.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeDuplicateInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup2 |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dup2 := Arg1Reg)].
+ (value = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: dup2.
+ self ssPushNativeRegister: value;
+ ssPushNativeRegister: dup2.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeDuplicateInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value dup2Low dup2 valueLow dup2High valueHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+
+ (dup2Low := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dup2Low := SendNumArgsReg)].
+
+ (dup2High := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh)) bitOr: (self registerMaskFor: dup2Low))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dup2High := ClassReg)].
+ (((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [dup2Low = ReceiverResultReg]) or: [dup2High = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self MoveR: valueLow R: dup2Low.
+ self MoveR: valueHigh R: dup2High.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+ self ssPushNativeRegister: dup2Low secondRegister: dup2High.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dup2 := Arg1Reg)].
+ (value = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: dup2.
+ self ssPushNativeRegister: value.
+ self ssPushNativeRegister: dup2.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicatePointer (in category 'inline primitive generators generated code') -----
+ genLowcodeDuplicatePointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | dup2 pointerValue |
+
+ (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointerValue := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointerValue))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dup2 := Arg1Reg)].
+ (pointerValue = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointerValue.
+ self ssNativePop: 1.
+
+ self MoveR: pointerValue R: dup2.
+ self ssPushNativeRegister: pointerValue;
+ ssPushNativeRegister: dup2.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeEffectiveAddress32 (in category 'inline primitive generators generated code') -----
+ genLowcodeEffectiveAddress32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | offset base index scale |
+
+ (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (offset := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (scale := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (scale := Arg1Reg)].
+
+ (index := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (index := SendNumArgsReg)].
+
+ (base := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (base := ClassReg)].
+ (((offset = ReceiverResultReg or: [scale = ReceiverResultReg]) or: [index = ReceiverResultReg]) or: [base = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: offset.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: scale.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: index.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: base.
+ self ssNativePop: 1.
+
+ self MulR: scale R: index.
+ self AddR: index R: base.
+ self AddR: offset R: base.
+ self ssPushNativeRegister: base.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeEffectiveAddress64 (in category 'inline primitive generators generated code') -----
+ genLowcodeEffectiveAddress64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | base index indexLow indexHigh scaleHigh offsetLow scaleLow offset offsetHigh result scale |
+
+ (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (offset := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (scale := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (scale := Arg1Reg)].
+
+ (index := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (index := SendNumArgsReg)].
+
+ (base := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (base := ClassReg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index)) bitOr: (self registerMaskFor: base))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := ReceiverResultReg)].
+ ((((offset = ReceiverResultReg or: [scale = ReceiverResultReg]) or: [index = ReceiverResultReg]) or: [base = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: offset.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: scale.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: index.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: base.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeEndCall (in category 'inline primitive generators generated code') -----
+ genLowcodeEndCall
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self endHighLevelCallWithCleanup.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeEndCallNoCleanup (in category 'inline primitive generators generated code') -----
+ genLowcodeEndCallNoCleanup
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self endHighLevelCallWithoutCleanup.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFirstFieldPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeFirstFieldPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcFirstFieldPointer: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFirstIndexableFieldPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeFirstIndexableFieldPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcFirstIndexableFieldPointer: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Add (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Add
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self AddRs: second Rs: first.
+ self ssPushNativeRegisterSingleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Div (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Div
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self DivRs: second Rs: first.
+ self ssPushNativeRegisterSingleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Equal (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRs: second Rs: first.
+ falseJump := self JumpFPNotEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Great (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRs: second Rs: first.
+ falseJump := self JumpFPLessOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32GreatEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRs: second Rs: first.
+ falseJump := self JumpFPLess: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Less (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRs: second Rs: first.
+ falseJump := self JumpFPGreaterOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32LessEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRs: second Rs: first.
+ falseJump := self JumpFPGreater: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Mul (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Mul
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self MulRs: second Rs: first.
+ self ssPushNativeRegisterSingleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Neg (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Neg
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg1)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self XorRs: result Rs: result.
+ self SubRs: value Rs: result.
+ self ssPushNativeRegisterSingleFloat: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32NotEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRs: second Rs: first.
+ falseJump := self JumpFPEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Sqrt (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Sqrt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self SqrtRs: value.
+ self ssPushNativeRegisterSingleFloat: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Sub (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32Sub
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self SubRs: second Rs: first.
+ self ssPushNativeRegisterSingleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | singleFloatValue |
+
+ (singleFloatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (singleFloatValue := DPFPReg0)].
+ self ssNativeTop nativePopToReg: singleFloatValue.
+ self ssNativePop: 1.
+
+ self ConvertRs: singleFloatValue Rd: singleFloatValue.
+ self ssPushNativeRegisterDoubleFloat: singleFloatValue.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32ToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ConvertRs: value R: result.
+ self ssPushNativeRegister: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32ToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | resultLow resultHigh value result |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | singleFloatValue object |
+
+ (singleFloatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (singleFloatValue := DPFPReg0)].
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: singleFloatValue.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcFloat32: singleFloatValue toOop: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToUInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32ToUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ConvertRs: value R: result.
+ self ssPushNativeRegister: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToUInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat32ToUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | resultLow resultHigh value result |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Add (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Add
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self AddRd: second Rd: first.
+ self ssPushNativeRegisterDoubleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Div (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Div
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self DivRd: second Rd: first.
+ self ssPushNativeRegisterDoubleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Equal (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRd: second Rd: first.
+ falseJump := self JumpFPNotEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Great (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRd: second Rd: first.
+ falseJump := self JumpFPLessOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64GreatEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRd: second Rd: first.
+ falseJump := self JumpFPLess: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Less (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRd: second Rd: first.
+ falseJump := self JumpFPGreaterOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64LessEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRd: second Rd: first.
+ falseJump := self JumpFPGreater: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Mul (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Mul
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self MulRd: second Rd: first.
+ self ssPushNativeRegisterDoubleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Neg (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Neg
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg1)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self XorRd: result Rd: result.
+ self SubRd: value Rd: result.
+ self ssPushNativeRegisterDoubleFloat: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64NotEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpRd: second Rd: first.
+ falseJump := self JumpFPEqual: 0.
+ "True result"
+ self MoveCq: 1 R: value.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: value.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Sqrt (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Sqrt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self SqrtRd: value.
+ self ssPushNativeRegisterDoubleFloat: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Sub (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64Sub
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
+
+ (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self SubRd: second Rd: first.
+ self ssPushNativeRegisterDoubleFloat: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue |
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+ self ssNativeTop nativePopToReg: floatValue.
+ self ssNativePop: 1.
+
+ self ConvertRd: floatValue Rs: floatValue.
+ self ssPushNativeRegisterSingleFloat: floatValue.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64ToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int32Result |
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+
+ (int32Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (int32Result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ int32Result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: floatValue.
+ self ssNativePop: 1.
+
+ self ConvertRd: floatValue R: int32Result.
+ self ssPushNativeRegister: int32Result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64ToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int64ResultLow int64Result int64ResultHigh |
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+
+ (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (int64Result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ int64Result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: floatValue.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue object |
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: floatValue.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcFloat64: floatValue toOop: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToUInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64ToUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int64Result |
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+
+ (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (int64Result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ int64Result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: floatValue.
+ self ssNativePop: 1.
+
+ self ConvertRd: floatValue R: int64Result.
+ self ssPushNativeRegister: int64Result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToUInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeFloat64ToUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue int64ResultLow int64Result int64ResultHigh |
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+
+ (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (int64Result := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ int64Result = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: floatValue.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeFree (in category 'inline primitive generators generated code') -----
+ genLowcodeFree
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ pointer ~= ReceiverResultReg ifTrue: [self MoveR: pointer R: ReceiverResultReg ].
+ self CallRT: ceFreeTrampoline.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateIndexable32Oop (in category 'inline primitive generators generated code') -----
+ genLowcodeInstantiateIndexable32Oop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | indexableSize object classOop |
+
+ (indexableSize := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (indexableSize := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (classOop := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: indexableSize))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (classOop := Arg1Reg)].
+
+ (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: indexableSize)) bitOr: (self registerMaskFor: classOop))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
+ ((indexableSize = ReceiverResultReg or: [classOop = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: indexableSize.
+ self ssNativePop: 1.
+ self ssTop popToReg: classOop.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcInstantiateOop: classOop indexableSize: indexableSize.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateIndexableOop (in category 'inline primitive generators generated code') -----
+ genLowcodeInstantiateIndexableOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | indexableSize object classOop |
+ indexableSize := extA.
+
+ (classOop := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (classOop := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: classOop))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := Arg1Reg)].
+ (classOop = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: classOop.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcInstantiateOop: classOop constantIndexableSize: indexableSize.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateOop (in category 'inline primitive generators generated code') -----
+ genLowcodeInstantiateOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | classOop |
+
+ (classOop := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (classOop := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ classOop = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: classOop.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcInstantiateOop: classOop.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Equal (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpNonZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Great (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpLessOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32GreatEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpLess: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Less (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpGreaterOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32LessEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpGreater: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32NotEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ConvertR: value Rs: result.
+ self ssPushNativeRegisterSingleFloat: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ConvertR: value Rd: result.
+ self ssPushNativeRegisterDoubleFloat: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcInt32ToOop: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeInt32ToPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ "TODO: Perform a NOP here"
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Equal (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64Equal
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | falseLabel first contJump falseJump secondLow secondHigh second falseJump2 firstHigh firstLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (secondLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
+
+ (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
+
+ (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
+ (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
+ self ssNativePop: 1.
+
+ self CmpR: secondHigh R: firstHigh.
+ falseJump := self JumpNonZero: 0.
+ self CmpR: secondLow R: firstLow.
+ falseJump2 := self JumpNonZero: 0.
+ "True result"
+ self MoveCq: 1 R: firstLow.
+ contJump := self Jump: 0.
+ "False result"
+ falseLabel := self MoveCq: 0 R: firstLow.
+ falseJump jmpTarget: falseLabel.
+ falseJump2 jmpTarget: falseLabel.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: firstLow.
+
+ ] ifFalse: [
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpNonZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Great (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64GreatEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Less (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64LessEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64NotEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64NotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | falseLabel first contJump falseJump secondLow secondHigh second falseJump2 firstHigh firstLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (secondLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
+
+ (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
+
+ (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
+ (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
+ self ssNativePop: 1.
+
+ self CmpR: secondHigh R: firstHigh.
+ falseJump := self JumpNonZero: 0.
+ self CmpR: secondLow R: firstLow.
+ falseJump2 := self JumpNonZero: 0.
+ "False result"
+ self MoveCq: 0 R: firstLow.
+ contJump := self Jump: 0.
+ "True result"
+ falseLabel := self MoveCq: 1 R: firstLow.
+ falseJump jmpTarget: falseLabel.
+ falseJump2 jmpTarget: falseLabel.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: firstLow.
+
+ ] ifFalse: [
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpNonZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcInt64ToOop: valueLow highPart: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcInt64ToOop: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeInt64ToPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self ssPushNativeRegister: valueLow.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeIsBytes (in category 'inline primitive generators generated code') -----
+ genLowcodeIsBytes
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcIsBytes: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeIsFloatObject (in category 'inline primitive generators generated code') -----
+ genLowcodeIsFloatObject
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcIsFloatObject: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeIsIndexable (in category 'inline primitive generators generated code') -----
+ genLowcodeIsIndexable
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcIsIndexable: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeIsIntegerObject (in category 'inline primitive generators generated code') -----
+ genLowcodeIsIntegerObject
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcIsIntegerObject: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeIsPointers (in category 'inline primitive generators generated code') -----
+ genLowcodeIsPointers
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcIsPointers: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeIsWords (in category 'inline primitive generators generated code') -----
+ genLowcodeIsWords
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcIsWords: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeIsWordsOrBytes (in category 'inline primitive generators generated code') -----
+ genLowcodeIsWordsOrBytes
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcIsWordsOrBytes: object to: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLeftShift32 (in category 'inline primitive generators generated code') -----
+ genLowcodeLeftShift32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount |
+
+ (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (shiftAmount := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: shiftAmount.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self LogicalShiftLeftR: shiftAmount R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLeftShift64 (in category 'inline primitive generators generated code') -----
+ genLowcodeLeftShift64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh |
+
+ (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (shiftAmount := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: shiftAmount.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentAddress (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentAddress
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset pointer |
+ baseOffset := extA.
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: pointer.
+ self ssPushNativeRegister: pointer.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset floatValue |
+ baseOffset := extA.
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg Rs: floatValue.
+ self ssPushNativeRegisterSingleFloat: floatValue.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset doubleValue |
+ baseOffset := extA.
+
+ (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM64: 0 r: TempReg Rd: doubleValue.
+ self ssPushNativeRegisterDoubleFloat: doubleValue.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt16 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM16: 0 r: TempReg R: value.
+ self SignExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value valueLow valueHigh |
+ baseOffset := extA.
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ "TODO: Check the endianness"
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: valueLow.
+ self MoveM32: 4 r: TempReg R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM64: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt8 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM8: 0 r: TempReg R: value.
+ self SignExtend8R: value R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset pointerResult |
+ baseOffset := extA.
+
+ (pointerResult := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointerResult := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointerResult = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveMw: 0 r: TempReg R: pointerResult.
+ self ssPushNativeRegister: pointerResult.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt16 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentUInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM16: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value valueLow valueHigh |
+ baseOffset := extA.
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ "TODO: Check the endianness"
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: valueLow.
+ self MoveM32: 4 r: TempReg R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM64: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt8 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadArgumentUInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeArgumentAddress: baseOffset to: TempReg.
+ self MoveM8: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadFloat32FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadFloat32FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM32: 0 r: pointer Rs: value.
+ self ssPushNativeRegisterSingleFloat: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadFloat64FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadFloat64FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM64: 0 r: pointer Rd: value.
+ self ssPushNativeRegisterDoubleFloat: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt16FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadInt16FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM16: 0 r: pointer R: value.
+ self SignExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt32FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadInt32FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM32: 0 r: pointer R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt64FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadInt64FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh pointer value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
+ ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ "TODO: Check the endianness"
+ self MoveM32: 0 r: pointer R: valueLow.
+ self MoveM32: 4 r: pointer R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM64: 0 r: pointer R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt8FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadInt8FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM8: 0 r: pointer R: value.
+ self SignExtend8R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalAddress (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalAddress
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset pointer |
+ baseOffset := extA.
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: pointer.
+ self ssPushNativeRegister: pointer.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset floatValue |
+ baseOffset := extA.
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg Rs: floatValue.
+ self ssPushNativeRegisterSingleFloat: floatValue.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset doubleValue |
+ baseOffset := extA.
+
+ (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM64: 0 r: TempReg Rd: doubleValue.
+ self ssPushNativeRegisterDoubleFloat: doubleValue.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt16 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM16: 0 r: TempReg R: value.
+ self SignExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value valueLow valueHigh |
+ baseOffset := extA.
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ "TODO: Check the endianness"
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: valueLow.
+ self MoveM32: 4 r: TempReg R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM64: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt8 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM8: 0 r: TempReg R: value.
+ self SignExtend8R: value R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset pointerResult |
+ baseOffset := extA.
+
+ (pointerResult := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointerResult := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointerResult = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveMw: 0 r: TempReg R: pointerResult.
+ self ssPushNativeRegister: pointerResult.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt16 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalUInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM16: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value valueLow valueHigh |
+ baseOffset := extA.
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ "TODO: Check the endianness"
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM32: 0 r: TempReg R: valueLow.
+ self MoveM32: 4 r: TempReg R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM64: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt8 (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadLocalUInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | baseOffset value |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveM8: 0 r: TempReg R: value.
+ self ssPushNativeRegister: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadObjectAt (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadObjectAt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object |
+
+ (fieldIndex := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (fieldIndex := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: fieldIndex))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := Arg1Reg)].
+ (fieldIndex = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: fieldIndex.
+ self ssNativePop: 1.
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcLoadObject: object at: fieldIndex.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadObjectField (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadObjectField
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object |
+ fieldIndex := extA.
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcLoadObject: object field: fieldIndex.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadPointerFromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadPointerFromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerResult pointer |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (pointerResult := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (pointerResult := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [pointerResult = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveMw: 0 r: pointer R: pointerResult.
+ self ssPushNativeRegister: pointerResult.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt16FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadUInt16FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM16: 0 r: pointer R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt32FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadUInt32FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM32: 0 r: pointer R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt64FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadUInt64FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh pointer value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
+ ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ "TODO: Check the endianness"
+ self MoveM32: 0 r: pointer R: valueLow.
+ self MoveM32: 4 r: pointer R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM64: 0 r: pointer R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt8FromMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeLoadUInt8FromMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveM8: 0 r: pointer R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLocalFrameSize (in category 'inline primitive generators generated code') -----
+ genLowcodeLocalFrameSize
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | size |
+ size := extA.
+
+ self assert: needsFrame.
+ hasNativeFrame := true.
+ "Mark the stack frame"
+ self annotate: (self MoveCw: (objectMemory splObj: LowcodeContextMark) R: TempReg) objRef: (objectMemory splObj: LowcodeContextMark).
+ self MoveR: TempReg Mw: self frameOffsetOfNativeFrameMark r: FPReg.
+ "Fetch the stack"
+ self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
+ self AddCq: 1 R: TempReg.
+ self MoveR: TempReg Mw: self frameOffsetOfPreviousNativeStackPointer r: FPReg.
+ "Store the frame pointer"
+ self SubCq: size R: TempReg.
+ self MoveR: TempReg Mw: self frameOffsetOfNativeFramePointer r: FPReg.
+ "Store the new stack pointer"
+ self MoveR: TempReg Mw: self frameOffsetOfNativeStackPointer r: FPReg.
+ "Allocate space for the locals"
+ self SubCq: 1 + coInterpreter defaultNativeStackFrameSize R: TempReg.
+ self MoveR: TempReg Aw: coInterpreter nativeStackPointerAddress.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLockRegisters (in category 'inline primitive generators generated code') -----
+ genLowcodeLockRegisters
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssFlushAll.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeLockVM (in category 'inline primitive generators generated code') -----
+ genLowcodeLockVM
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMalloc32 (in category 'inline primitive generators generated code') -----
+ genLowcodeMalloc32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer size |
+
+ (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (size := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (pointer := Arg1Reg)].
+ (size = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: size.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ size ~= ReceiverResultReg ifTrue: [self MoveR: size R: ReceiverResultReg ].
+ self CallRT: ceMallocTrampoline.
+ self MoveR: TempReg R: pointer.
+ self ssPushNativeRegister: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMalloc64 (in category 'inline primitive generators generated code') -----
+ genLowcodeMalloc64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | sizeHigh size sizeLow pointer |
+ BytesPerWord = 4 ifTrue: [
+
+ (sizeLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (sizeLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (sizeHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: sizeLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (sizeHigh := Arg1Reg)].
+
+ (pointer := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: sizeLow)) bitOr: (self registerMaskFor: sizeHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (pointer := SendNumArgsReg)].
+ ((sizeLow = ReceiverResultReg or: [sizeHigh = ReceiverResultReg]) or: [pointer = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: sizeLow secondReg: sizeHigh.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ sizeLow ~= ReceiverResultReg ifTrue: [self MoveR: sizeLow R: ReceiverResultReg ].
+ self CallRT: ceMallocTrampoline.
+ self MoveR: TempReg R: pointer.
+ self ssPushNativeRegister: pointer.
+
+ ] ifFalse: [
+
+ (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (size := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (pointer := Arg1Reg)].
+ (size = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: size.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ size ~= ReceiverResultReg ifTrue: [self MoveR: size R: ReceiverResultReg ].
+ self CallRT: ceMallocTrampoline.
+ self MoveR: TempReg R: pointer.
+ self ssPushNativeRegister: pointer.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpy32 (in category 'inline primitive generators generated code') -----
+ genLowcodeMemcpy32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | source dest size |
+
+ (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (size := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (source := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (source := Arg1Reg)].
+
+ (dest := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: size)) bitOr: (self registerMaskFor: source))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dest := SendNumArgsReg)].
+ ((size = ReceiverResultReg or: [source = ReceiverResultReg]) or: [dest = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: size.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: source.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: dest.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ backEnd genMemCopy: source to: dest size: size.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpy64 (in category 'inline primitive generators generated code') -----
+ genLowcodeMemcpy64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | source sizeLow sizeHigh dest size |
+
+ (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (size := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (source := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (source := Arg1Reg)].
+
+ (dest := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: size)) bitOr: (self registerMaskFor: source))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dest := SendNumArgsReg)].
+ ((size = ReceiverResultReg or: [source = ReceiverResultReg]) or: [dest = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: size.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: source.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: dest.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ backEnd genMemCopy: source to: dest size: sizeLow.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpyFixed (in category 'inline primitive generators generated code') -----
+ genLowcodeMemcpyFixed
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | source size dest |
+ size := extA.
+
+ (source := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (source := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (dest := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: source))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (dest := Arg1Reg)].
+ (source = ReceiverResultReg or: [dest = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: source.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: dest.
+ self ssNativePop: 1.
+
+ size = BytesPerWord ifTrue: [
+ self MoveMw: 0 r: source R: TempReg.
+ self MoveR: TempReg Mw: 0 r: dest.
+ ] ifFalse: [
+ self ssFlushAll.
+ backEnd genMemCopy: source to: dest constantSize: size.
+ ].
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveFloat32ToPhysical (in category 'inline primitive generators generated code') -----
+ genLowcodeMoveFloat32ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ registerID := extA.
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveFloat64ToPhysical (in category 'inline primitive generators generated code') -----
+ genLowcodeMoveFloat64ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ registerID := extA.
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveInt32ToPhysical (in category 'inline primitive generators generated code') -----
+ genLowcodeMoveInt32ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID value |
+ registerID := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMoveInt64ToPhysical (in category 'inline primitive generators generated code') -----
+ genLowcodeMoveInt64ToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID valueHigh value valueLow |
+ registerID := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMovePointerToPhysical (in category 'inline primitive generators generated code') -----
+ genLowcodeMovePointerToPhysical
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID pointerValue |
+ registerID := extA.
+
+ (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointerValue := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointerValue = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointerValue.
+ self ssNativePop: 1.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMul32 (in category 'inline primitive generators generated code') -----
+ genLowcodeMul32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self MulR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeMul64 (in category 'inline primitive generators generated code') -----
+ genLowcodeMul64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeNeg32 (in category 'inline primitive generators generated code') -----
+ genLowcodeNeg32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self NegateR: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeNeg64 (in category 'inline primitive generators generated code') -----
+ genLowcodeNeg64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ "Two complement negation"
+ self NotR: valueLow.
+ self NotR: valueHigh.
+ self AddCq: 1 R: valueLow.
+ self AddcCq: 0 R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self NegateR: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeNot32 (in category 'inline primitive generators generated code') -----
+ genLowcodeNot32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self NotR: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeNot64 (in category 'inline primitive generators generated code') -----
+ genLowcodeNot64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self NotR: valueLow.
+ self NotR: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self NotR: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeNullaryInlinePrimitive: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeNullaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self genLowcodeBoolean32ToOop ].
+ [1] -> [ ^ self genLowcodeBoolean64ToOop ].
+ [2] -> [ ^ self genLowcodeFloat32ToOop ].
+ [3] -> [ ^ self genLowcodeFloat64ToOop ].
+ [4] -> [ ^ self genLowcodeInt32ToOop ].
+ [5] -> [ ^ self genLowcodeInt64ToOop ].
+ [6] -> [ ^ self genLowcodePointerToOop ].
+ [7] -> [ ^ self genLowcodePointerToOopReinterprer ].
+ [8] -> [ ^ self genLowcodeSmallInt32ToOop ].
+ [9] -> [ ^ self genLowcodeUint32ToOop ].
+ [10] -> [ ^ self genLowcodeUint64ToOop ].
+ }
+ otherwise: [ ^ EncounteredUnknownBytecode ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeOopEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value contJump falseJump first second |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: second.
+ self ssPop: 1.
+ self ssTop popToReg: first.
+ self ssPop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpNonZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopNotEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeOopNotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: second.
+ self ssPop: 1.
+ self ssTop popToReg: first.
+ self ssPop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopSmallIntegerToInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopSmallIntegerToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genConvertSmallIntegerToIntegerInReg: object.
+ self ssPushNativeRegister: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopSmallIntegerToInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopSmallIntegerToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh object value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
+ ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genConvertSmallIntegerToIntegerInReg: object.
+ self MoveCq: 0 R: valueHigh.
+ self ssPushNativeRegister: object secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genConvertSmallIntegerToIntegerInReg: object.
+ self ssPushNativeRegister: object.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToBoolean32 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToBoolean32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject.
+ self ssPushNativeRegister: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToBoolean64 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToBoolean64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh object value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
+ ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self MoveCq: 0 R: valueHigh.
+ self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject.
+ self ssPushNativeRegister: object secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject.
+ self ssPushNativeRegister: object.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOop: object toFloat32: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOop: object toFloat64: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOopToInt32: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh object value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
+ ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOop: object toInt64: valueLow highPart: valueHigh.
+
+ ] ifFalse: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOopToInt64: object.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcOopToPointer: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToPointerReinterpret (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToPointerReinterpret
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object pointer |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (pointer := Arg1Reg)].
+ (object = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ "TODO: Generate a nop here"
+ self ssPushNativeRegister: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToUInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object value |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOopToUInt32: object.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOopToUInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeOopToUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh object value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
+ ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOop: object toUInt64: valueLow highPart: valueHigh.
+
+ ] ifFalse: [
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcOopToUInt64: object.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOr32 (in category 'inline primitive generators generated code') -----
+ genLowcodeOr32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second result first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self OrR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeOr64 (in category 'inline primitive generators generated code') -----
+ genLowcodeOr64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh first second firstHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (secondLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
+
+ (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
+
+ (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
+ (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
+ self ssNativePop: 1.
+
+ self OrR: secondLow R: firstLow.
+ self OrR: secondHigh R: firstHigh.
+ self ssPushNativeRegister: firstLow secondRegister: firstHigh.
+
+ ] ifFalse: [
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self OrR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self callSwitchToCStack.
+ self MoveCw: extA R: TempReg.
+ self CallRT: ceFFICalloutTrampoline.
+ backEnd cFloatResultToRs: DPFPReg0.
+ self ssPushNativeRegisterSingleFloat: DPFPReg0.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self callSwitchToCStack.
+ self MoveCw: extA R: TempReg.
+ self CallRT: ceFFICalloutTrampoline.
+ backEnd cFloatResultToRd: DPFPReg0.
+ self ssPushNativeRegisterDoubleFloat: DPFPReg0.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallIndirectFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallIndirectFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self callSwitchToCStack.
+ self CallRT: ceFFICalloutTrampoline.
+ backEnd cFloatResultToRs: DPFPReg0.
+ self ssPushNativeRegisterSingleFloat: DPFPReg0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallIndirectFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallIndirectFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self callSwitchToCStack.
+ self CallRT: ceFFICalloutTrampoline.
+ backEnd cFloatResultToRd: DPFPReg0.
+ self ssPushNativeRegisterDoubleFloat: DPFPReg0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallIndirectInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallIndirectInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self callSwitchToCStack.
+ self CallRT: ceFFICalloutTrampoline.
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallIndirectInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallIndirectInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self callSwitchToCStack.
+ self CallRT: ceFFICalloutTrampoline.
+ BytesPerWord = 4 ifTrue: [
+ self MoveR: backEnd cResultRegisterLow R: ReceiverResultReg.
+ self MoveR: backEnd cResultRegisterHigh R: Arg0Reg.
+ self ssPushNativeRegister: ReceiverResultReg secondRegister: Arg0Reg.
+ ] ifFalse: [
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+ ].
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallIndirectPointer (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallIndirectPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self callSwitchToCStack.
+ self CallRT: ceFFICalloutTrampoline.
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallIndirectStructure (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallIndirectStructure
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ "Push the result space"
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self PushR: TempReg.
+ "Fetch the function pointer"
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ "Call the function"
+ self callSwitchToCStack.
+ self CallRT: ceFFICalloutTrampoline.
+ "Fetch the result"
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallIndirectVoid (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallIndirectVoid
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self callSwitchToCStack.
+ self CallRT: ceFFICalloutTrampoline.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self callSwitchToCStack.
+ self MoveCw: extA R: TempReg.
+ self CallRT: ceFFICalloutTrampoline.
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self callSwitchToCStack.
+ self MoveCw: extA R: TempReg.
+ self CallRT: ceFFICalloutTrampoline.
+ BytesPerWord = 4 ifTrue: [
+ self MoveR: backEnd cResultRegisterLow R: ReceiverResultReg.
+ self MoveR: backEnd cResultRegisterHigh R: Arg0Reg.
+ self ssPushNativeRegister: ReceiverResultReg secondRegister: Arg0Reg.
+ ] ifFalse: [
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+ ].
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallPointer (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self callSwitchToCStack.
+ self MoveCw: extA R: TempReg.
+ self CallRT: ceFFICalloutTrampoline.
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallStructure (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallStructure
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ "Push the result space"
+ self ssNativeTop nativeStackPopToReg: TempReg.
+ self ssNativePop: 1.
+ self PushR: TempReg.
+ "Call the function"
+ self callSwitchToCStack.
+ self MoveCw: extA R: TempReg.
+ self CallRT: ceFFICalloutTrampoline.
+ "Fetch the result"
+ self MoveR: backEnd cResultRegister R: ReceiverResultReg.
+ self ssPushNativeRegister: ReceiverResultReg.
+ extA := 0.
+ extB := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallVoid (in category 'inline primitive generators generated code') -----
+ genLowcodePerformCallVoid
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self callSwitchToCStack.
+ self MoveCw: extA R: TempReg.
+ self CallRT: ceFFICalloutTrampoline.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePin (in category 'inline primitive generators generated code') -----
+ genLowcodePin
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePlaftormCode (in category 'inline primitive generators generated code') -----
+ genLowcodePlaftormCode
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddConstantOffset (in category 'inline primitive generators generated code') -----
+ genLowcodePointerAddConstantOffset
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | base offset |
+ offset := extB.
+
+ (base := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (base := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ base = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: base.
+ self ssNativePop: 1.
+
+ self AddCq: offset R: base.
+ self ssPushNativeRegister: base.
+
+ extB := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddOffset32 (in category 'inline primitive generators generated code') -----
+ genLowcodePointerAddOffset32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | base offset |
+
+ (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (offset := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (base := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (base := Arg1Reg)].
+ (offset = ReceiverResultReg or: [base = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: offset.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: base.
+ self ssNativePop: 1.
+
+ self AddR: offset R: base.
+ self ssPushNativeRegister: base.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddOffset64 (in category 'inline primitive generators generated code') -----
+ genLowcodePointerAddOffset64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | offsetHigh base offset offsetLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (offsetLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (offsetLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (offsetHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offsetLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (offsetHigh := Arg1Reg)].
+
+ (base := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offsetLow)) bitOr: (self registerMaskFor: offsetHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (base := SendNumArgsReg)].
+ ((offsetLow = ReceiverResultReg or: [offsetHigh = ReceiverResultReg]) or: [base = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: offsetLow secondReg: offsetHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: base.
+ self ssNativePop: 1.
+
+ self AddR: offsetLow R: base.
+ self ssPushNativeRegister: base.
+
+ ] ifFalse: [
+
+ (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (offset := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (base := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (base := Arg1Reg)].
+ (offset = ReceiverResultReg or: [base = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: offset.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: base.
+ self ssNativePop: 1.
+
+ self AddR: offset R: base.
+ self ssPushNativeRegister: base.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerEqual (in category 'inline primitive generators generated code') -----
+ genLowcodePointerEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpNonZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerNotEqual (in category 'inline primitive generators generated code') -----
+ genLowcodePointerNotEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpZero: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodePointerToInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ "TODO: Perform a NOP here"
+ self ssPushNativeRegister: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodePointerToInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | resultLow pointer result resultHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultLow := Arg1Reg)].
+
+ (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)].
+ ((pointer = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self MoveR: pointer R: resultLow.
+ self MoveCq: 0 R: resultHigh.
+ self ssPushNativeRegister: resultLow secondRegister: resultHigh.
+
+ ] ifFalse: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self ssPushNativeRegister: pointer.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToOop (in category 'inline primitive generators generated code') -----
+ genLowcodePointerToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer pointerClassLiteral |
+ pointerClassLiteral := self getLiteral: extA.
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcPointerToOop: pointer class: pointerClassLiteral.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePointerToOopReinterprer (in category 'inline primitive generators generated code') -----
+ genLowcodePointerToOopReinterprer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+
+ "TODO: Generate a nop here"
+ self ssPushRegister: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePopFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodePopFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePopFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodePopFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePopInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodePopInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePopInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodePopInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePopMultipleNative (in category 'inline primitive generators generated code') -----
+ genLowcodePopMultipleNative
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPopNativeSize: extA.
+ extA := 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePopPointer (in category 'inline primitive generators generated code') -----
+ genLowcodePopPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerValue |
+
+ (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointerValue := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointerValue = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointerValue.
+ self ssNativePop: 1.
+
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushConstantUInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodePushConstantUInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | constant |
+ constant := extA.
+
+ self ssPushNativeConstantInt32: constant.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushConstantUInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodePushConstantUInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | constant |
+ constant := extA.
+
+ self ssPushNativeConstantInt64: constant.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushNullPointer (in category 'inline primitive generators generated code') -----
+ genLowcodePushNullPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantPointer: 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushOne32 (in category 'inline primitive generators generated code') -----
+ genLowcodePushOne32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantInt32: 1.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushOne64 (in category 'inline primitive generators generated code') -----
+ genLowcodePushOne64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantInt64: 1.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushOneFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodePushOneFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantFloat32: 1.0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushOneFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodePushOneFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantFloat64: 1.0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodePushPhysicalFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID |
+ registerID := extA.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodePushPhysicalFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID |
+ registerID := extA.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodePushPhysicalInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID |
+ registerID := extA.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodePushPhysicalInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID |
+ registerID := extA.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalPointer (in category 'inline primitive generators generated code') -----
+ genLowcodePushPhysicalPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | registerID |
+ registerID := extA.
+
+ self abort.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushSessionIdentifier (in category 'inline primitive generators generated code') -----
+ genLowcodePushSessionIdentifier
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantInt32: coInterpreter getThisSessionID.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushZero32 (in category 'inline primitive generators generated code') -----
+ genLowcodePushZero32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantInt32: 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushZero64 (in category 'inline primitive generators generated code') -----
+ genLowcodePushZero64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantInt64: 0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushZeroFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodePushZeroFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantFloat32: 0.0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodePushZeroFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodePushZeroFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self ssPushNativeConstantFloat64: 0.0.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeRem32 (in category 'inline primitive generators generated code') -----
+ genLowcodeRem32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self DivR: second R: first Quo: second Rem: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeRem64 (in category 'inline primitive generators generated code') -----
+ genLowcodeRem64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeRightShift32 (in category 'inline primitive generators generated code') -----
+ genLowcodeRightShift32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value shiftAmount |
+
+ (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (shiftAmount := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: shiftAmount.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self LogicalShiftRightR: shiftAmount R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeRightShift64 (in category 'inline primitive generators generated code') -----
+ genLowcodeRightShift64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh |
+
+ (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (shiftAmount := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: shiftAmount.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend32From16 (in category 'inline primitive generators generated code') -----
+ genLowcodeSignExtend32From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self SignExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend32From8 (in category 'inline primitive generators generated code') -----
+ genLowcodeSignExtend32From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self SignExtend8R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From16 (in category 'inline primitive generators generated code') -----
+ genLowcodeSignExtend64From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value isNegative cont valueLow valueHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self SignExtend16R: valueLow R: valueLow.
+ "Check the sign to set the high word"
+ self CmpCq: 0 R: valueLow.
+ "Positive"
+ isNegative := self JumpLess: 0.
+ self MoveCq: 0 R: valueHigh.
+ cont := self Jump: 0.
+ "Negative"
+ isNegative jmpTarget: (self MoveCq: -1 R: valueHigh).
+ cont jmpTarget: self Label.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self SignExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From32 (in category 'inline primitive generators generated code') -----
+ genLowcodeSignExtend64From32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result resultLow resultHigh isNegative cont |
+ BytesPerWord = 4 ifTrue: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultLow := Arg1Reg)].
+
+ (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)].
+ ((value = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: resultLow.
+ "Check the sign to set the high word"
+ self CmpCq: 0 R: value.
+ "Positive"
+ isNegative := self JumpLess: 0.
+ self MoveCq: 0 R: resultHigh.
+ cont := self Jump: 0.
+ "Negative"
+ isNegative jmpTarget: (self MoveCq: -1 R: resultHigh).
+ cont jmpTarget: self Label.
+ self ssPushNativeRegister: resultLow secondRegister: resultHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := Arg1Reg)].
+ (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self SignExtend32R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From8 (in category 'inline primitive generators generated code') -----
+ genLowcodeSignExtend64From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result resultLow resultHigh isNegative valueLow cont valueHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+
+ (resultLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultLow := SendNumArgsReg)].
+
+ (resultHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultHigh := ClassReg)].
+ (((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self SignExtend8R: valueLow R: valueLow.
+ "Check the sign to set the high word"
+ self CmpCq: 0 R: valueLow.
+ "Positive"
+ isNegative := self JumpLess: 0.
+ self MoveCq: 0 R: valueHigh.
+ cont := self Jump: 0.
+ "Negative"
+ isNegative jmpTarget: (self MoveCq: -1 R: valueHigh).
+ cont jmpTarget: self Label.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := Arg1Reg)].
+ (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ZeroExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSmallInt32ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeSmallInt32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self LogicalShiftLeftCq: 1 R: value.
+ self OrCq: 1 R: value.
+ self ssPushRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreFloat32ToMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreFloat32ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | floatValue pointer |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: floatValue.
+ self ssNativePop: 1.
+
+ self MoveRs: floatValue M32: 0 r: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreFloat64ToMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreFloat64ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | doubleValue pointer |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)].
+ pointer = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: doubleValue.
+ self ssNativePop: 1.
+
+ self MoveRd: doubleValue M64: 0 r: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt16ToMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreInt16ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: TempReg.
+ self MoveR: TempReg M16: 0 r: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt32ToMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreInt32ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value M32: 0 r: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt64ToMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreInt64ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh pointer value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
+ ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self MoveR: valueLow M32: 0 r: pointer.
+ self MoveR: valueHigh M32: 4 r: pointer.
+
+ ] ifFalse: [
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value M64: 0 r: pointer.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt8ToMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreInt8ToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointer value |
+
+ (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := Arg1Reg)].
+ (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: TempReg.
+ self MoveR: TempReg M8: 0 r: pointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreLocalFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ baseOffset := extA.
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveRs: value M32: 0 r: TempReg.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreLocalFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ baseOffset := extA.
+
+ (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveRd: value M64: 0 r: TempReg.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt16 (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreLocalInt16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: TempReg.
+ self loadNativeLocalAddress: baseOffset to: value.
+ self MoveR: TempReg M16: 0 r: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt32 (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreLocalInt32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveR: value M32: 0 r: TempReg.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt64 (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreLocalInt64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow baseOffset |
+ baseOffset := extA.
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveR: valueLow M32: 0 r: TempReg.
+ self MoveR: valueHigh M32: 4 r: TempReg.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value M64: 0 r: TempReg.
+
+ ].
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt8 (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreLocalInt8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value baseOffset |
+ baseOffset := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: TempReg.
+ self loadNativeLocalAddress: baseOffset to: value.
+ self MoveR: TempReg M8: 0 r: value.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalPointer (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreLocalPointer
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | pointerValue baseOffset |
+ baseOffset := extA.
+
+ (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (pointerValue := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ pointerValue = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: pointerValue.
+ self ssNativePop: 1.
+
+ self loadNativeLocalAddress: baseOffset to: TempReg.
+ self MoveR: pointerValue Mw: 0 r: TempReg.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreObjectField (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreObjectField
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object value |
+ fieldIndex := extA.
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := Arg1Reg)].
+ (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: value.
+ self ssPop: 1.
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcStore: value object: object field: fieldIndex.
+
+ extA := 0.
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStoreObjectFieldAt (in category 'inline primitive generators generated code') -----
+ genLowcodeStoreObjectFieldAt
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | fieldIndex object value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (fieldIndex := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (fieldIndex := Arg1Reg)].
+
+ (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: fieldIndex))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
+ ((value = ReceiverResultReg or: [fieldIndex = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: value.
+ self ssPop: 1.
+ self ssNativeTop nativePopToReg: fieldIndex.
+ self ssNativePop: 1.
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ objectRepresentation genLcStore: value object: object at: fieldIndex.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeStorePointerToMemory (in category 'inline primitive generators generated code') -----
+ genLowcodeStorePointerToMemory
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | memoryPointer pointerValue |
+
+ (memoryPointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (memoryPointer := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (pointerValue := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: memoryPointer))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (pointerValue := Arg1Reg)].
+ (memoryPointer = ReceiverResultReg or: [pointerValue = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: memoryPointer.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: pointerValue.
+ self ssNativePop: 1.
+
+ self MoveR: pointerValue Mw: 0 r: memoryPointer.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSub32 (in category 'inline primitive generators generated code') -----
+ genLowcodeSub32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self SubR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeSub64 (in category 'inline primitive generators generated code') -----
+ genLowcodeSub64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh first second firstHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (secondLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
+
+ (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
+
+ (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
+ (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
+ self ssNativePop: 1.
+
+ self SubR: secondLow R: firstLow.
+ self SubbR: secondHigh R: firstHigh.
+ self ssPushNativeRegister: firstLow secondRegister: firstHigh.
+
+ ] ifFalse: [
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self SubR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeTrinaryInlinePrimitive: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeTrinaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self genLowcodeOopEqual ].
+ [1] -> [ ^ self genLowcodeOopNotEqual ].
+ [2] -> [ ^ self genLowcodeStoreObjectField ].
+ [3] -> [ ^ self genLowcodeStoreObjectFieldAt ].
+ }
+ otherwise: [ ^ EncounteredUnknownBytecode ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate32To16 (in category 'inline primitive generators generated code') -----
+ genLowcodeTruncate32To16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self AndCq: 16rFFFF R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate32To8 (in category 'inline primitive generators generated code') -----
+ genLowcodeTruncate32To8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self AndCq: 16rFF R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To16 (in category 'inline primitive generators generated code') -----
+ genLowcodeTruncate64To16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self AndCq: 16rFFFF R: valueLow.
+ self ssPushNativeRegister: valueLow.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self AndCq: 16rFFFF R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To32 (in category 'inline primitive generators generated code') -----
+ genLowcodeTruncate64To32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self ssPushNativeRegister: valueLow.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self AndCq: 16rFFFFFFFF R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To8 (in category 'inline primitive generators generated code') -----
+ genLowcodeTruncate64To8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow result |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self AndCq: 16rFF R: valueLow.
+ self ssPushNativeRegister: valueLow.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := Arg1Reg)].
+ (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self AndCq: 16rFF R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUdiv32 (in category 'inline primitive generators generated code') -----
+ genLowcodeUdiv32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self DivR: second R: first Quo: first Rem: second.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUdiv64 (in category 'inline primitive generators generated code') -----
+ genLowcodeUdiv64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32Great (in category 'inline primitive generators generated code') -----
+ genLowcodeUint32Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpBelowOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32GreatEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeUint32GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpBelow: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32Less (in category 'inline primitive generators generated code') -----
+ genLowcodeUint32Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpAboveOrEqual: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32LessEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeUint32LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second falseJump contJump first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self CmpR: second R: first.
+ falseJump := self JumpAbove: 0.
+ "True result"
+ self MoveCq: 1 R: first.
+ contJump := self Jump: 0.
+ "False result"
+ falseJump jmpTarget: self Label.
+ self MoveCq: 0 R: first.
+ contJump jmpTarget: self Label.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeUint32ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ConvertR: value Rs: result.
+ self ssPushNativeRegisterSingleFloat: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeUint32ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ConvertR: value Rd: result.
+ self ssPushNativeRegisterDoubleFloat: result.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeUint32ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcUInt32ToOop: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64Great (in category 'inline primitive generators generated code') -----
+ genLowcodeUint64Great
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64GreatEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeUint64GreatEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64Less (in category 'inline primitive generators generated code') -----
+ genLowcodeUint64Less
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64LessEqual (in category 'inline primitive generators generated code') -----
+ genLowcodeUint64LessEqual
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh value first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToFloat32 (in category 'inline primitive generators generated code') -----
+ genLowcodeUint64ToFloat32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToFloat64 (in category 'inline primitive generators generated code') -----
+ genLowcodeUint64ToFloat64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow result |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToOop (in category 'inline primitive generators generated code') -----
+ genLowcodeUint64ToOop
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh object value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+
+ (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
+ ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcUInt64ToOop: valueLow highPart: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (object := Arg1Reg)].
+ (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ssFlushAll.
+ objectRepresentation genLcUInt64ToOop: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUmul32 (in category 'inline primitive generators generated code') -----
+ genLowcodeUmul32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self MulR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUmul64 (in category 'inline primitive generators generated code') -----
+ genLowcodeUmul64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnaryInlinePrimitive2: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeUnaryInlinePrimitive2: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [60] -> [ ^ self genLowcodeFloat64ToFloat32 ].
+ [61] -> [ ^ self genLowcodeFloat64ToInt32 ].
+ [62] -> [ ^ self genLowcodeFloat64ToInt64 ].
+ [63] -> [ ^ self genLowcodeFloat64ToUInt32 ].
+ [64] -> [ ^ self genLowcodeFloat64ToUInt64 ].
+ [65] -> [ ^ self genLowcodeFree ].
+ [66] -> [ ^ self genLowcodeInstantiateIndexable32Oop ].
+ [67] -> [ ^ self genLowcodeInstantiateIndexableOop ].
+ [68] -> [ ^ self genLowcodeInstantiateOop ].
+ [69] -> [ ^ self genLowcodeInt32Equal ].
+ [70] -> [ ^ self genLowcodeInt32Great ].
+ [71] -> [ ^ self genLowcodeInt32GreatEqual ].
+ [72] -> [ ^ self genLowcodeInt32Less ].
+ [73] -> [ ^ self genLowcodeInt32LessEqual ].
+ [74] -> [ ^ self genLowcodeInt32NotEqual ].
+ [75] -> [ ^ self genLowcodeInt32ToFloat32 ].
+ [76] -> [ ^ self genLowcodeInt32ToFloat64 ].
+ [77] -> [ ^ self genLowcodeInt32ToPointer ].
+ [78] -> [ ^ self genLowcodeInt64Equal ].
+ [79] -> [ ^ self genLowcodeInt64Great ].
+ [80] -> [ ^ self genLowcodeInt64GreatEqual ].
+ [81] -> [ ^ self genLowcodeInt64Less ].
+ [82] -> [ ^ self genLowcodeInt64LessEqual ].
+ [83] -> [ ^ self genLowcodeInt64NotEqual ].
+ [84] -> [ ^ self genLowcodeInt64ToFloat32 ].
+ [85] -> [ ^ self genLowcodeInt64ToFloat64 ].
+ [86] -> [ ^ self genLowcodeInt64ToPointer ].
+ [87] -> [ ^ self genLowcodeLeftShift32 ].
+ [88] -> [ ^ self genLowcodeLeftShift64 ].
+ [89] -> [ ^ self genLowcodeLoadArgumentAddress ].
+ [90] -> [ ^ self genLowcodeLoadArgumentFloat32 ].
+ [91] -> [ ^ self genLowcodeLoadArgumentFloat64 ].
+ [92] -> [ ^ self genLowcodeLoadArgumentInt16 ].
+ [93] -> [ ^ self genLowcodeLoadArgumentInt32 ].
+ [94] -> [ ^ self genLowcodeLoadArgumentInt64 ].
+ [95] -> [ ^ self genLowcodeLoadArgumentInt8 ].
+ [96] -> [ ^ self genLowcodeLoadArgumentPointer ].
+ [97] -> [ ^ self genLowcodeLoadArgumentUInt16 ].
+ [98] -> [ ^ self genLowcodeLoadArgumentUInt32 ].
+ [99] -> [ ^ self genLowcodeLoadArgumentUInt64 ].
+ [100] -> [ ^ self genLowcodeLoadArgumentUInt8 ].
+ [101] -> [ ^ self genLowcodeLoadFloat32FromMemory ].
+ [102] -> [ ^ self genLowcodeLoadFloat64FromMemory ].
+ [103] -> [ ^ self genLowcodeLoadInt16FromMemory ].
+ [104] -> [ ^ self genLowcodeLoadInt32FromMemory ].
+ [105] -> [ ^ self genLowcodeLoadInt64FromMemory ].
+ [106] -> [ ^ self genLowcodeLoadInt8FromMemory ].
+ [107] -> [ ^ self genLowcodeLoadLocalAddress ].
+ [108] -> [ ^ self genLowcodeLoadLocalFloat32 ].
+ [109] -> [ ^ self genLowcodeLoadLocalFloat64 ].
+ [110] -> [ ^ self genLowcodeLoadLocalInt16 ].
+ [111] -> [ ^ self genLowcodeLoadLocalInt32 ].
+ [112] -> [ ^ self genLowcodeLoadLocalInt64 ].
+ [113] -> [ ^ self genLowcodeLoadLocalInt8 ].
+ [114] -> [ ^ self genLowcodeLoadLocalPointer ].
+ [115] -> [ ^ self genLowcodeLoadLocalUInt16 ].
+ [116] -> [ ^ self genLowcodeLoadLocalUInt32 ].
+ [117] -> [ ^ self genLowcodeLoadLocalUInt64 ].
+ [118] -> [ ^ self genLowcodeLoadLocalUInt8 ].
+ [119] -> [ ^ self genLowcodeLoadObjectAt ].
+ }
+ otherwise: [ ^ self genLowcodeUnaryInlinePrimitive3: prim ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnaryInlinePrimitive3: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeUnaryInlinePrimitive3: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [120] -> [ ^ self genLowcodeLoadObjectField ].
+ [121] -> [ ^ self genLowcodeLoadPointerFromMemory ].
+ [122] -> [ ^ self genLowcodeLoadUInt16FromMemory ].
+ [123] -> [ ^ self genLowcodeLoadUInt32FromMemory ].
+ [124] -> [ ^ self genLowcodeLoadUInt64FromMemory ].
+ [125] -> [ ^ self genLowcodeLoadUInt8FromMemory ].
+ [126] -> [ ^ self genLowcodeLocalFrameSize ].
+ [127] -> [ ^ self genLowcodeLockRegisters ].
+ [128] -> [ ^ self genLowcodeLockVM ].
+ [129] -> [ ^ self genLowcodeMalloc32 ].
+ [130] -> [ ^ self genLowcodeMalloc64 ].
+ [131] -> [ ^ self genLowcodeMemcpy32 ].
+ [132] -> [ ^ self genLowcodeMemcpy64 ].
+ [133] -> [ ^ self genLowcodeMemcpyFixed ].
+ [134] -> [ ^ self genLowcodeMoveFloat32ToPhysical ].
+ [135] -> [ ^ self genLowcodeMoveFloat64ToPhysical ].
+ [136] -> [ ^ self genLowcodeMoveInt32ToPhysical ].
+ [137] -> [ ^ self genLowcodeMoveInt64ToPhysical ].
+ [138] -> [ ^ self genLowcodeMovePointerToPhysical ].
+ [139] -> [ ^ self genLowcodeMul32 ].
+ [140] -> [ ^ self genLowcodeMul64 ].
+ [141] -> [ ^ self genLowcodeNeg32 ].
+ [142] -> [ ^ self genLowcodeNeg64 ].
+ [143] -> [ ^ self genLowcodeNot32 ].
+ [144] -> [ ^ self genLowcodeNot64 ].
+ [145] -> [ ^ self genLowcodeOr32 ].
+ [146] -> [ ^ self genLowcodeOr64 ].
+ [147] -> [ ^ self genLowcodePerformCallFloat32 ].
+ [148] -> [ ^ self genLowcodePerformCallFloat64 ].
+ [149] -> [ ^ self genLowcodePerformCallIndirectFloat32 ].
+ [150] -> [ ^ self genLowcodePerformCallIndirectFloat64 ].
+ [151] -> [ ^ self genLowcodePerformCallIndirectInt32 ].
+ [152] -> [ ^ self genLowcodePerformCallIndirectInt64 ].
+ [153] -> [ ^ self genLowcodePerformCallIndirectPointer ].
+ [154] -> [ ^ self genLowcodePerformCallIndirectStructure ].
+ [155] -> [ ^ self genLowcodePerformCallIndirectVoid ].
+ [156] -> [ ^ self genLowcodePerformCallInt32 ].
+ [157] -> [ ^ self genLowcodePerformCallInt64 ].
+ [158] -> [ ^ self genLowcodePerformCallPointer ].
+ [159] -> [ ^ self genLowcodePerformCallStructure ].
+ [160] -> [ ^ self genLowcodePerformCallVoid ].
+ [161] -> [ ^ self genLowcodePlaftormCode ].
+ [162] -> [ ^ self genLowcodePointerAddConstantOffset ].
+ [163] -> [ ^ self genLowcodePointerAddOffset32 ].
+ [164] -> [ ^ self genLowcodePointerAddOffset64 ].
+ [165] -> [ ^ self genLowcodePointerEqual ].
+ [166] -> [ ^ self genLowcodePointerNotEqual ].
+ [167] -> [ ^ self genLowcodePointerToInt32 ].
+ [168] -> [ ^ self genLowcodePointerToInt64 ].
+ [169] -> [ ^ self genLowcodePopFloat32 ].
+ [170] -> [ ^ self genLowcodePopFloat64 ].
+ [171] -> [ ^ self genLowcodePopInt32 ].
+ [172] -> [ ^ self genLowcodePopInt64 ].
+ [173] -> [ ^ self genLowcodePopMultipleNative ].
+ [174] -> [ ^ self genLowcodePopPointer ].
+ [175] -> [ ^ self genLowcodePushConstantUInt32 ].
+ [176] -> [ ^ self genLowcodePushConstantUInt64 ].
+ [177] -> [ ^ self genLowcodePushNullPointer ].
+ [178] -> [ ^ self genLowcodePushOne32 ].
+ [179] -> [ ^ self genLowcodePushOne64 ].
+ }
+ otherwise: [ ^ self genLowcodeUnaryInlinePrimitive4: prim ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnaryInlinePrimitive4: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeUnaryInlinePrimitive4: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [180] -> [ ^ self genLowcodePushOneFloat32 ].
+ [181] -> [ ^ self genLowcodePushOneFloat64 ].
+ [182] -> [ ^ self genLowcodePushPhysicalFloat32 ].
+ [183] -> [ ^ self genLowcodePushPhysicalFloat64 ].
+ [184] -> [ ^ self genLowcodePushPhysicalInt32 ].
+ [185] -> [ ^ self genLowcodePushPhysicalInt64 ].
+ [186] -> [ ^ self genLowcodePushPhysicalPointer ].
+ [187] -> [ ^ self genLowcodePushSessionIdentifier ].
+ [188] -> [ ^ self genLowcodePushZero32 ].
+ [189] -> [ ^ self genLowcodePushZero64 ].
+ [190] -> [ ^ self genLowcodePushZeroFloat32 ].
+ [191] -> [ ^ self genLowcodePushZeroFloat64 ].
+ [192] -> [ ^ self genLowcodeRem32 ].
+ [193] -> [ ^ self genLowcodeRem64 ].
+ [194] -> [ ^ self genLowcodeRightShift32 ].
+ [195] -> [ ^ self genLowcodeRightShift64 ].
+ [196] -> [ ^ self genLowcodeSignExtend32From16 ].
+ [197] -> [ ^ self genLowcodeSignExtend32From8 ].
+ [198] -> [ ^ self genLowcodeSignExtend64From16 ].
+ [199] -> [ ^ self genLowcodeSignExtend64From32 ].
+ [200] -> [ ^ self genLowcodeSignExtend64From8 ].
+ [201] -> [ ^ self genLowcodeStoreFloat32ToMemory ].
+ [202] -> [ ^ self genLowcodeStoreFloat64ToMemory ].
+ [203] -> [ ^ self genLowcodeStoreInt16ToMemory ].
+ [204] -> [ ^ self genLowcodeStoreInt32ToMemory ].
+ [205] -> [ ^ self genLowcodeStoreInt64ToMemory ].
+ [206] -> [ ^ self genLowcodeStoreInt8ToMemory ].
+ [207] -> [ ^ self genLowcodeStoreLocalFloat32 ].
+ [208] -> [ ^ self genLowcodeStoreLocalFloat64 ].
+ [209] -> [ ^ self genLowcodeStoreLocalInt16 ].
+ [210] -> [ ^ self genLowcodeStoreLocalInt32 ].
+ [211] -> [ ^ self genLowcodeStoreLocalInt64 ].
+ [212] -> [ ^ self genLowcodeStoreLocalInt8 ].
+ [213] -> [ ^ self genLowcodeStoreLocalPointer ].
+ [214] -> [ ^ self genLowcodeStorePointerToMemory ].
+ [215] -> [ ^ self genLowcodeSub32 ].
+ [216] -> [ ^ self genLowcodeSub64 ].
+ [217] -> [ ^ self genLowcodeTruncate32To16 ].
+ [218] -> [ ^ self genLowcodeTruncate32To8 ].
+ [219] -> [ ^ self genLowcodeTruncate64To16 ].
+ [220] -> [ ^ self genLowcodeTruncate64To32 ].
+ [221] -> [ ^ self genLowcodeTruncate64To8 ].
+ [222] -> [ ^ self genLowcodeUdiv32 ].
+ [223] -> [ ^ self genLowcodeUdiv64 ].
+ [224] -> [ ^ self genLowcodeUint32Great ].
+ [225] -> [ ^ self genLowcodeUint32GreatEqual ].
+ [226] -> [ ^ self genLowcodeUint32Less ].
+ [227] -> [ ^ self genLowcodeUint32LessEqual ].
+ [228] -> [ ^ self genLowcodeUint32ToFloat32 ].
+ [229] -> [ ^ self genLowcodeUint32ToFloat64 ].
+ [230] -> [ ^ self genLowcodeUint64Great ].
+ [231] -> [ ^ self genLowcodeUint64GreatEqual ].
+ [232] -> [ ^ self genLowcodeUint64Less ].
+ [233] -> [ ^ self genLowcodeUint64LessEqual ].
+ [234] -> [ ^ self genLowcodeUint64ToFloat32 ].
+ [235] -> [ ^ self genLowcodeUint64ToFloat64 ].
+ [236] -> [ ^ self genLowcodeUmul32 ].
+ [237] -> [ ^ self genLowcodeUmul64 ].
+ [238] -> [ ^ self genLowcodeUnlockRegisters ].
+ [239] -> [ ^ self genLowcodeUnlockVM ].
+ }
+ otherwise: [ ^ self genLowcodeUnaryInlinePrimitive5: prim ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnaryInlinePrimitive5: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeUnaryInlinePrimitive5: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [240] -> [ ^ self genLowcodeUrem32 ].
+ [241] -> [ ^ self genLowcodeUrem64 ].
+ [242] -> [ ^ self genLowcodeXor32 ].
+ [243] -> [ ^ self genLowcodeXor64 ].
+ [244] -> [ ^ self genLowcodeZeroExtend32From16 ].
+ [245] -> [ ^ self genLowcodeZeroExtend32From8 ].
+ [246] -> [ ^ self genLowcodeZeroExtend64From16 ].
+ [247] -> [ ^ self genLowcodeZeroExtend64From32 ].
+ [248] -> [ ^ self genLowcodeZeroExtend64From8 ].
+ }
+ otherwise: [ ^ EncounteredUnknownBytecode ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnaryInlinePrimitive: (in category 'inline primitive generators dispatch generated code') -----
+ genLowcodeUnaryInlinePrimitive: prim
+ <option: #LowcodeVM> "Lowcode instruction generator dispatch"
+ prim
+ caseOf: {
+ [0] -> [ ^ self genLowcodeAdd32 ].
+ [1] -> [ ^ self genLowcodeAdd64 ].
+ [2] -> [ ^ self genLowcodeAlloca32 ].
+ [3] -> [ ^ self genLowcodeAlloca64 ].
+ [4] -> [ ^ self genLowcodeAnd32 ].
+ [5] -> [ ^ self genLowcodeAnd64 ].
+ [6] -> [ ^ self genLowcodeArithmeticRightShift32 ].
+ [7] -> [ ^ self genLowcodeArithmeticRightShift64 ].
+ [8] -> [ ^ self genLowcodeBeginCall ].
+ [9] -> [ ^ self genLowcodeCallArgumentFloat32 ].
+ [10] -> [ ^ self genLowcodeCallArgumentFloat64 ].
+ [11] -> [ ^ self genLowcodeCallArgumentInt32 ].
+ [12] -> [ ^ self genLowcodeCallArgumentInt64 ].
+ [13] -> [ ^ self genLowcodeCallArgumentPointer ].
+ [14] -> [ ^ self genLowcodeCallArgumentSpace ].
+ [15] -> [ ^ self genLowcodeCallArgumentStructure ].
+ [16] -> [ ^ self genLowcodeCallInstruction ].
+ [17] -> [ ^ self genLowcodeCallPhysical ].
+ [18] -> [ ^ self genLowcodeCheckSessionIdentifier ].
+ [19] -> [ ^ self genLowcodeCompareAndSwap32 ].
+ [20] -> [ ^ self genLowcodeDiv32 ].
+ [21] -> [ ^ self genLowcodeDiv64 ].
+ [22] -> [ ^ self genLowcodeDuplicateFloat32 ].
+ [23] -> [ ^ self genLowcodeDuplicateFloat64 ].
+ [24] -> [ ^ self genLowcodeDuplicateInt32 ].
+ [25] -> [ ^ self genLowcodeDuplicateInt64 ].
+ [26] -> [ ^ self genLowcodeDuplicatePointer ].
+ [27] -> [ ^ self genLowcodeEffectiveAddress32 ].
+ [28] -> [ ^ self genLowcodeEffectiveAddress64 ].
+ [29] -> [ ^ self genLowcodeEndCall ].
+ [30] -> [ ^ self genLowcodeEndCallNoCleanup ].
+ [31] -> [ ^ self genLowcodeFloat32Add ].
+ [32] -> [ ^ self genLowcodeFloat32Div ].
+ [33] -> [ ^ self genLowcodeFloat32Equal ].
+ [34] -> [ ^ self genLowcodeFloat32Great ].
+ [35] -> [ ^ self genLowcodeFloat32GreatEqual ].
+ [36] -> [ ^ self genLowcodeFloat32Less ].
+ [37] -> [ ^ self genLowcodeFloat32LessEqual ].
+ [38] -> [ ^ self genLowcodeFloat32Mul ].
+ [39] -> [ ^ self genLowcodeFloat32Neg ].
+ [40] -> [ ^ self genLowcodeFloat32NotEqual ].
+ [41] -> [ ^ self genLowcodeFloat32Sqrt ].
+ [42] -> [ ^ self genLowcodeFloat32Sub ].
+ [43] -> [ ^ self genLowcodeFloat32ToFloat64 ].
+ [44] -> [ ^ self genLowcodeFloat32ToInt32 ].
+ [45] -> [ ^ self genLowcodeFloat32ToInt64 ].
+ [46] -> [ ^ self genLowcodeFloat32ToUInt32 ].
+ [47] -> [ ^ self genLowcodeFloat32ToUInt64 ].
+ [48] -> [ ^ self genLowcodeFloat64Add ].
+ [49] -> [ ^ self genLowcodeFloat64Div ].
+ [50] -> [ ^ self genLowcodeFloat64Equal ].
+ [51] -> [ ^ self genLowcodeFloat64Great ].
+ [52] -> [ ^ self genLowcodeFloat64GreatEqual ].
+ [53] -> [ ^ self genLowcodeFloat64Less ].
+ [54] -> [ ^ self genLowcodeFloat64LessEqual ].
+ [55] -> [ ^ self genLowcodeFloat64Mul ].
+ [56] -> [ ^ self genLowcodeFloat64Neg ].
+ [57] -> [ ^ self genLowcodeFloat64NotEqual ].
+ [58] -> [ ^ self genLowcodeFloat64Sqrt ].
+ [59] -> [ ^ self genLowcodeFloat64Sub ].
+ }
+ otherwise: [ ^ self genLowcodeUnaryInlinePrimitive2: prim ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnlockRegisters (in category 'inline primitive generators generated code') -----
+ genLowcodeUnlockRegisters
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ "Do nothing for now"
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnlockVM (in category 'inline primitive generators generated code') -----
+ genLowcodeUnlockVM
+ <option: #LowcodeVM> "Lowcode instruction generator"
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUnpin (in category 'inline primitive generators generated code') -----
+ genLowcodeUnpin
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | object |
+
+ (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (object := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ object = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssTop popToReg: object.
+ self ssPop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUrem32 (in category 'inline primitive generators generated code') -----
+ genLowcodeUrem32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self DivR: second R: first Quo: second Rem: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeUrem64 (in category 'inline primitive generators generated code') -----
+ genLowcodeUrem64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+
+ (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
+ ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self abort.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeXor32 (in category 'inline primitive generators generated code') -----
+ genLowcodeXor32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | second first |
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self XorR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeXor64 (in category 'inline primitive generators generated code') -----
+ genLowcodeXor64
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | secondLow firstLow secondHigh first second firstHigh |
+ BytesPerWord = 4 ifTrue: [
+
+ (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (secondLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
+
+ (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
+
+ (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
+ (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
+ self ssNativePop: 1.
+
+ self XorR: secondLow R: firstLow.
+ self XorR: secondHigh R: firstHigh.
+ self ssPushNativeRegister: firstLow secondRegister: firstHigh.
+
+ ] ifFalse: [
+
+ (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (second := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (first := Arg1Reg)].
+ (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: second.
+ self ssNativePop: 1.
+ self ssNativeTop nativePopToReg: first.
+ self ssNativePop: 1.
+
+ self XorR: second R: first.
+ self ssPushNativeRegister: first.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend32From16 (in category 'inline primitive generators generated code') -----
+ genLowcodeZeroExtend32From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ZeroExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend32From8 (in category 'inline primitive generators generated code') -----
+ genLowcodeZeroExtend32From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | value |
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ZeroExtend8R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From16 (in category 'inline primitive generators generated code') -----
+ genLowcodeZeroExtend64From16
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self ZeroExtend16R: valueLow R: valueLow.
+ self MoveCq: 0 R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ZeroExtend16R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From32 (in category 'inline primitive generators generated code') -----
+ genLowcodeZeroExtend64From32
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | resultLow resultHigh value result |
+ BytesPerWord = 4 ifTrue: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultLow := Arg1Reg)].
+
+ (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)].
+ ((value = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self MoveR: value R: resultLow.
+ self MoveCq: 0 R: resultHigh.
+ self ssPushNativeRegister: resultLow secondRegister: resultHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (result := Arg1Reg)].
+ (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ZeroExtend32R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From8 (in category 'inline primitive generators generated code') -----
+ genLowcodeZeroExtend64From8
+ <option: #LowcodeVM> "Lowcode instruction generator"
+ | valueHigh value valueLow |
+ BytesPerWord = 4 ifTrue: [
+
+ (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (valueLow := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+
+ (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
+ [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
+ (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
+ self ssNativePop: 1.
+
+ self ZeroExtend8R: valueLow R: valueLow.
+ self MoveCq: 0 R: valueHigh.
+ self ssPushNativeRegister: valueLow secondRegister: valueHigh.
+
+ ] ifFalse: [
+
+ (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
+ [self ssAllocateRequiredReg:
+ (value := optStatus isReceiverResultRegLive
+ ifTrue: [Arg0Reg]
+ ifFalse: [ReceiverResultReg])].
+ value = ReceiverResultReg ifTrue:
+ [ optStatus isReceiverResultRegLive: false ].
+ self ssNativeTop nativePopToReg: value.
+ self ssNativePop: 1.
+
+ self ZeroExtend8R: value R: value.
+ self ssPushNativeRegister: value.
+
+ ].
+ ^ 0
+
+ !
Item was changed:
----- Method: StackToRegisterMappingCogit>>genUpArrowReturn (in category 'bytecode generators') -----
genUpArrowReturn
"Generate a method return from within a method or a block.
Frameless method activation looks like
CISCs (x86):
receiver
args
sp-> ret pc.
RISCs (ARM):
receiver
args
ret pc in LR.
A fully framed activation is described in CoInterpreter class>initializeFrameIndices.
Return pops receiver and arguments off the stack. Callee pushes the result."
| framelessReturn |
deadCode := true. "can't fall through"
inBlock > 0 ifTrue:
[self assert: needsFrame.
self CallRT: ceNonLocalReturnTrampoline.
self annotateBytecode: self Label.
^0].
self
cppIf: IMMUTABILITY
ifTrue: [framelessReturn := needsFrame and: [useTwoPaths not]]
ifFalse: [framelessReturn := needsFrame].
framelessReturn
ifTrue:
+ [
+ self cppIf: LowcodeVM ifTrue: [ hasNativeFrame ifTrue: [ self leaveNativeFrame ] ].
+ self MoveR: FPReg R: SPReg.
- [self MoveR: FPReg R: SPReg.
self PopR: FPReg.
backEnd hasLinkRegister ifTrue:
[self PopR: LinkReg].
self RetN: methodOrBlockNumArgs + 1 * objectMemory wordSize]
ifFalse:
[self RetN: ((methodOrBlockNumArgs > self numRegArgs
"A method with an interpreter prim will push its register args for the prim. If the failure
body is frameless the args must still be popped, see e.g. Behavior>>nextInstance."
or: [regArgsHaveBeenPushed])
ifTrue: [methodOrBlockNumArgs + 1 * objectMemory wordSize]
ifFalse: [0])].
^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>generateSistaRuntime (in category 'initialization') -----
+ generateSistaRuntime
+ "No sita vm"!
Item was changed:
----- Method: StackToRegisterMappingCogit>>initSimStackForFramefulMethod: (in category 'simulation stack') -----
initSimStackForFramefulMethod: startpc
<var: #desc type: #'CogSimStackEntry *'>
simSelf
type: SSBaseOffset;
spilled: true;
register: FPReg;
offset: FoxMFReceiver.
optStatus
isReceiverResultRegLive: false;
ssEntry: (self addressOf: simSelf).
simSpillBase := methodOrBlockNumTemps. "N.B. Includes num args"
simStackPtr := simSpillBase - 1.
+ self cppIf: LowcodeVM ifTrue: [
+ simNativeSpillBase := simNativeStackPtr := -1.
+ simNativeStackSize := 0.
+ ].
"args"
0 to: methodOrBlockNumArgs - 1 do:
[:i| | desc |
desc := self simStackAt: i.
desc
type: SSBaseOffset;
spilled: true;
register: FPReg;
offset: FoxCallerSavedIP + ((methodOrBlockNumArgs - i) * objectMemory wordSize);
bcptr: startpc].
"temps"
methodOrBlockNumArgs to: simStackPtr do:
[:i| | desc |
desc := self simStackAt: i.
desc
type: SSBaseOffset;
spilled: true;
register: FPReg;
offset: FoxMFReceiver - (i - methodOrBlockNumArgs + 1 * objectMemory wordSize);
bcptr: startpc]!
Item was changed:
----- Method: StackToRegisterMappingCogit>>initSimStackForFramelessBlock: (in category 'simulation stack') -----
initSimStackForFramelessBlock: startpc
"The register receiver (the closure itself) and args are pushed by the closure value primitive(s)
and hence a frameless block has all arguments and copied values pushed to the stack. However,
the method receiver (self) is put in the ReceiverResultRegister by the block entry."
| desc |
<var: #desc type: #'CogSimStackEntry *'>
simSelf
type: SSRegister;
spilled: false;
register: ReceiverResultReg.
optStatus
isReceiverResultRegLive: true;
ssEntry: (self addressOf: simSelf).
self assert: methodOrBlockNumTemps >= methodOrBlockNumArgs.
0 to: methodOrBlockNumTemps - 1 do:
[:i|
desc := self simStackAt: i.
desc
type: SSBaseOffset;
spilled: true;
register: SPReg;
offset: ((backEnd hasLinkRegister
ifTrue: [methodOrBlockNumArgs - 1- i]
ifFalse: [methodOrBlockNumArgs - i]) * objectMemory wordSize);
bcptr: startpc].
+ simSpillBase := simStackPtr := methodOrBlockNumTemps - 1.
+ self cppIf: LowcodeVM ifTrue: [
+ simNativeSpillBase := simNativeStackPtr := -1.
+ simNativeStackSize := 0.
+ ].!
- simSpillBase := simStackPtr := methodOrBlockNumTemps - 1!
Item was changed:
----- Method: StackToRegisterMappingCogit>>initSimStackForFramelessMethod: (in category 'simulation stack') -----
initSimStackForFramelessMethod: startpc
| desc |
<var: #desc type: #'CogSimStackEntry *'>
simSelf
type: SSRegister;
spilled: false;
register: ReceiverResultReg.
optStatus
isReceiverResultRegLive: true;
ssEntry: (self addressOf: simSelf).
self assert: methodOrBlockNumTemps = methodOrBlockNumArgs.
self assert: self numRegArgs <= 2.
(methodOrBlockNumArgs between: 1 and: self numRegArgs)
ifTrue:
[desc := self simStackAt: 0.
desc
type: SSRegister;
spilled: false;
register: Arg0Reg;
bcptr: startpc.
methodOrBlockNumArgs > 1 ifTrue:
[desc := self simStackAt: 1.
desc
type: SSRegister;
spilled: false;
register: Arg1Reg;
bcptr: startpc]]
ifFalse:
[0 to: methodOrBlockNumArgs - 1 do:
[:i|
desc := self simStackAt: i.
desc
type: SSBaseOffset;
register: SPReg;
spilled: true;
offset: ((backEnd hasLinkRegister
ifTrue: [methodOrBlockNumArgs - 1- i]
ifFalse: [methodOrBlockNumArgs - i]) * objectMemory wordSize);
bcptr: startpc]].
+ simSpillBase := simStackPtr := methodOrBlockNumArgs - 1.
+ self cppIf: LowcodeVM ifTrue: [
+ simNativeSpillBase := simNativeStackPtr := -1.
+ simNativeStackSize := 0.
+ ].!
- simSpillBase := simStackPtr := methodOrBlockNumArgs - 1!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>leaveNativeFrame (in category 'simulation stack') -----
+ leaveNativeFrame
+ <option: #LowcodeVM>
+ self assert: needsFrame.
+ self MoveMw: self frameOffsetOfPreviousNativeStackPointer r: FPReg R: TempReg.
+ self SubCq: 1 R: TempReg.
+ self MoveR: TempReg Aw: coInterpreter nativeStackPointerAddress!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>liveFloatRegisters (in category 'simulation stack') -----
+ liveFloatRegisters
+ | regsSet |
+ regsSet := 0.
+ (simSpillBase max: 0) to: simStackPtr do:
+ [:i|
+ regsSet := regsSet bitOr: (self simStackAt: i) floatRegisterMask].
+ self cppIf: LowcodeVM ifTrue: [
+ (simNativeSpillBase max: 0) to: simNativeStackPtr do:
+ [:i|
+ regsSet := regsSet bitOr: (self simNativeStackAt: i) nativeFloatRegisterMask].
+ ].
+ ^regsSet!
Item was changed:
----- Method: StackToRegisterMappingCogit>>liveRegisters (in category 'simulation stack') -----
liveRegisters
| regsSet |
needsFrame
ifTrue: [regsSet := 0]
ifFalse:
[regsSet := self registerMaskFor: ReceiverResultReg.
(methodOrBlockNumArgs <= self numRegArgs
and: [methodOrBlockNumArgs > 0]) ifTrue:
[regsSet := regsSet bitOr: (self registerMaskFor: Arg0Reg).
(self numRegArgs > 1 and: [methodOrBlockNumArgs > 1]) ifTrue:
[regsSet := regsSet bitOr: (self registerMaskFor: Arg1Reg)]]].
(simSpillBase max: 0) to: simStackPtr do:
[:i|
regsSet := regsSet bitOr: (self simStackAt: i) registerMask].
+ self cppIf: LowcodeVM ifTrue: [
+ (simNativeSpillBase max: 0) to: simNativeStackPtr do:
+ [:i|
+ regsSet := regsSet bitOr: (self simNativeStackAt: i) nativeRegisterMask].
+ ].
^regsSet!
Item was changed:
----- Method: StackToRegisterMappingCogit>>mapDeadDescriptorIfNeeded: (in category 'compile abstract instructions') -----
mapDeadDescriptorIfNeeded: descriptor
"insert nops for dead code that is mapped so that bc
to mc mapping is not many to one"
<var: #descriptor type: #'BytecodeDescriptor *'>
self flag: #annotateInstruction .
(descriptor isMapped
or: [inBlock > 0 and: [descriptor isMappedInBlock]])
ifTrue: [self annotateBytecode: self Nop].
^ 0!
Item was changed:
----- Method: StackToRegisterMappingCogit>>mergeWithFixupIfRequired: (in category 'simulation stack') -----
mergeWithFixupIfRequired: fixup
"If this bytecode has a fixup, some kind of merge needs to be done. There are 4 cases:
1) the bytecode has no fixup (fixup isNotAFixup)
do nothing
2) the bytecode has a non merge fixup
the fixup has needsNonMergeFixup.
The code generating non merge fixup (currently only special selector code) is responsible
for the merge so no need to do it.
We set deadCode to false as the instruction can be reached from jumps.
3) the bytecode has a merge fixup, but execution flow *cannot* fall through to the merge point.
the fixup has needsMergeFixup and deadCode = true.
ignores the current simStack as it does not mean anything
restores the simStack to the state the jumps to the merge point expects it to be.
4) the bytecode has a merge fixup and execution flow *can* fall through to the merge point.
the fixup has needsMergeFixup and deadCode = false.
flushes the stack to the stack pointer so the fall through execution path simStack is
in the state the merge point expects it to be.
restores the simStack to the state the jumps to the merge point expects it to be.
In addition, if this is a backjump merge point, we patch the fixup to hold the current simStackPtr
for later assertions."
<var: #fixup type: #'BytecodeFixup *'>
"case 1"
fixup notAFixup ifTrue: [^ 0].
"case 2"
fixup isNonMergeFixup ifTrue: [deadCode := false. ^ 0 ].
"cases 3 and 4"
self assert: fixup isMergeFixup.
self traceMerge: fixup.
+ deadCode ifTrue: [
+ "case 3"
+ simStackPtr := fixup simStackPtr.
+ self cppIf: LowcodeVM ifTrue: [
+ simNativeStackPtr := fixup simNativeStackPtr.
+ simNativeStackSize := fixup simNativeStackSize.
+ ]
+ ] ifFalse: [
+ "case 4"
+ self ssFlushTo: simStackPtr
+ ].
+
- deadCode
- ifTrue: [simStackPtr := fixup simStackPtr] "case 3"
- ifFalse: [self ssFlushTo: simStackPtr]. "case 4"
"cases 3 and 4"
deadCode := false.
+ fixup isBackwardBranchFixup ifTrue: [
+ fixup simStackPtr: simStackPtr.
+ self cppIf: LowcodeVM ifTrue: [
+ fixup simNativeStackPtr: simNativeStackPtr.
+ fixup simNativeStackSize: simNativeStackSize.
+ ]
+ ].
- fixup isBackwardBranchFixup ifTrue: [fixup simStackPtr: simStackPtr].
fixup targetInstruction: self Label.
self assert: simStackPtr = fixup simStackPtr.
+ self cppIf: LowcodeVM ifTrue: [
+ self assert: simNativeStackPtr = fixup simNativeStackPtr.
+ self assert: simNativeStackSize = fixup simNativeStackSize.
+ ].
+
self cCode: '' inSmalltalk:
[self assert: fixup simStackPtr = (self debugStackPointerFor: bytecodePC)].
self restoreSimStackAtMergePoint: fixup.
^0!
Item was changed:
----- Method: StackToRegisterMappingCogit>>restoreSimStackAtMergePoint: (in category 'simulation stack') -----
restoreSimStackAtMergePoint: fixup
<inline: true>
"All the execution paths reaching a merge point expect everything to be
spilled on stack and the optStatus is unknown. Throw away all simStack and
optStatus optimization state."
simSpillBase := methodOrBlockNumTemps.
optStatus isReceiverResultRegLive: false.
methodOrBlockNumTemps to: simStackPtr do:
[:i|
(self simStackAt: i)
type: SSSpill;
offset: FoxMFReceiver - (i - methodOrBlockNumArgs + 1 * objectMemory bytesPerOop);
register: FPReg;
spilled: true].
+ self cppIf: LowcodeVM ifTrue: [
+ 0 to: simNativeStackPtr do: [ :i |
+ (self simNativeStackAt: i)
+ ensureIsMarkedAsSpilled
+ ].
+ simNativeSpillBase := simNativeStackPtr + 1
+ ].
^ 0!
Item was changed:
----- Method: StackToRegisterMappingCogit>>scanBlock: (in category 'compile abstract instructions') -----
scanBlock: blockStart
"Scan the block to determine if the block needs a frame or not"
| descriptor pc end framelessStackDelta nExts pushingNils numPushNils |
<var: #blockStart type: #'BlockStart *'>
<var: #descriptor type: #'BytecodeDescriptor *'>
needsFrame := false.
+ self cppIf: LowcodeVM ifTrue: [ hasNativeFrame := false ].
prevBCDescriptor := nil.
methodOrBlockNumArgs := blockStart numArgs.
inBlock := InVanillaBlock.
pc := blockStart startpc.
end := blockStart startpc + blockStart span.
framelessStackDelta := nExts := extA := extB := 0.
+ extBFirstZero := false.
pushingNils := true.
[pc < end] whileTrue:
[byte0 := (objectMemory fetchByte: pc ofObject: methodObj) + bytecodeSetOffset.
descriptor := self generatorAt: byte0.
descriptor isExtension ifTrue:
[self loadSubsequentBytesForDescriptor: descriptor at: pc.
self perform: descriptor generator].
needsFrame ifFalse:
[(descriptor needsFrameFunction isNil
or: [self perform: descriptor needsFrameFunction with: framelessStackDelta])
ifTrue: [needsFrame := true]
ifFalse: [framelessStackDelta := framelessStackDelta + descriptor stackDelta]].
objectRepresentation maybeNoteDescriptor: descriptor blockStart: blockStart.
(pushingNils
and: [descriptor isExtension not]) ifTrue:
["Count the initial number of pushed nils acting as temp initializers. We can't tell
whether an initial pushNil is an operand reference or a temp initializer, except
when the pushNil is a jump target (has a fixup), which never happens:
self systemNavigation browseAllSelect:
[:m| | ebc |
(ebc := m embeddedBlockClosures
select: [:ea| ea decompile statements first isMessage]
thenCollect: [:ea| ea decompile statements first selector]) notEmpty
and: [(#(whileTrue whileFalse whileTrue: whileFalse:) intersection: ebc) notEmpty]]
or if the bytecode set has a push multiple nils bytecode. We simply count initial nils.
Rarely we may end up over-estimating. We will correct by checking the stack depth
at the end of the block in compileBlockBodies."
(numPushNils := self numPushNils: descriptor pc: pc nExts: nExts method: methodObj) > 0
ifTrue:
[self assert: (descriptor numBytes = 1
or: [descriptor generator == #genPushClosureTempsBytecode]).
blockStart numInitialNils: blockStart numInitialNils + numPushNils]
ifFalse:
[pushingNils := false]].
pc := self nextBytecodePCFor: descriptor at: pc exts: nExts in: methodObj.
descriptor isExtension
ifTrue: [nExts := nExts + 1]
ifFalse: [nExts := extA := extB := 0].
prevBCDescriptor := descriptor].
"It would be nice of this wasn't necessary but alas we need to do the eager
scan for frameless methods so that we don't end up popping too much off
the simulated stack, e.g. for pushNil; returnTopFromBlock methods."
needsFrame ifFalse:
[self assert: (framelessStackDelta >= 0 and: [blockStart numInitialNils >= framelessStackDelta]).
blockStart numInitialNils: blockStart numInitialNils - framelessStackDelta].
^0!
Item was changed:
----- Method: StackToRegisterMappingCogit>>scanMethod (in category 'compile abstract instructions') -----
scanMethod
"Scan the method (and all embedded blocks) to determine
- what the last bytecode is; extra bytes at the end of a method are used to encode things like source pointers or temp names
- if the method needs a frame or not
- what are the targets of any backward branches.
- how many blocks it creates
Answer the block count or on error a negative error code"
| latestContinuation nExts descriptor pc numBlocks distance targetPC framelessStackDelta seenInstVarStore |
<var: #descriptor type: #'BytecodeDescriptor *'>
needsFrame := useTwoPaths := seenInstVarStore := false.
+ self cppIf: LowcodeVM ifTrue: [ hasNativeFrame := false ].
self maybeInitNumFixups.
self maybeInitNumCounters.
prevBCDescriptor := nil.
NewspeakVM ifTrue:
[numIRCs := 0].
(primitiveIndex > 0
and: [coInterpreter isQuickPrimitiveIndex: primitiveIndex]) ifTrue:
[^0].
pc := latestContinuation := initialPC.
numBlocks := framelessStackDelta := nExts := extA := extB := 0.
+ extBFirstZero := false.
[pc <= endPC] whileTrue:
[byte0 := (objectMemory fetchByte: pc ofObject: methodObj) + bytecodeSetOffset.
descriptor := self generatorAt: byte0.
descriptor isExtension ifTrue:
[descriptor opcode = Nop ifTrue: "unknown bytecode tag; see Cogit class>>#generatorTableFrom:"
[^EncounteredUnknownBytecode].
self loadSubsequentBytesForDescriptor: descriptor at: pc.
self perform: descriptor generator].
(descriptor isReturn
and: [pc >= latestContinuation]) ifTrue:
[endPC := pc].
needsFrame ifFalse:
[(descriptor needsFrameFunction isNil
or: [self perform: descriptor needsFrameFunction with: framelessStackDelta])
ifTrue:
["With immutability we win simply by avoiding a frame build if the receiver is young and not immutable."
self cppIf: IMMUTABILITY
ifTrue: [descriptor is1ByteInstVarStore
ifTrue: [useTwoPaths := true]
ifFalse: [needsFrame := true. useTwoPaths := false]]
ifFalse: [needsFrame := true. useTwoPaths := false]]
ifFalse:
[framelessStackDelta := framelessStackDelta + descriptor stackDelta.
"Without immutability we win if there are two or more stores and the receiver is new."
self cppIf: IMMUTABILITY
ifTrue: []
ifFalse:
[descriptor is1ByteInstVarStore ifTrue:
[seenInstVarStore
ifTrue: [useTwoPaths := true]
ifFalse: [seenInstVarStore := true]]]]].
descriptor isBranch ifTrue:
[distance := self spanFor: descriptor at: pc exts: nExts in: methodObj.
targetPC := pc + descriptor numBytes + distance.
(self isBackwardBranch: descriptor at: pc exts: nExts in: methodObj)
ifTrue: [self initializeFixupAt: targetPC - initialPC]
ifFalse:
[latestContinuation := latestContinuation max: targetPC.
self maybeCountFixup.
self maybeCountCounter]].
descriptor isBlockCreation ifTrue:
[numBlocks := numBlocks + 1.
distance := self spanFor: descriptor at: pc exts: nExts in: methodObj.
targetPC := pc + descriptor numBytes + distance.
latestContinuation := latestContinuation max: targetPC.
self maybeCountFixup].
NewspeakVM ifTrue:
[descriptor hasIRC ifTrue:
[numIRCs := numIRCs + 1]].
pc := pc + descriptor numBytes.
descriptor isExtension
ifTrue: [nExts := nExts + 1]
ifFalse: [nExts := extA := extB := 0].
prevBCDescriptor := descriptor].
^numBlocks!
Item was changed:
----- Method: StackToRegisterMappingCogit>>setInterpreter: (in category 'initialization') -----
setInterpreter: aCoInterpreter
"Initialization of the code generator in the simulator.
These objects already exist in the generated C VM
or are used only in the simulation."
<doNotGenerate>
super setInterpreter: aCoInterpreter.
methodAbortTrampolines := CArrayAccessor on: (Array new: self numRegArgs + 2).
picAbortTrampolines := CArrayAccessor on: (Array new: self numRegArgs + 2).
picMissTrampolines := CArrayAccessor on: (Array new: self numRegArgs + 2).
simStack := CArrayAccessor on: ((1 to: self class simStackSlots) collect: [:i| self simStackEntryClass new cogit: self]).
+ simNativeStack := CArrayAccessor on: ((1 to: self class simStackSlots) collect: [:i| self simStackNativeEntryClass new cogit: self]).
simSelf := self simStackEntryClass new cogit: self.
optStatus := CogSSOptStatus new.
debugFixupBreaks := self class initializationOptions at: #debugFixupBreaks ifAbsent: [Set new].
numPushNilsFunction := self class numPushNilsFunction.
pushNilSizeFunction := self class pushNilSizeFunction!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>simNativeStackAt: (in category 'simulation stack') -----
+ simNativeStackAt: index
+ <cmacro: '(index) (simNativeStack + (index))'>
+ <returnTypeC: #'CogSimStackNativeEntry *'>
+ ^self addressOf: (simNativeStack at: index)!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>simStackNativeEntryClass (in category 'initialization') -----
+ simStackNativeEntryClass
+ <doNotGenerate>
+ ^CogSimStackNativeEntry!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssAllocateRequiredFloatReg: (in category 'simulation stack') -----
+ ssAllocateRequiredFloatReg: requiredReg
+ self ssAllocateRequiredFloatRegMask: (self registerMaskFor: requiredReg)
+ upThrough: simStackPtr upThroughNative: simNativeStackPtr!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssAllocateRequiredFloatRegMask:upThrough:upThroughNative: (in category 'simulation stack') -----
+ ssAllocateRequiredFloatRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: nativeStackPtr
+ | lastRequired lastRequiredNative liveRegs |
+ lastRequired := -1.
+ lastRequiredNative := -1.
+ "compute live regs while noting the last occurrence of required regs.
+ If these are not free we must spill from simSpillBase to last occurrence.
+ Note we are conservative here; we could allocate FPReg in frameless methods."
+ liveRegs := NoReg.
+ (simSpillBase max: 0) to: stackPtr do:
+ [:i|
+ liveRegs := liveRegs bitOr: (self simStackAt: i) registerMask.
+ ((self simStackAt: i) floatRegisterMask bitAnd: requiredRegsMask) ~= 0 ifTrue:
+ [lastRequired := i]].
+ self cppIf: LowcodeVM ifTrue: [
+ (simNativeSpillBase max: 0) to: nativeStackPtr do:
+ [:i|
+ liveRegs := liveRegs bitOr: (self simNativeStackAt: i) nativeRegisterMask.
+ ((self simNativeStackAt: i) floatRegisterMask bitAnd: requiredRegsMask) ~= 0 ifTrue:
+ [lastRequiredNative := i]].
+ ].
+
+ "If any of requiredRegsMask are live we must spill."
+ (liveRegs bitAnd: requiredRegsMask) = 0 ifFalse:
+ ["Some live, must spill"
+ self ssFlushTo: lastRequired nativeFlushTo: lastRequiredNative.
+ self assert: (self liveFloatRegisters bitAnd: requiredRegsMask) = 0]!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ssAllocateRequiredRegMask:upThrough: (in category 'simulation stack') -----
ssAllocateRequiredRegMask: requiredRegsMask upThrough: stackPtr
+ self ssAllocateRequiredRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: simNativeStackPtr.
+ !
- | lastRequired liveRegs |
- lastRequired := -1.
- "compute live regs while noting the last occurrence of required regs.
- If these are not free we must spill from simSpillBase to last occurrence.
- Note we are conservative here; we could allocate FPReg in frameless methods."
- liveRegs := self registerMaskFor: FPReg and: SPReg.
- (simSpillBase max: 0) to: stackPtr do:
- [:i|
- liveRegs := liveRegs bitOr: (self simStackAt: i) registerMask.
- ((self simStackAt: i) registerMask bitAnd: requiredRegsMask) ~= 0 ifTrue:
- [lastRequired := i]].
- "If any of requiredRegsMask are live we must spill."
- (liveRegs bitAnd: requiredRegsMask) = 0 ifFalse:
- ["Some live, must spill"
- self ssFlushTo: lastRequired.
- self assert: (self liveRegisters bitAnd: requiredRegsMask) = 0]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssAllocateRequiredRegMask:upThrough:upThroughNative: (in category 'simulation stack') -----
+ ssAllocateRequiredRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: nativeStackPtr
+ | lastRequired lastRequiredNative liveRegs |
+ lastRequired := -1.
+ lastRequiredNative := -1.
+ "compute live regs while noting the last occurrence of required regs.
+ If these are not free we must spill from simSpillBase to last occurrence.
+ Note we are conservative here; we could allocate FPReg in frameless methods."
+ liveRegs := self registerMaskFor: FPReg and: SPReg.
+ (simSpillBase max: 0) to: stackPtr do:
+ [:i|
+ liveRegs := liveRegs bitOr: (self simStackAt: i) registerMask.
+ ((self simStackAt: i) registerMask bitAnd: requiredRegsMask) ~= 0 ifTrue:
+ [lastRequired := i]].
+ self cppIf: LowcodeVM ifTrue: [
+ (simNativeSpillBase max: 0) to: nativeStackPtr do:
+ [:i|
+ liveRegs := liveRegs bitOr: (self simNativeStackAt: i) nativeRegisterMask.
+ ((self simNativeStackAt: i) nativeRegisterMask bitAnd: requiredRegsMask) ~= 0 ifTrue:
+ [lastRequiredNative := i]].
+ ].
+ "If any of requiredRegsMask are live we must spill."
+ (liveRegs bitAnd: requiredRegsMask) = 0 ifFalse:
+ ["Some live, must spill"
+ self ssFlushTo: lastRequired nativeFlushTo: lastRequiredNative.
+ self assert: (self liveRegisters bitAnd: requiredRegsMask) = 0]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssFlushAll (in category 'simulation stack') -----
+ ssFlushAll
+ self ssFlushTo: simStackPtr nativeFlushTo: simNativeStackPtr!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ssFlushTo: (in category 'simulation stack') -----
ssFlushTo: index
+ self ssFlushTo: index nativeFlushTo: simNativeStackPtr.!
- methodOrBlockNumTemps to: simSpillBase - 1 do:
- [:i| self assert: (self simStackAt: i) spilled].
- simSpillBase <= index ifTrue:
- [(simSpillBase max: 0) to: index do:
- [:i|
- self assert: needsFrame.
- (self simStackAt: i)
- ensureSpilledAt: (self frameOffsetOfTemporary: i)
- from: FPReg].
- simSpillBase := index + 1]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssFlushTo:nativeFlushTo: (in category 'simulation stack') -----
+ ssFlushTo: index nativeFlushTo: nativeIndex
+ self cppIf: LowcodeVM ifTrue: [
+ self ssNativeFlushTo: nativeIndex.
+ ].
+ methodOrBlockNumTemps to: simSpillBase - 1 do:
+ [:i| self assert: (self simStackAt: i) spilled].
+ simSpillBase <= index ifTrue:
+ [(simSpillBase max: 0) to: index do:
+ [:i|
+ self assert: needsFrame.
+ (self simStackAt: i)
+ ensureSpilledAt: (self frameOffsetOfTemporary: i)
+ from: FPReg].
+ simSpillBase := index + 1]!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ssFlushUpThroughReceiverVariable: (in category 'simulation stack') -----
ssFlushUpThroughReceiverVariable: slotIndex
"Any occurrences on the stack of the value being stored (which is the top of stack)
must be flushed, and hence any values colder than them stack."
<var: #desc type: #'CogSimStackEntry *'>
+ self cppIf: LowcodeVM ifTrue: [ self ssNativeFlushTo: simNativeStackPtr. ].
self ssFlushUpThrough:
[ :desc |
desc type = SSBaseOffset
and: [desc register = ReceiverResultReg
and: [desc offset = (objectRepresentation slotOffsetOfInstVarIndex: slotIndex) ] ] ]!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ssFlushUpThroughRegister: (in category 'simulation stack') -----
ssFlushUpThroughRegister: reg
"Any occurrences on the stack of the register must be
flushed, and hence any values colder than them stack."
<var: #desc type: #'CogSimStackEntry *'>
+ self cppIf: LowcodeVM ifTrue: [ self ssNativeFlushTo: simNativeStackPtr ].
self ssFlushUpThrough: [ :desc | desc type = SSRegister and: [ desc register = reg ] ]!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ssFlushUpThroughTemporaryVariable: (in category 'simulation stack') -----
ssFlushUpThroughTemporaryVariable: tempIndex
"Any occurrences on the stack of the value being stored (which is the top of stack)
must be flushed, and hence any values colder than them stack."
<var: #desc type: #'CogSimStackEntry *'>
+ self cppIf: LowcodeVM ifTrue: [ self ssNativeFlushTo: simNativeStackPtr ].
self ssFlushUpThrough:
[ :desc |
desc type = SSBaseOffset
and: [desc register = FPReg
and: [desc offset = (self frameOffsetOfTemporary: tempIndex) ] ] ]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssNativeFlushTo: (in category 'simulation stack') -----
+ ssNativeFlushTo: index
+ <option: #LowcodeVM>
+ | loadedPointer allocatedScratchRegister |
+ simNativeSpillBase <= index ifTrue: [
+ loadedPointer := false.
+ allocatedScratchRegister := false.
+
+ (simNativeSpillBase max: 0) to: index do: [:i|
+ loadedPointer ifFalse: [
+ self MoveMw: self frameOffsetOfNativeFramePointer r: FPReg R: TempReg.
+ loadedPointer := true.
+ ].
+
+ ((self simNativeStackAt: i) spillingNeedsScratchRegister and: [allocatedScratchRegister not ]) ifTrue: [
+ self PushR: FPReg.
+ allocatedScratchRegister := true.
+ ].
+
+ (self simNativeStackAt: i)
+ ensureSpilledSP: TempReg scratchRegister: FPReg
+ ].
+
+ simNativeSpillBase := index + 1.
+
+ allocatedScratchRegister ifTrue: [
+ self PopR: FPReg.
+ ].
+
+ loadedPointer ifTrue: [
+ self SubCq: simNativeStackSize R: TempReg.
+ self MoveR: TempReg Mw: self frameOffsetOfNativeStackPointer r: FPReg.
+ ]
+ ]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssNativePop: (in category 'simulation stack') -----
+ ssNativePop: n
+ <option: #LowcodeVM>
+ self assert: (simNativeStackPtr - n >= -1).
+ simNativeStackPtr := simNativeStackPtr - n.
+ simNativeStackPtr >= 0 ifTrue: [
+ simNativeStackSize := self ssNativeTop offset
+ ] ifFalse: [
+ simNativeStackSize := 0.
+ ]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssNativePush: (in category 'simulation stack') -----
+ ssNativePush: n
+ <option: #LowcodeVM>
+ simNativeStackPtr := simNativeStackPtr + n!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssNativeTop (in category 'simulation stack') -----
+ ssNativeTop
+ <option: #LowcodeVM>
+ <returnTypeC: #'CogSimStackNativeEntry *'>
+ self assert: simNativeStackPtr >= 0.
+ ^self simNativeStackAt: simNativeStackPtr!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPopNativeSize: (in category 'simulation stack') -----
+ ssPopNativeSize: popSize
+ <option: #LowcodeVM>
+ | poppingSize stackPosition popCount |
+ poppingSize := 0.
+ stackPosition := simNativeStackPtr.
+ [ poppingSize < popSize and: [ stackPosition >= 0 ] ] whileTrue: [
+ poppingSize := poppingSize + (self simNativeStackAt: stackPosition) stackSpillSize.
+ stackPosition := stackPosition - 1
+ ].
+
+ self assert: poppingSize = popSize.
+ popCount := simNativeStackPtr - stackPosition.
+ self ssNativePop: popCount.!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeConstantFloat32: (in category 'simulation stack') -----
+ ssPushNativeConstantFloat32: aFloat32
+ <option: #LowcodeVM>
+ <var: #aFloat32 type: #float>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + BytesPerWord.
+ self ssNativeTop
+ type: SSConstantFloat32;
+ spilled: false;
+ offset: simNativeStackSize;
+ constantFloat32: aFloat32;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeConstantFloat64: (in category 'simulation stack') -----
+ ssPushNativeConstantFloat64: aFloat64
+ <option: #LowcodeVM>
+ <var: #aFloat64 type: #double>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + 8.
+ self ssNativeTop
+ type: SSConstantFloat64;
+ spilled: false;
+ offset: simNativeStackSize;
+ constantFloat64: aFloat64;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeConstantInt32: (in category 'simulation stack') -----
+ ssPushNativeConstantInt32: anInt32
+ <option: #LowcodeVM>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + BytesPerWord.
+ self ssNativeTop
+ type: SSConstantInt32;
+ spilled: false;
+ offset: simNativeStackSize;
+ constantInt32: anInt32;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeConstantInt64: (in category 'simulation stack') -----
+ ssPushNativeConstantInt64: anInt64
+ <option: #LowcodeVM>
+ <var: #anInt64 type: #sqLong>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + 8.
+ self ssNativeTop
+ type: SSConstantInt64;
+ spilled: false;
+ offset: simNativeStackSize;
+ constantInt64: anInt64;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeConstantPointer: (in category 'simulation stack') -----
+ ssPushNativeConstantPointer: aNativePointer
+ <option: #LowcodeVM>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + BytesPerWord.
+ self ssNativeTop
+ type: SSConstantNativePointer;
+ spilled: false;
+ offset: simNativeStackSize;
+ constantNativePointer: aNativePointer;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeRegister: (in category 'simulation stack') -----
+ ssPushNativeRegister: reg
+ <option: #LowcodeVM>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + BytesPerWord.
+ self ssNativeTop
+ type: SSNativeRegister;
+ spilled: false;
+ offset: simNativeStackSize;
+ register: reg;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeRegister:secondRegister: (in category 'simulation stack') -----
+ ssPushNativeRegister: reg secondRegister: secondReg
+ <option: #LowcodeVM>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + 8.
+ self ssNativeTop
+ type: SSRegisterPair;
+ spilled: false;
+ offset: simNativeStackSize;
+ register: reg;
+ registerSecond: secondReg;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeRegisterDoubleFloat: (in category 'simulation stack') -----
+ ssPushNativeRegisterDoubleFloat: reg
+ <option: #LowcodeVM>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + 8.
+ self ssNativeTop
+ type: SSRegisterDoubleFloat;
+ spilled: false;
+ offset: simNativeStackSize;
+ register: reg;
+ bcptr: bytecodePC.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssPushNativeRegisterSingleFloat: (in category 'simulation stack') -----
+ ssPushNativeRegisterSingleFloat: reg
+ <option: #LowcodeVM>
+ self ssNativePush: 1.
+ simNativeSpillBase > simNativeStackPtr ifTrue:
+ [simNativeSpillBase := simNativeStackPtr max: 0].
+ simNativeStackSize := simNativeStackSize + BytesPerWord.
+ self ssNativeTop
+ type: SSRegisterSingleFloat;
+ spilled: false;
+ offset: simNativeStackSize;
+ register: reg;
+ bcptr: bytecodePC.
+ ^0!
Item was changed:
SharedPool subclass: #VMBasicConstants
instanceVariableNames: ''
+ classVariableNames: 'BaseHeaderSize BytesPerOop BytesPerWord COGMTVM COGVM DisownVMLockOutFullGC DoAssertionChecks DoExpensiveAssertionChecks GCCheckPrimCall GCModeBecome GCModeFreeSpace GCModeFull GCModeImageSegment GCModeIncremental GCModeNewSpace IMMUTABILITY LowcodeVM MULTIPLEBYTECODESETS NewspeakVM PharoVM PrimErrBadArgument PrimErrBadIndex PrimErrBadMethod PrimErrBadNumArgs PrimErrBadReceiver PrimErrGenericFailure PrimErrInappropriate PrimErrLimitExceeded PrimErrNamedInternal PrimErrNoCMemory PrimErrNoMemory PrimErrNoModification PrimErrNotFound PrimErrObjectIsPinned PrimErrObjectMayMove PrimErrUnsupported PrimErrWritePastObject PrimNoErr SPURVM STACKVM SistaVM VMBIGENDIAN'
- classVariableNames: 'BaseHeaderSize BytesPerOop BytesPerWord COGMTVM COGVM DisownVMLockOutFullGC DoAssertionChecks DoExpensiveAssertionChecks GCCheckPrimCall GCModeBecome GCModeFreeSpace GCModeFull GCModeImageSegment GCModeIncremental GCModeNewSpace IMMUTABILITY MULTIPLEBYTECODESETS NewspeakVM PharoVM PrimErrBadArgument PrimErrBadIndex PrimErrBadMethod PrimErrBadNumArgs PrimErrBadReceiver PrimErrGenericFailure PrimErrInappropriate PrimErrLimitExceeded PrimErrNamedInternal PrimErrNoCMemory PrimErrNoMemory PrimErrNoModification PrimErrNotFound PrimErrObjectIsPinned PrimErrObjectMayMove PrimErrUnsupported PrimErrWritePastObject PrimNoErr SPURVM STACKVM SistaVM VMBIGENDIAN'
poolDictionaries: ''
category: 'VMMaker-Interpreter'!
!VMBasicConstants commentStamp: '<historical>' prior: 0!
I am a shared pool for basic constants upon which the VM as a whole depends.
self ensureClassPool.
self classPool declare: #BytesPerWord from: VMSqueakV3ObjectRepresentationConstants classPool.
self classPool declare: #BaseHeaderSize from: VMSqueakV3ObjectRepresentationConstants classPool
(ObjectMemory classPool keys select: [:k| k beginsWith: 'Byte']) do:
[:k| self classPool declare: k from: ObjectMemory classPool]!
Item was changed:
----- Method: VMClass class>>initializeMiscConstants (in category 'initialization') -----
initializeMiscConstants
"Falsify the `what type of VM is this?' flags that are defined in the various interp.h files.
Subclass implementations need to include a super initializeMiscConstants"
| omc |
VMBIGENDIAN class. "Mention this for the benefit of CCodeGenerator>>emitCConstantsOn:"
SPURVM := STACKVM := COGVM := COGMTVM := false.
initializationOptions ifNil: [self initializationOptions: Dictionary new].
omc := initializationOptions at: #ObjectMemory ifAbsent: nil.
(omc isNil and: [self defaultObjectMemoryClass notNil]) ifTrue:
[omc := initializationOptions at: #ObjectMemory put: self defaultObjectMemoryClass name].
initializationOptions
at: #SqueakV3ObjectMemory "the good ole default"
ifAbsentPut: (omc
ifNil: [true]
ifNotNil: [(Smalltalk at: omc) includesBehavior: ObjectMemory]);
at: #SpurObjectMemory "the new contender"
ifAbsentPut: (omc
ifNil: [false]
ifNotNil: [(Smalltalk at: omc) includesBehavior: SpurMemoryManager]).
"Use ifAbsentPut: so that they will get copied back to the
VMMaker's options and dead code will likely be eliminated."
PharoVM := initializationOptions at: #PharoVM ifAbsentPut: [false].
NewspeakVM := initializationOptions at: #NewspeakVM ifAbsentPut: [false].
SistaVM := initializationOptions at: #SistaVM ifAbsentPut: [false].
+ LowcodeVM := initializationOptions at: #LowcodeVM ifAbsentPut: [false].
"But not these; they're compile-time"
MULTIPLEBYTECODESETS := initializationOptions at: #MULTIPLEBYTECODESETS ifAbsent: [false].
IMMUTABILITY := initializationOptions at: #IMMUTABILITY ifAbsent: [false].
"These must be set only if specified, not defaulted, because they are set on the command line or in include files."
initializationOptions
at: #VMBIGENDIAN ifPresent: [:value| VMBIGENDIAN := value];
at: #ObjectMemory ifPresent: [:value| SPURVM := value beginsWith: 'Spur'];
at: #STACKVM ifPresent: [:value| STACKVM := value];
at: #COGVM ifPresent: [:value| COGVM := initializationOptions at: #COGVM];
at: #COGMTVM ifPresent: [:value| COGMTVM := initializationOptions at: #COGMTVM]!
Item was added:
+ ----- Method: VMClass>>floatAtPointer: (in category 'memory access') -----
+ floatAtPointer: pointer
+ <doNotGenerate>
+ self halt.!
Item was added:
+ ----- Method: VMClass>>floatAtPointer:put: (in category 'memory access') -----
+ floatAtPointer: pointer put: value
+ <doNotGenerate>
+ self halt.!
Item was added:
+ ----- Method: VMClass>>free: (in category 'C library simulation') -----
+ free: pointer
+ <doNotGenerate>
+ "Do nothing"!
Item was added:
+ ----- Method: VMClass>>int16AtPointer: (in category 'memory access') -----
+ int16AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self shortAt: pointer!
Item was added:
+ ----- Method: VMClass>>int16AtPointer:put: (in category 'memory access') -----
+ int16AtPointer: pointer put: value
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self shortAt: pointer put: value!
Item was added:
+ ----- Method: VMClass>>int32AtPointer: (in category 'memory access') -----
+ int32AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 32 bit integer."
+ <doNotGenerate>
+
+ ^self longAt: pointer!
Item was added:
+ ----- Method: VMClass>>int32AtPointer:put: (in category 'memory access') -----
+ int32AtPointer: pointer put: value
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 32 bit integer."
+ <doNotGenerate>
+
+ ^self longAt: pointer put: value!
Item was added:
+ ----- Method: VMClass>>int64AtPointer: (in category 'memory access') -----
+ int64AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is the width of a machine word."
+ <doNotGenerate>
+
+ ^self halt!
Item was added:
+ ----- Method: VMClass>>int64AtPointer:put: (in category 'memory access') -----
+ int64AtPointer: pointer put: longValue
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and longValue is the width of a machine word."
+ <doNotGenerate>
+
+ ^self halt.!
Item was added:
+ ----- Method: VMClass>>int8AtPointer: (in category 'memory access') -----
+ int8AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self at: pointer!
Item was added:
+ ----- Method: VMClass>>int8AtPointer:put: (in category 'memory access') -----
+ int8AtPointer: pointer put: value
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self at: pointer put: value!
Item was added:
+ ----- Method: VMClass>>long64AtPointer: (in category 'memory access') -----
+ long64AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is the width of a machine word."
+ <doNotGenerate>
+
+ ^self halt!
Item was added:
+ ----- Method: VMClass>>long64AtPointer:put: (in category 'memory access') -----
+ long64AtPointer: pointer put: longValue
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and longValue is the width of a machine word."
+ <doNotGenerate>
+
+ ^self halt.!
Item was added:
+ ----- Method: VMClass>>malloc: (in category 'C library simulation') -----
+ malloc: size
+ <doNotGenerate>
+ ^ ByteArray new: size!
Item was added:
+ ----- Method: VMClass>>pointerAtPointer: (in category 'memory access') -----
+ pointerAtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is the width of a machine word."
+ <doNotGenerate>
+
+ ^self longAt: pointer!
Item was added:
+ ----- Method: VMClass>>pointerAtPointer:put: (in category 'memory access') -----
+ pointerAtPointer: pointer put: value
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is the width of a machine word."
+ <doNotGenerate>
+
+ ^self longAt: pointer put: value!
Item was added:
+ ----- Method: VMClass>>singleFloatAtPointer: (in category 'memory access') -----
+ singleFloatAtPointer: pointer
+ <doNotGenerate>
+ self halt.!
Item was added:
+ ----- Method: VMClass>>singleFloatAtPointer:put: (in category 'memory access') -----
+ singleFloatAtPointer: pointer put: value
+ <doNotGenerate>
+ self halt.!
Item was added:
+ ----- Method: VMClass>>uint16AtPointer: (in category 'memory access') -----
+ uint16AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self shortAt: pointer!
Item was added:
+ ----- Method: VMClass>>uint16AtPointer:put: (in category 'memory access') -----
+ uint16AtPointer: pointer put: value
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self shortAt: pointer put: value!
Item was added:
+ ----- Method: VMClass>>uint32AtPointer: (in category 'memory access') -----
+ uint32AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 32 bit integer."
+ <doNotGenerate>
+
+ ^self longAt: pointer!
Item was added:
+ ----- Method: VMClass>>uint32AtPointer:put: (in category 'memory access') -----
+ uint32AtPointer: pointer put: value
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 32 bit integer."
+ <doNotGenerate>
+
+ ^self longAt: pointer put: value!
Item was added:
+ ----- Method: VMClass>>uint64AtPointer: (in category 'memory access') -----
+ uint64AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is the width of a machine word."
+ <doNotGenerate>
+
+ ^self halt!
Item was added:
+ ----- Method: VMClass>>uint64AtPointer:put: (in category 'memory access') -----
+ uint64AtPointer: pointer put: longValue
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and longValue is the width of a machine word."
+ <doNotGenerate>
+
+ ^self halt.!
Item was added:
+ ----- Method: VMClass>>uint8AtPointer: (in category 'memory access') -----
+ uint8AtPointer: pointer
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self at: pointer!
Item was added:
+ ----- Method: VMClass>>uint8AtPointer:put: (in category 'memory access') -----
+ uint8AtPointer: pointer put: value
+ "This gets implemented by Macros in C, where its types will also be checked.
+ pointer is a raw address, and the result is an 16 bit integer."
+ <doNotGenerate>
+
+ ^self at: pointer put: value!
Item was changed:
SharedPool subclass: #VMObjectIndices
instanceVariableNames: ''
+ classVariableNames: 'ActiveProcessIndex CharacterTable CharacterValueIndex ClassAlien ClassArray ClassBitmap ClassBlockClosure ClassBlockContext ClassByteArray ClassByteString ClassCharacter ClassExternalAddress ClassExternalData ClassExternalFunction ClassExternalLibrary ClassExternalStructure ClassFloat ClassFullBlockClosure ClassLargeNegativeInteger ClassLargePositiveInteger ClassMessage ClassMethodContext ClassMutex ClassPoint ClassSemaphore ClassSmallInteger ClassString ClassUnsafeAlien ClassWeakFinalizer ClosureFirstCopiedValueIndex ClosureIndex ClosureNumArgsIndex ClosureOuterContextIndex ClosureStartPCIndex CompactClasses ConstMinusOne ConstOne ConstTwo ConstZero ExcessSignalsIndex ExternalObjectsArray FalseObject FirstLinkIndex ForeignCallbackProcess FullClosureCompiledBlockIndex FullClosureFirstCopiedValueIndex FullClosureReceiverIndex HeaderIndex InstanceSpecificationIndex InstructionPointerIndex KeyIndex LastLinkIndex LiteralStart LowcodeContextMark LowcodeNativeContextClass MessageArgumentsIndex MessageLookupClassIndex MessageSelectorIndex MethodArrayIndex MethodDictionaryIndex MethodIndex MyListIndex NextLinkIndex NilObject PrimErrTableIndex PriorityIndex ProcessInExternalCodeTag ProcessListsIndex ProcessSignalingLowSpace ReceiverIndex SchedulerAssociation SelectorAboutToReturn SelectorAttemptToAssign SelectorCannotInterpret SelectorCannotReturn SelectorCounterTripped SelectorDoesNotUnderstand SelectorInvokeCallback SelectorMustBeBoolean SelectorRunWithIn SelectorSistaTrap SelectorStart SelectorUnknownBytecode SenderIndex SpecialSelectors StackPointerIndex StreamArrayIndex StreamIndexIndex StreamReadLimitIndex StreamWriteLimitIndex SuperclassIndex SuspendedContextIndex TheDisplay TheFinalizationSemaphore TheInputSemaphore TheInterruptSemaphore TheLowSpaceSemaphore TheTimerSemaphore TrueObject ValueIndex XIndex YIndex'
- classVariableNames: 'ActiveProcessIndex CharacterTable CharacterValueIndex ClassAlien ClassArray ClassBitmap ClassBlockClosure ClassBlockContext ClassByteArray ClassByteString ClassCharacter ClassExternalAddress ClassExternalData ClassExternalFunction ClassExternalLibrary ClassExternalStructure ClassFloat ClassFullBlockClosure ClassLargeNegativeInteger ClassLargePositiveInteger ClassMessage ClassMethodContext ClassMutex ClassPoint ClassSemaphore ClassSmallInteger ClassString ClassUnsafeAlien ClassWeakFinalizer ClosureFirstCopiedValueIndex ClosureIndex ClosureNumArgsIndex ClosureOuterContextIndex ClosureStartPCIndex CompactClasses ConstMinusOne ConstOne ConstTwo ConstZero ExcessSignalsIndex ExternalObjectsArray FalseObject FirstLinkIndex ForeignCallbackProcess FullClosureCompiledBlockIndex FullClosureFirstCopiedValueIndex FullClosureReceiverIndex HeaderIndex InstanceSpecificationIndex InstructionPointerIndex KeyIndex LastLinkIndex LiteralStart MessageArgumentsIndex MessageLookupClassIndex MessageSelectorIndex MethodArrayIndex MethodDictionaryIndex MethodIndex MyListIndex NextLinkIndex NilObject PrimErrTableIndex PriorityIndex ProcessInExternalCodeTag ProcessListsIndex ProcessSignalingLowSpace ReceiverIndex SchedulerAssociation SelectorAboutToReturn SelectorAttemptToAssign SelectorCannotInterpret SelectorCannotReturn SelectorCounterTripped SelectorDoesNotUnderstand SelectorInvokeCallback SelectorMustBeBoolean SelectorRunWithIn SelectorSistaTrap SelectorStart SelectorUnknownBytecode SenderIndex SpecialSelectors StackPointerIndex StreamArrayIndex StreamIndexIndex StreamReadLimitIndex StreamWriteLimitIndex SuperclassIndex SuspendedContextIndex TheDisplay TheFinalizationSemaphore TheInputSemaphore TheInterruptSemaphore TheLowSpaceSemaphore TheTimerSemaphore TrueObject ValueIndex XIndex YIndex'
poolDictionaries: ''
category: 'VMMaker-Interpreter'!
!VMObjectIndices commentStamp: '<historical>' prior: 0!
I am a shared pool for the constants that define object layout and well-known objects shared between the object memories (e.g. ObjectMemory, NewObjectMemory), the interpreters (e.g. StackInterpreter, CoInterpreter) and the object representations (e.g. ObjectRepresentationForSqueakV3).
self classPool declare: #Foo from: StackInterpreter classPool
(ObjectMemory classPool keys select: [:k| (k beginsWith: 'Class') and: [(k endsWith: 'Index') not]]) do:
[:k| self classPool declare: k from: ObjectMemory classPool]!
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