[Vm-dev] Time primHighResClock truncated to 32 bits in 64 bits VMs.

Tobias Pape Das.Linux at gmx.de
Sun Dec 31 12:37:36 UTC 2017


> On 28.12.2017, at 20:07, tim Rowledge <tim at rowledge.org> wrote:
> 
> 
> 
>> On 28-12-2017, at 8:56 AM, David T. Lewis <lewis at mail.msen.com> wrote:
>> And the platform support code does this:
>> 
>> sqLong
>> ioHighResClock(void)
>> {
>> /* return the value of the high performance counter */
>> sqLong value = 0;
>> #if defined(__GNUC__) && ( defined(i386) || defined(__i386) || defined(__i386__)  \
>>                       || defined(i486) || defined(__i486) || defined (__i486__) \
>>                       || defined(intel) || defined(x86) || defined(i86pc) )
>>   __asm__ __volatile__ ("rdtsc" : "=A"(value));
>> #elif defined(__arm__) && (defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_7A__))
>>       /* tpr - do nothing for now; needs input from eliot to decide further */
>> #else
>> # error "no high res clock defined"
>> #endif
>> return value;
>> }
>> 
> 
> As a reminder to fix the ARM part someday, and because I am *so* not going to mess with git right now, here is an extract from 
> https://www.raspberrypi.org/forums/viewtopic.php?t=30821 "RDTSC on ARM”
> =====================
> Issue 1. The use of x86 assembly code.
> The FFTW project has a whole bunch of equivalents to rdtsc as part of its own profiling code. See https://github.com/vesperix/FFTW-for-AR ... el/cycle.h
> Replace the errant lines in nbeesrc-jan-10-2013/src/nbee/globals/profiling-functions.c (lines 49-50) with
> Code: Select all
> 
> volatile unsigned cc;
> static int init = 0;
> if(!init) {
>  __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 2" :: "r"(1<<31)); /* stop the cc */
>  __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 0" :: "r"(5));     /* initialize */
>  __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 1" :: "r"(1<<31)); /* start the cc */
>  init = 1;
> }
> __asm__ __volatile__ ("mrc p15, 0, %0, c9, c13, 0" : "=r"(cc));
> return cc;
> ====================


Looks interesting, but since when is this supported?
When I look for the ARM1176JZF-S Docu (aka Raspberry Pi 1), http://infocenter.arm.com/help/topic/com.arm.doc.ddi0290g/Bihbeabc.html
the CP15 info (see p15 above) has info on the c9 register, but not with c12 and c13 as second register.

OTOH, from the ARM Cortex-A7 (aka Raspberry Pi 2), the registers _are_ documented as "Performance monitor Control": http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BABFIBHD.html

Do we want to be pi2-above compatible or also below?

Best regards
	-Tobias


> 
> tim
> --
> tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
> All wiyht.  Rho sritched mg kegtops awound?
> 
> 



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