[Vm-dev] Small refactoring and Lowcode

[Eliot Miranda]

Hi Ronie,

On Sun, Feb 26, 2017 at 4:50 PM, Ronie Salgado <roniesalg at gmail.com> wrote:

>
> Hi Eliot,
>
> I will do it. In fact, I did not like the previous generated code because
> it has a bug. My only concern with that is when I need to allocate normal
> registers, and floating point registers. I guess that I would need to use
> more variations of allocate*RegistersForLowcodeInto: .
>

Yes, feel free to add as many variations as you need.

While you're at it it seems to me that the simNativeStackSize inst var
of StackToRegisterMappingCogit and CogSSBytecodeFixup are unused.  If so,
getting rid of it would  be a good idea, as the fixups have to be alloca'ed
and so this var can add a significant ammount of space to the allocation,
which can cause the JIT to not compile (see Cogit class
var MaxStackAllocSize).


>
> Best regards,
> Ronie
>
> 2017-02-26 4:42 GMT-03:00 Ben Coman <btc at openinworld.com>:
>
>>
>>
>>
>> On Sun, Feb 26, 2017 at 9:22 AM, Eliot Miranda <eliot.miranda at gmail.com>
>> wrote:
>>
>>>
>>> Hi Ronie, (Hi Clément),
>>>
>>>    for a while now Clément and I have been unhappy about optStatus
>>> (CogSSOptStatus).  Now that the RegisterAllocatingCogit is nearly working
>>> it's clear that a much nicer approach is to give CogSimStackEntry a
>>> liveRegister instance variable and have simSelf take the place of
>>> optStatus, so that what were
>>>
>>>     optStatus isReceiverResultRegLive
>>>     optStatus isReceiverResultRegLive: true
>>>     optStatus isReceiverResultRegLive: false
>>>
>>> are replaced by
>>>
>>>     simSelf liveRegister = ReceiverResultReg
>>>     simSelf liveRegister: ReceiverResultReg
>>>     simSelf liveRegister: NoReg
>>>
>>> To this end can you rewrite the Lowcode code generator so that e.g. the
>>> following
>>>
>>
>> Easier to compare for the casual viewer...
>> https://www.diffchecker.com/qF8tWcsT
>>
>> cheers -ben
>>
>>
>>>
>>> genLowcodeAlloca32
>>> <option: #LowcodeVM> "Lowcode instruction generator"
>>> | size |
>>>
>>> (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg
>>> ifTrue:
>>> [self ssAllocateRequiredReg:
>>> (size := optStatus isReceiverResultRegLive
>>> ifTrue: [Arg0Reg]
>>> ifFalse: [ReceiverResultReg])].
>>> size = ReceiverResultReg ifTrue:
>>> [ optStatus isReceiverResultRegLive: false ].
>>> self ssNativeTop nativePopToReg: size.
>>> self ssNativePop: 1.
>>>
>>> self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
>>> self SubR: size R: TempReg.
>>> self AndCq: -16 R: TempReg.
>>> self MoveR: TempReg R: size.
>>> self MoveR: size Aw: coInterpreter nativeStackPointerAddress.
>>> self ssPushNativeRegister: size.
>>>
>>> ^ 0
>>>
>>> reads something more like
>>>
>>> genLowcodeAlloca32
>>> <option: #LowcodeVM> "Lowcode instruction generator"
>>> | size |
>>>
>>> self allocateOneRegisterForLowcodeInto: [:reg| size := reg].
>>> self ssNativeTop nativePopToReg: size.
>>> self ssNativePop: 1.
>>>
>>> self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
>>> self SubR: size R: TempReg.
>>> self AndCq: -16 R: TempReg.
>>> self MoveR: TempReg R: size.
>>> self MoveR: size Aw: coInterpreter nativeStackPointerAddress.
>>> self ssPushNativeRegister: size.
>>>
>>> ^ 0
>>>
>>
>>> etc?  So there are allocateOneRegisterForLowcodeInto: through
>>> allocateThreeRegistersForLowcodeInto:. This way it'll be much easier to
>>> make the above change which I'm making now.
>>>
>>> _,,,^..^,,,_
>>> best, Eliot
>>>
>>>
>>
>>
>
>


-- 
_,,,^..^,,,_
best, Eliot
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