[Vm-dev] VM Maker: VMMaker.oscog-eem.2143.mcz

commits at source.squeak.org commits at source.squeak.org
Thu Mar 2 17:43:12 UTC 2017


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2143.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.2143
Author: eem
Time: 2 March 2017, 9:42:23.376209 am
UUID: fe064b6b-e530-4766-837d-799ffe1e8dcd
Ancestors: VMMaker.oscog-eem.2142

Fix regression in Sista sources due to receiverTags work.
Nuke unused method.

=============== Diff against VMMaker.oscog-eem.2142 ===============

Item was removed:
- ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') -----
- mergeCurrentSimStackWith: fixup
- 	<var: #fixup type: #'BytecodeFixup *'>
- 	| mergeSimStack currentEntry targetEntry |
- 	<var: #mergeSimStack type: #'SimStackEntry *'>
- 	"At a merge point the cogit expects the stack to be in the same state as mergeSimStack.
- 	 mergeSimStack is the state as of some jump forward to this point.  So make simStack agree
- 	 with mergeSimStack (it is, um, problematic to plant code at the jump).
- 	 Values may have to be assigned to registers.  Registers may have to be swapped.
- 	 The state of optStatus must agree."
- 	<var: #targetEntry type: #'SimStackEntry *'>
- 	<var: #currentEntry type: #'SimStackEntry *'>
- 	(mergeSimStack := fixup mergeSimStack) ifNil: [^self].
- 	"Assignments amongst the registers must be made in order to avoid overwriting.
- 	 If necessary exchange registers amongst simStack's entries to resolve any conflicts."
- 	self resolveRegisterOrderConflictsBetweenCurrentSimStackAnd: mergeSimStack.
- 	self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack).
- 	(self pushForMergeWith: mergeSimStack)
- 		ifTrue:
- 			[0 to: simStackPtr do:
- 				[:i|
- 				 currentEntry := self simStack: simStack at: i.
- 				 targetEntry := self simStack: mergeSimStack at: i.
- 				 (currentEntry reconcileForwardsWith: targetEntry) ifTrue:
- 					[self assert: i >= methodOrBlockNumArgs.
- 					 self deassignRegisterForTempVar: targetEntry in: mergeSimStack].
- 				 "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint:
- 				 spilled ifFalse:
- 					[simSpillBase := i - 1].
- 				 simStack
- 					at: i
- 					put: (self
- 							cCode: [mergeSimStack at: i]
- 							inSmalltalk: [(mergeSimStack at: i) copy])"]]
- 		ifFalse:
- 			[simStackPtr to: 0 by: -1 do:
- 				[:i|
- 				 currentEntry := self simStack: simStack at: i.
- 				 targetEntry := self simStack: mergeSimStack at: i.
- 				 (currentEntry reconcileForwardsWith: targetEntry) ifTrue:
- 					[self assert: i >= methodOrBlockNumArgs.
- 					 self deassignRegisterForTempVar: targetEntry in: mergeSimStack].
- 				 "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint:
- 				 spilled ifFalse:
- 					[simSpillBase := i - 1].
- 				 simStack
- 					at: i
- 					put: (self
- 							cCode: [mergeSimStack at: i]
- 							inSmalltalk: [(mergeSimStack at: i) copy])"]].
- 
- 	"a.k.a. fixup isReceiverResultRegSelf: (fixup isReceiverResultRegSelf and: [optStatus isReceiverResultRegLive])"
- 	optStatus isReceiverResultRegLive ifFalse:
- 		[fixup isReceiverResultRegSelf: false]!

Item was changed:
  ----- Method: SistaCogit>>genSpecialSelectorComparison (in category 'bytecode generators') -----
  genSpecialSelectorComparison
  	"Override to count inlined branches if followed by a conditional branch.
  	 We borrow the following conditional branch's counter and when about to
  	 inline the comparison we decrement the counter (without writing it back)
  	 and if it trips simply abort the inlining, falling back to the normal send which
  	 will then continue to the conditional branch which will trip and enter the abort."
  	| nextPC postBranchPC targetPC primDescriptor branchDescriptor
  	  rcvrIsInt rcvrIsConst argIsIntConst argInt jumpNotSmallInts inlineCAB
  	  counterAddress countTripped counterReg index |
  	<var: #countTripped type: #'AbstractInstruction *'>
  	<var: #primDescriptor type: #'BytecodeDescriptor *'>
  	<var: #jumpNotSmallInts type: #'AbstractInstruction *'>
  	<var: #branchDescriptor type: #'BytecodeDescriptor *'>
  
  	(coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ self genSpecialSelectorComparisonWithoutCounters ].
  
  	self ssFlushTo: simStackPtr - 2.
  	primDescriptor := self generatorAt: byte0.
  	argIsIntConst := self ssTop type = SSConstant
  				 and: [objectMemory isIntegerObject: (argInt := self ssTop constant)].
  	rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant)
  				  and: [objectMemory isIntegerObject:(self ssValue: 1) constant])
+ 				or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: (self addressOf: simSelf)]].
- 				or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: simSelf]].
  
  	"short-cut the jump if operands are SmallInteger constants."
  	(argIsIntConst and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue:
  		[^ self genStaticallyResolvedSpecialSelectorComparison].
  
  	self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | 
  		branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ].
  	
  	"Only interested in inlining if followed by a conditional branch."
  	inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse].
  	"Further, only interested in inlining = and ~= if there's a SmallInteger constant involved.
  	 The relational operators successfully statically predict SmallIntegers; the equality operators do not."
  	(inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue:
  		[inlineCAB := argIsIntConst or: [rcvrIsInt]].
  	inlineCAB ifFalse:
  		[^self genSpecialSelectorSend].
  
  	argIsIntConst
  		ifTrue:
  			[(self ssValue: 1) popToReg: ReceiverResultReg.
  			 self ssPop: 2]
  		ifFalse:
  			[self marshallSendArguments: 1].
  	jumpNotSmallInts := (rcvrIsInt and: [argIsIntConst]) ifFalse:
  							[argIsIntConst
  								ifTrue: [objectRepresentation genJumpNotSmallInteger: ReceiverResultReg]
  								ifFalse:
  									[rcvrIsInt
  										ifTrue: [objectRepresentation genJumpNotSmallInteger: Arg0Reg]
  										ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: ReceiverResultReg and: Arg0Reg scratch: TempReg]]].
  
  	counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg).
  	self 
  		genExecutionCountLogicInto: [ :cAddress :countTripBranch | 
  			counterAddress := cAddress. 
  			countTripped := countTripBranch ] 
  		counterReg: counterReg.
  
  	argIsIntConst
  		ifTrue: [self CmpCq: argInt R: ReceiverResultReg]
  		ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg].
  	"Cmp is weird/backwards so invert the comparison.  Further since there is a following conditional
  	 jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness."
  	self genConditionalBranch: (branchDescriptor isBranchTrue
  				ifTrue: [primDescriptor opcode]
  				ifFalse: [self inverseBranchFor: primDescriptor opcode])
  		operand: (self ensureNonMergeFixupAt: targetPC) asUnsignedInteger.
  		
  	self genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress.
  	
  	self Jump: (self ensureNonMergeFixupAt: postBranchPC).
  	countTripped jmpTarget: self Label.
  	jumpNotSmallInts ifNil:
  		[self annotateInstructionForBytecode.
  		 self ensureFixupAt: postBranchPC.
  		 self ensureFixupAt: targetPC.
  		 deadCode := true.
  		 ^0].
  	jumpNotSmallInts jmpTarget: countTripped getJmpTarget.
  	
  	argIsIntConst ifTrue:
  		[self MoveCq: argInt R: Arg0Reg].
  	index := byte0 - self firstSpecialSelectorBytecodeOffset.
  	^self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines!



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