[Vmdev] VM Maker: VMMaker.oscogeem.2603.mcz
commits at source.squeak.org
commits at source.squeak.org
Sun Dec 8 19:47:39 UTC 2019
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscogeem.2603.mcz
==================== Summary ====================
Name: VMMaker.oscogeem.2603
Author: eem
Time: 8 December 2019, 11:47:29.689495 am
UUID: aed4d5c33e5c4e358897c6f199406ccb
Ancestors: VMMaker.oscogeem.2602
Make A64 immediate logical bitmasks correct.
=============== Diff against VMMaker.oscogeem.2602 ===============
Item was added:
+  Method: CogARMv8Compiler>>decode64Imms:immr: (in category 'generate machine code  support') 
+ decode64Imms: imms immr: immr
+ "See aarch64/instrs/integer/bitmasks/DecodeBitMasks J17389.
+ This is a 64bit version computing the imm mask (wmask) only."
+  mask 
+ self assert: ((imms between: 0 and: 63) and: (immr between: 0 and: 63)).
+ "For logical immediates an allones value of S is reserved since it would generate a useless allones result (many times)"
+ imms = 63 ifTrue:
+ [^self cCode: [0] inSmalltalk: [#undefined]].
+
+ mask := 1 << (imms + 1)  1.
+ ^immr = 0
+ ifTrue: [mask]
+ ifFalse: [(mask << (64  immr) bitAnd: 1 << 64  1) + (mask >> immr)]!
Item was removed:
  Method: CogARMv8Compiler>>decodeBitMasksN:imms:immr: (in category 'generate machine code  support') 
 decodeBitMasksN: immN imms: imms immr: immr
 "See aarch64/instrs/integer/bitmasks/DecodeBitMasks J17389"
  tmask wmask levels 
 "eem 12/3/2019 18:17
 In

 len = HighestSetBit(immN:NOT(imms));

 I have no clue what is meant by

 immN:NOT(imms)

 Reading Arm Pseudocode Definition K13.4 Operators leaves me none the wiser."
 self shouldBeImplemented!
Item was changed:
 Method: CogARMv8Compiler>>isImmNImmSImmREncodableBitmask:ifTrue:ifFalse: (in category 'generate machine code  support') 
isImmNImmSImmREncodableBitmask: constant ifTrue: trinaryBlock "[:n :imms :immr...]" ifFalse: nullaryBlock
"See DecodeBitMasks J17389.
See https://dinfuehr.github.io/blog/encodingofimmediatevaluesonaarch64/
This method is adapted from The LLVM Compiler Infrastructure, AArch64AddressingModes.h processLogicalImmediate"
 imm size mask countLeadingOnes countTrailingOnes immr n nImms rotateCount 
(constant between: 1 and: 0) ifTrue:
[^nullaryBlock value].
imm := constant.
"First, determine the element size."
size := 32.
[mask := 1 << size  1.
(imm bitAnd: mask) ~= (imm >> size)
ifTrue: [size := size * 2. false]
ifFalse: [size > 2]]
whileTrue: [size := size / 2].
"Second, determine the rotation to make the element be: 0^m 1^n."
mask := 1 << 64  1 >> (64  size).
imm := imm bitAnd: mask.
(self isShiftedMask: imm)
ifTrue:
[rotateCount := self countTrailingZeros: imm.
countTrailingOnes := self countTrailingOnes: imm >> rotateCount]
ifFalse:
[imm := imm bitOr: mask bitInvert64.
(self isShiftedMask: imm) ifFalse:
[^nullaryBlock value].
countLeadingOnes := self countLeadingOnes: imm.
rotateCount := 64  countLeadingOnes.
countTrailingOnes := countLeadingOnes + (self countTrailingOnes: imm)  (64  size)].
"Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
to our target value, where I is the number of RORs to go the opposite direction."
self assert: size > rotateCount. "rotateCount should be smaller than element size"
immr := size  rotateCount bitAnd: size  1.
"If size has a 1 in the n'th bit, create a value that has zeroes in bits [0, n] and ones above that."
nImms := (size  1) bitInvert64 << 1.
"Or the CTO value into the low bits, which must be below the Nth bit mentioned above."
nImms := nImms bitOr: countTrailingOnes  1.
"Extract the seventh bit and toggle it to create the N field."
n := ((nImms >> 6) bitAnd: 1) bitXor: 1.
nImms := nImms bitAnd: 16r3F.
+ self assert: (self decode64Imms: nImms immr: immr) = constant.
 false ifTrue: [self assert: (self decodeBitMasksN: n imms: nImms immr: immr) = constant].
^trinaryBlock
value: n
value: nImms
value: immr
!
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