[Vm-dev] VM Maker: VMMaker.oscog-eem.2604.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2604.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.2604
Author: eem
Time: 8 December 2019, 12:26:04.834096 pm
UUID: 5cbfedbe-5d17-4395-b8b4-37fbf872405c
Ancestors: VMMaker.oscog-eem.2603

A64 M16rR & MbrR

=============== Diff against VMMaker.oscog-eem.2603 ===============

Item was added:
+ ----- Method: CogARMv8Compiler>>canZeroExtend (in category 'testing') -----
+ canZeroExtend
+ 	"x64 has native ZeroExtend8RR, ZeroExtend16RR, & ZeroExtend32RR."
+ 	<inline: true>
+ 	^true!

Item was added:
+ ----- Method: CogARMv8Compiler>>concretizeMoveM16rR (in category 'generate machine code - concretize') -----
+ concretizeMoveM16rR
+ 	"C6.2.168	LDURH	C6-1061"
+ 	| offset destReg srcReg |
+ 	offset := operands at: 0.
+ 	srcReg := operands at: 1.
+ 	destReg := operands at: 2.
+ 	(offset between: -256 and: 255)
+ 		ifTrue:
+ 			[machineCode
+ 				at: 0
+ 				put: 2r0111100001 << 22
+ 					+ ((offset bitAnd: 1 << 9 - 1) << 12)
+ 					+ (srcReg << 5)
+ 					+ destReg.
+ 			^machineCodeSize := 4]
+ 		ifFalse:
+ 			[self shouldBeImplemented]!

Item was added:
+ ----- Method: CogARMv8Compiler>>concretizeMoveMbrR (in category 'generate machine code - concretize') -----
+ concretizeMoveMbrR
+ 	"C6.2.167	LDURB	C6-1060"
+ 	| offset destReg srcReg |
+ 	offset := operands at: 0.
+ 	srcReg := operands at: 1.
+ 	destReg := operands at: 2.
+ 	(offset between: -256 and: 255)
+ 		ifTrue:
+ 			[machineCode
+ 				at: 0
+ 				put: 2r0011100001 << 22
+ 					+ ((offset bitAnd: 1 << 9 - 1) << 12)
+ 					+ (srcReg << 5)
+ 					+ destReg.
+ 			^machineCodeSize := 4]
+ 		ifFalse:
+ 			[self shouldBeImplemented]!

Item was changed:
  ----- Method: CogARMv8Compiler>>strn:rt:imm:shiftBy12: (in category 'generate machine code - support') -----
  strn: srcReg rt: targetReg imm: offset shiftBy12: shiftBy12
  	"C6.2.273	STR (immediate)	C6-1239
  	 C6.2.297	STUR				C6-1290"
  
+ 	self deny: SP = targetReg.
- 	self deny: srcReg = SP.
  	self deny: srcReg = targetReg.
  	"Unsigned offset, C6-1240"
  	(offset \\ 8 = 0
  	 and: [offset / 8 between: 0 and: 1 << 12 - 1]) ifTrue:
  		[^2r1111100100 << 22
  		+ (offset << 7 "10 - 3")
  		+ (targetReg << 5)
  		+ srcReg].
  	self assert: (offset between: -256 and: 255).
  	^2r11111000000 << 21
  	  + ((offset bitAnd: 511) << 12)
  	  + (targetReg << 5)
  	  + srcReg!