[Vm-dev] VM Maker: VMMaker.oscog-nice.2714.mcz
commits at source.squeak.org
commits at source.squeak.org
Tue Feb 18 23:56:55 UTC 2020
Nicolas Cellier uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-nice.2714.mcz
==================== Summary ====================
Name: VMMaker.oscog-nice.2714
Author: nice
Time: 19 February 2020, 12:55:52.495801 am
UUID: 9fb2d939-6a11-4c06-9e0f-6805c9aa48d3
Ancestors: VMMaker.oscog-nice.2713
Fix incorrect IA32/X64 encoding of operands LZCNT (ClzRR) and BSR instructions.
I did swap the operands, destReg is in reg/opcode (RO) field, and maskReg (source) is in r/m (RM) field.
=============== Diff against VMMaker.oscog-nice.2713 ===============
Item was changed:
----- Method: CogIA32Compiler>>concretizeBSR (in category 'generate machine code - concretize') -----
concretizeBSR
"Bit Scan Reverse
First operand is input register (mask)
Second operand is output register (dest)"
"BSR"
<inline: true>
+ | dest maskReg |
+ maskReg := operands at: 0.
- | dest mask |
- mask := operands at: 0.
dest := operands at: 1.
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rBD;
+ at: 2 put: (self mod: ModReg RM: maskReg RO: dest).
- at: 2 put: (self mod: ModReg RM: dest RO: mask).
^3!
Item was changed:
----- Method: CogIA32Compiler>>concretizeClzRR (in category 'generate machine code - concretize') -----
concretizeClzRR
"Count leading zeros
First operand is output (dest)
Second operand is input (mask)"
"LZCNT"
<inline: true>
| maskReg dest |
maskReg := operands at: 0.
dest := operands at: 1.
machineCode
at: 0 put: 16rF3;
at: 1 put: 16r0F;
at: 2 put: 16rBD;
+ at: 3 put: (self mod: ModReg RM: maskReg RO: dest).
- at: 3 put: (self mod: ModReg RM: dest RO: maskReg).
^4!
Item was changed:
----- Method: CogX64Compiler>>concretizeBSR (in category 'generate machine code - concretize') -----
concretizeBSR
"Bit Scan Reverse
First operand is input register (mask)
Second operand is output register (dest)"
"BSR"
<inline: true>
+ | dest maskReg |
+ maskReg := operands at: 0.
- | dest mask |
- mask := operands at: 0.
dest := operands at: 1.
+ (dest <= 7 and: [maskReg <= 7])
- (dest <= 7 and: [mask <= 7])
ifTrue: [machineCode at: 0 put: (self rexw: true r: 0 x: 0 b: 0)]
ifFalse: ["Beware: operation is on 32bits for R8-15"machineCode at: 0 put: (self rexw: false r: 0 x: 0 b: 0)].
machineCode
at: 1 put: 16r0F;
at: 2 put: 16rBD;
+ at: 3 put: (self mod: ModReg RM: maskReg RO: dest).
- at: 3 put: (self mod: ModReg RM: dest RO: mask).
^4!
Item was changed:
----- Method: CogX64Compiler>>concretizeClzRR (in category 'generate machine code - concretize') -----
concretizeClzRR
"Count leading zeros
First operand is output (dest)
Second operand is input (mask)"
"LZCNT"
<inline: true>
| maskReg dest |
maskReg := operands at: 0.
dest := operands at: 1.
machineCode
at: 0 put: 16rF3;
at: 1 put: (self rexw: true r: 0 x: 0 b: 0);
at: 2 put: 16r0F;
at: 3 put: 16rBD;
+ at: 4 put: (self mod: ModReg RM: maskReg RO: dest).
- at: 4 put: (self mod: ModReg RM: dest RO: maskReg).
^5!
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