[Vm-dev] Aarch64 number bug

[tim Rowledge]

> On 2021-08-04, at 12:05 PM, Bruce O'Neel <bruce.oneel at pckswarms.ch> wrote:
> 
> Hi,
> 
> Excellent!
> 
> So can someone see what am I doing wrong because mine segfaults pretty quickly.

This is a bit weird. For ages the flushXcache code has been happily working on my Pi 4 based on CogARMv8Compiler>>#generateICacheFlush using the dc instruction. I have a working VM that uses it.

On Sunday (or Monday? Days mean so little...) Eliot & I were trying something out and the VM built then (with the dc instruction flushing) simply blew up, segfaulting at that dc instruction. We changed to use the same flushing as CogARMv8Compiler>>#initialFlushICacheFrom:to: instead and ... no segfault.

I could imagine this becoming an issue if I had updated the OS kernel etc, but I haven't. Just how is it possible ... I dunno. Maybe some GDB examinations will reveal the dc instruction being created differently because of some seemingly unrelated change moving an instruction 4 bytes and triggering an obscure alignment issue that causes a bit to get dropped in the code word. Or perhaps the universe is just annoyed with me again.

This is the change, try it and see if it helps you -

-------------- next part --------------
A non-text attachment was scrubbed...
Name: ARMv8FlushIssue.st
Type: application/octet-stream
Size: 1394 bytes
Desc: not available
URL: <http://lists.squeakfoundation.org/pipermail/vm-dev/attachments/20210804/c7d7aa47/attachment.obj>
-------------- next part --------------


tim
--
tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
People who deal with bits should expect to get bitten.