[Vm-dev] CNTVCT, Counter-timer Virtual Count register on AArch32

[ken.dickey at whidbey.com]

On 2021-08-04 11:35, Eliot Miranda wrote:

> I see that ARM32 does indeed support a 64-bit performance counter.  See 
> G8.7.23
> 
> .. ARM32 is the only one of our platforms not to implement this yet.

Eliot,

Slogged through the ARM documentation mud and tried some experiments.  
It does not look feasible to me to do a portable, direct, user level 
implementation of this because:

[1] Different arm32 cores have different co-processor support -- i.e. 
for counters.

[2] More importantly, one has to enable the counters in kernel mode to 
be read from user mode using a loadable kernel module.  Else one just 
gets illegal instruction faults.

Clearest write up of this I have found is:

https://matthewarcus.wordpress.com/2018/01/27/using-the-cycle-counter-registers-on-the-raspberry-pi-3/

IMHO this is an OS support level issue.  Too complex for me.

FYI,
-KenD