[Vm-dev] VM Maker: VMMaker.oscog-eem.3117.mcz
commits at source.squeak.org
commits at source.squeak.org
Thu Dec 2 21:52:32 UTC 2021
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.3117.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.3117
Author: eem
Time: 2 December 2021, 1:52:19.724775 pm
UUID: ede3f763-e691-4662-91d0-34fc19bc39a1
Ancestors: VMMaker.oscog-eem.3116
Since id_aa64isar0_el1 is a priviledged instruction use getauxval on linux to derive the value(s) derived there-from, currenty whether atomic instructions are available or not. This addresses opensmalltalk-vm Issue #608.
=============== Diff against VMMaker.oscog-eem.3116 ===============
Item was changed:
----- Method: CogARMv8Compiler class>>preambleCCode (in category 'translation') -----
preambleCCode
+ ^ '#if __APPLE__ && __MACH__ // Mac OS X\# include <libkern/OSCacheControl.h>\#endif\' withCRs,
+ '#if __linux__\# include <sys/auxv.h>\#endif' withCRs!
- ^'#if __APPLE__ && __MACH__ /* Mac OS X */\#include <libkern/OSCacheControl.h>\#endif' withCRs!
Item was changed:
----- Method: CogARMv8Compiler>>detectFeatures (in category 'feature detection') -----
detectFeatures
<inline: #always>
+ self cppIf: #__APPLE__ ifTrue:
+ [self detectFeaturesOnMacOS] ifFalse:
+ [self cppIf: #__linux__ ifTrue:
+ [self detectFeaturesOnLinux]
+ ifFalse:
+ [self detectFeaturesOnRawMachine]]!
- self cppIf: #__APPLE__
- ifTrue: [self detectFeaturesOnMacOS]
- ifFalse: [self detectFeaturesOnLinux]!
Item was changed:
----- Method: CogARMv8Compiler>>detectFeaturesOnLinux (in category 'feature detection') -----
detectFeaturesOnLinux
+ "Do a throw-away compilation to read CTR_EL0 and initialize ctrEl0.
+ Some linux kernels trap and synthesize access to ID_AA64ISAR0_EL1,
+ and some do not, so use getauxval(3) to access value(s) derived there-from,
+ i.e. whether the processor has atomic instructions."
+ <option: #__linux__>
+ | startAddress getFeatureReg ctrEL0 |
- "Do throw-away compilations to read CTR_EL0 & ID_AA64ISAR0_EL1 and initialize ctrEl0 & idISAR0"
- <notOption: #__APPLE__>
- | startAddress getFeatureReg ctrEL0 idISAR0 |
<var: 'getFeatureReg' declareC: 'usqIntptr_t (*getFeatureReg)(void)'>
startAddress := cogit methodZoneBase.
cogit allocateOpcodes: 4 bytecodes: 0.
getFeatureReg := cogit cCoerceSimple: startAddress to: #'usqIntptr_t (*)(void)'.
"Return the value of CTR_EL0; that's the control register that defines the vital statistics of the processor's caches."
cogit
gen: Nop; "do something anodyne so it is easy to distinguish MRS_CTR_EL0 being an illegal instruction rather than the code zone not being executable."
gen: MRS_CTR_EL0 operand: ABIResultReg;
RetN: 0.
cogit outputInstructionsForGeneratedRuntimeAt: startAddress.
cogit resetMethodZoneBase: startAddress.
cogit ensureExecutableCodeZoneWithin:
[ctrEL0 := (self cCode: 'getFeatureReg()' inSmalltalk: [cogit simulateLeafCallOf: startAddress]).
"see e.g. CogARMv8Compiler class>>printCTR_EL0:, concretizeCacheControlOp1:CRm:Op2: &
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100403_0200_00_en/lau1443435580346.html
DminLine & IminLine are Log2 words; 16 words miniumum"
self setDataCacheFlushRequired: (ctrEL0 noMask: 1 << 28).
self setDataCacheLineLength: 4 << (ctrEL0 >> 16 bitAnd: 15).
self dataCacheLineLength = 0 ifTrue:
[self setDataCacheLineLength: 4 << 4].
self setInstructionCacheFlushRequired: (ctrEL0 noMask: 1 << 29).
self setInstructionCacheLineLength: 4 << (ctrEL0 bitAnd: 15)].
self instructionCacheLineLength = 0 ifTrue:
[self setInstructionCacheLineLength: 4 << 4].
+ self setHasAtomicInstructions: ((self getauxval: #AT_HWCAP) anyMask: #HWCAP_ATOMICS)!
- cogit zeroOpcodeIndexForNewOpcodes.
- cogit
- gen: Nop; "do something anodyne so it is easy to distinguish MRS_CTR_EL0 being an illegal instruction rather than the code zone not being executable."
- gen: MRS_ID_AA64ISAR0_EL1 operand: ABIResultReg;
- RetN: 0.
- cogit outputInstructionsForGeneratedRuntimeAt: startAddress.
- cogit resetMethodZoneBase: startAddress.
- cogit ensureExecutableCodeZoneWithin:
- [idISAR0 := (self cCode: 'getFeatureReg()' inSmalltalk: [cogit simulateLeafCallOf: startAddress]).
- self setHasAtomicInstructions: (idISAR0 >> 20 bitAnd: 2r1111) = 2r10]!
Item was added:
+ ----- Method: CogARMv8Compiler>>detectFeaturesOnRawMachine (in category 'feature detection') -----
+ detectFeaturesOnRawMachine
+ "Do throw-away compilations to read CTR_EL0 & ID_AA64ISAR0_EL1 and initialize ctrEl0 & idISAR0"
+ <notOption: #__APPLE__>
+ <notOption: #__linux__>
+ | startAddress getFeatureReg ctrEL0 idISAR0 |
+ <var: 'getFeatureReg' declareC: 'usqIntptr_t (*getFeatureReg)(void)'>
+ startAddress := cogit methodZoneBase.
+ cogit allocateOpcodes: 4 bytecodes: 0.
+ getFeatureReg := cogit cCoerceSimple: startAddress to: #'usqIntptr_t (*)(void)'.
+ "Return the value of CTR_EL0; that's the control register that defines the vital statistics of the processor's caches."
+ cogit
+ gen: Nop; "do something anodyne so it is easy to distinguish MRS_CTR_EL0 being an illegal instruction rather than the code zone not being executable."
+ gen: MRS_CTR_EL0 operand: ABIResultReg;
+ RetN: 0.
+ cogit outputInstructionsForGeneratedRuntimeAt: startAddress.
+ cogit resetMethodZoneBase: startAddress.
+ cogit ensureExecutableCodeZoneWithin:
+ [ctrEL0 := (self cCode: 'getFeatureReg()' inSmalltalk: [cogit simulateLeafCallOf: startAddress]).
+ "see e.g. CogARMv8Compiler class>>printCTR_EL0:, concretizeCacheControlOp1:CRm:Op2: &
+ http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100403_0200_00_en/lau1443435580346.html
+ DminLine & IminLine are Log2 words; 16 words miniumum"
+ self setDataCacheFlushRequired: (ctrEL0 noMask: 1 << 28).
+ self setDataCacheLineLength: 4 << (ctrEL0 >> 16 bitAnd: 15).
+ self dataCacheLineLength = 0 ifTrue:
+ [self setDataCacheLineLength: 4 << 4].
+ self setInstructionCacheFlushRequired: (ctrEL0 noMask: 1 << 29).
+ self setInstructionCacheLineLength: 4 << (ctrEL0 bitAnd: 15)].
+ self instructionCacheLineLength = 0 ifTrue:
+ [self setInstructionCacheLineLength: 4 << 4].
+ cogit zeroOpcodeIndexForNewOpcodes.
+ cogit
+ gen: Nop; "do something anodyne so it is easy to distinguish MRS_ID_AA64ISAR0_EL1 being an illegal instruction rather than the code zone not being executable."
+ gen: MRS_ID_AA64ISAR0_EL1 operand: ABIResultReg;
+ RetN: 0.
+ cogit outputInstructionsForGeneratedRuntimeAt: startAddress.
+ cogit resetMethodZoneBase: startAddress.
+ cogit ensureExecutableCodeZoneWithin:
+ [idISAR0 := (self cCode: 'getFeatureReg()' inSmalltalk: [cogit simulateLeafCallOf: startAddress]).
+ self setHasAtomicInstructions: (idISAR0 >> 20 bitAnd: 2r1111) = 2r10]!
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