[Vm-dev] VM Maker: VMMaker.oscog-tpr.1253.mcz
commits at source.squeak.org
commits at source.squeak.org
Fri Apr 24 22:36:32 UTC 2015
tim Rowledge uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1253.mcz
==================== Summary ====================
Name: VMMaker.oscog-tpr.1253
Author: tpr
Time: 24 April 2015, 3:34:54.257 pm
UUID: 8f8f4942-2558-4a50-a21a-80d513acf9f0
Ancestors: VMMaker.oscog-cb.1252
Add ARM opcodes for MSR (status register updating) and CMPSMULL (a virtual instruction that actually uses a CMP but brings in an ASR 31 of one arg; this is only for use in the genMulR:R:)
Since fixing the mulitply breaks things - we think because the sim code does not handle it correctly though cannot be sure yet - turn off usage of it by setting canMulRR to false.
Add a crucial rewriteInlineCacheTag:at: for ARM.
We can now sim the trunk46-spur image up to where Balloon does something the simulator code can't handle. 130 million bytecodes or so and a full scale gc, compaction, pig compact and code compact.
=============== Diff against VMMaker.oscog-cb.1252 ===============
Item was changed:
CogAbstractInstruction subclass: #CogARMCompiler
instanceVariableNames: 'conditionOrNil'
+ classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CMPSMULL CPSRReg CS CmpOpcode ConcreteIPReg ConcreteVarBaseReg EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveNotOpcode MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode'
- classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode ConcreteIPReg ConcreteVarBaseReg EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveNotOpcode MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0!
I generate ARM instructions from CogAbstractInstructions. For reference see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html
The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw).
This class does not take any special action to flush the instruction cache on instruction-modification.!
Item was changed:
----- Method: CogARMCompiler class>>initialize (in category 'class initialization') -----
initialize
"Initialize various ARM instruction-related constants."
"CogARMCompiler initialize"
| specificOpcodes refs |
super initialize.
self ~~ CogARMCompiler ifTrue: [^self].
R0 := 0.
R1 := 1.
R2 := 2.
R3 := 3.
R4 := 4.
R5 := 5.
R6 := 6.
R7 := 7.
R8 := 8.
R9 := 9.
R10 := 10.
R11 := 11.
R12 := 12.
SP := 13.
LR := 14.
PC := 15.
CArg0Reg := 0.
CArg1Reg := 1.
CArg2Reg := 2.
CArg3Reg := 3.
ConcreteVarBaseReg := 10.
ConcreteIPReg := 12. "IP, The Intra-Procedure-call scratch register."
"Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1"
EQ := 0.
NE := 1.
CS := 2.
CC := 3.
MI := 4.
PL := 5.
VS := 6.
VC := 7.
HI := 8.
LS := 9.
GE := 10.
LT := 11.
GT := 12.
LE := 13.
AL := 14.
AddOpcode := 4.
AndOpcode := 0.
BicOpcode := 14.
CmpOpcode := 10.
MoveOpcode := 13.
MoveNotOpcode := 15.
OrOpcode := 12.
RsbOpcode := 3.
SubOpcode := 2.
XorOpcode := 1.
SMLALOpcode := 7.
CPSRReg := 16.
OverflowFlag := 1 << 28.
"Specific instructions"
LastRTLCode isNil ifTrue:
[CogRTLOpcodes initialize].
+ specificOpcodes := #(SMULL MSR MRS LDMFD STMFD BICCqR CMPSMULL).
- specificOpcodes := #(SMULL MSR MRS LDMFD STMFD BICCqR).
refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
[:ea| ea key].
(classPool keys reject: [:k| (specificOpcodes includes: k) or: [refs includes: k]]) do:
[:k|
Undeclared declare: k from: classPool].
specificOpcodes withIndexDo:
[:classVarName :value|
self classPool
declare: classVarName from: Undeclared;
at: classVarName put: value + LastRTLCode - 1]!
Item was changed:
----- Method: CogARMCompiler>>canMulRR (in category 'testing') -----
canMulRR
<inline: true>
+ ^false!
- ^true!
Item was changed:
----- Method: CogARMCompiler>>computeMaximumSize (in category 'generate machine code') -----
computeMaximumSize
"Because we don't use Thumb, each ARM instruction has 4 bytes. Some abstract opcodes need more than one instruction. We only handle those in this caseOf: and let the default return 4"
opcode
caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^maxSize := 0].
[AlignmentNops] -> [^maxSize := (operands at: 0) - 4].
[Fill16] -> [^maxSize := 4].
[Fill32] -> [^maxSize := 4].
[FillFromWord] -> [^maxSize := 4].
[Nop] -> [^maxSize := 4].
"ARM Specific Control/Data Movement"
[BICCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[TstCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[SMULL] -> [^maxSize := 4].
+ [MSR] -> [^maxSize := 4].
+ [CMPSMULL] -> [^maxSize := 4]. "special compare for genMulR:R: usage"
"Control"
[Call] -> [^maxSize := 4].
[CallFull] -> [^maxSize := 20].
[JumpR] -> [^maxSize := 4].
[Jump] -> [^maxSize := 4].
[JumpFull] -> [^maxSize := 20].
[JumpLong] -> [^maxSize := 4].
[JumpZero] -> [^maxSize := 4].
[JumpNonZero] -> [^maxSize := 4].
[JumpNegative] -> [^maxSize := 4].
[JumpNonNegative] -> [^maxSize := 4].
[JumpOverflow] -> [^maxSize := 4].
[JumpNoOverflow] -> [^maxSize := 4].
[JumpCarry] -> [^maxSize := 4].
[JumpNoCarry] -> [^maxSize := 4].
[JumpLess] -> [^maxSize := 4].
[JumpGreaterOrEqual] -> [^maxSize := 4].
[JumpGreater] -> [^maxSize := 4].
[JumpLessOrEqual] -> [^maxSize := 4].
[JumpBelow] -> [^maxSize := 4].
[JumpAboveOrEqual] -> [^maxSize := 4].
[JumpAbove] -> [^maxSize := 4].
[JumpBelowOrEqual] -> [^maxSize := 4].
[JumpLongZero] -> [^maxSize := 4].
[JumpLongNonZero] -> [^maxSize := 4].
[JumpFPEqual] -> [^maxSize := 8].
[JumpFPNotEqual] -> [^maxSize := 8].
[JumpFPLess] -> [^maxSize := 8].
[JumpFPGreaterOrEqual]-> [^maxSize := 8].
[JumpFPGreater] -> [^maxSize := 8].
[JumpFPLessOrEqual] -> [^maxSize := 8].
[JumpFPOrdered] -> [^maxSize := 8].
[JumpFPUnordered] -> [^maxSize := 8].
[RetN] -> [^(operands at: 0) = 0
ifTrue: [maxSize := 4]
ifFalse: [maxSize := 8]].
[Stop] -> [^maxSize := 4].
"Arithmetic"
[AddCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[AndCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[AndCqRR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[CmpCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[OrCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[SubCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[XorCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[AddCwR] -> [^maxSize := 20].
[AndCwR] -> [^maxSize := 20].
[CmpCwR] -> [^maxSize := 20].
[OrCwR] -> [^maxSize := 20].
[SubCwR] -> [^maxSize := 20].
[XorCwR] -> [^maxSize := 20].
[AddRR] -> [^maxSize := 4].
[AndRR] -> [^maxSize := 4].
[CmpRR] -> [^maxSize := 4].
[OrRR] -> [^maxSize := 4].
[XorRR] -> [^maxSize := 4].
[SubRR] -> [^maxSize := 4].
[NegateR] -> [^maxSize := 4].
[LoadEffectiveAddressMwrR]
-> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[LogicalShiftLeftCqR] -> [^maxSize := 4].
[LogicalShiftRightCqR] -> [^maxSize := 4].
[ArithmeticShiftRightCqR] -> [^maxSize := 4].
[LogicalShiftLeftRR] -> [^maxSize := 4].
[LogicalShiftRightRR] -> [^maxSize := 4].
[ArithmeticShiftRightRR] -> [^maxSize := 4].
[AddRdRd] -> [^maxSize := 4].
[CmpRdRd] -> [^maxSize := 4].
[SubRdRd] -> [^maxSize := 4].
[MulRdRd] -> [^maxSize := 4].
[DivRdRd] -> [^maxSize := 4].
[SqrtRd] -> [^maxSize := 4].
"Data Movement"
[MoveCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 16]].
[MoveCwR] -> [^maxSize := 16].
[MoveRR] -> [^maxSize := 4].
[MoveRdRd] -> [^maxSize := 4].
[MoveAwR] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [4]
ifFalse: [20]].
[MoveRAw] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [4]
ifFalse: [20]].
[MoveRMwr] -> [self is12BitValue: (operands at: 1)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[MoveRdM64r] -> [^maxSize := 20].
[MoveMbrR] -> [self is12BitValue: (operands at: 0)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[MoveRMbr] -> [self is12BitValue: (operands at: 1)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[MoveM16rR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[MoveM64rRd] -> [^maxSize := 20].
[MoveMwrR] -> [self is12BitValue: (operands at: 0)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[MoveXbrRR] -> [^maxSize := 4].
[MoveRXbrR] -> [^maxSize := 4].
[MoveXwrRR] -> [^maxSize := 4].
[MoveRXwrR] -> [^maxSize := 4].
[PopR] -> [^maxSize := 4].
[PushR] -> [^maxSize := 4].
[PushCw] -> [^maxSize := 20].
[PushCq] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 8]
ifFalse: [maxSize := 20]].
[PrefetchAw] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [4]
ifFalse: [20]].
"Conversion"
[ConvertRRd] -> [^maxSize := 4].
}.
^0 "to keep C compiler quiet"
!
Item was added:
+ ----- Method: CogARMCompiler>>concretizeCMPSMULL (in category 'generate machine code - concretize') -----
+ concretizeCMPSMULL
+ "Generate a CMP a, b, ASR #31 instruction, specifically for comparing the resutls of SMULLs in genMulR:R:"
+ | hiReg loReg |
+ hiReg := self concreteRegister: (operands at: 0).
+ loReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0
+ put: (self type: 0 op: CmpOpcode set: 1 rn: hiReg rd: 0)
+ + (31<<7) "the shift amount"
+ + (2<<5) "the shift type - ASR"
+ + loReg.
+ ^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeDataOperationCqR: (in category 'generate machine code - concretize') -----
concretizeDataOperationCqR: armOpcode
"Will get inlined into concretizeAt: switch."
"4 == Add, 2 == Sub, Xor == 1, And == 0, Or == 12, Bic == 14"
<inline: true>
|val rd rn |
val := operands at: 0.
rn := self concreteRegister: (operands at: 1).
+ rd := opcode = CmpOpcode ifTrue: [0] ifFalse:[rn]. "Extra note - if ever a version of this code wants to NOT set the Set flag - Cmp must always have it set or it will pretend to be a SMALALBT and Very Bad Things might happen"
- rd := opcode = CmpOpcode ifTrue: [0] ifFalse:[rn].
self rotateable8bitImmediate: val
ifTrue: [:rot :immediate |
self machineCodeAt: 0 put: (self type: 1 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: ((rot>>1)"in this usage we have to halve the rot value" << 8 bitOr: immediate)).
^machineCodeSize := 4]
ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
val > 0 ifTrue: [
|hb |
hb := val highBit.
1 << hb = (val +1)
ifTrue: [ "MVN temp, #0, making 0xffffffff"
self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0).
"Then armOpcode reg, temp reg, lsr #(32-hb)"
self machineCodeAt: 4 put:(self dataOpType: armOpcode rd: rd rn: rn rm: ConcreteIPReg lsr: (32-hb)).
^machineCodeSize :=8]].
^self concretizeDataOperationCwR: armOpcode].
^0 "to keep Slang happy"
!
Item was added:
+ ----- Method: CogARMCompiler>>concretizeMSR (in category 'generate machine code - concretize') -----
+ concretizeMSR
+ "Generate an MSR CPSR_f, #flags instruction.
+ Note that we only have business with the NZCV flags so we use
+ N -> 8
+ Z -> 4
+ C -> 2
+ V -> 1.
+ You don't want to mess with this too much."
+ | flags |
+ flags := self concreteRegister: (operands at: 0).
+ self machineCodeAt: 0 put: (self msr: flags).
+ ^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeSMULL (in category 'generate machine code - concretize') -----
concretizeSMULL
+ | srcA srcB hiResultReg loResultReg |
+ "Generate an SMULL loResultReg, hiResultReg, srcA, srcB instruction"
+ srcA := self concreteRegister: (operands at: 0).
+ "NOTE: srcB contains the other mutiplicand at this point. It is OK to use it as the destination for the low part of the result and in fact this saves us moving it later"
+ loResultReg := srcB := self concreteRegister: (operands at: 1).
+ hiResultReg := self concreteRegister: RISCTempReg.
- | srcReg destReg hiReg loReg |
- srcReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
- hiReg := self concreteRegister: RISCTempReg.
- loReg := self concreteRegister: TempReg.
self machineCodeAt: 0
+ put: (self type: 0 op: 6 set: 0 rn: hiResultReg rd: loResultReg)
+ + (srcA << 8)
- put: (self type: 0 op: 6 set: 0 rn: hiReg rd: loReg)
- + (srcReg << 8)
+ (9 << 4)
+ + srcB.
- + destReg.
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>dispatchConcretize (in category 'generate machine code') -----
dispatchConcretize
"Attempt to generate concrete machine code for the instruction at address.
This is the inner dispatch of concretizeAt: actualAddress which exists only
to get around the branch size limits in the SqueakV3 (blue book derived)
bytecode set."
<returnTypeC: #void>
conditionOrNil ifNotNil:
[self concretizeConditionalInstruction.
^self].
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^self concretizeLabel].
[AlignmentNops] -> [^self concretizeAlignmentNops].
[Fill16] -> [^self concretizeFill16].
[Fill32] -> [^self concretizeFill32].
[FillFromWord] -> [^self concretizeFillFromWord].
[Nop] -> [^self concretizeNop].
"ARM Specific Control/Data Movement"
[LDMFD] -> [^self concretizeLDMFD].
[STMFD] -> [^self concretizeSTMFD].
[SMULL] -> [^self concretizeSMULL] .
+ [CMPSMULL] -> [^self concretizeCMPSMULL].
+ [MSR] -> [^self concretizeMSR].
[BICCqR] -> [^self concretizeDataOperationCqR: BicOpcode].
"Control"
[Call] -> [^self concretizeCall]. "call code within code space"
[CallFull] -> [^self concretizeCallFull]. "call code anywhere in address space"
[JumpR] -> [^self concretizeJumpR].
[JumpFull] -> [^self concretizeJumpFull]."jump within address space"
[JumpLong] -> [^self concretizeConditionalJump: AL]."jumps witihn code space"
[JumpLongZero] -> [^self concretizeConditionalJump: EQ].
[JumpLongNonZero] -> [^self concretizeConditionalJump: NE].
[Jump] -> [^self concretizeConditionalJump: AL].
[JumpZero] -> [^self concretizeConditionalJump: EQ].
[JumpNonZero] -> [^self concretizeConditionalJump: NE].
[JumpNegative] -> [^self concretizeConditionalJump: MI].
[JumpNonNegative] -> [^self concretizeConditionalJump: PL].
[JumpOverflow] -> [^self concretizeConditionalJump: VS].
[JumpNoOverflow] -> [^self concretizeConditionalJump: VC].
[JumpCarry] -> [^self concretizeConditionalJump: CS].
[JumpNoCarry] -> [^self concretizeConditionalJump: CC].
[JumpLess] -> [^self concretizeConditionalJump: LT].
[JumpGreaterOrEqual] -> [^self concretizeConditionalJump: GE].
[JumpGreater] -> [^self concretizeConditionalJump: GT].
[JumpLessOrEqual] -> [^self concretizeConditionalJump: LE].
[JumpBelow] -> [^self concretizeConditionalJump: CC]. "unsigned lower"
[JumpAboveOrEqual] -> [^self concretizeConditionalJump: CS]. "unsigned greater or equal"
[JumpAbove] -> [^self concretizeConditionalJump: HI].
[JumpBelowOrEqual] -> [^self concretizeConditionalJump: LS].
[JumpFPEqual] -> [^self concretizeFPConditionalJump: EQ].
[JumpFPNotEqual] -> [^self concretizeFPConditionalJump: NE].
[JumpFPLess] -> [^self concretizeFPConditionalJump: LT].
[JumpFPGreaterOrEqual] -> [^self concretizeFPConditionalJump: GE].
[JumpFPGreater] -> [^self concretizeFPConditionalJump: GT].
[JumpFPLessOrEqual] -> [^self concretizeFPConditionalJump: LE].
[JumpFPOrdered] -> [^self concretizeFPConditionalJump: VC].
[JumpFPUnordered] -> [^self concretizeFPConditionalJump: VS].
[RetN] -> [^self concretizeRetN].
[Stop] -> [^self concretizeStop].
"Arithmetic"
[AddCqR] -> [^self concretizeAddCqR].
[AddCwR] -> [^self concretizeDataOperationCwR: AddOpcode].
[AddRR] -> [^self concretizeDataOperationRR: AddOpcode].
[AddRdRd] -> [^self concretizeAddRdRd].
[AndCqR] -> [^self concretizeAndCqR].
[AndCqRR] -> [^self concretizeAndCqRR].
[AndCwR] -> [^self concretizeDataOperationCwR: AndOpcode].
[AndRR] -> [^self concretizeDataOperationRR: AndOpcode].
[CmpCqR] -> [^self concretizeDataOperationCqR: CmpOpcode].
[CmpCwR] -> [^self concretizeDataOperationCwR: CmpOpcode].
[CmpRR] -> [^self concretizeDataOperationRR: CmpOpcode].
[CmpRdRd] -> [^self concretizeCmpRdRd].
[DivRdRd] -> [^self concretizeDivRdRd].
[MulRdRd] -> [^self concretizeMulRdRd].
[OrCqR] -> [^self concretizeDataOperationCqR: OrOpcode].
[OrCwR] -> [^self concretizeDataOperationCwR: OrOpcode].
[OrRR] -> [^self concretizeDataOperationRR: OrOpcode].
[SubCqR] -> [^self concretizeSubCqR].
[SubCwR] -> [^self concretizeDataOperationCwR: SubOpcode].
[SubRR] -> [^self concretizeDataOperationRR: SubOpcode].
[SubRdRd] -> [^self concretizeSubRdRd].
[SqrtRd] -> [^self concretizeSqrtRd].
[TstCqR] -> [^self concretizeTstCqR].
[XorCqR] -> [^self concretizeDataOperationCqR: XorOpcode].
[XorCwR] -> [^self concretizeDataOperationCwR: XorOpcode].
[XorRR] -> [^self concretizeDataOperationRR: XorOpcode].
[NegateR] -> [^self concretizeNegateR].
[LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR].
[ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR].
[LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR].
[LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR].
[ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR].
[LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR].
[LogicalShiftRightRR] -> [^self concretizeLogicalShiftRightRR].
"Data Movement"
[MoveCqR] -> [^self concretizeMoveCqR].
[MoveCwR] -> [^self concretizeMoveCwR].
[MoveRR] -> [^self concretizeMoveRR].
[MoveAwR] -> [^self concretizeMoveAwR].
[MoveRAw] -> [^self concretizeMoveRAw].
[MoveMbrR] -> [^self concretizeMoveMbrR].
[MoveRMbr] -> [^self concretizeMoveRMbr].
[MoveM16rR] -> [^self concretizeMoveM16rR].
[MoveM64rRd] -> [^self concretizeMoveM64rRd].
[MoveMwrR] -> [^self concretizeMoveMwrR].
[MoveXbrRR] -> [^self concretizeMoveXbrRR].
[MoveRXbrR] -> [^self concretizeMoveRXbrR].
[MoveXwrRR] -> [^self concretizeMoveXwrRR].
[MoveRXwrR] -> [^self concretizeMoveRXwrR].
[MoveRMwr] -> [^self concretizeMoveRMwr].
[MoveRdM64r] -> [^self concretizeMoveRdM64r].
[PopR] -> [^self concretizePopR].
[PushR] -> [^self concretizePushR].
[PushCq] -> [^self concretizePushCq].
[PushCw] -> [^self concretizePushCw].
[PrefetchAw] -> [^self concretizePrefetchAw].
"Conversion"
[ConvertRRd] -> [^self concretizeConvertRRd]}!
Item was changed:
----- Method: CogARMCompiler>>genMulR:R: (in category 'abstract instructions') -----
genMulR: regSource R: regDest
+ "Use SMULL to produce a 64-bit result, explicitly in RISCTempReg,regDest.
+ By comparing RISCTempReg with regDest ASR 31(which effectively makes it 0 or -1) we know that the result being EQ means the hi reg and the top bit of the lo reg are the same - ie no overflow. The condition code can then be forced to oVerflow by use of MSR APSR_nzcvq, #1, lsl 28"
- "Use SMULL to produce a 64-bit result, implicitly in TempReg,RISCTempReg.
- Test the top word for 0 or 1 and set oVerflow if not equal. Move result in
- TempReg into regDest."
cogit
+ gen: SMULL operand: regSource operand: regDest; "result in RISCTempReg,regDest"
+ gen: CMPSMULL operand: RISCTempReg operand: regDest;
+ gen: MSR operand: 1!
- gen: SMULL operand: regSource operand: regDest; "result in TempReg,RISCTempReg"
- gen: AddCqR operand: 1 operand: RISCTempReg; "turn -1,0 into 0,1"
- gen: AddCqR operand: -1 operand: RISCTempReg; "turn 0,1 into not oVerflow"
- gen: MoveRR operand: TempReg operand: regDest!
Item was added:
+ ----- Method: CogARMCompiler>>msr: (in category 'encoding') -----
+ msr: flags
+ "Generate an MSR CPSR_f, #flags instruction.
+ Note that
+ a) CPSR_f is equivalent to APSR_nzcvq (ARM ARM DDI0406A p A8-209 & A2-14)
+ b) We only have business with the NZCV flags so the generated instruction shifts the flags value <<28 - which is a ROR 4"
+
+ ^16r1328F000
+ + (2 "rotate rights are in units of 2, remember" << 8)
+ + (flags bitAnd: 16rF) " to make sure we don't have silly values here"!
Item was added:
+ ----- Method: CogARMCompiler>>rewriteInlineCacheTag:at: (in category 'inline cacheing') -----
+ rewriteInlineCacheTag: cacheTag at: callSiteReturnAddress
+ "Rewrite an inline cache with a new tag. This variant is used
+ by the garbage collector."
+ self insert32BitOperand: cacheTag into4InstructionsPreceeding: callSiteReturnAddress -4!
More information about the Vm-dev
mailing list