[Vm-dev] VM Maker: VMMaker.oscog-eem.1129.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1129.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1129
Author: eem
Time: 29 March 2015, 12:09:02.727 am
UUID: b103538d-b36d-4c70-9600-57ee25a189aa
Ancestors: VMMaker.oscog-eem.1128

Add support for the VarBaseReg scheme to ARM
MoveMbrR & MoveRMbr sicne these are used for
accessing the primTraceLogIndex.

Add hasPCRelativeAddressing and for the ARM,
isAddressRelativeToPC:.  We can use this to refer
to the method without generating a map entry.

Mark the remaining relevant feature test methods in
CogAbstractInstruciton as <inline: true>.

=============== Diff against VMMaker.oscog-eem.1128 ===============

Item was changed:
  ----- Method: CogARMCompiler>>concretizeMoveMbrR (in category 'generate machine code - concretize') -----
  concretizeMoveMbrR
  	"Will get inlined into concretizeAt: switch."
  	"ldrb destReg, [srcReg, #immediate] or ldrb destReg, [srcReg, ConcreteIPReg]"
  	<inline: true>
  	| srcReg offset destReg instrOffset|
  	offset := operands at: 0.
  	srcReg := self concreteRegister: (operands at: 1).
  	destReg := self concreteRegister: (operands at: 2).
  	self is12BitValue: offset
  		ifTrue:
  			[ :u :immediate | 
  			self machineCodeAt: 0 "ldrb destReg, [srcReg, #immediate]"
  				put: (self ldrb: destReg rn: srcReg plus: u imm: immediate).
  			^machineCodeSize := 4]
  		ifFalse:
+ 			[(self isAddressRelativeToVarBase: offset)
+ 				ifTrue:
+ 					[self machineCodeAt: 0 put: (self ldr: ConcreteIPReg rn: ConcreteVarBaseReg plusImm: offset - cogit varBaseAddress).
+ 					 instrOffset := 4]
+ 				ifFalse:
+ 					[instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg].
+ 			 "ldrb destReg, [srcReg, ConcreteIPReg]"
+ 			 self machineCodeAt: instrOffset put: (self ldrb: destReg rn: srcReg rm: ConcreteIPReg).
+ 			 ^machineCodeSize := instrOffset + 4]!
- 			[instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg.
- 			"ldrb destReg, [srcReg, ConcreteIPReg]"
- 			self machineCodeAt: instrOffset put: (self ldrb: destReg rn: srcReg rm: ConcreteIPReg).
- 			^machineCodeSize := instrOffset + 4 ]!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeMoveRMbr (in category 'generate machine code - concretize') -----
  concretizeMoveRMbr
  	"Will get inlined into concretizeAt: switch."
  	<inline: true>
  	| srcReg offset baseReg instrOffset|
  	srcReg := self concreteRegister: (operands at: 0).
  	offset := operands at: 1.
  	baseReg := self concreteRegister: (operands at: 2).
  	self is12BitValue: offset
  		ifTrue:
  			[ :u :immediate | 
  			self machineCodeAt: 0 "strb 	srcReg, [baseReg, #immediate]"
  				put: (self strb: srcReg rn: baseReg plus: u imm: immediate).
  			^machineCodeSize := 4]
  		ifFalse:
+ 			[(self isAddressRelativeToVarBase: offset)
+ 				ifTrue:
+ 					[self machineCodeAt: 0 put: (self ldr: ConcreteIPReg rn: ConcreteVarBaseReg plusImm: offset - cogit varBaseAddress).
+ 					 instrOffset := 4]
+ 				ifFalse:
+ 					[instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg].
- 			[instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg.
  			"strb 	srcReg, [baseReg, ConcreteIPReg]"
  			self machineCodeAt: instrOffset put: (self strb: srcReg rn: baseReg rm: ConcreteIPReg).
  			^machineCodeSize := instrOffset + 4 ]!

Item was changed:
  ----- Method: CogARMCompiler>>hasDoublePrecisionFloatingPointSupport (in category 'testing') -----
  hasDoublePrecisionFloatingPointSupport
  	"might be true, but is for the forseeable future disabled"
+ 	<inline: true>
  	^false!

Item was added:
+ ----- Method: CogARMCompiler>>isAddressRelativeToPC: (in category 'testing') -----
+ isAddressRelativeToPC: pcAddress
+ 	"Support for addressing the method relative to the PC."
+ 	^pcAddress notNil
+ 	  and: [pcAddress <= address
+ 	  and: [address - pcAddress < (1 << 12)]]!

Item was changed:
  ----- Method: CogARMCompiler>>isAddressRelativeToVarBase: (in category 'testing') -----
+ isAddressRelativeToVarBase: varAddress
+ 	"Support for addressing variables off the dedicated VarBaseReg"
+ 	^varAddress notNil
+ 	  and: [varAddress >= cogit varBaseAddress
+ 	  and: [varAddress - cogit varBaseAddress < (1 << 12)]]!
- isAddressRelativeToVarBase: address
- 	^address notNil
- 	  and: [address >= cogit varBaseAddress
- 	  and: [address - cogit varBaseAddress < (1 << 12)]]!

Item was changed:
  ----- Method: CogARMCompiler>>isBigEndian (in category 'testing') -----
  isBigEndian
+ 	<inline: true>
  	^false!

Item was changed:
  ----- Method: CogAbstractInstruction>>hasDoublePrecisionFloatingPointSupport (in category 'testing') -----
  hasDoublePrecisionFloatingPointSupport
+ 	<inline: true>
  	^self subclassResponsibility!

Item was changed:
  ----- Method: CogAbstractInstruction>>hasLinkRegister (in category 'testing') -----
  hasLinkRegister
  	"Answer if the processor has a link register, i.e. if calls pass
  	 the return pc in a register instead of pushing it on a stack."
+ 	<inline: true>
  	^self subclassResponsibility!

Item was removed:
- ----- Method: CogAbstractInstruction>>hasPCDependentInstructions (in category 'testing') -----
- hasPCDependentInstructions
- 	"Answer whether the concrete machine code contains pc-dependent
- 	 instructions, such as the IA32/x86's short and long relative jumps
- 	 and the EMT64/x86-64's pc-relative addressing mode.  Such
- 	 instructions require an extra pass to generate them correctly."
- 	^false!

Item was changed:
  ----- Method: CogAbstractInstruction>>hasPCRegister (in category 'testing') -----
  hasPCRegister
  	"Answer if the processor has a generally addressable pc register, such as the ARM.
  	 On such processors we can execute jumping to pop top of stack by popping into
  	 the pc register.  Note that this is not a generic RISC feature.  The PowerPC does not
  	 allow one to pop into the pc for example.  So by default, answer false."
+ 	<inline: true>
  	^false!

Item was added:
+ ----- Method: CogAbstractInstruction>>hasPCRelativeAddressing (in category 'testing') -----
+ hasPCRelativeAddressing
+ 	"Answer if the processor has PC-relative addressing."
+ 	<inline: true>
+ 	^self subclassResponsibility!

Item was changed:
  ----- Method: CogAbstractInstruction>>isBigEndian (in category 'testing') -----
  isBigEndian
+ 	<inline: true>
  	^self subclassResponsibility!

Item was changed:
  ----- Method: CogIA32Compiler>>hasDoublePrecisionFloatingPointSupport (in category 'testing') -----
  hasDoublePrecisionFloatingPointSupport
  	"We can generate dpfp support if the processor has SSE2 instructions."
+ 	<inline: true>
  	^self hasSSE2Instructions!

Item was removed:
- ----- Method: CogIA32Compiler>>hasPCDependentInstructions (in category 'testing') -----
- hasPCDependentInstructions
- 	"Answer whether the concrete machine code contains pc-dependent
- 	 instructions, such as the IA32/x86's short and long relative jumps
- 	 and the EMT64/x86-64's pc-relative addressing mode.  Such
- 	 instructions require an extra pass to generate them correctly."
- 	^true!

Item was changed:
  ----- Method: CogIA32Compiler>>isBigEndian (in category 'testing') -----
  isBigEndian
+ 	<inline: true>
  	^false!