[Vm-dev] VM Maker: Cog-eem.442.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of Cog to project VM Maker:
http://source.squeak.org/VMMaker/Cog-eem.442.mcz

==================== Summary ====================

Name: Cog-eem.442
Author: eem
Time: 1 October 2021, 2:38:40.891132 pm
UUID: 91994ee1-d997-4095-9167-2d1b2d6254a0
Ancestors: Cog-eem.441

Sionara fromIEEE64BitWord:; Kon'nichiwa fromIEEE64Bit:

=============== Diff against Cog-eem.441 ===============

Item was changed:
  ----- Method: GdbARMAlien>>handleBasicDoubleArithmetic:at: (in category 'floating-point emulation') -----
  handleBasicDoubleArithmetic: instr at: pc
  	"Emulate a basic math - add/sub/mul/div -  VFP instruction."
  	| rn rd rm vn vm |
  	rn := instr >> 16 bitAnd: 15.
  	rd := instr >> 12 bitAnd: 15.
  	rm := instr bitAnd: 15.
+ 	vn := Float fromIEEE64Bit: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs"
+ 	vm := Float fromIEEE64Bit: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs"
- 	vn := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs"
- 	vm := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs"
  
  	"simplest to match the entire instruction pattern rather than mess around shifting and masking and merging"
  	(instr  bitAnd: 16rFF00FF0)
  		caseOf: {
  		[16rE200B00 "FMULD"]	->
  			[| r |
  			 r := vn * vm.
  			 self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].
  		[16rE300B00 "FADDD"]	->
  			[| r |
  			 r := vn + vm.
  			 self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].
  		[16rE300B40 "FSUBD"]	->
  			[| r |
  			 r := vn - vm.
  			 self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].
  		[16rE800B00"FDIVD"]	->
  			[| r |
  			 r := vn / vm.
  			 self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].}
  		otherwise: [self reportPrimitiveFailure].
  	self pc: pc + 4!

Item was changed:
  ----- Method: GdbARMAlien>>handleExtendedDoubleArithmetic:at: (in category 'floating-point emulation') -----
  handleExtendedDoubleArithmetic: instr at: pc
  	"Emulate an extended math - cmp/sqrt/sitod -  VFP instruction."
  	| rn rd rm vn vm vd |
  	rn := instr >> 16 bitAnd: 15.
  	rd := instr >> 12 bitAnd: 15.
  	rm := instr bitAnd: 15.
+ 	vn := Float fromIEEE64Bit: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs"
+ 	vm := Float fromIEEE64Bit: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs"
- 	vn := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs"
- 	vm := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs"
  
  	"simplest to match the entire instruction pattern rather than mess around shifting and masking and merging"
  	(instr  bitAnd: 16rFF00FF0)
  		caseOf: {
  		[16rEB80B80 "FCMPD"]	->
  			["read rd, compare with rm (ignore rn) and set FPSCR NZCV flags. Sigh"
+ 				vd := Float fromIEEE64Bit: (self perform: (self registerStateGetters at: rd + 18)).
- 				vd := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rd + 18)).
  				self break].
  		[16rEB80BC0 "FSITOD"]	->
  			[| r |
  			 r := vm asFloat.
  			 self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].
  		[16rEB10BC0 "FSQRTD"]	->
  			[| r |
  			 r := vm sqrt.
  			 self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].
  		}
  		otherwise: [self reportPrimitiveFailure].
  	self pc: pc + 4!

Item was changed:
  ----- Method: GdbARMAlien>>handleOneRegTransferDoubleArithmetic:at: (in category 'floating-point emulation') -----
  handleOneRegTransferDoubleArithmetic: instr at: pc
  	"Emulate a one-register transfer VFP instruction."
  	| rn rd rm vn vm |
  	rn := instr >> 16 bitAnd: 15.
  	rd := instr >> 12 bitAnd: 15.
  	rm := instr bitAnd: 15.
+ 	vn := Float fromIEEE64Bit: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs"
+ 	vm := Float fromIEEE64Bit: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs"
- 	vn := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs"
- 	vm := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs"
  	(instr >> 18 bitAnd: 31)
  		caseOf: {
  		[8 "FMULD"]	->
  			[| r |
  			 r := vn * vm.
  			 self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord].
  		[12"FADDD/FSUBD"]	->
  			[self shouldBeImplemented].
  		[32"FDIVD"]	->
  			[self shouldBeImplemented].
  		[45"FCMPD"]	->
  			[self shouldBeImplemented]. }
  		otherwise: [self reportPrimitiveFailure].
  	self pc: pc + 4!