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22 discussions

Intel Readies Research Papers On Programmable Multicore Architectures
by Klaus D. Witzel 16 Aug '07

16 Aug '07

Hi list, Intel's blogging that they will talk about interesting developments: multiple independent threads of execution of tasks, a cache quality of service, and more. You can find a news report at - http://news.yahoo.com/s/cmp/20070815/tc_cmp/201800159 /Klaus

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Re: [Hardware] FPGAs
by Herbert König 13 Aug '07

13 Aug '07

Hello Jecel, thank you for the overview. JAJ> The Erasable PROM (EPROM) allowed you to reuse the same device since you JAJ> could expose it to ultraviolet light to reset it to the blank state. JAJ> These devices were larger and slower than PROMs. The only example I know JAJ> of an EPROM being use as logic was for the video signals generator on my JAJ> own Merlin 2 design. I can add two examples: -at Vuko we used an EPROM as a character generator too. The EPROM was driving DA converters to paint the characters on a CRT which otherwise was a digital oscilloscope. I thought of this as a common design for the earlier digital oscilloscopes. Was in about 1982. They sold some thousand units. More uncommon I used an EPROM as the logic control unit for a four channel digital oscilloscope. Every logical expression was written in FORTH like "trigger_occurred channel3 and add_ch3_and_ch4 and ...." Then overnight a counter ran over all adresses of the EPROM, the counter was decomposed into the logical functions which where all run and the result was put into the EPROM at the address of the counter. It was about 1985 and Vuko also sold a few thousand of these. FORTH was nice for this, computer was a 6502 32K ram. Cheers Herbert mailto:herbertkoenig@gmx.net

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FPGAs
by Jecel Assumpcao Jr 11 Aug '07

11 Aug '07

I was asked about FPGAs and materials about them. Perhaps my reply will be of interest to other people on this list, so here is what I wrote: I happen to be writting a 20 page report on "reconfigurable computing" which includes some material that might be interesting, but sadly it is in Portuguese. I did a search for "fpga tutorial" but was not happy with the results I saw. This site has some interesting stuff but is probably not the first place you should look: http://www.fpga4fun.com/ Here is a very short version of the introduction I am writing: There are two types of logic circuits - combinational ones which depend only on their current inputs and sequential ones which depend on their current and past inputs. The latter are circuits which include memory. Normally combinational circuits are implemented by connecting together a bunch of simple logic gates, like AND, OR and NOT. But an alternative is to use a memory circuit, ironically enough. You simple connect the inputs to the address pins and use the data pins as the outputs. For example, imagine you have a combinational circuit which takes two inputs of two bits each (A1, A0, B1 and B0) and outputs three bits representing their sum. You can do this with about four AND gates and four Exclusive-OR gates but a memory chip programmed like this would also work: #(0 1 2 3 1 2 3 4 2 3 4 5 3 4 5 6) at: ((a1 * 8) + (a0 * 4) + (b1 * 2) + b0) So one way to implement logic circuits would be to use Read-Only Memory chips (ROMs), but these are "programmed" at the factory by designing a special layer to be used when manufacturing. That takes many weeks and is very expensive. An alternative is to use Programmable ROMs (PROMs) which can be inserted into a low cost device and have their contents changed by blowing out tiny fuses. There is no way to "unblow" a fuse so if you make a mistake you have to throw the device away and use another one. PROMs were used on the Xerox Alto computer and the disk controller for the Apple II, among many other designs of the 1970s. The Erasable PROM (EPROM) allowed you to reuse the same device since you could expose it to ultraviolet light to reset it to the blank state. These devices were larger and slower than PROMs. The only example I know of an EPROM being use as logic was for the video signals generator on my own Merlin 2 design. If you look at any of these memory devices, you will see a decoder circuit which takes the address and outputs a separate line of each possible input combinations. If you have 9 address lines on a small PROM, for example, then the decoder will activate one of 512 lines. These lines are connected to the data lines via transistors and fuses. The decoder part is equivalent to 512 AND circuits of 9 inputs each while the second section is equivalent to 8 (if that is how many data outputs this PROM has) OR circuits with 512 inputs each where some (actually, most) of these inputs can be disabled by the programming device. A very reasonable alternative is to have a smaller number of ANDs and let their inputs be programmable as well. This is known as a Programmable Logic Array (PLA) and like a ROM there is a version "programmed" in the factory (often included as part of a larger design) and versions which can be programemd "in the field" using a low cost device. Yet another variation has programmable inputs for the ANDs but fixed connections for the ORs and these Programmable Array Logic (PAL) circuits became far more popular - eight of them were used in the original Mac, for example. An entirely different kind of user defined devices are the Gate Arrays (GA, or Uncommited Logic Array, ULA, as it was known in the UK). Like ROMs they have several layers which are exactly the same for all clients and an additional layer which is defined for each design. This makes it far cheaper than a chip where all layers are unique to a single design. Unlike the ROM, however, the fixed layers of the GA have a large number of simple gates. While with a ROM, PROM or even PAL you had essentially a single combinational block per integrated circuit, with the GA you could have many such blocks and connect them together. You could even implement memory circuits and have sequential designs as well. So we get to the Field Programmable Gate Array (FPGA) invented by Xilinx in 1984. Instead of using a custom layer to connect the blocks like in the GA, the FPGA had a switching circuit similar to the old telephone system where any block could be connected to any other block. And these blocks were 16 by 1 memory circuits (known as Look Up Tables, LUTs), which allowed any of 64 thousand possible logic functions of 4 inputs to be programmed. In addition, each block could have an optional flip-flop (1 bit memory circuit) connected to its output for sequential designs. Meanwhile, the PALs grew and grew and become known as Complex Programmable Devices (CPLDs). These normally keep their programming (using Flash memory technology these days) when the power is out and are used for the smaller designs while FPGAs are used for large designs. Some FPGAs also keep their programming but most of them have to be reprogrammed every time you turn them one. The first major change in FPGAs was allowing the LUT to be used as an actual 16 by 1 memory in a design, which is a 16 fold increase in density compared to using just the flip-flops. With this change it started to become practical to put very small processor designs into a FPGA. By the end of 1990s actual memory blocks started to be added to FPGAs and then multiplier circuits. This made them particularly useful for digital signal processing (DSP) applications and made them even nicer for processor designs. As FPGAs got larger and larger we went from needing many FPGAs to implement a single processor to being able to put many processors into a single FPGA. Around the end of 2000 there was a dramatic drop in prices for low end FPGAs due to intense competition between Xilinx and Altera and they made FPGAs practical for end products rather than just for prototypes. I hope this helps give you a better idea of where these things came from. Perhaps I should send this to the list. Cheers, -- Jecel

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Re: [Hardware] language neutral processors
by Hans-Martin Mosner 02 Aug '07

02 Aug '07

Jecel Assumpcao Jr schrieb: > I am back from a nice vacation (my first since 1982...) and see that you > have all been waiting patiently for me to return before starting any > interesting discussions ;-) > Ok, now that you're back, I can finally ask the questions which have puzzled me ever since :-) When implementing Smalltalk hardware, what kind of object memory design would you prefer: - object table vs. direct pointer - ref counting vs. generation scavenging cs -whatever- - page-based virtual memory vs. object-based VM vs. none at all - in-band tags vs. out-of-band tags Let me explain the last one. Smalltalk Implementations have typically had in-bad tags, i.e. the tags have only meaning in a word which is known to be an oop. The Burroughs machines had out-of-band tags, that is, every memory word had an additional tag. That way, you could even know whether a memory word contained uninterpreted bytes, a float value, or an "oop" (descriptor). > One interesting side effect of this trip is that I now have a new FPGA > development kit - the ML401 from Xilinx. > Just out of curiosity: how much does one pay for such a kit? I don't know whether my wife would approve of a major investment into something of little perceived value :-) Cheers, Hans-Martin

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Re: [Hardware] language neutral processors
by David T. Lewis 02 Aug '07

02 Aug '07

On Tue, Jul 31, 2007 at 06:46:24PM -0300, Jecel Assumpcao Jr wrote: > I am back from a nice vacation (my first since 1982...) and see that you > have all been waiting patiently for me to return before starting any > interesting discussions ;-) Well, I don't have anything worthwhile to add, but I'm certainly interested in your discussions. Hope you don't mind folks just lurking and enjoying the read :) Dave

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language neutral processors
by Jecel Assumpcao Jr 31 Jul '07

31 Jul '07

I am back from a nice vacation (my first since 1982...) and see that you have all been waiting patiently for me to return before starting any interesting discussions ;-) One interesting side effect of this trip is that I now have a new FPGA development kit - the ML401 from Xilinx. It has some limitations (like the 50MHz video and soldered 64MB of SDRAM) compared to newer kits but makes a far nicer Smalltalk computer than what I had been using up to now. The FPGA is about twice as large as what I plan to use in the Merlin 6 board I am designing and the Virtex 4 FPGAs allow designs to run at twice the clock of what the low end Spartan 3 can deliver. For the next couple of months I will focus on this board so I will return the Spartan 3 Starter Kit that I had borrowed the my university. Besides a FAQ I should probably set up a "Frequent Suggestions" page for my project so people don't waste their time giving my advice I have heard many times before. Certainly the number one on that page would be "some people have already tried to make a language specific computer... using Lisp or something like that... and it was a horrible failure, so you should do a language neutral processor instead or just use what is commercially available". The problem with this advice is that it assumes that a "language neutral processor" exists and is a good thing. If we define that to mean "a processor so primitive and horrible that no high level language is practical on it so you limit yourself to assembly" then I have seen a few. Other than that, I have never seen such a beast since the 8 bit microprocessor days (or early mainframes or early minis - each generation recapitulated what the previous one had done so it would be redudant to tell the same story three times). The 8086 was a mix of features to support the assembly programmer and to deal with Pascal. The segments, the frame pointer and similar stuff made it trivial to implement the UCSD virtual machine on it or have Turbo Pascal generate code for it. Meanwhile, Intel's 32 bit iAPX432 started life as a PL/I+objects machine and was converted into an Ada+objects processor when that language started to make headlines (even before it was defined!) and some of what was learned in that design was applied to the 80286 (which was even renamed iAPX286 to reflect this). Unfortunately for Intel the C/Unix virus was taking over the market and their pride and joy couldn't run C. Oh, it could run something very much like C with near and far pointers and other horrors or it could run real C if you contented yourself with 128KB or less, but you couldn't just take some application running on the VAX and recompile it for the 286. Motorola had done something halfway between a PDP-11 and a VAX in its 68000 processor. So even though it put a lot of effort into Pascal (see LINK and UNLINK instructions, for example) it naturally did well with the "portable PDP-11 assembly" that is C. But they got scared with all the Ada/Modula-2 noise Intel and National were making and made the 68020 a Modula-2 machine to compete with National's 32032. Except that the market was interested in C, so Motorola actually removed the extra features from the 68030. And nobody noticed :-) Intel decided that "if you can't beat them, join them" with its 386 processor. With some very well thought out hacks it was a hybrid capable of dealing with C and Unix as well as its competitors while at the same time running all the old code, including what really mattered through the new "virtual 8086" mode. Meanwhile, some university people figured out that these C and assembly processors were more expensive and slower than what a pure C processor would be and soon their RISCs were putting commercial cpus to shame. Intel split its 486 into a pure C part and an extras part in order to keep up, and followed NextGen's (bought by AMD) lead into the core RISC plus translation style with its Pentium Pro (also released as the Pentium II, Pentium II and Pentium M not to mention Celerons and stuff like that). The Pascal and iAPX432 stuff is still in our x86 processors today (as is the BCD math from the 8080 days) but the designers don't put any effort on them and so it is far faster to do the same thing with lots of C instructions instead. Now that we have a world where every OS is Unix (yes, I even count Windows NT in that crowd), every language is C or a front end for it and every PC has a x86 processor it is no wonder that people can't imagine alternatives, nor even imagine why you might want to imagine alternatives. I have heard many times in the past couple of years that "C is the actually language of the machine, so even if you do stuff in other languages it has to be translated into C or you need short fragments of C code". I normally point out "just try clearing the cache from C" but in a way they are right. But I don't agree that this is how things have to be. Oh, and about those Lisp Machines: they died off but so did the VAX which were as "language neutral" as anything we have today. -- Jecel

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Compiler optimizations on OO hardware
by Matthew Fulmer 03 Jul '07

03 Jul '07

My professor showed me this paper on compiler optimizations that can be applied to make asynchronous message passing fast on current multicore processors: http://veda.eas.asu.edu/~vrudhula/OO-multiproc.pdf I wonder exactly what hardware features could make this even faster. My first guess is tagging; by tagging I mean that some objects could be stored un-boxed, and so preventing an additional memory lookup to determine the class of the object. Tagging seems to mean different things to different people; what I mean is that every word would have a few extra bits that the CPU would generally ignore, and so were free to be used by the programmer any way they want. One use would be to use the extra bits to store some type information; for example, one could use one code to represent pointers, another for integers, another for future objects, etc. Some classes could be fully represented with just a one-word pointer, like Smalltalk does with SmallIntegers. What other ways could this be better? -- Matthew Fulmer -- http://mtfulmer.wordpress.com/ Help improve Squeak Documentation: http://wiki.squeak.org/squeak/808

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Re: [Box-Admins] Missing reply-to header from hardware@lists.squeakfoundation.org
by Klaus D. Witzel 11 Jun '07

11 Jun '07

On Mon, 11 Jun 2007 22:10:30 +0200, Marcus Denker wrote: > > On 11.06.2007, at 20:15, Ken Causey wrote: > >> I believe that's due to a configuration choice that Matthew made >> for the mailing list. >> > > The standard for new lists is that they have no reply-to-list, but > this can be easily > changes... I could do it, if needed/wanted. Yes please. And thank you. Cheers Klaus > Marcus > >> Ken >> >> On Mon, 2007-06-11 at 19:16 +0200, Klaus D. Witzel wrote: >>> Hi box admins, >>> >>> the recent posting from hardware(a)lists.squeakfoundation.org >>> arrived here >>> without reply-to header (all other lists from >>> lists.squeakfoundation.org >>> which I'm subscribed to seem to transmit that header). >>> >>> So when doing a reply, the original sender (the poster's email >>> address) is >>> only available :( >>> >>> Thanx in advance. >>> >>> Cheers >>> Klaus >>> >

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Missing reply-to header from hardware@lists.squeakfoundation.org
by Klaus D. Witzel 11 Jun '07

11 Jun '07

Hi box admins, the recent posting from hardware(a)lists.squeakfoundation.org arrived here without reply-to header (all other lists from lists.squeakfoundation.org which I'm subscribed to seem to transmit that header). So when doing a reply, the original sender (the poster's email address) is only available :( Thanx in advance. Cheers Klaus

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FPGA Pointers and Device Poll
by Travis Kay 11 Jun '07

11 Jun '07

Hello All, I've recently bought a Spartan 3E Starter Kit and I'm wondering what other devices people are using. I'm new to hardware design and any pointers to material would be appreciated. I've found a few online resources for soft cores and stack machines etc... However, I know this list is for squeak and I would like to do some research in this area. Regards, Travis

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