Vm-dev December 2015

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33 participants
207 discussions

VM Maker: Cog-eem.300.mcz
by commits＠source.squeak.org 02 Dec '15

02 Dec '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.300.mcz ==================== Summary ==================== Name: Cog-eem.300 Author: eem Time: 1 December 2015, 11:15:12.912 pm UUID: 4ea0fa76-d948-4b34-9a26-c1ba7cc5bba1 Ancestors: Cog-rmacnak.299 Add some safety in case of disassembler failure. =============== Diff against Cog-rmacnak.299 =============== Item was changed: ----- Method: CogProcessorAlien>>disassembleNextInstructionIn:for: (in category 'disassembly') ----- disassembleNextInstructionIn: memory for: aSymbolManager "<Cogit|nil>" | string | + self pc >= memory size ifTrue: + [string := aSymbolManager ifNotNil: - string := self pc < memory size - ifTrue: [(self primitiveDisassembleAt: self pc inMemory: memory) last.] - ifFalse: [string := aSymbolManager ifNotNil: [aSymbolManager lookupAddress: self pc]. ^self pc hex, ' : ', (string ifNil: ['Invalid address'])]. + string := self primitiveDisassembleAt: self pc inMemory: memory. + string isString ifFalse: + [^'ERROR: ', (string printString contractTo: 40)]. ^aSymbolManager ifNil: [string] ifNotNil: [self decorateDisassembly: string for: aSymbolManager fromAddress: self pc]!

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Re: [Vm-dev] VM Maker: VMMaker.oscog-rmacnak.1537.mcz
by tim Rowledge 01 Dec '15

01 Dec '15

> On 01-12-2015, at 4:32 AM, commits(a)source.squeak.org wrote: > > > Ryan Macnak uploaded a new version of VMMaker to project VM Maker: > http://source.squeak.org/VMMaker/VMMaker.oscog-rmacnak.1537.mcz > > ==================== Summary ==================== > > Name: VMMaker.oscog-rmacnak.1537 > Author: rmacnak > Time: 30 November 2015, 8:32:24.833 pm > UUID: 090316cc-9bb5-4d24-9597-c464661d9b48 > Ancestors: VMMaker.oscog-eem.1536 > > MIPS: Get simulation past the first display update. Congratulations That’s always a special moment. tim -- tim Rowledge; tim(a)rowledge.org; http://www.rowledge.org/tim Strange OpCodes: DO: Deadstart Operator

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Compilation on GCC 5.1.1
by Pavel Krivanek 01 Dec '15

01 Dec '15

Hi, I asked Jaroslav Škarvada from Red Hat to shortly look at VM compilation problems on GCC 5 (5.1.1) and he sent me the patch [1]. We have declaration: static sqInt compileAbstractInstructionsFromthrough(sqInt start, sqInt end) NoDbgRegParms; but the definition is: static sqInt compileAbstractInstructionsFromthrough(sqInt start, sqInt end) { They must be the same so we need to fix the generator. It is debugging code so the next add-hoc option is to simply set -DPRODUCTION=1 [1] http://fpaste.org/296294/44898789/ Cheers, -- Pavel

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VM Maker: VMMaker.oscog-rmacnak.1537.mcz
by commits＠source.squeak.org 01 Dec '15

01 Dec '15

Ryan Macnak uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-rmacnak.1537.mcz ==================== Summary ==================== Name: VMMaker.oscog-rmacnak.1537 Author: rmacnak Time: 30 November 2015, 8:32:24.833 pm UUID: 090316cc-9bb5-4d24-9597-c464661d9b48 Ancestors: VMMaker.oscog-eem.1536 MIPS: Get simulation past the first display update. Remove Jump[No]Overflow in noteFollowingConditionalBranch: as a different check is needed for add/sub and mul. Use the right destination for MulRR. Rename locals in concretization of binops to help clarify the pattern. Add the short-immediate variants of the binops. Disable disassembly prints on code patching. =============== Diff against VMMaker.oscog-eem.1536 =============== Item was changed: ----- Method: CogMIPSELCompiler class>>initialize (in category 'class initialization') ----- initialize "CogRTLOpcodes initialize. CogMIPSELCompiler initialize" super initialize. ConcreteVarBaseReg := S6. Cmp := T0. Overflow := T0. OverflowTemp1 := T1. OverflowTemp2 := T2. "Can't use AT, Cmp or Overflow because we may need to preserve them for sequences like CmpCwR JumpZero JumpBelow" + BranchTemp := T3. - BranchTemp := T1. "OABI position independent code expects T9 to have its entry point on entry?" self flag: #OABI. TargetReg := T9. "Specific instructions" self initializeSpecificOpcodes: #( MulRR DivRR MoveLowR MoveHighR AddCheckOverflowCqR AddCheckOverflowRR MulCheckOverflowRR SubCheckOverflowCqR SubCheckOverflowRR BrEqualRR BrNotEqualRR BrUnsignedLessRR BrUnsignedLessEqualRR BrUnsignedGreaterRR BrUnsignedGreaterEqualRR BrSignedLessRR BrSignedLessEqualRR BrSignedGreaterRR BrSignedGreaterEqualRR BrLongEqualRR BrLongNotEqualRR) in: thisContext method ! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAddCheckOverflowCqR (in category 'generate machine code - concretize') ----- concretizeAddCheckOverflowCqR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). - | value reg | - value := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + "Save original LHS" + self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: leftReg R: ZR). - self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: reg R: ZR). "The actual addition" + self machineCodeAt: 12 put: (self adduR: destReg R: leftReg R: AT). - self machineCodeAt: 12 put: (self adduR: reg R: reg R: AT). "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS." + self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: destReg R: AT). - self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: reg R: AT). "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS." + self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1). - self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: reg R: OverflowTemp1). "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow." self machineCodeAt: 24 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2). ^machineCodeSize := 28! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAddCheckOverflowRR (in category 'generate machine code - concretize') ----- concretizeAddCheckOverflowRR + | destReg leftReg rightReg | + rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). - | leftReg rightReg | - leftReg := self concreteRegister: (operands at: 0). - rightReg := self concreteRegister: (operands at: 1). + "Save original LHS" + self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: leftReg R: ZR). - "Save original RHS" - self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: rightReg R: ZR). "The actual addition" + self machineCodeAt: 4 put: (self adduR: destReg R: leftReg R: rightReg). - self machineCodeAt: 4 put: (self adduR: rightReg R: leftReg R: rightReg). "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS." + self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: destReg R: rightReg). - self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: rightReg R: leftReg). "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS." + self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1). - self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: rightReg R: OverflowTemp1). "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow." self machineCodeAt: 16 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2). ^machineCodeSize := 20! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAddCqR (in category 'generate machine code - concretize') ----- concretizeAddCqR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + + (rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAddCwR]. + + self machineCodeAt: 0 put: (self addiuR: destReg R: leftReg C: rightImm). + ^machineCodeSize := 4! - ^self concretizeAddCwR! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAddCwR (in category 'generate machine code - concretize') ----- concretizeAddCwR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + self machineCodeAt: 8 put: (self adduR: destReg R: leftReg R: AT). - | val reg | - val := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: val)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: val)). - self machineCodeAt: 8 put: (self adduR: reg R: reg R: AT). ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAddRR (in category 'generate machine code - concretize') ----- concretizeAddRR + | destReg leftReg rightReg | + rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self adduR: destReg R: leftReg R: rightReg). - | leftReg rightReg | - leftReg := self concreteRegister: (operands at: 0). - rightReg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self adduR: rightReg R: leftReg R: rightReg). ^machineCodeSize := 4! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAndCqR (in category 'generate machine code - concretize') ----- concretizeAndCqR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + + (rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAndCwR]. + + self machineCodeAt: 0 put: (self andiR: destReg R: leftReg C: rightImm). + ^machineCodeSize := 4! - ^self concretizeAndCwR! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAndCwR (in category 'generate machine code - concretize') ----- concretizeAndCwR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + self machineCodeAt: 8 put: (self andR: destReg R: leftReg R: AT). - | value reg | - value := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)). - self machineCodeAt: 8 put: (self andR: reg R: reg R: AT). ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeAndRR (in category 'generate machine code - concretize') ----- concretizeAndRR + | destReg leftReg rightReg | + rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self andR: destReg R: leftReg R: rightReg). - | leftReg rightReg | - leftReg := self concreteRegister: (operands at: 0). - rightReg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self andR: rightReg R: leftReg R: rightReg). ^machineCodeSize := 4! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrSignedGreaterEqualRR (in category 'generate machine code - concretize') ----- concretizeBrSignedGreaterEqualRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg). self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrSignedGreaterRR (in category 'generate machine code - concretize') ----- concretizeBrSignedGreaterRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg). self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrSignedLessEqualRR (in category 'generate machine code - concretize') ----- concretizeBrSignedLessEqualRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg). self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrSignedLessRR (in category 'generate machine code - concretize') ----- concretizeBrSignedLessRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg). self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedGreaterEqualRR (in category 'generate machine code - concretize') ----- concretizeBrUnsignedGreaterEqualRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg). self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedGreaterRR (in category 'generate machine code - concretize') ----- concretizeBrUnsignedGreaterRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg). self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedLessEqualRR (in category 'generate machine code - concretize') ----- concretizeBrUnsignedLessEqualRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg). self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedLessRR (in category 'generate machine code - concretize') ----- concretizeBrUnsignedLessRR | offset leftReg rightReg | offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot" leftReg := self concreteRegister: (operands at: 1). rightReg := self concreteRegister: (operands at: 2). + self assert: leftReg ~= BranchTemp. + self assert: rightReg ~= BranchTemp. self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg). self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset). self machineCodeAt: 8 put: (self nop). "Delay slot" ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeJumpNoOverflow (in category 'generate machine code - concretize') ----- concretizeJumpNoOverflow + self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:" + ^0! - | offset | - offset := self computeJumpTargetOffsetPlus: 4. - self flag: #BranchRange. - self machineCodeAt: 0 put: (self bgezR: Overflow offset: offset). - self machineCodeAt: 4 put: self nop. "Delay slot" - ^machineCodeSize := 8! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeJumpOverflow (in category 'generate machine code - concretize') ----- concretizeJumpOverflow + self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:" + ^0! - | offset | - offset := self computeJumpTargetOffsetPlus: 4. - self flag: #BranchRange. - self machineCodeAt: 0 put: (self bltzR: Overflow offset: offset). - self machineCodeAt: 4 put: self nop. "Delay slot" - ^machineCodeSize := 8! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeMulCheckOverflowRR (in category 'generate machine code - concretize') ----- concretizeMulCheckOverflowRR + | destReg leftReg rightReg | + rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). - | leftReg rightReg | - leftReg := self concreteRegister: (operands at: 0). - rightReg := self concreteRegister: (operands at: 1). "Also destReg." "Overflow occured if the sign bit of the low part is different from the high part." self machineCodeAt: 0 put: (self multR: leftReg R: rightReg). + self machineCodeAt: 4 put: (self mfloR: destReg). + self machineCodeAt: 8 put: (self sraR: OverflowTemp1 R: destReg C: 31). - self machineCodeAt: 4 put: (self mfloR: rightReg). - self machineCodeAt: 8 put: (self sraR: OverflowTemp1 R: rightReg C: 31). self machineCodeAt: 12 put: (self mfhiR: OverflowTemp2). + ^machineCodeSize := 16! - "Overflow contains 0 on overflow, non-zero otherwise." - self machineCodeAt: 16 put: (self subuR: Overflow R: OverflowTemp1 R: OverflowTemp2). - ^machineCodeSize := 20! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeOrCqR (in category 'generate machine code - concretize') ----- concretizeOrCqR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + + (rightImm between: 0 and: 16rFFFF) ifFalse: [^self concretizeOrCwR]. + + self machineCodeAt: 0 put: (self oriR: destReg R: leftReg C: rightImm). + ^machineCodeSize := 4! - ^self concretizeOrCwR! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeOrCwR (in category 'generate machine code - concretize') ----- concretizeOrCwR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + self machineCodeAt: 8 put: (self orR: destReg R: leftReg R: AT). - | value reg | - value := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)). - self machineCodeAt: 8 put: (self orR: reg R: reg R: AT). ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeOrRR (in category 'generate machine code - concretize') ----- concretizeOrRR + | destReg leftReg rightReg | + rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self orR: destReg R: leftReg R: rightReg). - | leftReg rightReg | - leftReg := self concreteRegister: (operands at: 0). - rightReg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self orR: rightReg R: leftReg R: rightReg). ^machineCodeSize := 4! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeSubCheckOverflowCqR (in category 'generate machine code - concretize') ----- concretizeSubCheckOverflowCqR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). - | value reg | - value := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + "Save original LHS" + self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: leftReg R: ZR). - self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: reg R: ZR). "The actual subtraction" + self machineCodeAt: 12 put: (self subuR: destReg R: leftReg R: AT). - self machineCodeAt: 12 put: (self subuR: reg R: reg R: AT). "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS." + self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: destReg R: AT). - self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: reg R: AT). "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS." + self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1). - self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: reg R: OverflowTemp1). "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow." self machineCodeAt: 24 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2). ^machineCodeSize := 28! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeSubCheckOverflowRR (in category 'generate machine code - concretize') ----- concretizeSubCheckOverflowRR + | destReg leftReg rightReg | + rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). - | leftReg rightReg | - leftReg := self concreteRegister: (operands at: 0). - rightReg := self concreteRegister: (operands at: 1). + "Save original LHS" + self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: leftReg R: ZR). - "Save original RHS" - self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: rightReg R: ZR). "The actual subtraction" + self machineCodeAt: 4 put: (self subuR: destReg R: leftReg R: rightReg). - self machineCodeAt: 4 put: (self subuR: rightReg R: leftReg R: rightReg). "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS." + self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: destReg R: rightReg). - self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: rightReg R: leftReg). "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS." + self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1). - self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: rightReg R: OverflowTemp1). "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow." self machineCodeAt: 16 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2). ^machineCodeSize := 20! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeSubCqR (in category 'generate machine code - concretize') ----- concretizeSubCqR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + + (rightImm negated between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeSubCwR]. + + self machineCodeAt: 0 put: (self addiuR: destReg R: leftReg C: rightImm negated). + ^machineCodeSize := 4! - ^self concretizeSubCwR! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeSubCwR (in category 'generate machine code - concretize') ----- concretizeSubCwR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + self machineCodeAt: 8 put: (self subuR: destReg R: leftReg R: AT). - | value reg | - value := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)). - self machineCodeAt: 8 put: (self subuR: reg R: reg R: AT). ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeSubRR (in category 'generate machine code - concretize') ----- concretizeSubRR + | destReg leftReg rightReg | - | leftReg rightReg | rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self subuR: destReg R: leftReg R: rightReg). - leftReg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self subuR: leftReg R: leftReg R: rightReg). ^machineCodeSize := 4! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeTstCqR (in category 'generate machine code - concretize') ----- concretizeTstCqR + | leftReg rightImm | + rightImm := operands at: 0. + leftReg := self concreteRegister: (operands at: 1). + + (rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeTstCwR]. + + self machineCodeAt: 0 put: (self andiR: Cmp R: leftReg C: rightImm). + ^machineCodeSize := 4! - ^self concretizeTstCwR! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeTstCwR (in category 'generate machine code - concretize') ----- concretizeTstCwR + | leftReg rightImm | + rightImm := operands at: 0. + leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + self machineCodeAt: 8 put: (self andR: Cmp R: leftReg R: AT). - | val reg | - val := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: val)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: val)). - self machineCodeAt: 8 put: (self andR: Cmp R: reg R: AT). ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeXorCwR (in category 'generate machine code - concretize') ----- concretizeXorCwR + | destReg leftReg rightImm | + rightImm := operands at: 0. + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)). + self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)). + self machineCodeAt: 8 put: (self xorR: destReg R: leftReg R: AT). - | val reg | - val := operands at: 0. - reg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: val)). - self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: val)). - self machineCodeAt: 8 put: (self xorR: reg R: reg R: AT). ^machineCodeSize := 12! Item was changed: ----- Method: CogMIPSELCompiler>>concretizeXorRR (in category 'generate machine code - concretize') ----- concretizeXorRR + | destReg leftReg rightReg | + rightReg := self concreteRegister: (operands at: 0). + destReg := leftReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 put: (self xorR: destReg R: leftReg R: rightReg). - | leftReg rightReg | - leftReg := self concreteRegister: (operands at: 0). - rightReg := self concreteRegister: (operands at: 1). - self machineCodeAt: 0 put: (self xorR: rightReg R: leftReg R: rightReg). ^machineCodeSize := 4! Item was changed: ----- Method: CogMIPSELCompiler>>isCallPrecedingReturnPC: (in category 'testing') ----- isCallPrecedingReturnPC: mcpc + "cogit disassembleFrom: mcpc - 8 to: mcpc." - cogit disassembleFrom: mcpc - 8 to: mcpc. (self opcodeAtAddress: mcpc - 8) = JAL ifTrue: [^true]. ((self opcodeAtAddress: mcpc - 8) = SPECIAL and: [(self opcodeAtAddress: mcpc - 8) = JALR]) ifTrue: [^true]. ^false! Item was changed: ----- Method: CogMIPSELCompiler>>jumpLongConditionalTargetBeforeFollowingAddress: (in category 'inline cacheing') ----- jumpLongConditionalTargetBeforeFollowingAddress: mcpc - Transcript nextPutAll: mcpc hex; cr. "mcpc - 16: beq/ne Cmp, ZR, +12 mcpc - 12: nop (delay slot) mcpc - 8: j psuedo-address mcpc - 4: nop (delay slot)" self assert: (((self opcodeAtAddress: mcpc - 16) == BEQ) or: [(self opcodeAtAddress: mcpc - 16) == BNE]). self assert: (objectMemory longAt: mcpc - 12) == self nop. "Delay slot" self assert: (self opcodeAtAddress: mcpc - 8) == J. self assert: (objectMemory longAt: mcpc - 4) == self nop. "Delay slot" ^self targetFromJTypeAtAddress: mcpc - 8! Item was changed: ----- Method: CogMIPSELCompiler>>machineCodeWords (in category 'generate machine code') ----- machineCodeWords "Answer the maximum number of words of machine code generated for any abstract instruction. + e.g. AddCheckOverflowCqR" - e.g. CmpCwR => - lui at, <high> - ori at, <low> - subu Cmp, reg, at - slt CmpSLT, reg, at - slt CmpSGT, reg, at - slt CmpULT, reg, at - slt CmpUGT, reg, at" - self flag: #inefficient. ^7! Item was changed: ----- Method: CogMIPSELCompiler>>noteFollowingConditionalBranch: (in category 'abstract instructions') ----- noteFollowingConditionalBranch: branch "Support for processors without condition codes, such as the MIPS. Answer the branch opcode. Modify the receiver and the branch to implement a suitable conditional branch that doesn't depend on condition codes being set by the receiver." <var: #branch type: #'AbstractInstruction *'> | newBranchLeft newBranchOpcode newBranchRight | + + ((branch opcode = JumpOverflow) or: [branch opcode = JumpNoOverflow]) + ifTrue: [^self noteFollowingOverflowBranch: branch]. - ((branch opcode = JumpOverflow) or: [branch opcode = JumpNoOverflow]) ifTrue: - [opcode := opcode caseOf: { - [AddCqR] -> [AddCheckOverflowCqR]. - [AddRR] -> [AddCheckOverflowRR]. - [MulRR] -> [MulCheckOverflowRR]. - [SubCqR] -> [SubCheckOverflowCqR]. - [SubRR] -> [SubCheckOverflowRR]. - } otherwise: [self unreachable]. - ^branch]. - newBranchOpcode := branch opcode caseOf: { [JumpZero] -> [BrEqualRR]. [JumpNonZero] -> [BrNotEqualRR]. [JumpBelow] -> [BrUnsignedLessRR]. [JumpBelowOrEqual] -> [BrUnsignedLessEqualRR]. [JumpAbove] -> [BrUnsignedGreaterRR]. [JumpAboveOrEqual] -> [BrUnsignedGreaterEqualRR]. [JumpLess] -> [BrSignedLessRR]. [JumpLessOrEqual] -> [BrSignedLessEqualRR]. [JumpGreater] -> [BrSignedGreaterRR]. [JumpGreaterOrEqual] -> [BrSignedGreaterEqualRR]. [JumpLongZero] -> [BrLongEqualRR]. [JumpLongNonZero] -> [BrLongNotEqualRR]. [JumpNegative] -> [BrSignedLessRR]. } otherwise: [self unreachable]. opcode caseOf: { [BrEqualRR] -> ["I.e., two jumps after a compare." newBranchLeft := operands at: 1. newBranchRight := operands at: 2]. [BrUnsignedLessRR] -> ["I.e., two jumps after a compare." newBranchLeft := operands at: 1. newBranchRight := operands at: 2]. [CmpRR] -> [newBranchLeft := operands at: 1. newBranchRight := operands at: 0. opcode := Label]. [CmpCqR] -> [newBranchLeft := operands at: 1. newBranchRight := AT. opcode := MoveCqR. operands at: 1 put: AT]. [CmpCwR] -> [newBranchLeft := operands at: 1. newBranchRight := AT. opcode := MoveCwR. operands at: 1 put: AT]. [TstCqR] -> [newBranchLeft := Cmp. newBranchRight := ZR]. [AndCqR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [AndCqRR] -> [newBranchLeft := operands at: 2. newBranchRight := ZR]. [OrRR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [XorRR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [SubCwR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [SubCqR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. [ArithmeticShiftRightCqR] -> [newBranchLeft := operands at: 1. newBranchRight := ZR]. } otherwise: [self unreachable]. branch rewriteOpcode: newBranchOpcode with: newBranchLeft with: newBranchRight. ^branch! Item was added: + ----- Method: CogMIPSELCompiler>>noteFollowingOverflowBranch: (in category 'abstract instructions') ----- + noteFollowingOverflowBranch: branch + "Support for processors without condition codes, such as the MIPS. + Answer the branch opcode. Modify the receiver and the branch to + implement a suitable conditional branch that doesn't depend on + condition codes being set by the receiver." + <var: #branch type: #'AbstractInstruction *'> + | newBranchOpcode | + + (opcode = MulRR) ifTrue: + [opcode := MulCheckOverflowRR. + newBranchOpcode := branch opcode caseOf: { + [JumpOverflow] -> [BrNotEqualRR]. + [JumpNoOverflow] -> [BrEqualRR]. + } otherwise: [self unreachable]. + branch rewriteOpcode: newBranchOpcode with: OverflowTemp1 with: OverflowTemp2. + ^branch]. + + + opcode := opcode caseOf: { + [AddCqR] -> [AddCheckOverflowCqR]. + [AddRR] -> [AddCheckOverflowRR]. + [SubCqR] -> [SubCheckOverflowCqR]. + [SubRR] -> [SubCheckOverflowRR]. + } otherwise: [self unreachable]. + + newBranchOpcode := branch opcode caseOf: { + [JumpOverflow] -> [BrSignedLessRR]. + [JumpNoOverflow] -> [BrSignedGreaterEqualRR]. + } otherwise: [self unreachable]. + branch rewriteOpcode: newBranchOpcode with: Overflow with: ZR. + ^branch! Item was changed: ----- Method: CogMIPSELCompiler>>relocateMethodReferenceBeforeAddress:by: (in category 'inline cacheing') ----- relocateMethodReferenceBeforeAddress: pc by: delta | oldValue newValue | + "cogit disassembleFrom: pc - 8 to: pc." - cogit disassembleFrom: pc - 8 to: pc. oldValue := self literalAtAddress: pc - 4. newValue := oldValue + delta. self literalAtAddress: pc - 4 put: newValue. + "cogit disassembleFrom: pc - 8 to: pc." - cogit disassembleFrom: pc - 8 to: pc. self assert: (self literalAtAddress: pc - 4) = newValue. ! Item was changed: ----- Method: CogMIPSELCompiler>>rewriteCPICJumpAt:target: (in category 'inline cacheing') ----- rewriteCPICJumpAt: addressFollowingJump target: jumpTargetAddress "Rewrite a jump instruction to call a different target. This variant is used to reset the jumps in the prototype CPIC to suit each use,. Answer the extent of the code change which is used to compute the range of the icache to flush." <var: #addressFollowingJump type: #usqInt> <var: #jumpTargetAddress type: #usqInt> "self CmpR: ClassReg R: TempReg. ^self JumpNonZero: 0" "bne s5, s3, +156 ; =BE7C nop (delay slot) .... <-- addressFollowingJump" self assert: (self opcodeAtAddress: addressFollowingJump - 8) = BNE. self assert: (objectMemory longAt: addressFollowingJump - 4) = self nop. + "cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump." - cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump. self rewriteITypeBranchAtAddress: addressFollowingJump - 8 target: jumpTargetAddress. self assert: (self opcodeAtAddress: addressFollowingJump - 8) = BNE. self assert: (objectMemory longAt: addressFollowingJump - 4) = self nop. + "cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump."! - cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump.! Item was changed: ----- Method: CogMIPSELCompiler>>rewriteCallAt:target: (in category 'inline cacheing') ----- rewriteCallAt: callSiteReturnAddress target: callTargetAddress "Rewrite a call instruction to call a different target. This variant is used to link PICs in ceSendMiss et al,. Answer the extent of the code change which is used to compute the range of the icache to flush." <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> "lui t9, stub/targetHigh ori t9, t9, stub/targetLow jalr t9 nop (delay slot) ... <-- callSiteReturnAddress" self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress." - - cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress. self literalAtAddress: callSiteReturnAddress - 12 put: callTargetAddress. self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress." - cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress. - ^20! Item was changed: ----- Method: CogMIPSELCompiler>>rewriteConditionalJumpLongAt:target: (in category 'inline cacheing') ----- rewriteConditionalJumpLongAt: callSiteReturnAddress target: callTargetAddress "Rewrite a jump instruction to call a different target. This variant is used to reset the jumps in the prototype CPIC to suit each use,. Answer the extent of the code change which is used to compute the range of the icache to flush." <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = J. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress." - cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress. self rewriteJTypeAtAddress: callSiteReturnAddress - 8 target: callTargetAddress. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = J. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress." - cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress. ! Item was changed: ----- Method: CogMIPSELCompiler>>rewriteInlineCacheAt:tag:target: (in category 'inline cacheing') ----- rewriteInlineCacheAt: callSiteReturnAddress tag: cacheTag target: callTargetAddress "Rewrite an inline cache to call a different target for a new tag. This variant is used to link unlinked sends in ceSend:to:numArgs: et al. Answer the extent of the code change which is used to compute the range of the icache to flush." "MoveCwR ClassReg selectorIndex/expectedClass Call: unlinked send stub/expectedTarget Push ReceiverResult <-- callSiteReturnAddress" "lui s3, selector/tagHigh ori s3, s3, selector/tagLow lui t9, stub/targetHigh ori t9, t9, stub/targetLow jalr t9 nop (delay slot) ... <-- callSiteReturnAddress" <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress." - - cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress. self literalAtAddress: callSiteReturnAddress - 20 put: cacheTag. self literalAtAddress: callSiteReturnAddress - 12 put: callTargetAddress. self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress." - cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress. - ^28! Item was changed: ----- Method: CogMIPSELCompiler>>rewriteJumpLongAt:target: (in category 'inline cacheing') ----- rewriteJumpLongAt: callSiteReturnAddress target: callTargetAddress "Rewrite a jump instruction to call a different target. This variant is used to reset the jumps in the prototype CPIC to suit each use,. Answer the extent of the code change which is used to compute the range of the icache to flush." <var: #callSiteReturnAddress type: #usqInt> <var: #callTargetAddress type: #usqInt> "lui t9, stub/targetHigh ori t9, t9, stub/targetLow jr t9 nop (delay slot) ... <-- callSiteReturnAddress" self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress." - - cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress. self literalAtAddress: callSiteReturnAddress - 12 put: callTargetAddress. self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI. self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL. self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JR. self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop. + "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress." - cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress. - ^20! Item was changed: ----- Method: CogMIPSELCompilerTests>>assertCheckQuickArithOpCodeSize: (in category 'as yet unclassified') ----- assertCheckQuickArithOpCodeSize: bytes + self assert: bytes <= 12! - self flag: #todo. "We always generate the full 3 instructions for now." - self assert: bytes = 12!

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VM Maker: Cog-rmacnak.299.mcz
by commits＠source.squeak.org 01 Dec '15

01 Dec '15

Ryan Macnak uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-rmacnak.299.mcz ==================== Summary ==================== Name: Cog-rmacnak.299 Author: rmacnak Time: 30 November 2015, 6:55:38.035 pm UUID: 5cf0cfa6-509a-48f5-ae66-4375da66ffa1 Ancestors: Cog-rmacnak.298 MIPS simulator and disassembler: fix decoding R-type shift amount. =============== Diff against Cog-rmacnak.298 =============== Item was added: + ----- Method: MIPSELSimulatorTests>>testSllLarge (in category 'tests - arithmetic') ----- + testSllLarge + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sllR: V0 R: A0 C: 31). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 000417C0 sll v0, a0, 31 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 42 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -42 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 1 with: 0 with: 0 with: 0. + self assert: result equals: -16r80000000. + result := simulator call: 0 with: -1 with: 0 with: 0 with: 0. + self assert: result equals: -16r80000000].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSraLarge (in category 'tests - arithmetic') ----- + testSraLarge + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler sraR: V0 R: A0 C: 31). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 000417C3 sra v0, a0, 31 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 42 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -42 with: 0 with: 0 with: 0. + self assert: result equals: -1].! Item was added: + ----- Method: MIPSELSimulatorTests>>testSrlLarge (in category 'tests - arithmetic') ----- + testSrlLarge + | result | + self + testGenerateInto: + [:stream :compiler | + stream nextPut: (compiler srlR: V0 R: A0 C: 31). + stream nextPut: (compiler jR: RA). + stream nextPut: (compiler nop). "Delay slot"] + disassembly: + '00000000 000417C2 srl v0, a0, 31 + 00000004 03E00008 jr ra + 00000008 00000000 nop + ' run: + [:simulator | + result := simulator call: 0 with: 0 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: 42 with: 0 with: 0 with: 0. + self assert: result equals: 0. + result := simulator call: 0 with: -42 with: 0 with: 0 with: 0. + self assert: result equals: 1].! Item was changed: ----- Method: MIPSInstruction>>sa (in category 'fields') ----- sa + ^(value >> 6) bitAnd: 31! - ^(value >> 6) bitAnd: 15!

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VM Maker: VMMaker.oscog-eem.1536.mcz
by commits＠source.squeak.org 01 Dec '15

01 Dec '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1536.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1536 Author: eem Time: 30 November 2015, 5:54:18.551 pm UUID: fe6b5e3a-872a-44b3-bae8-d4a2cbb678f8 Ancestors: VMMaker.oscog-eem.1535 X64 Cogit: Make rewriteConditionalJumpLongAt:target: a default to be overridden. Now that the 64-bit Alien accessors and the Bochs x64 emulator have been fixed, get division working on x64. Add XorRR support for the division primitives. =============== Diff against VMMaker.oscog-eem.1535 =============== Item was removed: - ----- Method: CogARMCompiler>>rewriteConditionalJumpLongAt:target: (in category 'inline cacheing') ----- - rewriteConditionalJumpLongAt: callSiteReturnAddress target: callTargetAddress - ^self rewriteJumpLongAt: callSiteReturnAddress target: callTargetAddress! Item was added: + ----- Method: CogAbstractInstruction>>rewriteConditionalJumpLongAt:target: (in category 'inline cacheing') ----- + rewriteConditionalJumpLongAt: callSiteReturnAddress target: callTargetAddress + "Rewrite a conditional jump long to jump to target. This version defaults to using + rewriteJumpLongAt:, which works for many ISAs. Subclasses override if necessary." + ^self rewriteJumpLongAt: callSiteReturnAddress target: callTargetAddress! Item was removed: - ----- Method: CogIA32Compiler>>rewriteConditionalJumpLongAt:target: (in category 'inline cacheing') ----- - rewriteConditionalJumpLongAt: callSiteReturnAddress target: callTargetAddress - ^self rewriteJumpLongAt: callSiteReturnAddress target: callTargetAddress! Item was added: + ----- Method: CogX64Compiler>>canDivQuoRem (in category 'testing') ----- + canDivQuoRem + <inline: true> + ^true! Item was added: + ----- Method: CogX64Compiler>>concretizeXorRR (in category 'generate machine code') ----- + concretizeXorRR + "Will get inlined into concretizeAt: switch." + <inline: true> + | regLHS regRHS | + regLHS := self concreteRegister: (operands at: 0). + regRHS := self concreteRegister: (operands at: 1). + machineCode + at: 0 put: (self rexR: regRHS x: 0 b: regLHS); + at: 1 put: 16r33; + at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS). + ^machineCodeSize := 3! Item was added: + ----- Method: CogX64Compiler>>setsConditionCodesFor: (in category 'testing') ----- + setsConditionCodesFor: aConditionalJumpOpcode + <inline: false> "to save Slang from having to be a real compiler (it can't inline switches that return)" + "Answer if the receiver's opcode sets the condition codes correctly for the given conditional jump opcode." + ^opcode caseOf: + { [ArithmeticShiftRightCqR] -> [self shiftSetsConditionCodesFor: aConditionalJumpOpcode]. + [ArithmeticShiftRightRR] -> [self shiftSetsConditionCodesFor: aConditionalJumpOpcode]. + [LogicalShiftLeftCqR] -> [self shiftSetsConditionCodesFor: aConditionalJumpOpcode]. + [LogicalShiftLeftRR] -> [self shiftSetsConditionCodesFor: aConditionalJumpOpcode]. + [XorRR] -> [true] + } + otherwise: [self halt: 'unhandled opcode in setsConditionCodesFor:'. false]! Item was added: + ----- Method: CogX64Compiler>>shiftSetsConditionCodesFor: (in category 'testing') ----- + shiftSetsConditionCodesFor: aConditionalJumpOpcode + "OF flag only guaranteed to be set for 1-bit shifts. See [1] p 490. + Only SF, ZF & PF set according to result. Since the question is currently + asked only for Zero and Negative use the following simplification." + <inline: true> + ^(aConditionalJumpOpcode between: JumpZero and: JumpNonNegative)!

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[commit][3510] CogVM source as per VMMaker.oscog-eem.1535
by commits＠squeakvm.org 01 Dec '15

01 Dec '15

Revision: 3510 Author: eliot Date: 2015-11-30 16:32:22 -0800 (Mon, 30 Nov 2015) Log Message: ----------- CogVM source as per VMMaker.oscog-eem.1535 All: Fix maybeInlinePositive32BitIntegerFor: and hence positive64BitIntegerFor: for values that look like 32-bit negative SmallIntegers. Cogit: Move noteFollowingConditionalBranch: to catch branches created outside of Jump<Cond>, and hence generate a lot less junk in the cogit c files. CPIC patching (architecture independent): fix call mistaken for a jump and conditional branch mistaken for a jump. BochsX64Plugin: back port a fix from Bochs v2.6.8 that fixes the sign of 64-bit divisions. Mac OS Spur build: preserve dates when copying resources into .app bundles. Modified Paths: -------------- branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm branches/Cog/nsspursrc/vm/cogit.h branches/Cog/nsspursrc/vm/cogitARMv5.c branches/Cog/nsspursrc/vm/cogitIA32.c branches/Cog/nsspursrc/vm/cointerp.c branches/Cog/nsspursrc/vm/cointerp.h branches/Cog/nsspursrc/vm/gcc3x-cointerp.c branches/Cog/nsspurstack64src/vm/gcc3x-interp.c branches/Cog/nsspurstack64src/vm/interp.c branches/Cog/nsspurstacksrc/vm/gcc3x-interp.c branches/Cog/nsspurstacksrc/vm/interp.c branches/Cog/processors/IA32/bochs/cpu/mult64.cc branches/Cog/spursistasrc/vm/cogit.h branches/Cog/spursistasrc/vm/cogitARMv5.c branches/Cog/spursistasrc/vm/cogitIA32.c branches/Cog/spursistasrc/vm/cointerp.c branches/Cog/spursistasrc/vm/cointerp.h branches/Cog/spursistasrc/vm/gcc3x-cointerp.c branches/Cog/spursrc/vm/cogit.h branches/Cog/spursrc/vm/cogitARMv5.c branches/Cog/spursrc/vm/cogitIA32.c branches/Cog/spursrc/vm/cointerp.c branches/Cog/spursrc/vm/cointerp.h branches/Cog/spursrc/vm/gcc3x-cointerp.c branches/Cog/spurstack64src/vm/gcc3x-interp.c branches/Cog/spurstack64src/vm/interp.c branches/Cog/spurstacksrc/vm/gcc3x-interp.c branches/Cog/spurstacksrc/vm/interp.c branches/Cog/src/vm/cogit.h branches/Cog/src/vm/cogitARMv5.c branches/Cog/src/vm/cogitIA32.c branches/Cog/src/vm/cointerp.c branches/Cog/src/vm/cointerp.h branches/Cog/src/vm/cointerpmt.c branches/Cog/src/vm/cointerpmt.h branches/Cog/src/vm/gcc3x-cointerp.c branches/Cog/src/vm/gcc3x-cointerpmt.c branches/Cog/stacksrc/vm/gcc3x-interp.c branches/Cog/stacksrc/vm/interp.c Property Changed: ---------------- branches/Cog/platforms/Cross/vm/sqSCCSVersion.h Modified: branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm 2015-11-30 20:53:12 UTC (rev 3509) +++ branches/Cog/build.macos32x86/squeak.cog.spur/makeiosvm 2015-12-01 00:32:22 UTC (rev 3510) @@ -73,41 +73,41 @@ echo FloatMathPlugin xcodebuild -project FloatMathPlugin/FloatMathPlugin.xcodeproj -configuration Release xcodebuild -project FloatMathPlugin/FloatMathPlugin.xcodeproj -configuration Release rm -rf "$DEST/Contents/Resources/FloatMathPlugin.bundle" -echo cp -R FloatMathPlugin/build/Release/FloatMathPlugin.bundle "$DEST/Contents/Resources" -cp -R FloatMathPlugin/build/Release/FloatMathPlugin.bundle "$DEST/Contents/Resources" +echo cp -Rp FloatMathPlugin/build/Release/FloatMathPlugin.bundle "$DEST/Contents/Resources" +cp -Rp FloatMathPlugin/build/Release/FloatMathPlugin.bundle "$DEST/Contents/Resources" # Build the FloatArray plugin echo echo FloatArrayPlugin xcodebuild -project FloatArrayPlugin/FloatArrayPlugin.xcodeproj -configuration Release xcodebuild -project FloatArrayPlugin/FloatArrayPlugin.xcodeproj -configuration Release rm -rf "$DEST/Contents/Resources/FloatArrayPlugin.bundle" -cp -R FloatArrayPlugin/build/Release/FloatArrayPlugin.bundle "$DEST/Contents/Resources" +cp -Rp FloatArrayPlugin/build/Release/FloatArrayPlugin.bundle "$DEST/Contents/Resources" # Build the Croquet plugin echo echo CroquetPlugin xcodebuild -project CroquetPlugin/CroquetPlugin.xcodeproj -configuration Release xcodebuild -project CroquetPlugin/CroquetPlugin.xcodeproj -configuration Release rm -rf "$DEST/Contents/Resources/CroquetPlugin.bundle" -cp -R CroquetPlugin/build/Release/CroquetPlugin.bundle "$DEST/Contents/Resources" +cp -Rp CroquetPlugin/build/Release/CroquetPlugin.bundle "$DEST/Contents/Resources" #Build the mpeg3 plugin echo echo Mpeg3Plugin xcodebuild -project Mpeg3Plugin/Mpeg3Plugin.xcodeproj -configuration $NSD_BUILD_CONFIGURATION xcodebuild -project Mpeg3Plugin/Mpeg3Plugin.xcodeproj -configuration $NSD_BUILD_CONFIGURATION -cp -R Mpeg3Plugin/build/$NSD_BUILD_CONFIGURATION/Mpeg3Plugin.bundle "$DEST/Contents/Resources" +cp -Rp Mpeg3Plugin/build/$NSD_BUILD_CONFIGURATION/Mpeg3Plugin.bundle "$DEST/Contents/Resources" echo echo SqueakFFIPlugin xcodebuild -project $SFP/SqueakFFI.xcodeproj -configuration $NSD_BUILD_CONFIGURATION xcodebuild -project $SFP/SqueakFFI.xcodeproj -configuration $NSD_BUILD_CONFIGURATION rm -rf "$DEST/Contents/Resources/SqueakFFIPrims.bundle" -cp -R $SFP/build/$NSD_BUILD_CONFIGURATION/SqueakFFIPrims.bundle "$DEST/Contents/Resources" +cp -Rp $SFP/build/$NSD_BUILD_CONFIGURATION/SqueakFFIPrims.bundle "$DEST/Contents/Resources" # Build the SSL plugin (New as of 25 March 2013) echo echo SqueakSSL xcodebuild -project SqueakSSL/SqueakSSL.xcodeproj -configuration $XCD_BUILD_CONFIGURATION xcodebuild -project SqueakSSL/SqueakSSL.xcodeproj -configuration $XCD_BUILD_CONFIGURATION rm -rf "$DEST/Contents/Resources/SqueakSSL.bundle" -cp -R SqueakSSL/build/$XCD_BUILD_CONFIGURATION/SqueakSSL.bundle "$DEST/Contents/Resources" +cp -Rp SqueakSSL/build/$XCD_BUILD_CONFIGURATION/SqueakSSL.bundle "$DEST/Contents/Resources" # Build the BochsIA32Plugin # N.B. To build the plugin you also have to build the Bochs libraries in @@ -116,7 +116,7 @@ echo BochsIA32Plugin xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project BochsIA32Plugin/BochsIA32Plugin.xcodeproj xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project BochsIA32Plugin/BochsIA32Plugin.xcodeproj rm -rf "$DEST/Contents/Resources/BochsIA32Plugin.bundle" -cp -R BochsIA32Plugin/build/$XCD_BUILD_CONFIGURATION/BochsIA32Plugin.bundle "$DEST/Contents/Resources" +cp -Rp BochsIA32Plugin/build/$XCD_BUILD_CONFIGURATION/BochsIA32Plugin.bundle "$DEST/Contents/Resources" else echo "not building BochsIA32Plugin; support libraries unavailable" fi @@ -128,7 +128,7 @@ echo BochsX64Plugin xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project BochsX64Plugin/BochsX64Plugin.xcodeproj xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project BochsX64Plugin/BochsX64Plugin.xcodeproj rm -rf "$DEST/Contents/Resources/BochsX64Plugin.bundle" -cp -R BochsX64Plugin/build/$XCD_BUILD_CONFIGURATION/BochsX64Plugin.bundle "$DEST/Contents/Resources" +cp -Rp BochsX64Plugin/build/$XCD_BUILD_CONFIGURATION/BochsX64Plugin.bundle "$DEST/Contents/Resources" else echo "not building BochsX64Plugin; support libraries unavailable" fi @@ -140,7 +140,7 @@ echo GdbARMPlugin xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project GdbARMPlugin/GdbARMPlugin.xcodeproj xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project GdbARMPlugin/GdbARMPlugin.xcodeproj rm -rf "$DEST/Contents/Resources/GdbARMPlugin.bundle" -cp -R GdbARMPlugin/build/$XCD_BUILD_CONFIGURATION/GdbARMPlugin.bundle "$DEST/Contents/Resources" +cp -Rp GdbARMPlugin/build/$XCD_BUILD_CONFIGURATION/GdbARMPlugin.bundle "$DEST/Contents/Resources" else echo "not building GdbARMPlugin; support libraries unavailable" fi @@ -149,7 +149,7 @@ echo UnixOSProcessPlugin xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj xcodebuild -configuration $XCD_BUILD_CONFIGURATION -project UnixOSProcessPlugin/UnixOSProcessPlugin.xcodeproj rm -rf "$DEST/Contents/Resources/UnixOSProcessPlugin.bundle" -cp -R UnixOSProcessPlugin/build/$XCD_BUILD_CONFIGURATION/UnixOSProcessPlugin.bundle "$DEST/Contents/Resources" +cp -Rp UnixOSProcessPlugin/build/$XCD_BUILD_CONFIGURATION/UnixOSProcessPlugin.bundle "$DEST/Contents/Resources" # Clean out any .svn directories (result of copying) in the VM find "$DEST" -name .svn -exec rm -rf {} \; Modified: branches/Cog/nsspursrc/vm/cogit.h =================================================================== --- branches/Cog/nsspursrc/vm/cogit.h 2015-11-30 20:53:12 UTC (rev 3509) +++ branches/Cog/nsspursrc/vm/cogit.h 2015-12-01 00:32:22 UTC (rev 3510) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-rmacnak.1532 uuid: 20303656-4854-4e5b-8bcd-eeff8cf5d262 + CCodeGenerator VMMaker.oscog-eem.1535 uuid: eceebca6-4bc3-4640-b1eb-18e0ea917247 */ Modified: branches/Cog/nsspursrc/vm/cogitARMv5.c =================================================================== --- branches/Cog/nsspursrc/vm/cogitARMv5.c 2015-11-30 20:53:12 UTC (rev 3509) +++ branches/Cog/nsspursrc/vm/cogitARMv5.c 2015-12-01 00:32:22 UTC (rev 3510) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-rmacnak.1532 uuid: 20303656-4854-4e5b-8bcd-eeff8cf5d262 + CCodeGenerator VMMaker.oscog-eem.1535 uuid: eceebca6-4bc3-4640-b1eb-18e0ea917247 from - StackToRegisterMappingCogit VMMaker.oscog-rmacnak.1532 uuid: 20303656-4854-4e5b-8bcd-eeff8cf5d262 + StackToRegisterMappingCogit VMMaker.oscog-eem.1535 uuid: eceebca6-4bc3-4640-b1eb-18e0ea917247 */ -static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-rmacnak.1532 uuid: 20303656-4854-4e5b-8bcd-eeff8cf5d262 " __DATE__ ; +static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.1535 uuid: eceebca6-4bc3-4640-b1eb-18e0ea917247 " __DATE__ ; char *__cogitBuildInfo = __buildInfo; @@ -547,6 +547,7 @@ static AbstractInstruction * NoDbgRegParms relocateCallBeforeReturnPCby(AbstractInstruction * self_in_relocateCallBeforeReturnPCby, sqInt retpc, sqInt delta); static sqInt NoDbgRegParms rewriteCallAttarget(AbstractInstruction * self_in_rewriteCallAttarget, usqInt callSiteReturnAddress, usqInt callTargetAddress); static sqInt NoDbgRegParms rewriteCallFullAttarget(AbstractInstruction * self_in_rewriteCallFullAttarget, sqInt callSiteReturnAddress, sqInt callTargetAddress); +static sqInt NoDbgRegParms rewriteConditionalJumpLongAttarget(AbstractInstruction * self_in_rewriteConditionalJumpLongAttarget, sqInt callSiteReturnAddress, sqInt callTargetAddress); static sqInt NoDbgRegParms rewriteJumpFullAttarget(AbstractInstruction * self_in_rewriteJumpFullAttarget, sqInt callSiteReturnAddress, sqInt callTargetAddress); static sqInt NoDbgRegParms rewriteJumpLongAttarget(AbstractInstruction * self_in_rewriteJumpLongAttarget, usqInt callSiteReturnAddress, usqInt callTargetAddress); static sqInt NoDbgRegParms rewriteTransferAttarget(AbstractInstruction * self_in_rewriteTransferAttarget, usqInt callSiteReturnAddress, usqInt callTargetAddress); @@ -650,6 +651,7 @@ static void freePICsWithFreedTargets(void); extern void freeUnmarkedMachineCode(void); static sqInt genCheckForInterruptsTrampoline(void); +static AbstractInstruction * NoDbgRegParms genConditionalBranchoperand(sqInt opcode, sqInt operandOne); static void (*genEnilopmartForandandforCallcalled(sqInt regArg1, sqInt regArg2, sqInt regArg3, sqInt forCall, char *trampolineName))(void) ; static void NoDbgRegParms genEnilopmartReturn(sqInt forCall); static void NoDbgRegParms generateCaptureCStackPointers(sqInt captureFramePointer); @@ -7406,7 +7408,14 @@ return rewriteFullTransferAttargetexpectedInstruction(self_in_rewriteCallFullAttarget, callSiteReturnAddress, callTargetAddress, 3778019132UL); } + /* CogARMCompiler>>#rewriteConditionalJumpLongAt:target: */ +static sqInt NoDbgRegParms +rewriteConditionalJumpLongAttarget(AbstractInstruction * self_in_rewriteConditionalJumpLongAttarget, sqInt callSiteReturnAddress, sqInt callTargetAddress) +{ + return rewriteJumpLongAttarget(self_in_rewriteConditionalJumpLongAttarget, callSiteReturnAddress, callTargetAddress); +} + /* Rewrite a full jump instruction to jump to a different target. This variant is used to rewrite cached primitive calls where we load the target address into ip @@ -9411,18 +9420,12 @@ compileBlockDispatchFromto(sqInt lowBlockStartIndex, sqInt highBlockStartIndex) { BlockStart *blockStart; - AbstractInstruction *branch; - AbstractInstruction *branch1; - AbstractInstruction *branch2; sqInt halfWay; AbstractInstruction *jmp; void *jumpTarget; void *jumpTarget1; void *jumpTarget2; sqInt quickConstant; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - AbstractInstruction * self_in_noteFollowingConditionalBranch1; - AbstractInstruction * self_in_noteFollowingConditionalBranch2; if (lowBlockStartIndex == highBlockStartIndex) { blockStart = blockStartAt(lowBlockStartIndex); @@ -9444,10 +9447,7 @@ if (lowBlockStartIndex == halfWay) { /* begin JumpLessOrEqual: */ jumpTarget1 = (blockStart->entryLabel); - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpLessOrEqual, ((sqInt)jumpTarget1)); - branch; + genConditionalBranchoperand(JumpLessOrEqual, ((sqInt)jumpTarget1)); compileBlockDispatchFromto(halfWay + 1, highBlockStartIndex); return null; } @@ -9455,17 +9455,11 @@ blockStart = blockStartAt(highBlockStartIndex); /* begin JumpGreater: */ jumpTarget2 = (blockStart->entryLabel); - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch1 = previousInstruction(); - branch1 = genoperand(JumpGreater, ((sqInt)jumpTarget2)); - branch1; + genConditionalBranchoperand(JumpGreater, ((sqInt)jumpTarget2)); return compileBlockDispatchFromto(lowBlockStartIndex, halfWay); } /* begin JumpGreater: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch2 = previousInstruction(); - branch2 = genoperand(JumpGreater, ((sqInt)0)); - jmp = branch2; + jmp = genConditionalBranchoperand(JumpGreater, ((sqInt)0)); compileBlockDispatchFromto(lowBlockStartIndex, halfWay); if (halfWay == highBlockStartIndex) { blockStart = blockStartAt(highBlockStartIndex); @@ -9647,17 +9641,11 @@ static AbstractInstruction * compileCPICEntry(void) { - AbstractInstruction *branch; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - entry = genGetInlineCacheClassTagFromintoforEntry(ReceiverResultReg, TempReg, 1); /* begin CmpR:R: */ genoperandoperand(CmpRR, ClassReg, TempReg); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpNonZero, ((sqInt)0)); - return branch; + return genConditionalBranchoperand(JumpNonZero, ((sqInt)0)); } @@ -9673,18 +9661,13 @@ compileEntry(void) { AbstractInstruction *abstractInstruction; - AbstractInstruction *branch; AbstractInstruction * inst; - AbstractInstruction * self_in_noteFollowingConditionalBranch; entry = genGetInlineCacheClassTagFromintoforEntry(ReceiverResultReg, TempReg, 1); /* begin CmpR:R: */ genoperandoperand(CmpRR, ClassReg, TempReg); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpNonZero, ((sqInt)sendMiss)); - branch; + genConditionalBranchoperand(JumpNonZero, ((sqInt)sendMiss)); /* begin Label */ noCheckEntry = genoperandoperand(Label, (labelCounter += 1), bytecodePC); if (compileSendTrace()) { @@ -9967,7 +9950,7 @@ sqInt operand; sqInt target; - rewriteJumpLongAttarget(backEnd, (((sqInt)cPIC)) + missOffset, picAbortTrampolineFor(numArgs)); + rewriteCallAttarget(backEnd, (((sqInt)cPIC)) + missOffset, picAbortTrampolineFor(numArgs)); /* set the jump to the case0 method */ @@ -10663,7 +10646,20 @@ return genTrampolineForcallednumArgsargargargargsaveRegspushLinkRegresultRegappendOpcodes(ceCheckForInterrupts, "ceCheckForInterruptsTrampoline", 0, null, null, null, null, 0, 0, null, 1); } + /* Cogit>>#genConditionalBranch:operand: */ +static AbstractInstruction * NoDbgRegParms +genConditionalBranchoperand(sqInt opcode, sqInt operandOne) +{ + AbstractInstruction *branch; + AbstractInstruction * self_in_noteFollowingConditionalBranch; + /* begin noteFollowingConditionalBranch: */ + self_in_noteFollowingConditionalBranch = previousInstruction(); + branch = genoperand(opcode, operandOne); + return branch; +} + + /* An enilopmart (the reverse of a trampoline) is a piece of code that makes the system-call-like transition from the C runtime into generated machine code. The desired arguments and entry-point are pushed on a stackPage's @@ -10818,7 +10814,6 @@ { AbstractInstruction *anInstruction; AbstractInstruction *anInstruction1; - AbstractInstruction *branch; CogMethod *cPIC; AbstractInstruction * cPICEndOfCodeLabel; sqInt endAddress; @@ -10832,7 +10827,6 @@ sqInt numArgs; sqInt opcode; sqInt opcodeSize; - AbstractInstruction * self_in_noteFollowingConditionalBranch; sqInt wordConstant; @@ -10867,8 +10861,8 @@ (anInstruction1->dependent = allocateLiteral(99282957)); anInstruction1; /* begin JumpLong: */ - jumpTarget = (cPICPrototypeCaseOffset()) + 13262352; - genoperand(JumpLong, jumpTarget); + jumpTarget1 = (cPICPrototypeCaseOffset()) + 13262352; + genoperand(JumpLong, jumpTarget1); /* begin Label */ endCPICCase0 = genoperandoperand(Label, (labelCounter += 1), bytecodePC); for (h = 1; h < maxCPICCases; h += 1) { @@ -10887,11 +10881,8 @@ opcode = CmpCwR; checkLiteralforInstruction(3133021973UL + h, genoperandoperand(opcode, 3133021973UL + h, TempReg)); /* begin JumpLongZero: */ - jumpTarget2 = ((cPICPrototypeCaseOffset()) + 13262352) + (h * 16); - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpLongZero, ((sqInt)jumpTarget2)); - branch; + jumpTarget = ((cPICPrototypeCaseOffset()) + 13262352) + (h * 16); + genConditionalBranchoperand(JumpLongZero, ((sqInt)jumpTarget)); if (h == 1) { /* begin Label */ endCPICCase1 = genoperandoperand(Label, (labelCounter += 1), bytecodePC); @@ -10902,8 +10893,8 @@ /* begin gen:literal:operand: */ checkLiteralforInstruction(wordConstant, genoperandoperand(MoveCwR, wordConstant, ClassReg)); /* begin JumpLong: */ - jumpTarget1 = cPICMissTrampolineFor(numArgs); - genoperand(JumpLong, jumpTarget1); + jumpTarget2 = cPICMissTrampolineFor(numArgs); + genoperand(JumpLong, jumpTarget2); /* begin Label */ cPICEndOfCodeLabel = genoperandoperand(Label, (labelCounter += 1), bytecodePC); dumpLiterals(0); @@ -11041,12 +11032,12 @@ generateMapAtstart(sqInt addressOrNull, sqInt startAddress) { unsigned char annotation; - usqInt delta; + sqInt delta; sqInt i; AbstractInstruction *instruction; sqInt length; - usqInt location; - usqInt mapEntry; + sqInt location; + sqInt mapEntry; sqInt maxDelta; usqInt mcpc; @@ -11359,18 +11350,13 @@ static sqInt NoDbgRegParms genInnerPICAbortTrampoline(char *name) { - AbstractInstruction *branch; AbstractInstruction *jumpMNUCase; - AbstractInstruction * self_in_noteFollowingConditionalBranch; /* begin CmpCq:R: */ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(0, genoperandoperand(CmpCqR, 0, ClassReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpZero, ((sqInt)0)); - jumpMNUCase = branch; + jumpMNUCase = genConditionalBranchoperand(JumpZero, ((sqInt)0)); compileTrampolineFornumArgsargargargargsaveRegspushLinkRegresultReg(ceInterpretMethodFromPICreceiver, 2, SendNumArgsReg, ReceiverResultReg, null, null, 0, 0, null); jmpTarget(jumpMNUCase, gLabel()); return genTrampolineForcallednumArgsargargargargsaveRegspushLinkRegresultRegappendOpcodes(ceMNUFromPICMNUMethodreceiver, name, 2, SendNumArgsReg, ReceiverResultReg, null, null, 0, 0, null, 1); @@ -11489,13 +11475,9 @@ static sqInt NoDbgRegParms genNSSendTrampolineFornumArgsenclosingObjectCheckcalled(void *aRoutine, sqInt numArgs, sqInt eoCheckFlag, char *aString) { - AbstractInstruction *branch; - AbstractInstruction *branch1; AbstractInstruction *jumpItsTheReceiverStupid; AbstractInstruction *jumpMiss; sqInt offset; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - AbstractInstruction * self_in_noteFollowingConditionalBranch1; zeroOpcodeIndex(); genGetInlineCacheClassTagFromintoforEntry(ReceiverResultReg, ClassReg, 0); @@ -11505,10 +11487,7 @@ /* begin CmpR:R: */ genoperandoperand(CmpRR, ClassReg, TempReg); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch1 = previousInstruction(); - branch1 = genoperand(JumpNonZero, ((sqInt)0)); - jumpMiss = branch1; + jumpMiss = genConditionalBranchoperand(JumpNonZero, ((sqInt)0)); if (eoCheckFlag) { /* begin MoveMw:r:R: */ /* begin gen:quickConstant:operand:operand: */ @@ -11517,10 +11496,7 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(0, genoperandoperand(CmpCqR, 0, TempReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpZero, ((sqInt)0)); - jumpItsTheReceiverStupid = branch; + jumpItsTheReceiverStupid = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, TempReg, ReceiverResultReg); if (numArgs > 2) { @@ -14616,7 +14592,7 @@ classTagPC = followingAddress - (jumpLongConditionalByteSize(backEnd)); storeLiteralbeforeFollowingAddress(backEnd, newTag, classTagPC); - rewriteJumpLongAttarget(backEnd, followingAddress, newTarget); + rewriteConditionalJumpLongAttarget(backEnd, followingAddress, newTarget); } /* Cogit>>#SubCw:R: */ @@ -16580,8 +16556,6 @@ static AbstractInstruction * NoDbgRegParms genGetInlineCacheClassTagFromintoforEntry(sqInt sourceReg, sqInt destReg, sqInt forEntry) { - AbstractInstruction *branch; - AbstractInstruction *branch1; AbstractInstruction *entryLabel; AbstractInstruction *first; AbstractInstruction *first1; @@ -16591,8 +16565,6 @@ sqInt quickConstant; sqInt quickConstant1; sqInt quickConstant2; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - AbstractInstruction * self_in_noteFollowingConditionalBranch1; if (forEntry) { /* begin AlignmentNops: */ @@ -16625,10 +16597,7 @@ first; l1: /* end AndCq:R:R: */; /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpNonZero, ((sqInt)immLabel)); - branch; + genConditionalBranchoperand(JumpNonZero, ((sqInt)immLabel)); flag("endianness"); /* begin MoveMw:r:R: */ /* begin gen:quickConstant:operand:operand: */ @@ -16659,10 +16628,7 @@ first1; l2: /* end AndCq:R:R: */; /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch1 = previousInstruction(); - branch1 = genoperand(JumpZero, ((sqInt)0)); - jumpNotImm = branch1; + jumpNotImm = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin AndCq:R: */ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(1, genoperandoperand(AndCqR, 1, destReg)); @@ -16685,10 +16651,8 @@ static sqInt NoDbgRegParms genGetNumBytesOfinto(sqInt srcReg, sqInt destReg) { - AbstractInstruction *branch; AbstractInstruction *jmp; sqInt quickConstant; - AbstractInstruction * self_in_noteFollowingConditionalBranch; genGetRawSlotSizeOfNonImminto(srcReg, destReg); /* begin CmpCq:R: */ @@ -16696,10 +16660,7 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant, genoperandoperand(CmpCqR, quickConstant, destReg)); /* begin JumpLess: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpLess, ((sqInt)0)); - jmp = branch; + jmp = genConditionalBranchoperand(JumpLess, ((sqInt)0)); genGetOverflowSlotsOfinto(srcReg, destReg); jmpTarget(jmp, gLogicalShiftLeftCqR(shiftForWord(), destReg)); genGetBitsofFormatByteOfintobaseHeaderIntoScratch(3, srcReg, TempReg, null); @@ -16725,20 +16686,6 @@ static sqInt NoDbgRegParms genInnerPrimitiveAtPut(sqInt retNoffset) { - AbstractInstruction *branch; - AbstractInstruction *branch1; - AbstractInstruction *branch10; - AbstractInstruction *branch11; - AbstractInstruction *branch12; - AbstractInstruction *branch13; - AbstractInstruction *branch2; - AbstractInstruction *branch3; - AbstractInstruction *branch4; - AbstractInstruction *branch5; - AbstractInstruction *branch6; - AbstractInstruction *branch7; - AbstractInstruction *branch8; - AbstractInstruction *branch9; sqInt formatReg; AbstractInstruction *jumpArrayOutOfBounds; AbstractInstruction *jumpBadIndex; @@ -16766,20 +16713,6 @@ sqInt quickConstant3; sqInt quickConstant4; sqInt quickConstant5; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - AbstractInstruction * self_in_noteFollowingConditionalBranch1; - AbstractInstruction * self_in_noteFollowingConditionalBranch10; - AbstractInstruction * self_in_noteFollowingConditionalBranch11; - AbstractInstruction * self_in_noteFollowingConditionalBranch12; - AbstractInstruction * self_in_noteFollowingConditionalBranch13; - AbstractInstruction * self_in_noteFollowingConditionalBranch2; - AbstractInstruction * self_in_noteFollowingConditionalBranch3; - AbstractInstruction * self_in_noteFollowingConditionalBranch4; - AbstractInstruction * self_in_noteFollowingConditionalBranch5; - AbstractInstruction * self_in_noteFollowingConditionalBranch6; - AbstractInstruction * self_in_noteFollowingConditionalBranch7; - AbstractInstruction * self_in_noteFollowingConditionalBranch8; - AbstractInstruction * self_in_noteFollowingConditionalBranch9; /* c.f. StackInterpreter>>stSizeOf: SpurMemoryManager>>lengthOf:format: fixedFieldsOf:format:length: */ @@ -16797,32 +16730,20 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant, genoperandoperand(CmpCqR, quickConstant, formatReg)); /* begin JumpAbove: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpAbove, ((sqInt)0)); - jumpNotPointers = branch; + jumpNotPointers = genConditionalBranchoperand(JumpAbove, ((sqInt)0)); genStoreCheckReceiverRegvalueRegscratchReginFrame(ReceiverResultReg, Arg1Reg, TempReg, 0); /* begin CmpCq:R: */ quickConstant1 = arrayFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant1, genoperandoperand(CmpCqR, quickConstant1, formatReg)); /* begin JumpBelow: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch1 = previousInstruction(); - branch1 = genoperand(JumpBelow, ((sqInt)0)); - jumpNotIndexablePointers = branch1; + jumpNotIndexablePointers = genConditionalBranchoperand(JumpBelow, ((sqInt)0)); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch2 = previousInstruction(); - branch2 = genoperand(JumpNonZero, ((sqInt)0)); - jumpHasFixedFields = branch2; + jumpHasFixedFields = genConditionalBranchoperand(JumpNonZero, ((sqInt)0)); /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg0Reg, ClassReg); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch3 = previousInstruction(); - branch3 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpArrayOutOfBounds = branch3; + jumpArrayOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin AddCq:R: */ /* begin gen:quickConstant:operand: */ operandOne = ((usqInt) BaseHeaderSize) >> (shiftForWord()); @@ -16839,10 +16760,7 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(ClassMethodContextCompactIndex, genoperandoperand(CmpCqR, ClassMethodContextCompactIndex, formatReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch4 = previousInstruction(); - branch4 = genoperand(JumpZero, ((sqInt)0)); - jumpIsContext = branch4; + jumpIsContext = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin PushR: */ genoperand(PushR, ClassReg); genGetClassObjectOfClassIndexintoscratchReg(formatReg, ClassReg, TempReg); @@ -16863,10 +16781,7 @@ /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg0Reg, ClassReg); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch5 = previousInstruction(); - branch5 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpFixedFieldsOutOfBounds = branch5; + jumpFixedFieldsOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin AddR:R: */ genoperandoperand(AddRR, formatReg, Arg0Reg); /* begin MoveR:Xwr:R: */ @@ -16877,45 +16792,30 @@ genoperand(RetN, retNoffset); jmpTarget(jumpNotPointers, gCmpCqR(firstCompiledMethodFormat(), formatReg)); /* begin JumpAboveOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch6 = previousInstruction(); - branch6 = genoperand(JumpAboveOrEqual, ((sqInt)0)); - jumpIsCompiledMethod = branch6; + jumpIsCompiledMethod = genConditionalBranchoperand(JumpAboveOrEqual, ((sqInt)0)); jumpNonSmallIntegerValue = genJumpNotSmallIntegerscratchReg(Arg1Reg, TempReg); /* begin CmpCq:R: */ quickConstant3 = firstByteFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant3, genoperandoperand(CmpCqR, quickConstant3, formatReg)); /* begin JumpAboveOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch7 = previousInstruction(); - branch7 = genoperand(JumpAboveOrEqual, ((sqInt)0)); - jumpIsBytes = branch7; + jumpIsBytes = genConditionalBranchoperand(JumpAboveOrEqual, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant4 = firstShortFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant4, genoperandoperand(CmpCqR, quickConstant4, formatReg)); /* begin JumpAboveOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch8 = previousInstruction(); - branch8 = genoperand(JumpAboveOrEqual, ((sqInt)0)); - jumpShortsUnsupported = branch8; + jumpShortsUnsupported = genConditionalBranchoperand(JumpAboveOrEqual, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant5 = firstLongFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant5, genoperandoperand(CmpCqR, quickConstant5, formatReg)); /* begin JumpBelow: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch9 = previousInstruction(); - branch9 = genoperand(JumpBelow, ((sqInt)0)); - jumpNotIndexableBits = branch9; + jumpNotIndexableBits = genConditionalBranchoperand(JumpBelow, ((sqInt)0)); /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg0Reg, ClassReg); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch10 = previousInstruction(); - branch10 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpWordsOutOfBounds = branch10; + jumpWordsOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, Arg1Reg, TempReg); genConvertSmallIntegerToIntegerInReg(TempReg); @@ -16925,10 +16825,7 @@ checkQuickConstantforInstruction(0, genoperandoperand(CmpCqR, 0, ClassReg)); } /* begin JumpNegative: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch11 = previousInstruction(); - branch11 = genoperand(JumpNegative, ((sqInt)0)); - jumpNegative = branch11; + jumpNegative = genConditionalBranchoperand(JumpNegative, ((sqInt)0)); /* begin AddCq:R: */ /* begin gen:quickConstant:operand: */ operandOne2 = ((usqInt) BaseHeaderSize) >> (shiftForWord()); @@ -16941,10 +16838,7 @@ genoperand(RetN, retNoffset); jmpTarget(jumpIsBytes, gCmpCqR(((0xFF << 1) | 1), Arg1Reg)); /* begin JumpAbove: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch12 = previousInstruction(); - branch12 = genoperand(JumpAbove, ((sqInt)0)); - jumpBytesOutOfRange = branch12; + jumpBytesOutOfRange = genConditionalBranchoperand(JumpAbove, ((sqInt)0)); /* begin LogicalShiftLeftCq:R: */ genoperandoperand(LogicalShiftLeftCqR, shiftForWord(), ClassReg); /* begin AndCq:R: */ @@ -16955,10 +16849,7 @@ /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg0Reg, ClassReg); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch13 = previousInstruction(); - branch13 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpBytesOutOfBounds = branch13; + jumpBytesOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, Arg1Reg, TempReg); genConvertSmallIntegerToIntegerInReg(TempReg); @@ -16987,18 +16878,6 @@ static sqInt NoDbgRegParms genInnerPrimitiveAt(sqInt retNoffset) { - AbstractInstruction *branch; - AbstractInstruction *branch1; - AbstractInstruction *branch10; - AbstractInstruction *branch11; - AbstractInstruction *branch2; - AbstractInstruction *branch3; - AbstractInstruction *branch4; - AbstractInstruction *branch5; - AbstractInstruction *branch6; - AbstractInstruction *branch7; - AbstractInstruction *branch8; - AbstractInstruction *branch9; sqInt formatReg; AbstractInstruction *jumpArrayOutOfBounds; AbstractInstruction *jumpBadIndex; @@ -17029,18 +16908,6 @@ sqInt quickConstant4; sqInt quickConstant5; sqInt quickConstant6; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - AbstractInstruction * self_in_noteFollowingConditionalBranch1; - AbstractInstruction * self_in_noteFollowingConditionalBranch10; - AbstractInstruction * self_in_noteFollowingConditionalBranch11; - AbstractInstruction * self_in_noteFollowingConditionalBranch2; - AbstractInstruction * self_in_noteFollowingConditionalBranch3; - AbstractInstruction * self_in_noteFollowingConditionalBranch4; - AbstractInstruction * self_in_noteFollowingConditionalBranch5; - AbstractInstruction * self_in_noteFollowingConditionalBranch6; - AbstractInstruction * self_in_noteFollowingConditionalBranch7; - AbstractInstruction * self_in_noteFollowingConditionalBranch8; - AbstractInstruction * self_in_noteFollowingConditionalBranch9; /* c.f. StackInterpreter>>stSizeOf: SpurMemoryManager>>lengthOf:format: fixedFieldsOf:format:length: */ @@ -17060,51 +16927,33 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant, genoperandoperand(CmpCqR, quickConstant, formatReg)); /* begin JumpAboveOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpAboveOrEqual, ((sqInt)0)); - jumpIsBytes = branch; + jumpIsBytes = genConditionalBranchoperand(JumpAboveOrEqual, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant1 = arrayFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant1, genoperandoperand(CmpCqR, quickConstant1, formatReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch1 = previousInstruction(); - branch1 = genoperand(JumpZero, ((sqInt)0)); - jumpIsArray = branch1; + jumpIsArray = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin JumpBelow: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch2 = previousInstruction(); - branch2 = genoperand(JumpBelow, ((sqInt)0)); - jumpNotIndexable = branch2; + jumpNotIndexable = genConditionalBranchoperand(JumpBelow, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant2 = weakArrayFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant2, genoperandoperand(CmpCqR, quickConstant2, formatReg)); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch3 = previousInstruction(); - branch3 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpHasFixedFields = branch3; + jumpHasFixedFields = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant3 = firstShortFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant3, genoperandoperand(CmpCqR, quickConstant3, formatReg)); /* begin JumpAboveOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch4 = previousInstruction(); - branch4 = genoperand(JumpAboveOrEqual, ((sqInt)0)); - jumpIsShorts = branch4; + jumpIsShorts = genConditionalBranchoperand(JumpAboveOrEqual, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant4 = firstLongFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant4, genoperandoperand(CmpCqR, quickConstant4, formatReg)); /* begin JumpAboveOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch5 = previousInstruction(); - branch5 = genoperand(JumpAboveOrEqual, ((sqInt)0)); - jumpIsWords = branch5; + jumpIsWords = genConditionalBranchoperand(JumpAboveOrEqual, ((sqInt)0)); jmpTarget(jumpNotIndexable, gLabel()); /* begin Jump: */ jumpNotIndexable = genoperand(Jump, ((sqInt)0)); @@ -17117,10 +16966,7 @@ /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg1Reg, ClassReg); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch6 = previousInstruction(); - branch6 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpBytesOutOfBounds = branch6; + jumpBytesOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin AddCq:R: */ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(BaseHeaderSize, genoperandoperand(AddCqR, BaseHeaderSize, Arg1Reg)); @@ -17138,10 +16984,7 @@ /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg1Reg, ClassReg); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch7 = previousInstruction(); - branch7 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpShortsOutOfBounds = branch7; + jumpShortsOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin AddR:R: */ genoperandoperand(AddRR, Arg1Reg, ReceiverResultReg); /* begin MoveM16:r:R: */ @@ -17152,10 +16995,7 @@ jumpShortsDone = genoperand(Jump, ((sqInt)0)); jmpTarget(jumpIsWords, gCmpRR(Arg1Reg, ClassReg)); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch8 = previousInstruction(); - branch8 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpWordsOutOfBounds = branch8; + jumpWordsOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin AddCq:R: */ /* begin gen:quickConstant:operand: */ operandOne = ((usqInt) BaseHeaderSize) >> (shiftForWord()); @@ -17179,10 +17019,7 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(ClassMethodContextCompactIndex, genoperandoperand(CmpCqR, ClassMethodContextCompactIndex, TempReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch9 = previousInstruction(); - branch9 = genoperand(JumpZero, ((sqInt)0)); - jumpIsContext = branch9; + jumpIsContext = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin PushR: */ genoperand(PushR, ClassReg); genGetClassObjectOfClassIndexintoscratchReg(formatReg, ClassReg, TempReg); @@ -17199,10 +17036,7 @@ /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg1Reg, ClassReg); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch10 = previousInstruction(); - branch10 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpFixedFieldsOutOfBounds = branch10; + jumpFixedFieldsOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin AddR:R: */ genoperandoperand(AddRR, formatReg, Arg1Reg); /* begin AddCq:R: */ @@ -17215,10 +17049,7 @@ jumpFixedFieldsDone = genoperand(Jump, ((sqInt)0)); jmpTarget(jumpIsArray, gCmpRR(Arg1Reg, ClassReg)); /* begin JumpBelowOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch11 = previousInstruction(); - branch11 = genoperand(JumpBelowOrEqual, ((sqInt)0)); - jumpArrayOutOfBounds = branch11; + jumpArrayOutOfBounds = genConditionalBranchoperand(JumpBelowOrEqual, ((sqInt)0)); /* begin AddCq:R: */ /* begin gen:quickConstant:operand: */ operandOne2 = ((usqInt) BaseHeaderSize) >> (shiftForWord()); @@ -17234,12 +17065,10 @@ static sqInt NoDbgRegParms genInnerPrimitiveIdentityHash(sqInt retNoffset) { - AbstractInstruction *branch; AbstractInstruction *jumpImm; AbstractInstruction *jumpNotSet; AbstractInstruction *jumpSI; AbstractInstruction * ret; - AbstractInstruction * self_in_noteFollowingConditionalBranch; jumpImm = genJumpImmediate(ReceiverResultReg); genGetHashFieldNonImmOfasSmallIntegerInto(ReceiverResultReg, TempReg); @@ -17247,10 +17076,7 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(ConstZero, genoperandoperand(CmpCqR, ConstZero, TempReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpZero, ((sqInt)0)); - jumpNotSet = branch; + jumpNotSet = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, TempReg, ReceiverResultReg); /* begin RetN: */ @@ -17282,18 +17108,6 @@ { sqInt address; sqInt address1; - AbstractInstruction *branch; - AbstractInstruction *branch1; - AbstractInstruction *branch10; - AbstractInstruction *branch11; - AbstractInstruction *branch2; - AbstractInstruction *branch3; - AbstractInstruction *branch4; - AbstractInstruction *branch5; - AbstractInstruction *branch6; - AbstractInstruction *branch7; - AbstractInstruction *branch8; - AbstractInstruction *branch9; sqInt byteSizeReg; AbstractInstruction *fillLoop; sqInt fillReg; @@ -17325,18 +17139,6 @@ sqInt quickConstant6; sqInt quickConstant7; sqInt quickConstant8; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - AbstractInstruction * self_in_noteFollowingConditionalBranch1; - AbstractInstruction * self_in_noteFollowingConditionalBranch10; - AbstractInstruction * self_in_noteFollowingConditionalBranch11; - AbstractInstruction * self_in_noteFollowingConditionalBranch2; - AbstractInstruction * self_in_noteFollowingConditionalBranch3; - AbstractInstruction * self_in_noteFollowingConditionalBranch4; - AbstractInstruction * self_in_noteFollowingConditionalBranch5; - AbstractInstruction * self_in_noteFollowingConditionalBranch6; - AbstractInstruction * self_in_noteFollowingConditionalBranch7; - AbstractInstruction * self_in_noteFollowingConditionalBranch8; - AbstractInstruction * self_in_noteFollowingConditionalBranch9; AbstractInstruction *skip; sqInt wordConstant; @@ -17367,25 +17169,16 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant, genoperandoperand(CmpCqR, quickConstant, TempReg)); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpNonZero, ((sqInt)0)); - jumpNotFixedPointers = branch; + jumpNotFixedPointers = genConditionalBranchoperand(JumpNonZero, ((sqInt)0)); genGetRawSlotSizeOfNonImminto(Arg0Reg, TempReg); /* begin CmpCq:R: */ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(InstanceSpecificationIndex + 1, genoperandoperand(CmpCqR, InstanceSpecificationIndex + 1, TempReg)); /* begin JumpLess: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch1 = previousInstruction(); - branch1 = genoperand(JumpLess, ((sqInt)0)); - jumpTooSmall = branch1; + jumpTooSmall = genConditionalBranchoperand(JumpLess, ((sqInt)0)); genGetHashFieldNonImmOfinto(Arg0Reg, halfHeaderReg); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch2 = previousInstruction(); - branch2 = genoperand(JumpZero, ((sqInt)0)); - jumpUnhashed = branch2; + jumpUnhashed = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin PushR: */ genoperand(PushR, ReceiverResultReg); /* begin MoveR:R: */ @@ -17419,36 +17212,24 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant4, genoperandoperand(CmpCqR, quickConstant4, instSpecReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch3 = previousInstruction(); - branch3 = genoperand(JumpZero, ((sqInt)0)); - jumpArrayFormat = branch3; + jumpArrayFormat = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant5 = firstByteFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant5, genoperandoperand(CmpCqR, quickConstant5, instSpecReg)); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch4 = previousInstruction(); - branch4 = genoperand(JumpZero, ((sqInt)0)); - jumpByteFormat = branch4; + jumpByteFormat = genConditionalBranchoperand(JumpZero, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant6 = firstLongFormat(); /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant6, genoperandoperand(CmpCqR, quickConstant6, instSpecReg)); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch5 = previousInstruction(); - branch5 = genoperand(JumpNonZero, ((sqInt)0)); - jumpFailCuzFixed = branch5; + jumpFailCuzFixed = genConditionalBranchoperand(JumpNonZero, ((sqInt)0)); /* begin CmpCq:R: */ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(((maxSlots << 1) | 1), genoperandoperand(CmpCqR, ((maxSlots << 1) | 1), Arg0Reg)); /* begin JumpAbove: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch6 = previousInstruction(); - branch6 = genoperand(JumpAbove, ((sqInt)0)); - jumpLongTooBig = branch6; + jumpLongTooBig = genConditionalBranchoperand(JumpAbove, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, TempReg, instSpecReg); /* begin PushCq: */ @@ -17458,10 +17239,7 @@ jumpLongPrepDone = genoperand(Jump, ((sqInt)0)); jmpTarget(jumpByteFormat, gCmpCqR((((maxSlots * BytesPerWord) << 1) | 1), Arg0Reg)); /* begin JumpAbove: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch7 = previousInstruction(); - branch7 = genoperand(JumpAbove, ((sqInt)0)); - jumpByteTooBig = branch7; + jumpByteTooBig = genConditionalBranchoperand(JumpAbove, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, TempReg, instSpecReg); /* begin MoveCq:R: */ @@ -17489,10 +17267,7 @@ jumpBytePrepDone = genoperand(Jump, ((sqInt)0)); jmpTarget(jumpArrayFormat, gCmpCqR(((maxSlots << 1) | 1), Arg0Reg)); /* begin JumpAbove: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch8 = previousInstruction(); - branch8 = genoperand(JumpAbove, ((sqInt)0)); - jumpArrayTooBig = branch8; + jumpArrayTooBig = genConditionalBranchoperand(JumpAbove, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, TempReg, instSpecReg); /* begin PushCw: */ @@ -17509,10 +17284,7 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(0, genoperandoperand(CmpCqR, 0, byteSizeReg)); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch9 = previousInstruction(); - branch9 = genoperand(JumpNonZero, ((sqInt)0)); - jumpHasSlots = branch9; + jumpHasSlots = genConditionalBranchoperand(JumpNonZero, ((sqInt)0)); /* begin MoveCq:R: */ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(BaseHeaderSize * 2, genoperandoperand(MoveCqR, BaseHeaderSize * 2, byteSizeReg)); @@ -17538,10 +17310,7 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant8, genoperandoperand(CmpCqR, quickConstant8, byteSizeReg)); /* begin JumpAboveOrEqual: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch10 = previousInstruction(); - branch10 = genoperand(JumpAboveOrEqual, ((sqInt)0)); - jumpNoSpace = branch10; + jumpNoSpace = genConditionalBranchoperand(JumpAboveOrEqual, ((sqInt)0)); /* begin MoveR:R: */ genoperandoperand(MoveRR, Arg1Reg, ReceiverResultReg); /* begin MoveR:Aw: */ @@ -17570,10 +17339,7 @@ /* begin CmpR:R: */ genoperandoperand(CmpRR, Arg1Reg, byteSizeReg); /* begin JumpAbove: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch11 = previousInstruction(); - branch11 = genoperand(JumpAbove, ((sqInt)fillLoop)); - branch11; + genConditionalBranchoperand(JumpAbove, ((sqInt)fillLoop)); /* begin RetN: */ genoperand(RetN, retNoffset); jmpTarget(jumpNoSpace, gPopR(TempReg)); @@ -17603,14 +17369,6 @@ { sqInt address; sqInt address1; - AbstractInstruction *branch; - AbstractInstruction *branch1; - AbstractInstruction *branch2; - AbstractInstruction *branch3; - AbstractInstruction *branch4; - AbstractInstruction *branch5; - AbstractInstruction *branch6; - AbstractInstruction *branch7; sqInt byteSizeReg; AbstractInstruction *fillLoop; sqInt fillReg; @@ -17635,14 +17393,6 @@ sqInt quickConstant6; sqInt quickConstant7; sqInt quickConstant8; - AbstractInstruction * self_in_noteFollowingConditionalBranch; - AbstractInstruction * self_in_noteFollowingConditionalBranch1; - AbstractInstruction * self_in_noteFollowingConditionalBranch2; - AbstractInstruction * self_in_noteFollowingConditionalBranch3; - AbstractInstruction * self_in_noteFollowingConditionalBranch4; - AbstractInstruction * self_in_noteFollowingConditionalBranch5; - AbstractInstruction * self_in_noteFollowingConditionalBranch6; - AbstractInstruction * self_in_noteFollowingConditionalBranch7; AbstractInstruction *skip; @@ -17671,25 +17421,16 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant, genoperandoperand(CmpCqR, quickConstant, TempReg)); /* begin JumpNonZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch = previousInstruction(); - branch = genoperand(JumpNonZero, ((sqInt)0)); - jumpNotFixedPointers = branch; + jumpNotFixedPointers = genConditionalBranchoperand(JumpNonZero, ((sqInt)0)); genGetRawSlotSizeOfNonImminto(Arg0Reg, TempReg); /* begin CmpCq:R: */ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(InstanceSpecificationIndex + 1, genoperandoperand(CmpCqR, InstanceSpecificationIndex + 1, TempReg)); /* begin JumpLess: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch1 = previousInstruction(); - branch1 = genoperand(JumpLess, ((sqInt)0)); - jumpTooSmall = branch1; + jumpTooSmall = genConditionalBranchoperand(JumpLess, ((sqInt)0)); genGetHashFieldNonImmOfinto(Arg0Reg, halfHeaderReg); /* begin JumpZero: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch2 = previousInstruction(); - branch2 = genoperand(JumpZero, ((sqInt)0)); - jumpUnhashed = branch2; + jumpUnhashed = genConditionalBranchoperand(JumpZero, ((sqInt)0)); genLoadSlotsourceRegdestReg(InstanceSpecificationIndex, Arg0Reg, instSpecReg); jumpBadFormat = genJumpNotSmallIntegerscratchReg(instSpecReg, TempReg); genConvertSmallIntegerToIntegerInReg(instSpecReg); @@ -17711,19 +17452,13 @@ /* begin gen:quickConstant:operand: */ checkQuickConstantforInstruction(quickConstant4, genoperandoperand(CmpCqR, quickConstant4, TempReg)); /* begin JumpAbove: */ - /* begin noteFollowingConditionalBranch: */ - self_in_noteFollowingConditionalBranch3 = previousInstruction(); - branch3 = genoperand(JumpAbove, ((sqInt)0)); - jumpVariableOrEphemeron = branch3; + jumpVariableOrEphemeron = genConditionalBranchoperand(JumpAbove, ((sqInt)0)); /* begin CmpCq:R: */ quickConstant5 = numSlotsMask(); @@ Diff output truncated at 50000 characters. @@

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Vm-dev December 2015