Vm-dev March 2015

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VM Maker: Cog-eem.255.mcz
by commits＠source.squeak.org 28 Mar '15

28 Mar '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.255.mcz ==================== Summary ==================== Name: Cog-eem.255 Author: eem Time: 28 March 2015, 1:30:14.558 pm UUID: 87ca5f19-8aeb-4c97-b111-3d67ea88e11a Ancestors: Cog-eem.254 Include the offset in the relevant addressing modes in load and store exceptions in the ARM alien. =============== Diff against Cog-eem.254 =============== Item was changed: ----- Method: GdbARMAlien>>handleFailingLoadStore:at: (in category 'error handling') ----- handleFailingLoadStore: instr at: pc + | baseReg destReg srcReg offset | - | baseReg destReg srcReg | baseReg := self registerStateGetters at: (instr >> 16 bitAnd: 15)+ 1. destReg := self registerStateSetters at: (instr >> 12 bitAnd: 15) + 1. srcReg := self registerStateGetters at: (instr >> 12 bitAnd: 15) + 1. + "See e.g. A5.2.2/A5-20 ARM ARM v6" + offset := (instr >> 21 bitAnd: 2r1111001) = 2r0101000 + ifTrue: + [(instr >> 23 anyMask: 1) "U bit" + ifTrue: [instr bitAnd: 16rFFF] + ifFalse: [(instr bitAnd: 16rFFF) negated]] + ifFalse: + [0]. (self instructionIsLDR: instr) ifTrue: [^(ProcessorSimulationTrap pc: pc nextpc: pc + 4 + address: (self perform: baseReg) + offset - address: (self perform: baseReg) type: #read accessor: destReg) signal]. (self instructionIsSTR: instr) ifTrue: [^(ProcessorSimulationTrap pc: pc nextpc: pc + 4 + address: (self perform: baseReg) + offset - address: (self perform: baseReg) type: #write accessor: srcReg) signal]. "Lars handled byte read/write failures. i don't think we need to" "(self instructionIsLDRB: instr) ifTrue: [??]. (self instructionIsSTRB: instr) ifTrue: [??]." self error: 'handleFailingLoadStore:at: invoked for non-load/store?'!

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VM Maker: Cog-eem.254.mcz
by commits＠source.squeak.org 28 Mar '15

28 Mar '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.254.mcz ==================== Summary ==================== Name: Cog-eem.254 Author: eem Time: 28 March 2015, 12:38:17.653 pm UUID: b39ba7f7-4c90-4f69-ad6b-4302b529111a Ancestors: Cog-tpr.253 Rewrite GdbARMAlien>>handleExecutionPrimitiveFailureIn:minimumAddress: to be simpler and faster, using the endCondition to identify call, jump and return traps. No longer extract addresses from previous instructions (which presumes a code generation stategy), but access the underlying register state. This is a RSISC after all! Rename registerStateNames to registerStateGetters to accord with the IA32 Alien. =============== Diff against Cog-tpr.253 =============== Item was changed: ----- Method: GdbARMAlien>>decorateDisassembly:for:fromAddress: (in category 'disassembly') ----- decorateDisassembly: anInstructionString for: aSymbolManager fromAddress: address | word opcode rotate mode operand | word := aSymbolManager objectMemory longAt: address. (self instructionIsAnyB: word) ifTrue: [operand := word bitAnd: 16rFFFFFF. (operand anyMask: 16r800000) ifTrue: [operand := operand - 16r1000000]. operand := operand * 4 + address + 8 bitAnd: aSymbolManager addressSpaceMask] ifFalse: + [((self instructionIsAnyLoadStore: word) + and: [(word >> 16 bitAnd: 15) = CogARMCompiler VarBaseReg]) + ifTrue: + [operand := aSymbolManager varBaseAddress + (word bitAnd: 1 << 12 - 1)] + ifFalse: + [opcode := word >> 21 bitAnd: 16rF. + opcode ~= CogARMCompiler orOpcode ifTrue: + [^anInstructionString]. + rotate := word >> 8 bitAnd: 16rF. + mode := word >> 25 bitAnd: 7. + "CogARMCompiler always uses a 0 rotate in the last operand of the final ORR when building long constants." + (mode = 1 and: [rotate ~= 0]) ifTrue: + [^anInstructionString]. + operand := aSymbolManager backEnd literalBeforeFollowingAddress: address + 4]]. - [opcode := word >> 21 bitAnd: 16rF. - opcode ~= CogARMCompiler orOpcode ifTrue: - [^anInstructionString]. - rotate := word >> 8 bitAnd: 16rF. - mode := word >> 25 bitAnd: 7. - "CogARMCompiler always uses a 0 rotate in the last operand of the final ORR when building long constants." - (mode = 1 and: [rotate ~= 0]) ifTrue: - [^anInstructionString]. - operand := aSymbolManager backEnd literalBeforeFollowingAddress: address + 4]. "is there an intersting address with this?" ^(aSymbolManager lookupAddress: operand) ifNotNil: [:string| anInstructionString, ' = ', (operand printStringRadix: 16), ' = ', string] ifNil: [anInstructionString, ' = ', (operand printStringRadix: 16)]! Item was removed: - ----- Method: GdbARMAlien>>handleCallFailureAt:in: (in category 'error handling') ----- - handleCallFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a call into a ProcessorSimulationTrap signal." - | callAddress failedInstruction| - "grab the instruction at issue" - failedInstruction := memoryArray unsignedLongAt: pc + 1 bigEndian: false. - (self instructionIsBL: failedInstruction) - ifFalse:[self halt]. - "short jump via BL, therefore we have a 24bit signed integer offset" - callAddress := (pc + 8 + (self extractOffsetFromBL: failedInstruction)). - - ^(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: callAddress signedIntToLong - type: #call) - signal! Item was changed: ----- Method: GdbARMAlien>>handleExecutionPrimitiveFailureIn:minimumAddress: (in category 'error handling') ----- handleExecutionPrimitiveFailureIn: memoryArray "<Bitmap|ByteArray>" minimumAddress: minimumAddress "<Integer>" "Handle an execution primitive failure. Convert out-of-range call and absolute memory read into register instructions into ProcessorSimulationTrap signals." "self printRegistersOn: Transcript" + | pcOnEntry pc instr | - | pcOnEntry pc | pcOnEntry := self pc. self endCondition = InstructionPrefetchError ifTrue: [self pc: self priorPc]. + ((pc := self pc) between: minimumAddress and: memoryArray byteSize - 1) ifTrue: + [instr := memoryArray unsignedLongAt: pc + 1 bigEndian: false. + + (self endCondition = InstructionPrefetchError) ifTrue: + [^self handleFailingBranch: instr to: pcOnEntry at: pc]. + + (self instructionIsAnyLoadStore: instr) ifTrue: + [^self handleFailingLoadStore: instr at: pc]. + + ^self handleExecutionPrimitiveFailureAt: pc in: memoryArray]. + - [(self instructionTypeAt: pc in: memoryArray) - caseOf: { - [#Call] -> [^self handleCallFailureAt: pc in: memoryArray]. - [#LongCall] -> [^self handleLongCallFailureAt: pc in: memoryArray]. - [#Jump] -> [^self handleJmpFailureAt: pc in: memoryArray]. - [#LongJump] -> [^self handleLongJmpFailureAt: pc in: memoryArray]. - [#MoveAwR] -> [^self handleMoveAwRFailureAt: pc in: memoryArray]. - [#MoveMbrR] -> [^self handleMoveMbrRFailureAt: pc in: memoryArray]. - [#MoveRAw] -> [^self handleMoveRAwFailureAt: pc in: memoryArray]. - [#MoveRMbr] -> [^self handleMoveRMbrFailureAt: pc in: memoryArray]. - [#Ret] -> [^self handleRetFailureAt: pc in: memoryArray].} - otherwise: [^self handleExecutionPrimitiveFailureAt: pc in: memoryArray]]. ^self reportPrimitiveFailure! Item was added: + ----- Method: GdbARMAlien>>handleFailingBranch:to:at: (in category 'error handling') ----- + handleFailingBranch: instr to: address at: pc + (self instructionIsBL: instr) ifTrue: + [self assert: address = (pc + 8 + (self extractOffsetFromBL: instr)) signedIntToLong. + ^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 4 + address: (pc + 8 + (self extractOffsetFromBL: instr)) signedIntToLong + type: #call) + signal]. + (self instructionIsBLX: instr) ifTrue: + [self assert: address = (self perform: (self registerStateGetters at: (instr bitAnd: 15) + 1)). + ^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 4 + address: (self perform: (self registerStateGetters at: (instr bitAnd: 15) + 1)) + type: #call) + signal]. + (self instructionIsBX: instr) ifTrue: + [self assert: address = (self perform: (self registerStateGetters at: (instr bitAnd: 15) + 1)). + ^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 4 + address: (self perform: (self registerStateGetters at: (instr bitAnd: 15) + 1)) + type: #jump) + signal]. + (self instructionIsB: instr) ifTrue: + [self assert: address = (pc + 8 + (self extractOffsetFromBL: instr)) signedIntToLong. + ^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 4 + address: (pc + 8 + (self extractOffsetFromBL: instr)) signedIntToLong + type: #jump) + signal]. + (self instructionIsReturnViaLR: instr) ifTrue: + [^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 4 + address: self lr + type: #return) + signal]. + ^self reportPrimitiveFailure! Item was added: + ----- Method: GdbARMAlien>>handleFailingLoadStore:at: (in category 'error handling') ----- + handleFailingLoadStore: instr at: pc + | baseReg destReg srcReg | + baseReg := self registerStateGetters at: (instr >> 16 bitAnd: 15)+ 1. + destReg := self registerStateSetters at: (instr >> 12 bitAnd: 15) + 1. + srcReg := self registerStateGetters at: (instr >> 12 bitAnd: 15) + 1. + (self instructionIsLDR: instr) ifTrue: + [^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 4 + address: (self perform: baseReg) + type: #read + accessor: destReg) + signal]. + (self instructionIsSTR: instr) ifTrue: + [^(ProcessorSimulationTrap + pc: pc + nextpc: pc + 4 + address: (self perform: baseReg) + type: #write + accessor: srcReg) + signal]. + "Lars handled byte read/write failures. i don't think we need to" + "(self instructionIsLDRB: instr) ifTrue: + [??]. + (self instructionIsSTRB: instr) ifTrue: + [??]." + self error: 'handleFailingLoadStore:at: invoked for non-load/store?'! Item was removed: - ----- Method: GdbARMAlien>>handleJmpFailureAt:in: (in category 'error handling') ----- - handleJmpFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a jump into a ProcessorSimulationTrap signal." - | callAddress failedInstruction| - "grab the instruction at issue" - failedInstruction := memoryArray unsignedLongAt: pc + 1 bigEndian: false. - (self instructionIsB: failedInstruction) - ifFalse:[self halt]. - "short jump via B, therefore we have a 24bit signed integer offset" - callAddress := (pc + 8 + (self extractOffsetFromBL: failedInstruction)). - - ^(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: callAddress signedIntToLong - type: #jump) - signal! Item was removed: - ----- Method: GdbARMAlien>>handleLongCallFailureAt:in: (in category 'error handling') ----- - handleLongCallFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a long call into a ProcessorSimulationTrap signal." - | callAddress failedInstruction| - "grab the instruction at issue" - failedInstruction := memoryArray unsignedLongAt: pc + 1 bigEndian: false. - "Hmm. Perhaps we ought to test for an actual BLX here rather than assuming?" - (self instructionIsBLX: failedInstruction) - ifFalse:[ self halt: 'failed call type test']. - "The memoryArray starts indexing from 1, whereas the pc is based on 0-indexing, therefore all access-offsets are one greater than expected" - "address, combined from prior four MOV/ORR instructions. See CogARMCompiler>concretizeLongCall" - callAddress := (memoryArray byteAt: pc -3) - + ((memoryArray byteAt: pc - 7) << 8) - + ((memoryArray byteAt: pc - 11) << 16) - + ((memoryArray byteAt: pc - 15) << 24). - ^(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: callAddress signedIntToLong - type: #call) - signal! Item was removed: - ----- Method: GdbARMAlien>>handleLongJmpFailureAt:in: (in category 'error handling') ----- - handleLongJmpFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a long jump into a ProcessorSimulationTrap signal." - | callAddress failedInstruction| - "grab the instruction at issue" - failedInstruction := memoryArray unsignedLongAt: pc + 1 bigEndian: false. - "Hmm. Perhaps we ought to test for an actual BX here rather than assuming?" - (self instructionIsBX: failedInstruction) - ifFalse:[ self halt: 'failed call type test']. - "The memoryArray starts indexing from 1, whereas the pc is based on 0-indexing, therefore all access-offsets are one greater than expected" - "address, combined from prior four MOV/ORR instructions. See CogARMCompiler>concretizeLongCall" - callAddress := (memoryArray byteAt: pc -3) - + ((memoryArray byteAt: pc - 7) << 8) - + ((memoryArray byteAt: pc - 11) << 16) - + ((memoryArray byteAt: pc - 15) << 24). - ^(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: callAddress signedIntToLong - type: #jump) - signal! Item was removed: - ----- Method: GdbARMAlien>>handleMoveAwRFailureAt:in: (in category 'error handling') ----- - handleMoveAwRFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a register load from an Address into a ProcessorSimulationTrap signal." - ((memoryArray byteAt: pc + 4) = 16rE5 "test for 0xE59X as the most significant two bytes - X being the index of the RISCTempReg (or 0xA in current code). - LDR Rx, [RiscTempReg, #0]" - and: [(memoryArray byteAt: pc + 3) = (16r90 + CogARMCompiler ARMTempReg)]) - ifTrue: - [(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: (memoryArray byteAt: pc -3) "address, combined from prior four MOV/ORR instructions. See CogARMCompiler>concretizeMoveAwR" - + ((memoryArray byteAt: pc - 7) << 8) - + ((memoryArray byteAt: pc - 11) << 16) - + ((memoryArray byteAt: pc - 15) << 24) - type: #read - accessor: (self registerStateSetters at: ("destination register" (memoryArray byteAt: pc + 2) >> 4) + 1)) - signal] - ifFalse: - [self reportPrimitiveFailure]! Item was removed: - ----- Method: GdbARMAlien>>handleMoveMbrRFailureAt:in: (in category 'error handling') ----- - handleMoveMbrRFailureAt: pc in: memoryArray - "Convert an execution primitive failure for a byte register load into a ProcessorSimulationTrap signal." - "generated by MoveMbrR" - "might be ldrb destReg, [srcReg, #immediate] or ldrb destReg, [srcReg, RISCTempReg] " - - "first test for ldrb destReg, [srcReg, RISCTempReg] - -test for 0xE7DX as the most significant three nibbles" - ((memoryArray byteAt: pc + 4) = 16rE7 and: [(memoryArray byteAt: pc + 3) >> 4 = 13]) - ifTrue: [(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: (memoryArray byteAt: pc - 3) - + ((memoryArray byteAt: pc - 7) - << 8) + ((memoryArray byteAt: pc - 11) - << 16) + ((memoryArray byteAt: pc - 15) - << 24) - type: #read - accessor: ("work out the dest register name"self registerStateSetters at: (memoryArray byteAt: pc + 2) >> 4 + 1)) signal - ] - ifFalse: [self reportPrimitiveFailure]! Item was removed: - ----- Method: GdbARMAlien>>handleMoveRAwFailureAt:in: (in category 'error handling') ----- - handleMoveRAwFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a register write into Memory at a predefined address into a ProcessorSimulationTrap signal." - "LEA RISCTempReg - str srcReg, [RISCTempReg]" - "first we check this is a str r?, [sl]" - ^((memoryArray byteAt: pc + 4) = 16rE5 - and: [(memoryArray byteAt: pc + 3) = (16r80 + CogARMCompiler ARMTempReg)]) - ifTrue: - [(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: (memoryArray byteAt: pc -3) - + ((memoryArray byteAt: pc - 7) << 8) - + ((memoryArray byteAt: pc - 11) << 16) - + ((memoryArray byteAt: pc - 15) <<24) - type: #write - accessor: ("work out the dest register name" self registerStateNames at: ((memoryArray byteAt: pc + 2) >> 4) + 1)) - signal] - ifFalse: - [self reportPrimitiveFailure]! Item was removed: - ----- Method: GdbARMAlien>>handleMoveRMbrFailureAt:in: (in category 'error handling') ----- - handleMoveRMbrFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a byte register write into a ProcessorSimulationTrap signal." - "generated by MoveRMbr" - - "might be strb destReg, [srcReg, #immediate] or strb destReg, [srcReg, RISCTempReg] " - - "first test for ldrb destReg, [srcReg, RISCTempReg] - -test for 0xE7CX as the most significant three nibbles" - ((memoryArray byteAt: pc + 4) = 16rE7 and: [(memoryArray byteAt: pc + 3) >> 4 = 16rC]) - ifTrue: [(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: (memoryArray byteAt: pc - 3) - + ((memoryArray byteAt: pc - 7) - << 8) + ((memoryArray byteAt: pc - 11) - << 16) + ((memoryArray byteAt: pc - 15) - << 24) - type: #write - accessor: ("work out the dest register name"self registerStateNames at: (memoryArray byteAt: pc + 2) >> 4 + 1)) signal - ] - ifFalse: - [self reportPrimitiveFailure]! Item was removed: - ----- Method: GdbARMAlien>>handleRetFailureAt:in: (in category 'error handling') ----- - handleRetFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Convert an execution primitive failure for a ret into a ProcessorSimulationTrap signal." - ^(ProcessorSimulationTrap - pc: pc - nextpc: pc + 4 - address: self lr - type: #return) - signal! Item was added: + ----- Method: GdbARMAlien>>instructionIsAnyLoadStore: (in category 'testing') ----- + instructionIsAnyLoadStore: instr + "is this any of the LDR,STR instructions?" + ^(instr >> 24 bitAnd: 15) = 5! Item was removed: - ----- Method: GdbARMAlien>>instructionIsLDR:byReg: (in category 'testing') ----- - instructionIsLDR: instr byReg: rn - "is this a LDR r1, [r2, rn] instruction? Special case to detect MoveAwR case" - | foo | - ^instr >> 28 < 16rF "test for allowed condcode - 0xF is extension" and: [foo := (instr >> 20 bitAnd: 16rFF). foo = 16r59 and:[(instr >>16 bitAnd: 16rF) = rn]]! Item was removed: - ----- Method: GdbARMAlien>>instructionIsSTR:byReg: (in category 'testing') ----- - instructionIsSTR: instr byReg: rn - "is this a STR r1, [r2, rn] instruction? Special case to detect MoveRAw case" - | foo | - ^instr >> 28 < 16rF "test for allowed condcode - 0xF is extension" and: [foo := (instr >> 20 bitAnd: 16rFF). foo = 16r58 and:[(instr >>16 bitAnd: 16rF) = rn]]! Item was removed: - ----- Method: GdbARMAlien>>instructionTypeAt:in: (in category 'error handling') ----- - instructionTypeAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" - "Identify which type of instruction is at pc in memoryArray. For the time being, only those instructions needed for PrimitiveFailure are identified." - | RISCTempReg lastInstruction typeOperandStatus | - RISCTempReg := CogARMCompiler ARMTempReg. - lastInstruction := memoryArray unsignedLongAt: pc + 1 bigEndian: false . - "self disassembleFrom: pc - 16 to: pc + 11 in: memoryArray on: Transcript cr" - - "Ret" - (self instructionIsReturnViaLR: lastInstruction ) ifTrue: [^#Ret]. - - "Call" - (self instructionIsBL: lastInstruction) ifTrue: [^#Call]. - "long call" - (self instructionIsBLX: lastInstruction) ifTrue: [^#LongCall]. - - - "Jump" - (self instructionIsB: lastInstruction) ifTrue: [^#Jump]. - "long Jump" - (self instructionIsBX: lastInstruction) ifTrue: [^#LongJump]. - - typeOperandStatus := lastInstruction >> 20 bitAnd: 16rFF. - "MoveRMbr" - (self instructionIsSTRB: lastInstruction) ifTrue: [^#MoveRMbr]. - - "MoveRAw" - (self instructionIsSTR: lastInstruction byReg: RISCTempReg) ifTrue: [^#MoveRAw]. - - "MoveMbrR" - (self instructionIsLDRB: lastInstruction) ifTrue: [^#MoveMbrR]. - - "MoveAwR" - (self instructionIsLDR: lastInstruction byReg: RISCTempReg) ifTrue: [^#MoveAwR]. - - - ^#UnidentifiedInstruction! Item was changed: ----- Method: GdbARMAlien>>postCallArgumentsNumArgs:in: (in category 'execution') ----- postCallArgumentsNumArgs: numArgs "<Integer>" in: memory "<ByteArray|Bitmap>" "Answer an argument vector of the requested size after a vanilla ABI call. For ARM the Procedure Calling Specification can be found in IHI0042D_aapcs.pdf. On ARM this typically means accessing r0 through r3 and fetching additional arguments from the stack, acording to pages 20f. aapcs. We assume that all arguments are single word arguments, which can not be supplied on co-processor-registers. For compatibility with Cog/Slang we answer unsigned values." ^(1 to: numArgs) collect: [:i | i < 5 + ifTrue: [self perform: (self registerStateGetters at: i)] - ifTrue: [self perform: (self registerStateNames at: i)] "ARM uses a full descending stack. Directly after calling a procedure, nothing but the arguments are pushed." ifFalse: [memory unsignedLongAt: self sp + (i-5)*4 bigEndian: false]].! Item was changed: ----- Method: GdbARMAlien>>printOn: (in category 'printing') ----- printOn: aStream aStream nextPutAll: 'an ARMAlien('. + self registerState allButLast with: self registerStateGetters allButLast do: [ :state :i | - self registerState allButLast with: self registerStateNames allButLast do: [ :state :i | aStream << i << ': ' << (state abs > 15 ifTrue: [state hex] ifFalse: [state asString]) << ', ']. aStream << 'NZCVIF: ' << (self registerState last printStringBase: 2 length: 6 padded: true) << ')'.! Item was changed: ----- Method: GdbARMAlien>>r10 (in category 'accessing') ----- r10 + ^self unsignedLongAt: 53! - ^self sl! Item was changed: ----- Method: GdbARMAlien>>r10: (in category 'accessing') ----- r10: anUnsignedInteger + ^self unsignedLongAt: 53 put: anUnsignedInteger! - ^self sl: anUnsignedInteger! Item was changed: ----- Method: GdbARMAlien>>registerAt: (in category 'accessing') ----- registerAt: index + ^self perform: (self registerStateGetters at: index + 1)! - ^self perform: (self registerStateNames at: index + 1)! Item was added: + ----- Method: GdbARMAlien>>registerStateGetters (in category 'accessing-abstract') ----- + registerStateGetters + ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 sp lr pc eflags)! Item was removed: - ----- Method: GdbARMAlien>>registerStateNames (in category 'accessing-abstract') ----- - registerStateNames - ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 sp lr pc eflags)!

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VM Maker: VMMaker.oscog-tpr.1126.mcz
by commits＠source.squeak.org 28 Mar '15

28 Mar '15

tim Rowledge uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1126.mcz ==================== Summary ==================== Name: VMMaker.oscog-tpr.1126 Author: tpr Time: 27 March 2015, 7:18:08.438 pm UUID: beeacd84-5c81-496d-b734-2da3371e344e Ancestors: VMMaker.oscog-eem.1125 Add an improved constant generator that can deal with consts like 0x3FFFF where it can be made fro m0xFFFFFFFF shifted right a few places. This saves several instructions in some important places. =============== Diff against VMMaker.oscog-eem.1125 =============== Item was changed: CogAbstractInstruction subclass: #CogARMCompiler instanceVariableNames: 'cond' + classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveNotOpcode MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode' - classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode' poolDictionaries: '' category: 'VMMaker-JIT'! !CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0! I generate ARM instructions from CogAbstractInstructions. For reference see http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architectur… The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw). This class does not take any special action to flush the instruction cache on instruction-modification.! Item was changed: ----- Method: CogARMCompiler class>>initialize (in category 'class initialization') ----- initialize "Initialize various ARM instruction-related constants." "CogARMCompiler initialize" | specificOpcodes refs | super initialize. self ~~ CogARMCompiler ifTrue: [^self]. R0 := 0. R1 := 1. R2 := 2. R3 := 3. R4 := 4. R5 := 5. R6 := 6. R7 := 7. R8 := 8. R9 := 9. R10 := 10. R11 := 11. R12 := 12.. SP := 13.. LR := 14. PC := 15. CArg0Reg := 0. CArg1Reg := 1. CArg2Reg := 2. CArg3Reg := 3. RISCTempReg := R10. "Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1" EQ := 0. NE := 1. CS := 2. CC := 3. MI := 4. PL := 5. VS := 6. VC := 7. HI := 8. LS := 9. GE := 10. LT := 11. GT := 12. LE := 13. AL := 14. AddOpcode := 4. AndOpcode := 0. BicOpcode := 14. CmpOpcode := 10. MoveOpcode := 13. OrOpcode := 12. RsbOpcode := 3. SubOpcode := 2. XorOpcode := 1. SMLALOpcode := 7. + MoveNotOpcode := 15. CPSRReg := 16. OverflowFlag := 1 << 28. "Specific instructions" LastRTLCode isNil ifTrue: [CogRTLOpcodes initialize]. specificOpcodes := #(SMULL MSR MRS LDMFD STMFD BICCqR). refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect: [:ea| ea key]. (classPool keys reject: [:k| (specificOpcodes includes: k) or: [refs includes: k]]) do: [:k| Undeclared declare: k from: classPool]. specificOpcodes withIndexDo: [:classVarName :value| self classPool declare: classVarName from: Undeclared; at: classVarName put: value + LastRTLCode - 1]! Item was added: + ----- Method: CogARMCompiler>>ands:rn:rm:lsr: (in category 'ARM convenience instructions') ----- + ands: destReg rn: srcReg rm: addReg lsr: shft + "return an ANDS destReg, srcReg, addReg lsl #shft" + "important detail - a 0 shft requires setting the shift-type code to 0 to avoid potential instruction confusion" + shft = 0 + ifTrue:[^self type: 0 op: AndOpcode set: 1 rn: srcReg rd: destReg shifterOperand: addReg] + ifFalse:[^self type: 0 op: AndOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((shft <<7 bitOr: 32) bitOr: addReg)]! Item was changed: ----- Method: CogARMCompiler>>concretizeAndCqR (in category 'generate machine code - concretize') ----- concretizeAndCqR "Will get inlined into concretizeAt: switch." + "AND is very important since it's used to mask all sorts of flags in the jit. We take special care to try to find fast ways to make the masks" <inline: true> + |val| + val := operands at: 0. + self rotateable8bitImmediate: val - self rotateable8bitImmediate: (operands at: 0) ifTrue: [ :rot :immediate | | reg | reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self ands: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: [ "see if the constant bit-inverted makes a quick value and if so BIC it instead If the value is -ve, we 2s complement it instead" + |invVal| + val <0 + ifTrue:[invVal := -1 - val] + ifFalse:[invVal := val bitInvert32]. + self rotateable8bitImmediate: invVal - |val| - val := operands at: 0. - val <0 ifTrue:[val := -1 - val] ifFalse:[val := val bitInvert32]. - self rotateable8bitImmediate: val ifTrue: [ :rot :immediate | |reg| reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self bics: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] + ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF" + |hb reg| + reg := self concreteRegister: (operands at: 1). + hb := (operands at: 0) highBit. + 1 << hb = (val +1) + ifTrue: [ "MVN temp reg, 0, making 0xffffffff" + self machineCodeAt: 0 put:(self mvn: RISCTempReg imm: 0 ror: 0). + "Then AND reg, temp reg, lsr #(32-hb)" + self machineCodeAt: 4 put:(self ands: reg rn: reg rm: RISCTempReg lsr: (32-hb )). + ^machineCodeSize :=8] + ifFalse: [^self concretizeDataOperationCwR: AndOpcode]]]! - ifFalse: [^self concretizeDataOperationCwR: 0]]! Item was added: + ----- Method: CogARMCompiler>>mvn:imm:ror: (in category 'ARM convenience instructions') ----- + mvn: destReg imm: immediate8bitValue ror: rot + "Remember the ROR is doubled by the cpu so use 30>>1 etc. + MVN destReg, #immediate8BitValue ROR rot" + ^self type: 1 op: MoveNotOpcode set: 0 rn: 0 rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)!

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musing on thread immutability
by Ben Coman 27 Mar '15

27 Mar '15

Just a random idea that been floating in my head for a few weeks... As I understand it, with Spur we can now have immutable objects. I guess this will help when a functional style programming may be useful (such as background tasks). Newly designed applications might make good use of this, but I am wondering about where you might have a large existing code base (e.g. Squeak/Pharo) and you want to background some small part of the existing code. A great effort would be needed to dig deep into object composition to understand how disparate parts of the system may hold references to object internals several layers down, that may get updated unexpectedly. So I am wondering if instead / or as well as object-immutability it is feasible to get thread-immutability, meaning: * writing to any object state is prevented - which prevents the background thread changing the foreground (UI) state unexpectedly; and/or * reading or writing any object automatically sets its immutability bit - which prevents other unknown threads changing the state the background thread has come to rely on. No doubt pushing any existing single-threaded code into such a background immutable-thread will cause immutablity-write-errors - but the advantage is that such conflicts are brought to light rather than biting you from the shadows. cheers -ben

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VM Maker: Cog-tpr.253.mcz
by commits＠source.squeak.org 26 Mar '15

26 Mar '15

tim Rowledge uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-tpr.253.mcz ==================== Summary ==================== Name: Cog-tpr.253 Author: tpr Time: 26 March 2015, 3:32:27.212 pm UUID: 4619166e-331d-4725-85f3-124619991442 Ancestors: Cog-eem.252 convert various methods to refer to 'sl' instead of 'r10' since that is what we print out in debugging messages. Clean up a couple of alien tests =============== Diff against Cog-eem.252 =============== Item was changed: ----- Method: GdbARMAlien>>integerRegisterState (in category 'accessing-abstract') ----- integerRegisterState ^{ self r0. self r1. self r2. self r3. self r4. self r5. self r6. self r7. self r8. + self r9. self sl. self fp. self r12. self sp. self lr. self pc}! - self r9. self r10. self fp. self r12. self sp. self lr. self pc}! Item was removed: - ----- Method: GdbARMAlien>>postTrapCorrectedPC (in category 'accessing') ----- - postTrapCorrectedPC - "return the pc - 8 for trap handling - remember the ARM alwayshas that funky +8 offset vs the actual instruction running/failig" - ^self pc -8! Item was changed: ----- Method: GdbARMAlien>>printRegisterState:on: (in category 'printing') ----- printRegisterState: registerStateVector on: aStream self printFields: #( r0 r1 r2 r3 cr r4 r5 r6 r7 cr + r8 r9 sl fp cr - r8 r9 r10 fp cr r12 sp lr pc eflags cr) inRegisterState: registerStateVector on: aStream! Item was changed: ----- Method: GdbARMAlien>>printRegisterStateExceptPC:on: (in category 'printing') ----- printRegisterStateExceptPC: registerStateVector on: aStream self printFields: #( r0 r1 r2 r3 cr r4 r5 r6 r7 cr + r8 r9 sl fp cr - r8 r9 r10 fp cr r12 sp lr eflags cr) inRegisterState: registerStateVector on: aStream! Item was added: + ----- Method: GdbARMAlien>>priorPc: (in category 'accessing') ----- + priorPc: val + "set the priorPC cached pc so it isn't random nonsense" + ^self unsignedLongAt: 609 put: val! Item was changed: ----- Method: GdbARMAlien>>r10 (in category 'accessing') ----- r10 + ^self sl! - ^self unsignedLongAt: 53! Item was changed: ----- Method: GdbARMAlien>>r10: (in category 'accessing') ----- r10: anUnsignedInteger + ^self sl: anUnsignedInteger! - ^self unsignedLongAt: 53 put: anUnsignedInteger! Item was changed: ----- Method: GdbARMAlien>>registerState (in category 'accessing-abstract') ----- registerState ^{ self r0. self r1. self r2. self r3. self r4. self r5. self r6. self r7. + self r8. self r9. self sl. self fp. self r12. self sp. self lr. self pc. self eflags }! - self r8. self r9. self r10. self fp. self r12. self sp. self lr. self pc. self eflags }! Item was changed: ----- Method: GdbARMAlien>>registerStateNames (in category 'accessing-abstract') ----- registerStateNames + ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 sp lr pc eflags)! - ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 fp r12 sp lr pc eflags)! Item was changed: ----- Method: GdbARMAlien>>registerStateSetters (in category 'accessing-abstract') ----- registerStateSetters "a list of register setting messages used to initialise or reset registers" + ^#( r0: r1: r2: r3: r4: r5: r6: r7: r8: r9: sl: fp: r12: sp: lr: pc: eflags:)! - ^#( r0: r1: r2: r3: r4: r5: r6: r7: r8: r9: r10: fp: r12: sp: lr: pc: eflags:)! Item was changed: ----- Method: GdbARMAlien>>reset (in category 'accessing') ----- reset + self priorPc: 0; + primitiveResetCPU! - self primitiveResetCPU! Item was added: + ----- Method: GdbARMAlien>>sl (in category 'accessing') ----- + sl + ^self unsignedLongAt: 53! Item was added: + ----- Method: GdbARMAlien>>sl: (in category 'accessing') ----- + sl: anUnsignedInteger + + ^self unsignedLongAt: 53 put: anUnsignedInteger! Item was changed: ----- Method: GdbARMAlien>>writePopPushDetailsIn:in:for: (in category 'printing') ----- writePopPushDetailsIn: memory in: transcript for: aCogit "if the next instruction is a pop or push, or a ldr/str that touches the SP, write the details ontranscript" | instr | [instr := memory unsignedLongAt: self pc + 1 bigEndian: false] on: Error do: [:ex | ^ self]. (self instructionIsPop: instr) ifTrue: [^transcript tab; nextPutAll: 'POP ' , (memory unsignedLongAt: self sp + 1 bigEndian: false) hex , ' from ' , self sp hex; cr]. (self instructionIsPush: instr) ifTrue: [^transcript tab; nextPutAll: 'PUSH ' , (self register: (instr bitAnd: 61440) >> 12) hex , ' to ' , (self sp - 4) hex; cr]. (self instructionIsLDRSP: instr) ifTrue: [| val | + val := self sl > memory size + ifTrue: [aCogit simulatedVariableAt: self sl] + ifFalse: [memory unsignedLongAt: self sl + 1 bigEndian: false]. + ^transcript tab; nextPutAll: 'LOAD SP ' , val hex , ' from ' , self sl hex; cr]. - val := self r10 > memory size - ifTrue: [aCogit simulatedVariableAt: self r10] - ifFalse: [memory unsignedLongAt: self r10 + 1 bigEndian: false]. - ^transcript tab; nextPutAll: 'LOAD SP ' , val hex , ' from ' , self r10 hex; cr]. (self instructionIsSTRSP: instr) + ifTrue: [^transcript tab; nextPutAll: 'STORE SP ' , self sp hex , ' to ' , self sl hex; cr]. - ifTrue: [^transcript tab; nextPutAll: 'STORE SP ' , self sp hex , ' to ' , self r10 hex; cr]. (self instructionIsAlignSP: instr) ifTrue: [^transcript tab; nextPutAll: 'ALIGN SP ' , self sp hex; cr]. (self instructionIsAddSP: instr) ifTrue:[^transcript tab; nextPutAll: 'ADD ', (instr bitAnd: 16rFF) asString,' to SP = ' , self sp hex; cr]! Item was changed: ----- Method: GdbARMAlienTests>>integerRegisterGetters (in category 'accessing') ----- integerRegisterGetters + ^#(r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 lr sp pc)! - ^#(r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 fp r12 lr sp pc)! Item was changed: ----- Method: GdbARMAlienTests>>memory (in category 'accessing') ----- memory "build a memory for this test; a ByteArray of 1024 bytes, filled with NOPs" + | mem nop| + nop := CogARMCompiler new mov: 0 rn: 0. - | mem | mem := ByteArray new: 1024. 1 to: 1024 by: 4do:[:i| + mem unsignedLongAt: i put: nop bigEndian: false]. - mem unsignedLongAt: i put: 16rE1A00000 bigEndian: false]. ^mem! Item was changed: ----- Method: GdbARMAlienTests>>testDisassembling (in category 'tests') ----- testDisassembling "self new testDisassembling" | memory result | memory := WordArray new: 2. + memory at: 1 put: (CogARMCompiler new add: 15 rn: 10 imm: 100 ror:0). - memory at: 1 put: 3800756324. result := self processor disassembleInstructionAt: 0 In: memory into: [:str :len | self assert: len = 4; assert: str = '00000000: add pc, sl, #100 ; 0x64'].! Item was changed: ----- Method: GdbARMAlienTests>>testLongJumpAddressForming (in category 'tests') ----- testLongJumpAddressForming "self new testLongJumpAddressForming" "test of the somewhat loopy code used in CogARMCompiler>concretizeConditionalJumpLong: to generate the oading of a long address for jumps" | memory | memory := self memory. self processor reset. memory unsignedLongAt: 1 put: (CogARMCompiler new mov: 10 imm: 16r7F ror: 8) bigEndian: false. memory unsignedLongAt: 5 put: (CogARMCompiler new orr: 10 imm: 16rFF ror: 16) bigEndian: false. memory unsignedLongAt: 9 put: (CogARMCompiler new orr: 10 imm: 16rFE ror: 24) bigEndian: false. memory unsignedLongAt: 13 put: (CogARMCompiler new orr: 10 imm: 16r68 ror: 0) bigEndian: false. self processor disassembleInstructionAt: 0 In: memory into: [:str :len | self assert: len = 4; assert: str equals: '00000000: mov sl, #2130706432 ; 0x7f000000']. self processor disassembleInstructionAt: 4 In: memory into: [:str :len | self assert: len = 4; assert: str equals: '00000004: orr sl, sl, #16711680 ; 0xff0000']. self processor disassembleInstructionAt: 8 In: memory into: [:str :len | self assert: len = 4; assert: str equals: '00000008: orr sl, sl, #65024 ; 0xfe00']. self processor disassembleInstructionAt: 12 In: memory into: [:str :len | self assert: len = 4; assert: str equals: '0000000c: orr sl, sl, #104 ; 0x68']. self processor pc: 0; singleStepIn: memory; singleStepIn: memory; singleStepIn: memory; singleStepIn: memory. self assert: self processor pc = 16; + assert: self processor sl = 16r7FFFFE68; - assert: self processor r10 = 16r7FFFFE68; assert: self processor zflag = 0; assert: self processor cflag = 0; assert: self processor vflag = 0; assert: self processor nflag = 0. ! Item was changed: ----- Method: GdbARMAlienTests>>testMoveRAw (in category 'tests') ----- testMoveRAw "Write a register to a constant address that is in-range." "self new testMoveRAw" | memory | memory := self memory. self processor reset. "LEA sl, #16r3FC" memory unsignedLongAt: 5 put: (CogARMCompiler new mov: 10 imm: 0 ror: 0) bigEndian: false. memory unsignedLongAt: 9 put: (CogARMCompiler new orr: 10 imm: 0 ror: 0) bigEndian: false. memory unsignedLongAt: 13 put: (CogARMCompiler new orr: 10 imm: 2 ror: 24) bigEndian: false. memory unsignedLongAt: 17 put: (CogARMCompiler new orr: 10 imm: 40 ror: 0) bigEndian: false. "STR R5, [sl]" memory unsignedLongAt: 21 put: (CogARMCompiler new str: 5 rn: 10 plusImm: 0) bigEndian: false. "processor disassembleFrom: 0 to: 60 in: memory on: Transcript cr" self processor pc: 4; sp: (memory size - 4); "Room for return address" r5: 99; singleStepIn: memory readExecuteOnlyBelow: memory size / 2. "We have to step several times, because the first step only changes the pc, but does not fetch anything from the address it points to." self processor singleStepIn: memory readExecuteOnlyBelow: memory size / 2. self processor singleStepIn: memory readExecuteOnlyBelow: memory size / 2. self processor singleStepIn: memory readExecuteOnlyBelow: memory size / 2. self processor singleStepIn: memory readExecuteOnlyBelow: memory size / 2. self processor singleStepIn: memory readExecuteOnlyBelow: memory size / 2. + self assert:[(memory unsignedLongAt: (processor sl) + 1) = processor r5] - self assert:[(memory unsignedLongAt: (processor r10) + 1) = processor r5] ! Item was changed: ----- Method: GdbARMAlienTests>>testQuickDisassemby (in category 'tests') ----- testQuickDisassemby "self new testQuickDisassemby" | memory result | memory := WordArray new: 2. + memory at: 1 put: (CogARMCompiler new orr: 6 imm: 16r3F ror: 16). - memory at: 1 put: 3858758348. result := self processor disassembleInstructionAt: 0 In: memory into: [:str :len | + ^str = '00000000: orr r6, r6, #4128768 ; 0x3f0000'].! - ^str].!

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VM Maker: VMMaker.oscog-eem.1125.mcz
by commits＠source.squeak.org 26 Mar '15

26 Mar '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1125.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1125 Author: eem Time: 26 March 2015, 2:17:38.667 pm UUID: 7d683ed5-85b1-4f54-b6d6-f869fd20e944 Ancestors: VMMaker.oscog-eem.1124 On ARM the abort sequence pushes the link reg. This means that in the stack overflow case the link reg gets opushed twice and hence the trampoline must overwrite the stacked link reg with the one for the ceMethodAbort call, not push the link reg twice. Now the system gets beyond the first stack check into some interesting infinite recursion around Interval(Object)>adaptToInteger:andCompare: ;) =============== Diff against VMMaker.oscog-eem.1124 =============== Item was changed: ----- Method: Cogit>>genMethodAbortTrampoline (in category 'initialization') ----- genMethodAbortTrampoline "Generate the abort for a method. This abort performs either a call of ceSICMiss: to handle a single-in-line cache miss or a call of ceStackOverflow: to handle a stack overflow. It distinguishes the two by testing ResultReceiverReg. If the register is zero then this is a stack-overflow because a) the receiver has already been pushed and so can be set to zero before calling the abort, and b) the receiver must always contain an object (and hence be non-zero) on SIC miss." | jumpSICMiss | <var: #jumpSICMiss type: #'AbstractInstruction *'> opcodeIndex := 0. self CmpCq: 0 R: ReceiverResultReg. jumpSICMiss := self JumpNonZero: 0. + "The abort sequencer has pushed the LinkReg a second time. + Overwrite it with the right one." + backEnd hasLinkRegister ifTrue: + [self MoveR: LinkReg Mw: 0 r: SPReg]. self compileTrampolineFor: #ceStackOverflow: numArgs: 1 arg: SendNumArgsReg arg: nil arg: nil arg: nil saveRegs: false + pushLinkReg: false "The LinkReg has already been set above." - pushLinkReg: false "The LinkReg has already been pushed in the abort sequence." resultReg: nil. jumpSICMiss jmpTarget: self Label. ^self genTrampolineFor: #ceSICMiss: called: 'ceMethodAbort' numArgs: 1 arg: ReceiverResultReg arg: nil arg: nil arg: nil saveRegs: false + pushLinkReg: true "Push the LinkReg for the ceMethodAbort call." - pushLinkReg: false "The LinkReg has already been pushed in the abort sequence." resultReg: nil appendOpcodes: true! Item was changed: ----- Method: StackToRegisterMappingCogit>>genMethodAbortTrampolineFor: (in category 'initialization') ----- genMethodAbortTrampolineFor: numArgs "Generate the abort for a method. This abort performs either a call of ceSICMiss: to handle a single-in-line cache miss or a call of ceStackOverflow: to handle a stack overflow. It distinguishes the two by testing ResultReceiverReg. If the register is zero then this is a stack-overflow because a) the receiver has already been pushed and so can be set to zero before calling the abort, and b) the receiver must always contain an object (and hence be non-zero) on SIC miss." | jumpSICMiss | <var: #jumpSICMiss type: #'AbstractInstruction *'> opcodeIndex := 0. self CmpCq: 0 R: ReceiverResultReg. jumpSICMiss := self JumpNonZero: 0. + "The abort sequencer has pushed the LinkReg a second time. + Overwrite it with the right one." + backEnd hasLinkRegister ifTrue: + [self MoveR: LinkReg Mw: 0 r: SPReg]. self compileTrampolineFor: #ceStackOverflow: numArgs: 1 arg: SendNumArgsReg arg: nil arg: nil arg: nil saveRegs: false + pushLinkReg: false "The LinkReg has already been set above." - pushLinkReg: false "The LinkReg has already been pushed in the abort sequence." resultReg: nil. jumpSICMiss jmpTarget: self Label. backEnd genPushRegisterArgsForAbortMissNumArgs: numArgs. ^self genTrampolineFor: #ceSICMiss: called: (self trampolineName: 'ceMethodAbort' numArgs: (numArgs <= self numRegArgs ifTrue: [numArgs] ifFalse: [-1])) numArgs: 1 arg: ReceiverResultReg arg: nil arg: nil arg: nil saveRegs: false + pushLinkReg: false "The LinkReg will have been pushed in genPushRegisterArgsForAbortMissNumArgs: above." - pushLinkReg: false "The LinkReg has already been pushed in the abort sequence." resultReg: nil appendOpcodes: true!

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[commit][3295] Delete some redundancy in the ARM sim code.
by commits＠squeakvm.org 26 Mar '15

26 Mar '15

Revision: 3295 Author: eliot Date: 2015-03-26 13:23:09 -0700 (Thu, 26 Mar 2015) Log Message: ----------- Delete some redundancy in the ARM sim code. Modified Paths: -------------- branches/Cog/processors/ARM/gdb-7.6/sim/arm/armemu.c Modified: branches/Cog/processors/ARM/gdb-7.6/sim/arm/armemu.c =================================================================== --- branches/Cog/processors/ARM/gdb-7.6/sim/arm/armemu.c 2015-03-26 18:52:48 UTC (rev 3294) +++ branches/Cog/processors/ARM/gdb-7.6/sim/arm/armemu.c 2015-03-26 20:23:09 UTC (rev 3295) @@ -575,10 +575,6 @@ // if we get back an SWI_CogPrefetch then the pc was outside limits decoded = ARMul_ReLoadInstr (state, pc + isize, isize); loaded = ARMul_ReLoadInstr (state, pc + isize * 2, isize); - // TPR - save the pc to help in CogVM sim error handling, IFF the instr is not a SWI_CogPrefetch - if ( instr != (0xEF000000 | SWI_CogPrefetch)) { - state->temp = pc; - } NORMALCYCLE; // set to do simple SEQ next time & break to end of switch break; @@ -592,10 +588,6 @@ state->Aborted = 0; instr = ARMul_LoadInstrN (state, pc, isize); decoded = ARMul_LoadInstrS (state, pc + (isize), isize); -// TPR - save the pc to help in CogVM sim error handling, IFF the instr is not an abort SWI - if ( instr != (0xEF000000 | SWI_CogPrefetch)) { - state->temp = pc; - } loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize); NORMALCYCLE; break; @@ -603,12 +595,12 @@ // END OF SWITCH stmt, where the above breaks go // TPR - save the pc to help in CogVM sim error handling, IFF the instr is not an abort SWI - if ( instr != (0xEF000000 | SWI_CogPrefetch)) { - state->temp = pc; - } + if ( instr != (0xEF000000 | SWI_CogPrefetch)) { + state->temp = pc; + } - if (state->EventSet) - ARMul_EnvokeEvent (state); + if (state->EventSet) + ARMul_EnvokeEvent (state); #if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); if (instr == 0)

1 0

[commit][3294] Add a script to build debuggable ARM sim libraries.
by commits＠squeakvm.org 26 Mar '15

26 Mar '15

Revision: 3294 Author: eliot Date: 2015-03-26 11:52:48 -0700 (Thu, 26 Mar 2015) Log Message: ----------- Add a script to build debuggable ARM sim libraries. Make those makeit scripts for plugins install in all the right places. Modified Paths: -------------- branches/Cog/build.macos32x86/newspeak.cog.spur/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/newspeak.cog.v3/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/newspeak.stack.spur/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/squeak.cog.spur/BochsIA32Plugin/makeit branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/makeit branches/Cog/build.macos32x86/squeak.cog.spur/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/squeak.cog.v3/BochsIA32Plugin/makeit branches/Cog/build.macos32x86/squeak.cog.v3/GdbARMPlugin/makeit branches/Cog/build.macos32x86/squeak.cog.v3/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/squeak.sista.spur/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/squeak.sista.v3/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/squeak.stack.spur/UnixOSProcessPlugin/makeit branches/Cog/build.macos32x86/squeak.stack.v3/UnixOSProcessPlugin/makeit branches/Cog/processors/ARM/mac/BUILDarmsim.sh Added Paths: ----------- branches/Cog/processors/ARM/mac/BUILDarmsim-dbg.sh Modified: branches/Cog/build.macos32x86/newspeak.cog.spur/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/newspeak.cog.spur/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/newspeak.cog.spur/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Squeak.app Croquet.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/newspeak.cog.v3/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/newspeak.cog.v3/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/newspeak.cog.v3/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Squeak.app Croquet.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/newspeak.stack.spur/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/newspeak.stack.spur/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/newspeak.stack.spur/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Squeak.app Croquet.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.cog.spur/BochsIA32Plugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/BochsIA32Plugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.cog.spur/BochsIA32Plugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/BochsIA32Plugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app Croquet.app +for d in Fast.app Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release BochsIA32Plugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.cog.spur/GdbARMPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/GdbARMPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app Croquet.app +for d in Fast.app Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release GdbARMPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.cog.spur/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.spur/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.cog.spur/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.cog.v3/BochsIA32Plugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.v3/BochsIA32Plugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.cog.v3/BochsIA32Plugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/BochsIA32Plugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app Croquet.app +for d in Fast.app Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release BochsIA32Plugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.cog.v3/GdbARMPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.v3/GdbARMPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.cog.v3/GdbARMPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/GdbARMPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app Croquet.app +for d in Fast.app Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release GdbARMPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.cog.v3/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.cog.v3/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.cog.v3/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.sista.spur/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.sista.spur/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.sista.spur/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.sista.v3/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.sista.v3/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.sista.v3/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.stack.spur/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.stack.spur/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.stack.spur/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Modified: branches/Cog/build.macos32x86/squeak.stack.v3/UnixOSProcessPlugin/makeit =================================================================== --- branches/Cog/build.macos32x86/squeak.stack.v3/UnixOSProcessPlugin/makeit 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/build.macos32x86/squeak.stack.v3/UnixOSProcessPlugin/makeit 2015-03-26 18:52:48 UTC (rev 3294) @@ -9,7 +9,7 @@ cp -R build/Debug/UnixOSProcessPlugin.bundle "../$d/Contents/Resources" fi done -for d in Fast.app "Qwaq VM.app" +for d in Fast.app "Qwaq VM.app" Croquet.app Squeak.app do if [ -d "../$d" ]; then echo installed Release UnixOSProcessPlugin in ../$d Added: branches/Cog/processors/ARM/mac/BUILDarmsim-dbg.sh =================================================================== --- branches/Cog/processors/ARM/mac/BUILDarmsim-dbg.sh (rev 0) +++ branches/Cog/processors/ARM/mac/BUILDarmsim-dbg.sh 2015-03-26 18:52:48 UTC (rev 3294) @@ -0,0 +1,19 @@ +#!/bin/bash +# This script builds debug versions of +# gdb-7.6/opcodes/libopcodes.a +# gdb-7.6/sim/arm/libsim.a + +test -d gdb-7.6 || svn export ../gdb-7.6 + +ln -s ../../binutils-2.25/bfd/bfd.h gdb-7.6/bfd/bfd.h +ln -s ../../binutils-2.25/bfd/config.h gdb-7.6/bfd/config.h +libtool -V >gdb-7.6/bfd/libtool-soversion +(cd gdb-7.6/opcodes # i.e. processors/ARM/gdb-7.6/opcodes +./configure --target=arm-linux --build=i386-apple-darwin9 CFLAGS="-arch i386 -g -O0" LDFLAGS="-arch i386" +make + +cd ../sim/common # i.e. processors/ARM/gdb-7.6/sim/common +./configure --target=arm-linux --build=i386-apple-darwin9 CFLAGS="-arch i386 -g -O0" LDFLAGS="-arch i386" +cd ../arm # i.e. processors/ARM/gdb-7.6/sim/arm +./configure --target=arm-linux --build=i386-apple-darwin9 CFLAGS="-arch i386 -g -O0" LDFLAGS="-arch i386" +make) Property changes on: branches/Cog/processors/ARM/mac/BUILDarmsim-dbg.sh ___________________________________________________________________ Added: svn:executable + * Modified: branches/Cog/processors/ARM/mac/BUILDarmsim.sh =================================================================== --- branches/Cog/processors/ARM/mac/BUILDarmsim.sh 2015-03-26 05:37:40 UTC (rev 3293) +++ branches/Cog/processors/ARM/mac/BUILDarmsim.sh 2015-03-26 18:52:48 UTC (rev 3294) @@ -8,14 +8,6 @@ ln -s ../../binutils-2.25/bfd/bfd.h gdb-7.6/bfd/bfd.h ln -s ../../binutils-2.25/bfd/config.h gdb-7.6/bfd/config.h libtool -V >gdb-7.6/bfd/libtool-soversion -if false; then -ed - gdb-7.6/sim/arm/armos.c <<END -/^ARMul_OSHandleSWI/ -s/^/core_/ -w -q -END -fi (cd gdb-7.6/opcodes # i.e. processors/ARM/gdb-7.6/opcodes ./configure --target=arm-linux --build=i386-apple-darwin9 CFLAGS="-arch i386 -g -O2" LDFLAGS="-arch i386" make

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VM Maker: Cog-eem.252.mcz
by commits＠source.squeak.org 26 Mar '15

26 Mar '15

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.252.mcz ==================== Summary ==================== Name: Cog-eem.252 Author: eem Time: 26 March 2015, 11:30:55.219 am UUID: bf53e4bb-7d66-47d0-9c35-583d67a51a6c Ancestors: Cog-eem.251 Fix comments, and add the return codes as class vars. =============== Diff against Cog-eem.251 =============== Item was changed: CogProcessorAlien variableByteSubclass: #GdbARMAlien instanceVariableNames: '' + classVariableNames: 'BadCPUInstance ExecutionError InstructionPrefetchError LongConstReg LongConstStep LongConstValue MemoryLoadBoundsError MemoryWriteBoundsError NoError PanicError PostBuildStackDelta SomethingLoggedError UnsupportedOperationError' - classVariableNames: 'LongConstReg LongConstStep LongConstValue PostBuildStackDelta' poolDictionaries: '' category: 'Cog-Processors'! !GdbARMAlien commentStamp: 'lw 8/23/2012 19:17' prior: 0! I am a wrapper around the ARMulator CPU instance and emulator routines and I give access to disassembling using libopcodes. My C-part must be compiled with -DMODET, because otherwise my offesets are wrong by one field.! Item was changed: ----- Method: GdbARMAlien class>>initialize (in category 'class initialization') ----- initialize "GdbARMAlien initialize" + PostBuildStackDelta := 0. + + "Return errors from GdbARMPlugin.h" + NoError := 0. + ExecutionError := 1. + BadCPUInstance := 2. + MemoryLoadBoundsError := 3. + MemoryWriteBoundsError := 4. + InstructionPrefetchError := 5. + PanicError := 6. + UnsupportedOperationError := 7. + SomethingLoggedError := 8! - PostBuildStackDelta := 0.! Item was changed: ----- Method: GdbARMAlien>>handleExecutionPrimitiveFailureIn:minimumAddress: (in category 'error handling') ----- handleExecutionPrimitiveFailureIn: memoryArray "<Bitmap|ByteArray>" minimumAddress: minimumAddress "<Integer>" "Handle an execution primitive failure. Convert out-of-range call and absolute memory read into register instructions into ProcessorSimulationTrap signals." "self printRegistersOn: Transcript" | pcOnEntry pc | pcOnEntry := self pc. + self endCondition = InstructionPrefetchError ifTrue: - self endCondition = 5 ifTrue: [self pc: self priorPc]. ((pc := self pc) between: minimumAddress and: memoryArray byteSize - 1) ifTrue: [(self instructionTypeAt: pc in: memoryArray) caseOf: { [#Call] -> [^self handleCallFailureAt: pc in: memoryArray]. [#LongCall] -> [^self handleLongCallFailureAt: pc in: memoryArray]. [#Jump] -> [^self handleJmpFailureAt: pc in: memoryArray]. [#LongJump] -> [^self handleLongJmpFailureAt: pc in: memoryArray]. [#MoveAwR] -> [^self handleMoveAwRFailureAt: pc in: memoryArray]. [#MoveMbrR] -> [^self handleMoveMbrRFailureAt: pc in: memoryArray]. [#MoveRAw] -> [^self handleMoveRAwFailureAt: pc in: memoryArray]. [#MoveRMbr] -> [^self handleMoveRMbrFailureAt: pc in: memoryArray]. [#Ret] -> [^self handleRetFailureAt: pc in: memoryArray].} otherwise: [^self handleExecutionPrimitiveFailureAt: pc in: memoryArray]]. ^self reportPrimitiveFailure! Item was changed: ----- Method: GdbARMAlien>>handleRetFailureAt:in: (in category 'error handling') ----- handleRetFailureAt: pc "<Integer>" in: memoryArray "<Bitmap|ByteArray>" "Convert an execution primitive failure for a ret into a ProcessorSimulationTrap signal." - self halt. ^(ProcessorSimulationTrap pc: pc nextpc: pc + 4 + address: self lr + type: #return) - address: self lr " for popping off stack version of retiurn -> (memoryArray unsignedLongAt: self sp -3) " - type: #return - "don't quite know what to do with this yet ->accessor: #pc:") signal!

1 0

VM Maker: VMMaker.oscog-eem.1124.mcz
by commits＠source.squeak.org 26 Mar '15

26 Mar '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1124.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1124 Author: eem Time: 26 March 2015, 11:15:29.762 am UUID: 842fe1b7-f431-40f7-ba16-a156d4dafd38 Ancestors: VMMaker.oscog-eem.1123 A read simulation trap must not set the pc to next pc if the read wrte to the oc register (ARM does returns via pop into pc, etc, and we use this in cePrimReturnEnterCogCode to write instructionPointer directly into pc). =============== Diff against VMMaker.oscog-eem.1123 =============== Item was changed: ----- Method: Cogit>>handleReadSimulationTrap: (in category 'simulation only') ----- handleReadSimulationTrap: aProcessorSimulationTrap <doNotGenerate> + | variableValue accessor | - | variableValue | variableValue := (simulatedVariableGetters at: aProcessorSimulationTrap address) value asInteger. + accessor := aProcessorSimulationTrap registerAccessor. processor + perform: accessor - perform: aProcessorSimulationTrap registerAccessor with: variableValue signedIntToLong. + accessor ~~ #pc: ifTrue: + [processor pc: aProcessorSimulationTrap nextpc]! - processor pc: aProcessorSimulationTrap nextpc!

1 0

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Vm-dev March 2015