Vm-dev May 2016

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VM Maker: Cog-eem.319.mcz
by commits＠source.squeak.org 10 May '16

10 May '16

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.319.mcz ==================== Summary ==================== Name: Cog-eem.319 Author: eem Time: 10 May 2016, 11:53:43.273329 am UUID: 763f34da-8118-4645-9095-8decbcd3605a Ancestors: Cog-eem.318 Add VPF register state accessors to the GdbARMAlien; advance after a multiply, and fix printing. =============== Diff against Cog-eem.318 =============== Item was changed: ----- Method: GdbARMAlien class>>dataSize (in category 'instance creation') ----- dataSize + ^1788! - - ^1536! Item was added: + ----- Method: GdbARMAlien>>d0 (in category 'accessing') ----- + d0 + ^self unsignedLongLongAt: 1529! Item was added: + ----- Method: GdbARMAlien>>d0: (in category 'accessing') ----- + d0: anUnsignedInteger + ^self unsignedLongLongAt: 1529 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d1 (in category 'accessing') ----- + d1 + ^self unsignedLongLongAt: 1537! Item was added: + ----- Method: GdbARMAlien>>d10 (in category 'accessing') ----- + d10 + ^self unsignedLongLongAt: 1609! Item was added: + ----- Method: GdbARMAlien>>d10: (in category 'accessing') ----- + d10: anUnsignedInteger + ^self unsignedLongLongAt: 1609 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d11 (in category 'accessing') ----- + d11 + ^self unsignedLongLongAt: 1617! Item was added: + ----- Method: GdbARMAlien>>d11: (in category 'accessing') ----- + d11: anUnsignedInteger + ^self unsignedLongLongAt: 1617 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d12 (in category 'accessing') ----- + d12 + ^self unsignedLongLongAt: 1625! Item was added: + ----- Method: GdbARMAlien>>d12: (in category 'accessing') ----- + d12: anUnsignedInteger + ^self unsignedLongLongAt: 1625 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d13 (in category 'accessing') ----- + d13 + ^self unsignedLongLongAt: 1633! Item was added: + ----- Method: GdbARMAlien>>d13: (in category 'accessing') ----- + d13: anUnsignedInteger + ^self unsignedLongLongAt: 1633 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d14 (in category 'accessing') ----- + d14 + ^self unsignedLongLongAt: 1641! Item was added: + ----- Method: GdbARMAlien>>d14: (in category 'accessing') ----- + d14: anUnsignedInteger + ^self unsignedLongLongAt: 1641 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d15 (in category 'accessing') ----- + d15 + ^self unsignedLongLongAt: 1649! Item was added: + ----- Method: GdbARMAlien>>d15: (in category 'accessing') ----- + d15: anUnsignedInteger + ^self unsignedLongLongAt: 1649 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d16 (in category 'accessing') ----- + d16 + ^self unsignedLongLongAt: 1657! Item was added: + ----- Method: GdbARMAlien>>d16: (in category 'accessing') ----- + d16: anUnsignedInteger + ^self unsignedLongLongAt: 1657 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d17 (in category 'accessing') ----- + d17 + ^self unsignedLongLongAt: 1665! Item was added: + ----- Method: GdbARMAlien>>d17: (in category 'accessing') ----- + d17: anUnsignedInteger + ^self unsignedLongLongAt: 1665 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d18 (in category 'accessing') ----- + d18 + ^self unsignedLongLongAt: 1673! Item was added: + ----- Method: GdbARMAlien>>d18: (in category 'accessing') ----- + d18: anUnsignedInteger + ^self unsignedLongLongAt: 1673 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d19 (in category 'accessing') ----- + d19 + ^self unsignedLongLongAt: 1681! Item was added: + ----- Method: GdbARMAlien>>d19: (in category 'accessing') ----- + d19: anUnsignedInteger + ^self unsignedLongLongAt: 1681 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d1: (in category 'accessing') ----- + d1: anUnsignedInteger + ^self unsignedLongLongAt: 1537 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d2 (in category 'accessing') ----- + d2 + ^self unsignedLongLongAt: 1545! Item was added: + ----- Method: GdbARMAlien>>d20 (in category 'accessing') ----- + d20 + ^self unsignedLongLongAt: 1689! Item was added: + ----- Method: GdbARMAlien>>d20: (in category 'accessing') ----- + d20: anUnsignedInteger + ^self unsignedLongLongAt: 1689 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d21 (in category 'accessing') ----- + d21 + ^self unsignedLongLongAt: 1697! Item was added: + ----- Method: GdbARMAlien>>d21: (in category 'accessing') ----- + d21: anUnsignedInteger + ^self unsignedLongLongAt: 1697 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d22 (in category 'accessing') ----- + d22 + ^self unsignedLongLongAt: 1705! Item was added: + ----- Method: GdbARMAlien>>d22: (in category 'accessing') ----- + d22: anUnsignedInteger + ^self unsignedLongLongAt: 1705 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d23 (in category 'accessing') ----- + d23 + ^self unsignedLongLongAt: 1713! Item was added: + ----- Method: GdbARMAlien>>d23: (in category 'accessing') ----- + d23: anUnsignedInteger + ^self unsignedLongLongAt: 1713 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d24 (in category 'accessing') ----- + d24 + ^self unsignedLongLongAt: 1721! Item was added: + ----- Method: GdbARMAlien>>d24: (in category 'accessing') ----- + d24: anUnsignedInteger + ^self unsignedLongLongAt: 1721 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d25 (in category 'accessing') ----- + d25 + ^self unsignedLongLongAt: 1729! Item was added: + ----- Method: GdbARMAlien>>d25: (in category 'accessing') ----- + d25: anUnsignedInteger + ^self unsignedLongLongAt: 1729 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d26 (in category 'accessing') ----- + d26 + ^self unsignedLongLongAt: 1737! Item was added: + ----- Method: GdbARMAlien>>d26: (in category 'accessing') ----- + d26: anUnsignedInteger + ^self unsignedLongLongAt: 1737 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d27 (in category 'accessing') ----- + d27 + ^self unsignedLongLongAt: 1745! Item was added: + ----- Method: GdbARMAlien>>d27: (in category 'accessing') ----- + d27: anUnsignedInteger + ^self unsignedLongLongAt: 1745 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d28 (in category 'accessing') ----- + d28 + ^self unsignedLongLongAt: 1753! Item was added: + ----- Method: GdbARMAlien>>d28: (in category 'accessing') ----- + d28: anUnsignedInteger + ^self unsignedLongLongAt: 1753 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d29 (in category 'accessing') ----- + d29 + ^self unsignedLongLongAt: 1761! Item was added: + ----- Method: GdbARMAlien>>d29: (in category 'accessing') ----- + d29: anUnsignedInteger + ^self unsignedLongLongAt: 1761 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d2: (in category 'accessing') ----- + d2: anUnsignedInteger + ^self unsignedLongLongAt: 1545 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d3 (in category 'accessing') ----- + d3 + ^self unsignedLongLongAt: 1553! Item was added: + ----- Method: GdbARMAlien>>d30 (in category 'accessing') ----- + d30 + ^self unsignedLongLongAt: 1769! Item was added: + ----- Method: GdbARMAlien>>d30: (in category 'accessing') ----- + d30: anUnsignedInteger + ^self unsignedLongLongAt: 1769 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d31 (in category 'accessing') ----- + d31 + ^self unsignedLongLongAt: 1777! Item was added: + ----- Method: GdbARMAlien>>d31: (in category 'accessing') ----- + d31: anUnsignedInteger + ^self unsignedLongLongAt: 1777 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d3: (in category 'accessing') ----- + d3: anUnsignedInteger + ^self unsignedLongLongAt: 1553 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d4 (in category 'accessing') ----- + d4 + ^self unsignedLongLongAt: 1561! Item was added: + ----- Method: GdbARMAlien>>d4: (in category 'accessing') ----- + d4: anUnsignedInteger + ^self unsignedLongLongAt: 1561 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d5 (in category 'accessing') ----- + d5 + ^self unsignedLongLongAt: 1569! Item was added: + ----- Method: GdbARMAlien>>d5: (in category 'accessing') ----- + d5: anUnsignedInteger + ^self unsignedLongLongAt: 1569 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d6 (in category 'accessing') ----- + d6 + ^self unsignedLongLongAt: 1577! Item was added: + ----- Method: GdbARMAlien>>d6: (in category 'accessing') ----- + d6: anUnsignedInteger + ^self unsignedLongLongAt: 1577 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d7 (in category 'accessing') ----- + d7 + ^self unsignedLongLongAt: 1585! Item was added: + ----- Method: GdbARMAlien>>d7: (in category 'accessing') ----- + d7: anUnsignedInteger + ^self unsignedLongLongAt: 1585 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d8 (in category 'accessing') ----- + d8 + ^self unsignedLongLongAt: 1593! Item was added: + ----- Method: GdbARMAlien>>d8: (in category 'accessing') ----- + d8: anUnsignedInteger + ^self unsignedLongLongAt: 1593 put: anUnsignedInteger! Item was added: + ----- Method: GdbARMAlien>>d9 (in category 'accessing') ----- + d9 + ^self unsignedLongLongAt: 1601! Item was added: + ----- Method: GdbARMAlien>>d9: (in category 'accessing') ----- + d9: anUnsignedInteger + ^self unsignedLongLongAt: 1601 put: anUnsignedInteger! Item was changed: ----- Method: GdbARMAlien>>handleOneRegTransferDoubleArithmetic:at: (in category 'floating-point emulation') ----- handleOneRegTransferDoubleArithmetic: instr at: pc "Emulate a one-register transfer VFP instruction." | rn rd rm vn vm | rn := instr >> 16 bitAnd: 15. rd := instr >> 12 bitAnd: 15. rm := instr bitAnd: 15. vn := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs" vm := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs" (instr >> 18 bitAnd: 31) caseOf: { [8 "FMULD"] -> [| r | r := vn * vm. self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord]. [12"FADDD/FSUBD"] -> [self shouldBeImplemented]. [32"FDIVD"] -> [self shouldBeImplemented]. [45"FCMPD"] -> [self shouldBeImplemented]. } + otherwise: [self reportPrimitiveFailure]. + self pc: pc + 4! - otherwise: [self reportPrimitiveFailure]! Item was changed: ----- Method: GdbARMAlien>>printOn: (in category 'printing') ----- printOn: aStream + | first | + first := true. + aStream nextPutAll: 'an ARMAlien ('. + self registerState with: self registerStateGetters do: [ :state :getter | + first + ifTrue: [first := false] + ifFalse: [aStream << ', ']. + getter first = $d + ifTrue: + [aStream + << getter << ': ' + << (Float fromIEEE64BitWord: state)] + ifFalse: + [getter == #eflags + ifTrue: + [aStream + << 'NZCVIF: ' + << (state printStringBase: 2 length: 6 padded: true)] + ifFalse: + [aStream + << getter << ': ' + << (state printStringBase: 16)]]]! - aStream nextPutAll: 'an ARMAlien('. - self registerState allButLast with: self registerStateGetters allButLast do: [ :state :i | - aStream - << i << ': ' - << (state abs > 15 ifTrue: [state hex] ifFalse: [state asString]) - << ', ']. - aStream << 'NZCVIF: ' - << (self registerState last printStringBase: 2 length: 6 padded: true) << ')'.! Item was changed: ----- Method: GdbARMAlien>>registerState (in category 'accessing-abstract') ----- registerState ^{ self r0. self r1. self r2. self r3. self r4. self r5. self r6. self r7. + self r8. self r9. self sl. self fp. self r12. self sp. self lr. self pc. self eflags. + self d0. self d1. self d2. self d3. self d4. self d5. self d6. self d7. + self d8. self d9. self d10. self d11. self d12. self d13. self d14. self d15 }! - self r8. self r9. self sl. self fp. self r12. self sp. self lr. self pc. self eflags }!

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VM Maker: VMMaker.oscog-tpr.1857.mcz
by commits＠source.squeak.org 10 May '16

10 May '16

tim Rowledge uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1857.mcz ==================== Summary ==================== Name: VMMaker.oscog-tpr.1857 Author: tpr Time: 10 May 2016, 11:49:45.497012 am UUID: 01dc1cd0-4095-4ead-b3ca-408c051c29cf Ancestors: VMMaker.oscog-eem.1856 Add some hopefully helpful documentation page pointers to ARM instructions =============== Diff against VMMaker.oscog-eem.1856 =============== Item was changed: ----- Method: CogARMCompiler>>add:rn:imm:ror: (in category 'ARM convenience instructions') ----- add: destReg rn: srcReg imm: immediate ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc. + ADD destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-23" - ADD destReg, srcReg, #immediate ROR #rot" ^self type: 1 op: AddOpcode set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)! Item was changed: ----- Method: CogARMCompiler>>add:rn:rm: (in category 'ARM convenience instructions') ----- add: destReg rn: srcReg rm: addReg "return an ADD destReg, srcReg, addReg instruction + ADD destReg, srcReg, addReg - ARM_ARM v7 DDI10406 p. A8-24" - ADD destReg, srcReg, addReg" ^self type: 0 op: AddOpcode set: 0 rn: srcReg rd: destReg shifterOperand: addReg! Item was changed: ----- Method: CogARMCompiler>>adds:rn:imm:ror: (in category 'ARM convenience instructions') ----- adds: destReg rn: srcReg imm: immediate ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc + ADDS destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-23" - ADDS destReg, srcREg, #immediate ROR #rot" ^self type: 1 op: AddOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)! Item was changed: ----- Method: CogARMCompiler>>and:rn:imm:ror: (in category 'ARM convenience instructions') ----- and: destReg rn: srcReg imm: immediate ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc + AND destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-34" - AND destReg, srcReg, #immediate ROR #rot" ^self type: 1 op: AndOpcode set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)! Item was changed: ----- Method: CogARMCompiler>>ands:rn:imm:ror: (in category 'ARM convenience instructions') ----- ands: destReg rn: srcReg imm: immediate ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc + ANDS destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-34" - ANDS destReg, srcReg, #immediate ROR #rot" ^self type: 1 op: AndOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)! Item was changed: ----- Method: CogARMCompiler>>b: (in category 'ARM convenience instructions') ----- b: offset "return a B offset instruction; offset is signed 24bits of WORD offset, so +_32Mbyte range + B offset - ARM_ARM v7 DDI10406 pp. A8-44-5" - B offset" ^self cond: AL br: 0 offset: offset ! Item was changed: ----- Method: CogARMCompiler>>bics:rn:imm:ror: (in category 'ARM convenience instructions') ----- bics: destReg rn: srcReg imm: immediate ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc + BICS destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 pp. A8-50-1" - BICS destReg, srcReg, #immediate ROR #rot" ^self type: 1 op: BicOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)! Item was changed: ----- Method: CogARMCompiler>>bl: (in category 'ARM convenience instructions') ----- bl: offset "return a BL offset instruction; offset is signed 24bits of WORD offset, so +_32Mbyte range. Return address is in LR + BL offset - ARM_ARM v7 DDI10406 pp. A8-58-9" - BL offset" ^self cond: AL br: 1 offset: offset ! Item was changed: ----- Method: CogARMCompiler>>blx: (in category 'ARM convenience instructions') ----- blx: targetReg "Branch&link to the address in targetReg. Return address is in LR + BLX targetReg - ARM_ARM v7 DDI10406 pp. A8-60-1" - BX targetReg" <inline: true> ^self cond: AL bx: 1 target: targetReg ! Item was changed: ----- Method: CogARMCompiler>>bx: (in category 'ARM convenience instructions') ----- bx: targetReg + "Branch to address in targetReg. BX targetReg + BX targetReg - ARM_ARM v7 DDI10406 pp. A8-62-3" - "Branch to address in targetReg. BX targetReg" <inline: true> ^self cond: AL bx: 0 target: targetReg ! Item was changed: ----- Method: CogARMCompiler>>faddd:with: (in category 'ARM convenience instructions') ----- faddd: destReg with: srcReg "FADDD or VADD instruction to add double srcReg to double destReg and stick result in double destReg + FADDD destReg, destReg, srcReg - ARM_ARM v5 DDI 01001.pdf pp. C4-6 + VADD.F64 destReg, destReg, srcReg - ARM_ARM v7 DDI10406.pdf pp. A8-536-7" - ARM_ARM v5 DDI 01001.pdf pp. C4-6" <inline: true> ^((2r11101110001100000000101100000000 bitOr: destReg<<16 ) bitOr: destReg<<12) bitOr: srcReg! Item was changed: ----- Method: CogARMCompiler>>fcmpFrom:to: (in category 'ARM convenience instructions') ----- fcmpFrom: regA to: regB + "FCMPD or VCMP instruction to compare two fpu double registers. + FCMPD regA, regB - ARM_ARM v5 DDI 01001.pdf pp. C4-10 + VCMP.F64 regA, regB - ARM_ARM v7 DDI10406 -1" - "FCMP or VCMP instruction to compare two fpu double registers. - ARM_ARM v5 DDI 01001.pdf pp. C4-10" <inline: true> ^(2r11101110101101000000101101000000 bitOr:(regA <<12)) bitOr: regB! Item was changed: ----- Method: CogARMCompiler>>fcmpeFrom:to: (in category 'ARM convenience instructions') ----- fcmpeFrom: regA to: regB + "FCMPED or VCMPE instruction to compare two fpu double registers. + FCMPED regA, regB - ARM_ARM v5 DDI 01001.pdf pp. C4-12 + VCMPE.F64 regA,regB - ARM_ARM v7 DDI10406 pp. 570-1" - "FCMPE or VCMPE instruction to compare two fpu double registers. - ARM_ARM v5 DDI 01001.pdf pp. C4-12" <inline: true> ^(2r11101110101101000000101111000000 bitOr: (regA <<12)) bitOr: regB! Item was changed: ----- Method: CogARMCompiler>>fdivd:by: (in category 'ARM convenience instructions') ----- fdivd: dividend by: divisor "FDIVD or VDIV instruction to divide double dividend by double divisor and stick result in double dividend + FDIVD dividend, dividend, divisor - ARM_ARM v5 DDI 01001.pdf pp. C4-32 + VDIV.F64 dvidend, dividend, divisor - ARM_ARM v7 DDI10406 pp. A8-584-5" - ARM_ARM v5 DDI 01001.pdf pp. C4-32" <inline: true> ^((2r11101110100000000000101100000000 bitOr: dividend<<16 ) bitOr: dividend<<12) bitOr: divisor! Item was changed: ----- Method: CogARMCompiler>>fldd:rn:plus:imm: (in category 'ARM convenience instructions') ----- fldd: destReg rn: srcReg plus: u imm: immediate8bitValue "FLDD or VLDR instruction to move a value from address in an ARM srcReg +/- offset<<2 to an fpu double destReg + FLDD ARM_ARM v5 DDI 01001.pdf pp. C4-36 + VLDR.64 ARM_ARM v7 DDI10406 pp. A8-622-3" - ARM_ARM v5 DDI 01001.pdf pp. C4-36" <inline: true> "Note that offset is <<2 to make byte address u =1 -> srcReg + offset<<2 u=0 -> srgREg - offset<<2" ^(((2r11101101000100000000101100000000 bitOr:(srcReg <<16)) bitOr: destReg<<12) bitOr: u<<23) bitOr: immediate8bitValue! Item was changed: ----- Method: CogARMCompiler>>fmsrFrom:to: (in category 'ARM convenience instructions') ----- fmsrFrom: regA to: regB + "FMSR or VMOV instruction to move a value from an ARM reg to an fpu double register ready for conversion + FMSR regB, regA - ARM_ARM v5 DDI 01001.pdf pp. C4-68 + VMOV regB, regA - ARM_ARM v7 DDi10406 pp. A8-462-3" - "FMSR or VMSR instruction to move a value from an ARM reg to an fpu double register ready for conversion - ARM_ARM v5 DDI 01001.pdf pp. C4-68" <inline: true> |destReg| "the dest reg bits are spread out a little" destReg := (regB >>1) <<16 bitOr:(regB bitAnd: 1) << 7. ^(2r11101110000000000000101000010000 bitOr:(regA <<12)) bitOr: destReg! Item was changed: ----- Method: CogARMCompiler>>fmstat (in category 'ARM convenience instructions') ----- fmstat "FMSTAT or VMRS unconditional transfer FP status to cpsr to choose jumps etc. + FMSTAT r15, FPSCR - ARM_ARM v5 DDI 01001.pdf pp. C4-72 + VMRS APSR_nzcv, FPSCR - ARM_ARM v7 DDI10406 pp. A8-652-3" - ARM_ARM v5 DDI 01001.pdf pp. C4-72" <inline: true> ^2r11101110111100011111101000010000! Item was changed: ----- Method: CogARMCompiler>>fmuld:with: (in category 'ARM convenience instructions') ----- fmuld: destReg with: srcReg "FMULD or VMUL instruction to multiply double srcReg by double destReg and stick result in double destReg + FMULD destReg, destReg, srcReg - ARM_ARM v5 DDI 01001.pdf pp. C4-73 + VMUL.F64 destReg, destReg, srcReg - ARM_ARM v7 DDI10406 pp A8-658-9" - ARM_ARM v5 DDI 01001.pdf pp. C4-73" <inline: true> ^((2r11101110001000000000101100000000 bitOr: destReg<<16 ) bitOr: destReg<<12) bitOr: srcReg! Item was changed: ----- Method: CogARMCompiler>>fsitodFrom:to: (in category 'ARM convenience instructions') ----- fsitodFrom: regA to: regB "FSITOD or VCVT instruction to move convert an integer value to an fpu double + FSITOD regB, regA - ARM_ARM v5 DDI 01001.pdf pp. C4-95 + VCVTW. regB, regA - ARM_ARM v7 DDI10406.pdf pp. A8-576-8" - ARM_ARM v5 DDI 01001.pdf pp. C4-95" <inline: true> |srcReg| "the src reg bits are spread out a little" srcReg := (regA >>1) bitOr:(regA bitAnd: 1) << 5. ^(2r11101110101110000000101111000000 bitOr: srcReg ) bitOr: regB<<12! Item was changed: ----- Method: CogARMCompiler>>fsqrtd: (in category 'ARM convenience instructions') ----- fsqrtd: destReg "FSQRTD or VSQRT instruction to square root double dividend destReg and stick result in double destReg + ARM_ARM v5 DDI 01001.pdf pp. C4-97 + VSQRT.F64 destReg, destReg - ARM_ARM v7 DDI10406 pp. A8-756-7" - ARM_ARM v5 DDI 01001.pdf pp. C4-97" <inline: true> ^((2r11101110101100010000101111000000 ) bitOr: destReg<<12) bitOr: destReg! Item was changed: ----- Method: CogARMCompiler>>fstd:rn:plus:imm: (in category 'ARM convenience instructions') ----- + fstd: fpReg rn: addrReg plus: u imm: immediate8bitValue + "FSTD or VSTR instruction to move a value to address in an ARM addrReg +/- offset<<2 from an fpu double fpReg + FSTD fpReg, addrReg, #offset - ARM_ARM v5 DDI 01001.pdf pp. C4-101 + VSTR.64 fpReg, addrReg, #offset - ARM_ARM v7 DDI10406 pp. A8-780-1" - fstd: destReg rn: srcReg plus: u imm: immediate8bitValue - "FSTD or VSTR instruction to move a value to address in an ARM srcReg +/- offset<<2 from an fpu double destReg - ARM_ARM v5 DDI 01001.pdf pp. C4-101" <inline: true> "Note that offset is <<2 to make byte address + u =1 -> addrReg + offset<<2 + u=0 -> addrReg - offset<<2" + ^(((2r11101101000000000000101100000000 bitOr:(addrReg <<16)) bitOr: fpReg<<12) bitOr: u<<23) bitOr: immediate8bitValue! - u =1 -> srcReg + offset<<2 - u=0 -> srgREg - offset<<2" - ^(((2r11101101000000000000101100000000 bitOr:(srcReg <<16)) bitOr: destReg<<12) bitOr: u<<23) bitOr: immediate8bitValue! Item was changed: ----- Method: CogARMCompiler>>fsubd:with: (in category 'ARM convenience instructions') ----- fsubd: destReg with: srcReg "FSUBD or VSUB instruction to subtract double srcReg from double destREg and stick result in double destReg + FSUBD destReg, destReg, srcReg - ARM_ARM v5 DDI 01001.pdf pp. C4-112 + VSUB.F64 destReg, destReg, srcReg - ARM_ARM v7 DDI10406 pp. A8-784-5" - ARM_ARM v5 DDI 01001.pdf pp. C4-112" <inline: true> ^((2r11101110001100000000101101000000 bitOr: destReg<<16 ) bitOr: destReg<<12) bitOr: srcReg! Item was changed: ----- Method: CogARMCompiler>>genMulR:R: (in category 'abstract instructions') ----- genMulR: regSource R: regDest + "Use SMULL to produce a 64-bit result, explicitly in RISCTempReg,regDest. - ARM_ARM v7 DDI10406 pp. A8-354-5 - "Use SMULL to produce a 64-bit result, explicitly in RISCTempReg,regDest. By comparing RISCTempReg with regDest ASR 31(which effectively makes it 0 or -1) we know that the result being EQ means the hi reg and the top bit of the lo reg are the same - ie no overflow. The condition code can then be forced to oVerflow by use of MSR APSR_nzcvq, #1, lsl 28" | first | <var: 'first' type: #'AbstractInstruction *'> first := cogit gen: SMULL operand: regSource operand: regDest. "result in RISCTempReg,regDest" cogit gen: CMPSMULL operand: RISCTempReg operand: regDest. cogit gen: MSR operand: 1. ^first! Item was changed: ----- Method: CogARMCompiler>>ldr:rn:plus:imm: (in category 'ARM convenience instructions') ----- ldr: destReg rn: baseReg plus: u imm: immediate12bitValue + " LDR destReg, [baseReg, immediate12bitValue] u=0 -> subtract imm; =1 -> add imm - ARM_ARM v7 DDI10406 pp. A8-120-1" - " LDR destReg, [baseReg, immediate12bitValue] u=0 -> subtract imm; =1 -> add imm " ^self memMxr: AL reg: destReg base: baseReg u: u b: 0 l: 1 imm: immediate12bitValue! Item was changed: ----- Method: CogARMCompiler>>ldr:rn:plusImm: (in category 'ARM convenience instructions') ----- ldr: destReg rn: baseReg plusImm: immediate12bitValue + " LDR destReg, [baseReg, +immediate12bitValue] - ARM_ARM v7 DDI10406 pp. A8-120-1" - " LDR destReg, [baseReg, +immediate12bitValue]" ^self memMxr: AL reg: destReg base: baseReg u: 1 b: 0 l: 1 imm: immediate12bitValue! Item was changed: ----- Method: CogARMCompiler>>ldr:rn:rm: (in category 'ARM convenience instructions') ----- ldr: destReg rn: baseReg rm: offsetReg + " LDR destReg, [baseReg, + offsetReg] - ARM_ARM v7 DDI10406 pp. A8-124-5 - " LDR destReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed" ^self memMxr: AL reg: destReg base: baseReg p: 1 u: 1 b: 0 w: 0 l: 1 rm: offsetReg! Item was changed: ----- Method: CogARMCompiler>>ldrb:rn:plus:imm: (in category 'ARM convenience instructions') ----- ldrb: destReg rn: baseReg plus: u imm: immediate12bitValue + " LDRB destReg, [baseReg, 'u' immediate12bitValue] u=0 -> - ARM_ARM v7 DDI10406 pp. A8-128-9 - " LDRB destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm Note that this is a very low level interface that does not check the sign of the immediate, nor validity. See for example #concretizeMoveMbrR" ^self memMxr: AL reg: destReg base: baseReg u: u b: 1 l: 1 imm: immediate12bitValue! Item was changed: ----- Method: CogARMCompiler>>ldrb:rn:rm: (in category 'ARM convenience instructions') ----- ldrb: destReg rn: baseReg rm: offsetReg + " LDRB destReg, [baseReg, + offsetReg] - ARM_ARM v7 DDI10406 pp. A8-132-3 - " LDR destReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed" ^self memMxr: AL reg: destReg base: baseReg p: 1 u: 1 b: 1 w: 0 l: 1 rm: offsetReg! Item was changed: ----- Method: CogARMCompiler>>ldrh:rn:plus:imm: (in category 'ARM convenience instructions') ----- ldrh: destReg rn: baseReg plus: u imm: immediate8bitValue + " LDRH destReg, [baseReg, 'u' immediate8bitValue] u=0 -> subtract imm; =1 -> add imm - ARM_ARM v7 DDI10406 pp. A8-152-3" - " LDRH destReg, [baseReg, 'u' immediate8bitValue] u=0 -> subtract imm; =1 -> add imm " ^self memM16xr: AL reg: destReg base: baseReg p: 1 u: u w: 0 l: 1 offset: immediate8bitValue! Item was changed: ----- Method: CogARMCompiler>>ldrh:rn:rm: (in category 'ARM convenience instructions') ----- ldrh: destReg rn: baseReg rm: offsetReg + " LDRH destReg, [baseReg, +offsetReg] - ARM_ARM v7 DDI10406 pp. A8-156-7 - " LDRH destReg, [baseReg, +offsetReg] The contents of offsetReg are assumed to be correctly signed" ^self memM16xr: AL reg: destReg base: baseReg p: 1 u: 1 w: 0 l: 1 rm: offsetReg! Item was changed: ----- Method: CogARMCompiler>>mov:imm:ror: (in category 'ARM convenience instructions') ----- mov: destReg imm: immediate8bitValue ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc. + MOV destReg, #immediate8BitValue ROR rot - ARM_ARM v7 DDI10406 pp. A8-194-5" - MOV destReg, #immediate8BitValue ROR rot" ^self type: 1 op: MoveOpcode set: 0 rn: 0 rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)! Item was changed: ----- Method: CogARMCompiler>>mov:rn: (in category 'ARM convenience instructions') ----- mov: destReg rn: srcReg + " MOV destReg, srcReg - ARM_ARM v7 DDI10406 pp. A8-196-7" - " MOV destReg, srcReg" ^self type: 0 op: MoveOpcode set: 0 rn: 0 rd: destReg shifterOperand: srcReg! Item was changed: ----- Method: CogARMCompiler>>movs:rn: (in category 'ARM convenience instructions') ----- movs: destReg rn: srcReg + " MOVS destReg, srcReg - ARM_ARM v7 DDI10406 pp. A8-196-7" - " MOVS destReg, srcReg" ^self type: 0 op: MoveOpcode set: 1 rn: 0 rd: destReg shifterOperand: srcReg! Item was changed: ----- Method: CogARMCompiler>>mvn:imm:ror: (in category 'ARM convenience instructions') ----- mvn: destReg imm: immediate8bitValue ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc. + MVN destReg, #immediate8BitValue ROR rot - ARM_ARM v7 DDI10406 pp. A8-214-5" - MVN destReg, #immediate8BitValue ROR rot" ^self type: 1 op: MoveNotOpcode set: 0 rn: 0 rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)! Item was changed: ----- Method: CogARMCompiler>>orr:imm:ror: (in category 'ARM convenience instructions') ----- orr: destReg imm: immediate8bitValue ror: rot "Remember the ROR is doubled by the cpu so use 30>>1 etc. + ORR destReg, #immediate8BitValue ROR rot - ARM_ARM v7 DDI10406 pp. A8-228-9" - ORR destReg, #immediate8BitValue ROR rot" ^self type: 1 op: OrOpcode set: 0 rn: destReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)! Item was changed: ----- Method: CogARMCompiler>>pld:plus:offset: (in category 'encoding') ----- pld: baseReg plus: u offset: immediate + "hint to memory that we will want to read from baseReg +/- imediate sometime soon + PLD baseReg, immediate - ARM_ARM v7 DDI10406 pp. A8-236-7" - "hint to memory that we will want to read from baseReg +/- imediate sometime soon" <inline: true> ^ 2r11110101010100001111000000000000 bitOr: (baseReg<<16 bitOr:(u <<23 bitOr: immediate))! Item was changed: ----- Method: CogARMCompiler>>popR: (in category 'ARM convenience instructions') ----- popR: dstReg " pop word off TOS + LDR srcReg, [sp] #4 - ARM_ARM v7 DDI10406 pp. A8-120-1" - LDR srcReg, [sp] #4" ^self memMxr: AL reg: dstReg base: SP p: 0 u: 1 b: 0 w: 0 l: 1 imm: 4! Item was changed: ----- Method: CogARMCompiler>>pushR: (in category 'ARM convenience instructions') ----- pushR: srcReg " push word to TOS + STR srcReg, [sp, #-4]!! - ARM_ARM v7 DDI10406 pp. A8-382-3" - STR srcReg, [sp, #-4]!!" ^self memMxr: AL reg: srcReg base: SP p: 1 u: 0 b: 0 w: 1l: 0 imm: 4! Item was changed: ----- Method: CogARMCompiler>>stop (in category 'encoding') ----- stop + "generate a BKPT ( - ARM_ARM v7 DDI10406 pp. A8-56) instruction. We could, given a good enough creative impulse and an over-active sense of humour, add some numerically encoded witticism to this instruction in bits 8-19 & 0-3. It has no effect on the execution but can be a way to specify which breakpoint has been hit etc." - "generate a BKPT instruction. We could, given a good enough creative impulse and an over-active sense of humour, add some numerically encoded witticism to this instruction in bits 8-19 & 0-3. It has no effect on the execution but can be a way to specify which breakpoint has been hit etc." <inline: true> ^AL << 28 bitOr: (16r42 << 20 bitOr: (7 << 4))! Item was changed: ----- Method: CogARMCompiler>>str:rn:plus:imm: (in category 'ARM convenience instructions') ----- str: destReg rn: baseReg plus: u imm: immediate12bitValue + " STR destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm - ARM_ARM v7 DDI10406 pp. A8-382-3 " - " STR destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm " ^self memMxr: AL reg: destReg base: baseReg u: u b: 0 l: 0 imm: immediate12bitValue! Item was changed: ----- Method: CogARMCompiler>>str:rn:plusImm: (in category 'ARM convenience instructions') ----- str: srcReg rn: baseReg plusImm: immediate12bitValue + " STR srcReg, [baseReg, +immediate12bitValue] - ARM_ARM v7 DDI10406 pp. A8-382-3" - " STR srcReg, [baseReg, +immediate12bitValue]" ^self memMxr: AL reg: srcReg base: baseReg u: 1 b: 0 l: 0 imm: immediate12bitValue! Item was changed: ----- Method: CogARMCompiler>>str:rn:rm: (in category 'ARM convenience instructions') ----- str: srcReg rn: baseReg rm: offsetReg + " STR srcReg, [baseReg, + offsetReg] - ARM_ARM v7 DDI10406 pp. A8-384-5 - " STR srcReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed" ^self memMxr: AL reg: srcReg base: baseReg p: 1 u: 1 b: 0 w: 0 l: 0 rm: offsetReg! Item was changed: ----- Method: CogARMCompiler>>strb:rn:plus:imm: (in category 'ARM convenience instructions') ----- strb: destReg rn: baseReg plus: u imm: immediate12bitValue + " STRB destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm - ARM_ARM v7 DDI10406 pp. A8-388-9" - " STRB destReg, [baseReg, 'u' immediate12bitValue] u=0 -> subtract imm; =1 -> add imm " ^self memMxr: AL reg: destReg base: baseReg u: u b: 1 l: 0 imm: immediate12bitValue! Item was changed: ----- Method: CogARMCompiler>>strb:rn:rm: (in category 'ARM convenience instructions') ----- strb: srcReg rn: baseReg rm: offsetReg + " STRB srcReg, [baseReg, + offsetReg] - ARM_ARM v7 DDI10406 pp. A8-390-1 - " STRB srcReg, [baseReg, + offsetReg] The contents of offsetReg are assumed to be correctly signed" ^self memMxr: AL reg: srcReg base: baseReg p: 1 u: 1 b: 1 w: 0 l: 0 rm: offsetReg! Item was changed: ----- Method: CogARMCompiler>>strh:rn:plus:imm: (in category 'ARM convenience instructions') ----- strh: destReg rn: baseReg plus: u imm: immediate8bitValue + " STRH destReg, [baseReg, 'u' immediate8bitValue] u=0 -> subtract imm; =1 -> add imm - ARM_ARM v7 DDI10406 pp. A8-408-9" - " STRH destReg, [baseReg, 'u' immediate8bitValue] u=0 -> subtract imm; =1 -> add imm " ^self memM16xr: AL reg: destReg base: baseReg p: 1 u: u w: 0 l: 0 offset: immediate8bitValue! Item was changed: ----- Method: CogARMCompiler>>strh:rn:rm: (in category 'ARM convenience instructions') ----- strh: srcReg rn: baseReg rm: offsetReg + " STRH srcReg, [baseReg, +offsetReg] - ARM_ARM v7 DDI10406 pp. A8-410-1" - " STRH srcReg, [baseReg, +offsetReg]" ^self memM16xr: AL reg: srcReg base: baseReg p: 1 u: 1 w: 0 l: 0 rm: offsetReg! Item was changed: ----- Method: CogARMCompiler>>sub:rn:imm:ror: (in category 'ARM convenience instructions') ----- sub: destReg rn: srcReg imm: immediate ror: rot " Remember the ROR is doubled by the cpu so use 30>>1 etc + SUB destReg, srcReg, #immediate ROR rot - ARM_ARM v7 DDI10406 pp. A8-418-9" - SUB destReg, srcReg, #immediate ROR rot" ^self type: 1 op: SubOpcode set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)! Item was changed: ----- Method: CogARMCompiler>>subs:rn:imm:ror: (in category 'ARM convenience instructions') ----- subs: destReg rn: srcReg imm: immediate ror: rot " Remember the ROR is doubled by the cpu so use 30>>1 etc + SUBS destReg, srcReg, #immediate ROR rot - ARM_ARM v7 DDI10406 pp. A8-418-9" - SUBS destReg, srcReg, #immediate ROR rot" ^self type: 1 op: SubOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)! Item was changed: ----- Method: CogARMCompiler>>tst:rn:imm:ror: (in category 'ARM convenience instructions') ----- tst: ignored rn: srcReg imm: immediate ror: rot " Remember the ROR is doubled by the cpu so use 30>>1 etc" "also note that TST has no destReg + TST srcReg, #immediate ROR rot - ARM_ARM v7 DDI10406 pp. A8-452-3" - TST srcReg, #immediate ROR rot" ^self type: 1 op: TstOpcode set: 1 rn: srcReg rd: 0 shifterOperand: ((rot>>1) <<8 bitOr: immediate)!

1 0

[commit][3709] And get the method names for r0 through r12 right.
by commits＠squeakvm.org 10 May '16

10 May '16

Revision: 3709 Author: eliot Date: 2016-05-10 11:35:52 -0700 (Tue, 10 May 2016) Log Message: ----------- And get the method names for r0 through r12 right. Modified Paths: -------------- branches/Cog/processors/ARM/exploration/printcpu.c Modified: branches/Cog/processors/ARM/exploration/printcpu.c =================================================================== --- branches/Cog/processors/ARM/exploration/printcpu.c 2016-05-10 18:02:52 UTC (rev 3708) +++ branches/Cog/processors/ARM/exploration/printcpu.c 2016-05-10 18:35:52 UTC (rev 3709) @@ -45,19 +45,19 @@ printf("!GdbARMAlien class methodsFor: 'instance creation' stamp: 'eem %d/%d/%d %d:%02d'!\r" "dataSize\r\t^%ld! !\r", m,d,y,h,i, sizeof(ARMul_State)); - print(0,0); - print(1,1); - print(2,2); - print(3,3); - print(4,4); - print(5,5); - print(6,6); - print(7,7); - print(8,8); - print(9,9); - print(10,10); - print(11,11); - print(12,12); + print(0,r0); + print(1,r1); + print(2,r2); + print(3,r3); + print(4,r4); + print(5,r5); + print(6,r6); + print(7,r7); + print(8,r8); + print(9,r9); + print(10,r10); + print(11,r11); + print(12,r12); print(13,SP); print(14,LR); print(15,PC);

1 0

[commit][3708] Add code to generate some of the accessors for the GdbARMAlien.
by commits＠squeakvm.org 10 May '16

10 May '16

Revision: 3708 Author: eliot Date: 2016-05-10 11:02:52 -0700 (Tue, 10 May 2016) Log Message: ----------- Add code to generate some of the accessors for the GdbARMAlien. Modified Paths: -------------- branches/Cog/processors/ARM/exploration/Makefile branches/Cog/processors/ARM/exploration/printcpu.c Added Paths: ----------- branches/Cog/processors/ARM/exploration/ branches/Cog/processors/ARM/exploration/printcpuvfp.c Removed Paths: ------------- branches/Cog/processors/ARM/exploration/printcpucr.c branches/Cog/processors/ARM/exploration/printcpuxmm.c Modified: branches/Cog/processors/ARM/exploration/Makefile =================================================================== --- branches/Cog/processors/IA32/bochs/exploration/Makefile 2016-05-06 20:37:49 UTC (rev 3704) +++ branches/Cog/processors/ARM/exploration/Makefile 2016-05-10 18:02:52 UTC (rev 3708) @@ -1,41 +1,31 @@ -#LIBDEPS=../../bochs/cpu/libcpu.a -#BOCHS=../../bochs -#BOCHSEXP=../../bochs/exploration LIBDEPS=../cpu/libcpu.a -BOCHS=../../../processors/IA32/bochs -BOCHSEXP=. -CFLAGS=-m32 -I.. -I$(BOCHS) -I$(BOCHS)/cpu -I$(BOCHS)/instrument/stubs -L../cpu -lcpu +GDBARM=../../../processors/ARM/gdb-7.10 +GDBARMEXP=. +INCLUDES := -I$(GDBARM)/include \ + -I$(GDBARM)/sim/arm \ + -I$(GDBARM)/bfd \ + -I../bfd +LIBS:=-L../bfd -L../libiberty -L../opcodes -L../sim/arm -L../zlib \ + -lbfd -liberty -lopcodes -lopcodes -lsim -lz +CFLAGS=-m32 $(INCLUDES) $(LIBS) .PHONY: $(LIBDEPS) -#all: bxcpu.txt BochsIA32Alien-regs.st BochsIA32Alien-cr.st BochsIA32Alien-xmm.st -all: BochsIA32Alien-regs.st BochsIA32Alien-cr.st BochsIA32Alien-xmm.st +all: GdbARMAlien-regs.st GdbARMAlien-vfp.st -bxcpu.txt: printbxcpu - ./printbxcpu >bxcpu.txt +GdbARMAlien-regs.st: printcpu + ./printcpu >GdbARMAlien-regs.st -BochsIA32Alien-regs.st: printcpu - ./printcpu >BochsIA32Alien-regs.st +GdbARMAlien-vfp.st: printcpuvfp + ./printcpuvfp >GdbARMAlien-vfp.st -BochsIA32Alien-cr.st: printcpucr - ./printcpucr >BochsIA32Alien-cr.st - -BochsIA32Alien-xmm.st: printcpuxmm - ./printcpuxmm >BochsIA32Alien-xmm.st - clean: - rm -f BochsIA32Alien-regs.st BochsIA32Alien-cr.st BochsIA32Alien-xmm.st - rm -f printcpu printcpucr printcpuxmm - rm -f printcpu.exe printcpucr.exe printcpuxmm.exe + rm -f GdbARMAlien-regs.st GdbARMAlien-vfp.st + rm -f printcpu printcpuvfp + rm -f printcpu.exe printcpuvfp.exe -printbxcpu: $(BOCHSEXP)/printbxcpu.cpp $(LIBDEPS) - g++ -o $@ $< $(CFLAGS) +printcpu: $(GDBARMEXP)/printcpu.c $(LIBDEPS) + $(CC) -o $@ $< $(CFLAGS) -printcpu: $(BOCHSEXP)/printcpu.c $(LIBDEPS) - g++ -o $@ $< $(CFLAGS) - -printcpucr: $(BOCHSEXP)/printcpucr.c $(LIBDEPS) - g++ -o $@ $< $(CFLAGS) - -printcpuxmm: $(BOCHSEXP)/printcpuxmm.c $(LIBDEPS) - g++ -o $@ $< $(CFLAGS) +printcpuvfp: $(GDBARMEXP)/printcpuvfp.c $(LIBDEPS) + $(CC) -o $@ $< $(CFLAGS) Modified: branches/Cog/processors/ARM/exploration/printcpu.c =================================================================== --- branches/Cog/processors/IA32/bochs/exploration/printcpu.c 2016-05-06 20:37:49 UTC (rev 3704) +++ branches/Cog/processors/ARM/exploration/printcpu.c 2016-05-10 18:02:52 UTC (rev 3708) @@ -1,17 +1,13 @@ -/* -% g++ -I.. -I../cpu -I../instrument/stubs -Wno-invalid-offsetof @ -o # - */ +#include <stdlib.h> +#include <ctype.h> +#include <string.h> +#include <time.h> -#include <stddef.h> - #define COG 1 +#define FOR_COG_PLUGIN 1 -#include <bochs.h> +#include <armdefs.h> -#define NEED_CPU_REG_SHORTCUTS - -#include <cpu.h> - static char buf[10]; char * @@ -27,20 +23,15 @@ int main() { +#define offsetof(type,field) (long)(&(((type *)0)->field)) #define stoffsetof(type,field) (offsetof(type,field)+1) -#define print(r,n,b) \ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ +#define print(n,r) \ +printf("!GdbARMAlien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ "%s\r\t^self unsignedLongAt: %ld! !\r", m,d,y,h,i, lower(#r), \ - stoffsetof(BX_CPU_C,gen_reg[n].dword.erx));\ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ + stoffsetof(ARMul_State,Reg[n]));\ +printf("!GdbARMAlien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ "%s: anUnsignedInteger\r\t^self unsignedLongAt: %ld put: anUnsignedInteger! !\r", m,d,y,h,i, lower(#r), \ - stoffsetof(BX_CPU_C,gen_reg[n].dword.erx));\ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ - "%s\r\t^self unsignedByteAt: %ld! !\r", m,d,y,h,i, lower(#b), \ - stoffsetof(BX_CPU_C,gen_reg[n].dword.erx));\ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ - "%s: anUnsignedInteger\r\t^self unsignedByteAt: %ld put: anUnsignedInteger! !\r", m,d,y,h,i, lower(#b), \ - stoffsetof(BX_CPU_C,gen_reg[n].dword.erx)) + stoffsetof(ARMul_State,Reg[n])) time_t nowsecs = time(0); struct tm now = *localtime(&nowsecs); @@ -51,22 +42,25 @@ int i = now.tm_min; printf("\"Hello world!!\"!\r"); - printf("!BochsIA32Alien class methodsFor: 'instance creation' stamp: 'eem %d/%d/%d %d:%02d'!\r" - "dataSize\r\t^%ld! !\r", m,d,y,h,i, sizeof(BX_CPU_C)); + printf("!GdbARMAlien class methodsFor: 'instance creation' stamp: 'eem %d/%d/%d %d:%02d'!\r" + "dataSize\r\t^%ld! !\r", m,d,y,h,i, sizeof(ARMul_State)); - printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r" - "eflags\r\t^self unsignedLongAt: %ld! !\r", m,d,y,h,i, - stoffsetof(BX_CPU_C,eflags)); + print(0,0); + print(1,1); + print(2,2); + print(3,3); + print(4,4); + print(5,5); + print(6,6); + print(7,7); + print(8,8); + print(9,9); + print(10,10); + print(11,11); + print(12,12); + print(13,SP); + print(14,LR); + print(15,PC); - print(EAX,BX_32BIT_REG_EAX,al); - print(EBX,BX_32BIT_REG_EBX,bl); - print(ECX,BX_32BIT_REG_ECX,cl); - print(EDX,BX_32BIT_REG_EDX,dl); - print(ESP,BX_32BIT_REG_ESP,spl); - print(EBP,BX_32BIT_REG_EBP,bpl); - print(ESI,BX_32BIT_REG_ESI,sil); - print(EDI,BX_32BIT_REG_EDI,dil); - print(EIP,BX_32BIT_REG_EIP,ipl); /* the ipl: method should be discarded */ - return 0; } Deleted: branches/Cog/processors/ARM/exploration/printcpucr.c =================================================================== --- branches/Cog/processors/IA32/bochs/exploration/printcpucr.c 2016-05-06 20:37:49 UTC (rev 3704) +++ branches/Cog/processors/ARM/exploration/printcpucr.c 2016-05-10 18:02:52 UTC (rev 3708) @@ -1,62 +0,0 @@ -/* -% g++ -I.. -I../cpu -I../instrument/stubs -Wno-invalid-offsetof @ -o # - */ - -#include <stddef.h> - -#define COG 1 - -#include <bochs.h> - -#define NEED_CPU_REG_SHORTCUTS - -#include <cpu.h> - -static char buf[10]; - -char * -munge(char *s) -{ - int i, d; - for (i = 0, d = 0; i + d < strlen(s); i++) - buf[i] = (s[i+d] == '_' && s[i+d+1]) - ? toupper(s[++d+i]) - : tolower(s[i+d]); - buf[i] = 0; - return buf; -} - -int -main() -{ -#define stoffsetof(type,field) (offsetof(type,field)+1) -#define print(r,ra,len) \ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ - "%s\r\t^self unsigned" #len "At: %ld! !\r", m,d,y,h,i, munge(#r), \ - stoffsetof(BX_CPU_C,ra));\ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ - "%s: anUnsignedInteger\r\t^self unsigned" #len "At: %ld put: anUnsignedInteger! !\r", m,d,y,h,i, munge(#r), \ - stoffsetof(BX_CPU_C,ra)); - - time_t nowsecs = time(0); - struct tm now = *localtime(&nowsecs); - int m = now.tm_mon + 1; /* strange but true */ - int d = now.tm_mday; - int y = now.tm_year + 1900; - int h = now.tm_hour; - int i = now.tm_min; - - printf("\"Hello world!!\"!\r"); - - print(cr0,cr0.val32,LongLong); - print(cr1,cr1,LongLong); - print(cr2,cr2,LongLong); - print(cr3,cr3,LongLong); - print(cr4,cr4.val32,LongLong); - - print(stop_reason,stop_reason,Byte); - print(save_eip,save_eip,Long); - print(save_esp,save_esp,Long); - - return 0; -} Copied: branches/Cog/processors/ARM/exploration/printcpuvfp.c (from rev 3704, branches/Cog/processors/IA32/bochs/exploration/printcpuxmm.c) =================================================================== --- branches/Cog/processors/ARM/exploration/printcpuvfp.c (rev 0) +++ branches/Cog/processors/ARM/exploration/printcpuvfp.c 2016-05-10 18:02:52 UTC (rev 3708) @@ -0,0 +1,82 @@ +#include <stdlib.h> +#include <ctype.h> +#include <string.h> +#include <time.h> + +#define COG 1 +#define FOR_COG_PLUGIN 1 + +#include <armdefs.h> + +static char buf[10]; + +char * +lower(char *s) +{ + int i; + for (i = 0; i < strlen(s); i++) + buf[i] = tolower(s[i]); + buf[i] = 0; + return buf; +} + +int +main() +{ +#define offsetof(type,field) (long)(&(((type *)0)->field)) +#define stoffsetof(type,field) (offsetof(type,field)+1) +#define print(n,r) \ +printf("!GdbARMAlien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ + "%s\r\t^self unsignedLongLongAt: %ld! !\r", m,d,y,h,i, lower(#r), \ + stoffsetof(ARMul_State,VFP_Reg[n].dword));\ +printf("!GdbARMAlien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ + "%s: anUnsignedInteger\r\t^self unsignedLongLongAt: %ld put: anUnsignedInteger! !\r", m,d,y,h,i, lower(#r), \ + stoffsetof(ARMul_State,VFP_Reg[n].dword)) + + time_t nowsecs = time(0); + struct tm now = *localtime(&nowsecs); + int m = now.tm_mon + 1; /* strange but true */ + int d = now.tm_mday; + int y = now.tm_year + 1900; + int h = now.tm_hour; + int i = now.tm_min; + + printf("\"Hello world!!\"!\r"); + printf("!GdbARMAlien class methodsFor: 'instance creation' stamp: 'eem %d/%d/%d %d:%02d'!\r" + "dataSize\r\t^%ld! !\r", m,d,y,h,i, sizeof(ARMul_State)); + + print(0,d0); + print(1,d1); + print(2,d2); + print(3,d3); + print(4,d4); + print(5,d5); + print(6,d6); + print(7,d7); + print(8,d8); + print(9,d9); + print(10,d10); + print(11,d11); + print(12,d12); + print(13,d13); + print(14,d14); + print(15,d15); + print(16,d16); + print(17,d17); + print(18,d18); + print(19,d19); + print(20,d20); + print(21,d21); + print(22,d22); + print(23,d23); + print(24,d24); + print(25,d25); + print(26,d26); + print(27,d27); + print(28,d28); + print(29,d29); + print(30,d30); + print(31,d31); + + return 0; +} Deleted: branches/Cog/processors/ARM/exploration/printcpuxmm.c =================================================================== --- branches/Cog/processors/IA32/bochs/exploration/printcpuxmm.c 2016-05-06 20:37:49 UTC (rev 3704) +++ branches/Cog/processors/ARM/exploration/printcpuxmm.c 2016-05-10 18:02:52 UTC (rev 3708) @@ -1,68 +0,0 @@ -/* -% g++ -I.. -I../cpu -I../instrument/stubs -Wno-invalid-offsetof @ -o # - */ - -#include <stddef.h> - -#define COG 1 - -#include <bochs.h> - -#define NEED_CPU_REG_SHORTCUTS - -#include <cpu.h> - -static char buf[10]; - -char * -lower(char *s) -{ - int i; - for (i = 0; i < strlen(s); i++) - buf[i] = tolower(s[i]); - buf[i] = 0; - return buf; -} - -int -main() -{ -#define stoffsetof(type,field) (offsetof(type,field)+1) -#define print(r,n,lh) \ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ - "%s\r\t^self unsignedLongLongAt: %ld! !\r", m,d,y,h,i, lower(#r), \ - stoffsetof(BX_CPU_C,xmm[n]._u64[lh]));\ -printf("!BochsIA32Alien methodsFor: 'accessing' stamp: 'eem %d/%d/%d %d:%02d'!\r"\ - "%s: anUnsignedInteger\r\t^self unsignedLongLongAt: %ld put: anUnsignedInteger! !\r", m,d,y,h,i, lower(#r), \ - stoffsetof(BX_CPU_C,xmm[n]._u64[lh]));\ - - time_t nowsecs = time(0); - struct tm now = *localtime(&nowsecs); - int m = now.tm_mon + 1; /* strange but true */ - int d = now.tm_mday; - int y = now.tm_year + 1900; - int h = now.tm_hour; - int i = now.tm_min; - - printf("\"Hello world!!\"!\r"); - - print(XMM0Low,0,0); - print(XMM1Low,1,0); - print(XMM2Low,2,0); - print(XMM3Low,3,0); - print(XMM4Low,4,0); - print(XMM5Low,5,0); - print(XMM6Low,6,0); - print(XMM7Low,7,0); - - print(XMM0High,0,1); - print(XMM1High,1,1); - print(XMM2High,2,1); - print(XMM3High,3,1); - print(XMM4High,4,1); - print(XMM5High,5,1); - print(XMM6High,6,1); - print(XMM7High,7,1); - - return 0; -}

1 0

[commit][3704] converting int to pointer is 64bits risky, better use long even for dummy
by commits＠squeakvm.org 10 May '16

10 May '16

Revision: 3704 Author: nice Date: 2016-05-06 13:37:49 -0700 (Fri, 06 May 2016) Log Message: ----------- converting int to pointer is 64bits risky, better use long even for dummy Modified Paths: -------------- branches/Cog/platforms/iOS/plugins/SqueakFFIPrims/dummyFFI.c branches/Cog/platforms/iOS/vm/iPhone/plugins/SqueakFFIPrims/dummyFFI.c Modified: branches/Cog/platforms/iOS/plugins/SqueakFFIPrims/dummyFFI.c =================================================================== --- branches/Cog/platforms/iOS/plugins/SqueakFFIPrims/dummyFFI.c 2016-05-06 20:22:49 UTC (rev 3703) +++ branches/Cog/platforms/iOS/plugins/SqueakFFIPrims/dummyFFI.c 2016-05-06 20:37:49 UTC (rev 3704) @@ -157,7 +157,7 @@ /* ffiFree: Free space from the external heap */ -int ffiFree(int pointer) +int ffiFree(long pointer) { return 1; } Modified: branches/Cog/platforms/iOS/vm/iPhone/plugins/SqueakFFIPrims/dummyFFI.c =================================================================== --- branches/Cog/platforms/iOS/vm/iPhone/plugins/SqueakFFIPrims/dummyFFI.c 2016-05-06 20:22:49 UTC (rev 3703) +++ branches/Cog/platforms/iOS/vm/iPhone/plugins/SqueakFFIPrims/dummyFFI.c 2016-05-06 20:37:49 UTC (rev 3704) @@ -157,7 +157,7 @@ } -int ffiFree(int ptr) +int ffiFree(long ptr) { if (ptr) free((void *)ptr); return 1;

6 8

VM Maker: CogTools-eem.73.mcz
by commits＠source.squeak.org 10 May '16

10 May '16

Eliot Miranda uploaded a new version of CogTools to project VM Maker: http://source.squeak.org/VMMaker/CogTools-eem.73.mcz ==================== Summary ==================== Name: CogTools-eem.73 Author: eem Time: 9 May 2016, 10:47:35.884962 pm UUID: 61755c3f-e544-49bd-b2ac-62c7892fd89c Ancestors: CogTools-eem.72 Add the primitive that answers available machine code pcs for a method to the VMProfiler. As yet unused. =============== Diff against CogTools-eem.72 =============== Item was added: + ----- Method: CompiledMethod>>methodPCData (in category '*CogTools-method introspection') ----- + methodPCData + "If the method is linked to a cogit method, answers the values of the bytecode and + machine code pc pairs which are mapped to each other in the VM. The first two + pairs have nil byetcode pcs and map to the checked and unchecked entrypoints + for methods and the no-context-switch and normal entries for blocks." + <primitive: 'primitiveMethodPCData' module:''> + ^#()!

1 0

VM Maker: Cog-eem.318.mcz
by commits＠source.squeak.org 10 May '16

10 May '16

Eliot Miranda uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-eem.318.mcz ==================== Summary ==================== Name: Cog-eem.318 Author: eem Time: 9 May 2016, 10:46:11.557606 pm UUID: 089a0b72-a28d-4fda-8f87-7008a889773a Ancestors: Cog-eem.317 Add incomplete support for emulating floating point operations in the GdbARMAlien =============== Diff against Cog-eem.317 =============== Item was changed: ----- Method: GdbARMAlien>>handleExecutionPrimitiveFailureIn:minimumAddress: (in category 'error handling') ----- handleExecutionPrimitiveFailureIn: memoryArray "<Bitmap|ByteArray>" minimumAddress: minimumAddress "<Integer>" "Handle an execution primitive failure. Convert out-of-range call and absolute memory read into register instructions into ProcessorSimulationTrap signals." "self printRegistersOn: Transcript" | pcOnEntry pc instr | + pc := pcOnEntry := self pc. - pcOnEntry := self pc. self endCondition = InstructionPrefetchError ifTrue: + [pc := self pc: self priorPc]. - [self pc: self priorPc]. + (pc between: minimumAddress and: memoryArray byteSize - 1) ifTrue: - ((pc := self pc) between: minimumAddress and: memoryArray byteSize - 1) ifTrue: [instr := memoryArray unsignedLongAt: pc + 1 bigEndian: false. (self endCondition = InstructionPrefetchError) ifTrue: [^self handleFailingBranch: instr to: pcOnEntry at: pc]. (self instructionIsAnyLoadStore: instr) ifTrue: [^self handleFailingLoadStore: instr at: pc]. + (self instructionIsAnyFPArithmetic: instr) ifTrue: + [^self handleFailingFPArithmetic: instr at: pc]. + ^self handleExecutionPrimitiveFailureAt: pc in: memoryArray]. ^self reportPrimitiveFailure! Item was added: + ----- Method: GdbARMAlien>>handleFailingFPArithmetic:at: (in category 'error handling') ----- + handleFailingFPArithmetic: instr at: pc + | oneRegTransferMask twoRegTransferMask | + oneRegTransferMask := 16rF000F00. + (instr bitAnd: oneRegTransferMask) = 16rE000B00 ifTrue: + [^self handleOneRegTransferDoubleArithmetic: instr at: pc]. + (instr bitAnd: oneRegTransferMask) = 16rE000A00 ifTrue: + [^self handleOneRegTransferSingleArithmetic: instr at: pc]. + twoRegTransferMask := 16rFE00FC0. + (instr bitAnd: twoRegTransferMask) = 16rC400B00 ifTrue: + [^self handleTwoRegTransferDoubleArithmetic: instr at: pc]. + (instr bitAnd: twoRegTransferMask) = 16rC400A00 ifTrue: + [^self handleTwoRegTransferSingleArithmetic: instr at: pc]. + ^self reportPrimitiveFailure! Item was added: + ----- Method: GdbARMAlien>>handleOneRegTransferDoubleArithmetic:at: (in category 'floating-point emulation') ----- + handleOneRegTransferDoubleArithmetic: instr at: pc + "Emulate a one-register transfer VFP instruction." + | rn rd rm vn vm | + rn := instr >> 16 bitAnd: 15. + rd := instr >> 12 bitAnd: 15. + rm := instr bitAnd: 15. + vn := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rn + 18)). "Assume accesses fp regs" + vm := Float fromIEEE64BitWord: (self perform: (self registerStateGetters at: rm + 18)). "Assume accesses fp regs" + (instr >> 18 bitAnd: 31) + caseOf: { + [8 "FMULD"] -> + [| r | + r := vn * vm. + self perform: (self registerStateSetters at: rd + 18) with: r asIEEE64BitWord]. + [12"FADDD/FSUBD"] -> + [self shouldBeImplemented]. + [32"FDIVD"] -> + [self shouldBeImplemented]. + [45"FCMPD"] -> + [self shouldBeImplemented]. } + otherwise: [self reportPrimitiveFailure]! Item was added: + ----- Method: GdbARMAlien>>instructionIsAnyFPArithmetic: (in category 'testing') ----- + instructionIsAnyFPArithmetic: instr + "Identify single register transfer and double register transfer VFP instructions. + See C3.3 & C3.4 in the ARM ARM." + | oneRegTransferMask twoRegTransferMask | + oneRegTransferMask := 16rF000F00. + (instr bitAnd: oneRegTransferMask) = 16rE000A00 ifTrue: + [^true]. + (instr bitAnd: oneRegTransferMask) = 16rE000B00 ifTrue: + [^true]. + twoRegTransferMask := 16rFE00FC0. + (instr bitAnd: twoRegTransferMask) = 16rC400A00 ifTrue: + [^true]. + (instr bitAnd: twoRegTransferMask) = 16rC400B00 ifTrue: + [^true]. + ^false! Item was changed: ----- Method: GdbARMAlien>>registerStateGetters (in category 'accessing-abstract') ----- registerStateGetters + ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 sp lr pc eflags + d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15)! - ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 sl fp r12 sp lr pc eflags)! Item was changed: ----- Method: GdbARMAlien>>registerStateSetters (in category 'accessing-abstract') ----- registerStateSetters + ^#( r0: r1: r2: r3: r4: r5: r6: r7: r8: r9: sl: fp: r12: sp: lr: pc: eflags: + d0: d1: d2: d3: d4: d5: d6: d7: d8: d9: d10: d11: d12: d13: d14: d15:)! - "a list of register setting messages used to initialise or reset registers" - ^#( r0: r1: r2: r3: r4: r5: r6: r7: r8: r9: sl: fp: r12: sp: lr: pc: eflags:)!

1 0

[commit][3707] CogVM source as per VMMaker.oscog-eem.1856
by commits＠squeakvm.org 10 May '16

10 May '16

Revision: 3707 Author: eliot Date: 2016-05-09 19:18:53 -0700 (Mon, 09 May 2016) Log Message: ----------- CogVM source as per VMMaker.oscog-eem.1856 Fix two regressions introduced into the ARM cogit in the register allocation changes made recently. a) getSave/RestoreRegs: should do nothing on ARM, and b) Extra0Reg must be distinct from the other registers (!!). Modified Paths: -------------- branches/Cog/nsspur64src/vm/cogit.h branches/Cog/nsspur64src/vm/cogitX64.c branches/Cog/nsspur64src/vm/cointerp.c branches/Cog/nsspur64src/vm/cointerp.h branches/Cog/nsspur64src/vm/gcc3x-cointerp.c branches/Cog/nsspursrc/vm/cogit.h branches/Cog/nsspursrc/vm/cogitARMv5.c branches/Cog/nsspursrc/vm/cogitIA32.c branches/Cog/nsspursrc/vm/cogitMIPSEL.c branches/Cog/nsspursrc/vm/cointerp.c branches/Cog/nsspursrc/vm/cointerp.h branches/Cog/nsspursrc/vm/gcc3x-cointerp.c branches/Cog/nsspurstack64src/vm/gcc3x-interp.c branches/Cog/nsspurstack64src/vm/interp.c branches/Cog/nsspurstacksrc/vm/gcc3x-interp.c branches/Cog/nsspurstacksrc/vm/interp.c branches/Cog/spur64src/vm/cogit.h branches/Cog/spur64src/vm/cogitX64.c branches/Cog/spur64src/vm/cointerp.c branches/Cog/spur64src/vm/cointerp.h branches/Cog/spur64src/vm/gcc3x-cointerp.c branches/Cog/spursistasrc/vm/cogit.h branches/Cog/spursistasrc/vm/cogitARMv5.c branches/Cog/spursistasrc/vm/cogitIA32.c branches/Cog/spursistasrc/vm/cogitMIPSEL.c branches/Cog/spursistasrc/vm/cointerp.c branches/Cog/spursistasrc/vm/cointerp.h branches/Cog/spursistasrc/vm/gcc3x-cointerp.c branches/Cog/spursrc/vm/cogit.h branches/Cog/spursrc/vm/cogitARMv5.c branches/Cog/spursrc/vm/cogitIA32.c branches/Cog/spursrc/vm/cogitMIPSEL.c branches/Cog/spursrc/vm/cointerp.c branches/Cog/spursrc/vm/cointerp.h branches/Cog/spursrc/vm/gcc3x-cointerp.c branches/Cog/spurstack64src/vm/gcc3x-interp.c branches/Cog/spurstack64src/vm/interp.c branches/Cog/spurstacksrc/vm/gcc3x-interp.c branches/Cog/spurstacksrc/vm/interp.c branches/Cog/src/vm/cogit.h branches/Cog/src/vm/cogitARMv5.c branches/Cog/src/vm/cogitIA32.c branches/Cog/src/vm/cogitMIPSEL.c Property Changed: ---------------- branches/Cog/platforms/Cross/vm/sqSCCSVersion.h Modified: branches/Cog/nsspur64src/vm/cogit.h =================================================================== --- branches/Cog/nsspur64src/vm/cogit.h 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspur64src/vm/cogit.h 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ Modified: branches/Cog/nsspur64src/vm/cogitX64.c =================================================================== --- branches/Cog/nsspur64src/vm/cogitX64.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspur64src/vm/cogitX64.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e " __DATE__ ; +static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__cogitBuildInfo = __buildInfo; Modified: branches/Cog/nsspur64src/vm/cointerp.c =================================================================== --- branches/Cog/nsspur64src/vm/cointerp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspur64src/vm/cointerp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2436,7 +2436,7 @@ /*560*/ -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, 0, 0, 0,-1,-1 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1856"; sqInt minBackwardJumpCountForCompile = MinBackwardJumpCountForCompile /* 40 */; volatile int sendTrace; @@ -41189,7 +41189,7 @@ sqInt oopRcvr; sqInt oopResult; usqLong result; - sqInt resultIsNegative; + int resultIsNegative; char *sp; oopArg = longAt(GIV(stackPointer) + (0 * BytesPerWord)); @@ -42991,7 +42991,7 @@ sqInt fmt; usqInt instBytes; sqInt instFormat; - usqInt newFormat; + sqInt newFormat; sqInt normalizedInstFormat; usqInt numBytes; usqInt numSlots; @@ -47095,7 +47095,7 @@ sqInt effectsFlags1; sqInt errCode; sqInt fieldOffset; - sqInt fieldOffset1; + usqInt fieldOffset1; sqInt fmt; sqInt hash; sqInt header; @@ -61362,7 +61362,7 @@ usqInt prevFree; usqInt prevFreeChunk; usqInt prevPrevFree; - usqInt prevPrevFreeChunk; + sqInt prevPrevFreeChunk; sqInt slotBytes; sqInt slotBytes1; usqInt there; @@ -67174,7 +67174,7 @@ bridgeFromto(SpurSegmentInfo *aSegment, SpurSegmentInfo *nextSegmentOrNil) { usqInt bridgeSpan; - sqInt clifton; + usqInt clifton; usqInt segEnd; segEnd = ((aSegment->segSize)) + ((aSegment->segStart)); @@ -67355,7 +67355,7 @@ static void postSnapshot(void) { DECL_MAYBE_SQ_GLOBAL_STRUCT - sqInt address; + usqInt address; sqInt bytes; usqInt freeChunk; sqInt i; @@ -67418,7 +67418,7 @@ sqInt limit; sqInt newEndOfMemory; sqInt next; - sqInt node; + usqInt node; usqInt numSlots; usqInt numSlots1; SpurSegmentInfo *seg; Modified: branches/Cog/nsspur64src/vm/cointerp.h =================================================================== --- branches/Cog/nsspur64src/vm/cointerp.h 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspur64src/vm/cointerp.h 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ Modified: branches/Cog/nsspur64src/vm/gcc3x-cointerp.c =================================================================== --- branches/Cog/nsspur64src/vm/gcc3x-cointerp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspur64src/vm/gcc3x-cointerp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -2,11 +2,11 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2439,7 +2439,7 @@ /*560*/ -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, 0, 0, 0,-1,-1 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1856"; sqInt minBackwardJumpCountForCompile = MinBackwardJumpCountForCompile /* 40 */; volatile int sendTrace; @@ -41198,7 +41198,7 @@ sqInt oopRcvr; sqInt oopResult; usqLong result; - sqInt resultIsNegative; + int resultIsNegative; char *sp; oopArg = longAt(GIV(stackPointer) + (0 * BytesPerWord)); @@ -43000,7 +43000,7 @@ sqInt fmt; usqInt instBytes; sqInt instFormat; - usqInt newFormat; + sqInt newFormat; sqInt normalizedInstFormat; usqInt numBytes; usqInt numSlots; @@ -47104,7 +47104,7 @@ sqInt effectsFlags1; sqInt errCode; sqInt fieldOffset; - sqInt fieldOffset1; + usqInt fieldOffset1; sqInt fmt; sqInt hash; sqInt header; @@ -61371,7 +61371,7 @@ usqInt prevFree; usqInt prevFreeChunk; usqInt prevPrevFree; - usqInt prevPrevFreeChunk; + sqInt prevPrevFreeChunk; sqInt slotBytes; sqInt slotBytes1; usqInt there; @@ -67183,7 +67183,7 @@ bridgeFromto(SpurSegmentInfo *aSegment, SpurSegmentInfo *nextSegmentOrNil) { usqInt bridgeSpan; - sqInt clifton; + usqInt clifton; usqInt segEnd; segEnd = ((aSegment->segSize)) + ((aSegment->segStart)); @@ -67364,7 +67364,7 @@ static void postSnapshot(void) { DECL_MAYBE_SQ_GLOBAL_STRUCT - sqInt address; + usqInt address; sqInt bytes; usqInt freeChunk; sqInt i; @@ -67427,7 +67427,7 @@ sqInt limit; sqInt newEndOfMemory; sqInt next; - sqInt node; + usqInt node; usqInt numSlots; usqInt numSlots1; SpurSegmentInfo *seg; Modified: branches/Cog/nsspursrc/vm/cogit.h =================================================================== --- branches/Cog/nsspursrc/vm/cogit.h 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspursrc/vm/cogit.h 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ Modified: branches/Cog/nsspursrc/vm/cogitARMv5.c =================================================================== --- branches/Cog/nsspursrc/vm/cogitARMv5.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspursrc/vm/cogitARMv5.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e " __DATE__ ; +static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__cogitBuildInfo = __buildInfo; @@ -96,7 +96,7 @@ #define DPFPReg2 2 #define EncounteredUnknownBytecode -6 #define EQ 0 -#define Extra0Reg 12 +#define Extra0Reg 9 #define Fill32 4 #define FirstAnnotation 64 #define FirstJump 11 @@ -262,7 +262,6 @@ #define PushCw 75 #define PushR 73 #define R0 0 -#define R12 12 #define ReceiverIndex 5 #define ReceiverResultReg 7 #define RetN 8 @@ -753,7 +752,6 @@ extern sqInt recordPrimTraceFunc(void); static void recordRunTimeObjectReferences(void); static sqInt NoDbgRegParms registerMaskFor(sqInt reg); -static sqInt NoDbgRegParms registerMaskForandandand(sqInt reg1, sqInt reg2, sqInt reg3, sqInt reg4); static void NoDbgRegParms relocateCallsAndSelfReferencesInMethod(CogMethod *cogMethod); static void NoDbgRegParms relocateCallsInClosedPIC(CogMethod *cPIC); static sqInt NoDbgRegParms relocateIfCallOrMethodReferencemcpcdelta(sqInt annotation, char *mcpc, sqInt refDelta); @@ -2795,7 +2793,7 @@ { sqInt aWord; sqInt i; - usqInt instr; + sqInt instr; unsigned char savedCond; assert(((self_in_concretizeConditionalInstruction->conditionOrNil)) != null); @@ -6101,46 +6099,24 @@ /* Restore the registers in regMask as saved by genSaveRegs:. Restore none, because the ARM ABI only defines callee saved registers, no - caller-saved regs. - But for the future... */ + caller-saved regs. */ /* CogARMCompiler>>#genRestoreRegs: */ static sqInt NoDbgRegParms genRestoreRegs(AbstractInstruction * self_in_genRestoreRegs, sqInt regMask) { - sqInt reg; - - assert(regMask == 0); - assert(!((regMask & (registerMaskForandandand(SP, FPReg, LR, PC))))); - for (reg = R0; reg <= R12; reg += 1) { - if (regMask & (1L << reg)) { - /* begin PopR: */ - genoperand(PopR, reg); - } - } return 0; } /* Save the registers in regMask for a call into the C run-time from a trampoline. Save none, because the ARM ABI only defines callee saved - registers, no caller-saved regs. - But for the future... */ + registers, no caller-saved regs. */ /* CogARMCompiler>>#genSaveRegs: */ static sqInt NoDbgRegParms genSaveRegs(AbstractInstruction * self_in_genSaveRegs, sqInt regMask) { - sqInt reg; - - assert(regMask == 0); - assert(!((regMask & (registerMaskForandandand(SP, FPReg, LR, PC))))); - for (reg = R12; reg >= R0; reg += -1) { - if (regMask & (1L << reg)) { - /* begin PushR: */ - genoperand(PushR, reg); - } - } return 0; } @@ -9953,9 +9929,9 @@ findMapLocationForMcpcinMethod(sqInt targetMcpc, CogMethod *cogMethod) { sqInt annotation; - sqInt map; + usqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; mcpc = (0 ? (((usqInt)cogMethod)) + cbNoSwitchEntryOffset @@ -10037,7 +10013,7 @@ followForwardedLiteralsIn(CogMethod *cogMethod) { sqInt annotation; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -11956,7 +11932,7 @@ mapForperformUntilarg(CogMethod *cogMethod, sqInt (*functionSymbol)(sqInt annotation, char *mcpc, sqInt arg), sqInt arg) { sqInt annotation; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -12061,7 +12037,7 @@ sqInt freedPIC; sqInt hasYoungObj; sqInt hasYoungObjPtr; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt remappedMethod; @@ -12177,7 +12153,7 @@ { sqInt annotation; CogMethod *cogMethod; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -12255,7 +12231,7 @@ CogMethod *cogMethod; sqInt hasYoungObj; sqInt hasYoungObjPtr; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; usqInt pointer; @@ -12373,8 +12349,8 @@ sqInt annotation; sqInt annotation1; CogMethod *cogMethod; - usqInt map; - usqInt map1; + sqInt map; + sqInt map1; sqInt mapByte; sqInt mapByte1; sqInt mcpc; @@ -12529,7 +12505,7 @@ markAndTraceOrFreeCogMethodfirstVisit(CogMethod *cogMethod, sqInt firstVisit) { sqInt annotation; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -12869,7 +12845,7 @@ { sqInt annotation; CogMethod *cogMethod; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -13601,20 +13577,13 @@ return 1L << reg; } - /* Cogit>>#registerMaskFor:and:and:and: */ -static sqInt NoDbgRegParms -registerMaskForandandand(sqInt reg1, sqInt reg2, sqInt reg3, sqInt reg4) -{ - return (((1L << reg1) | (1L << reg2)) | (1L << reg3)) | (1L << reg4); -} - /* Cogit>>#relocateCallsAndSelfReferencesInMethod: */ static void NoDbgRegParms relocateCallsAndSelfReferencesInMethod(CogMethod *cogMethod) { sqInt annotation; sqLong callDelta; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqLong refDelta; @@ -14168,7 +14137,7 @@ { sqInt annotation; CogMethod *cogMethod; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -14609,7 +14578,7 @@ sqInt annotation; CogMethod *cogMethod; sqInt freedPIC; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -14684,7 +14653,7 @@ { sqInt annotation; CogMethod *cogMethod; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt mustScanAndUnlink; @@ -14781,7 +14750,7 @@ { sqInt annotation; CogMethod *cogMethod; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -14848,7 +14817,7 @@ sqInt annotation; CogMethod *cogMethod; sqInt freedPIC; - usqInt map; + sqInt map; sqInt mapByte; sqInt mcpc; sqInt result; Modified: branches/Cog/nsspursrc/vm/cogitIA32.c =================================================================== --- branches/Cog/nsspursrc/vm/cogitIA32.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspursrc/vm/cogitIA32.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e " __DATE__ ; +static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__cogitBuildInfo = __buildInfo; @@ -652,7 +652,7 @@ static AbstractInstruction * NoDbgRegParms gMoveMwrR(sqInt offset, sqInt baseReg, sqInt destReg); static AbstractInstruction * NoDbgRegParms gMoveRMwr(sqInt sourceReg, sqInt offset, sqInt baseReg); static AbstractInstruction * NoDbgRegParms gMoveRR(sqInt reg1, sqInt reg2); -static usqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); +static sqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); static sqInt NoDbgRegParms mapForperformUntilarg(CogMethod *cogMethod, sqInt (*functionSymbol)(sqInt annotation, char *mcpc, sqInt arg), sqInt arg); static sqInt NoDbgRegParms mapObjectReferencesInClosedPIC(CogMethod *cPIC); static void mapObjectReferencesInGeneratedRuntime(void); @@ -6584,7 +6584,7 @@ blockDispatchTargetsForperformarg(CogMethod *cogMethod, usqInt (*binaryFunction)(sqInt mcpc, sqInt arg), sqInt arg) { sqInt blockEntry; - usqInt end; + sqInt end; sqInt pc; sqInt result; usqInt targetpc; @@ -6633,7 +6633,7 @@ sqInt isBackwardBranch; sqInt isInBlock; sqInt latestContinuation; - usqInt map; + sqInt map; sqInt mapByte; usqInt mcpc1; sqInt nExts; @@ -9011,7 +9011,7 @@ findMapLocationForMcpcinMethod(sqInt targetMcpc, CogMethod *cogMethod) { sqInt annotation; - usqInt map; + sqInt map; sqInt mapByte; usqInt mcpc; @@ -9097,7 +9097,7 @@ sqInt annotation; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; assert((((cogMethod->cmType)) != CMMethod) @@ -9669,12 +9669,12 @@ generateMapAtstart(sqInt addressOrNull, sqInt startAddress) { unsigned char annotation; - usqInt delta; + sqInt delta; sqInt i; AbstractInstruction *instruction; sqInt length; - usqInt location; - usqInt mapEntry; + sqInt location; + sqInt mapEntry; sqInt maxDelta; usqInt mcpc; @@ -10920,10 +10920,10 @@ /* Answer the address of the null byte at the end of the method map. */ /* Cogit>>#mapEndFor: */ -static usqInt NoDbgRegParms +static sqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod) { - usqInt end; + sqInt end; end = ((((usqInt)cogMethod)) + ((cogMethod->blockSize))) - 1; while ((byteAt(end)) != MapEnd) { @@ -10943,7 +10943,7 @@ sqInt annotation; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; mcpc = (0 @@ -11048,7 +11048,7 @@ sqInt hasYoungObjPtr; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt remappedMethod; sqInt result; sqInt val; @@ -11164,7 +11164,7 @@ CogMethod *cogMethod; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; codeModified = 0; @@ -11242,7 +11242,7 @@ sqInt hasYoungObjPtr; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; usqInt pointer; sqInt result; sqInt val; @@ -11362,8 +11362,8 @@ sqInt map1; sqInt mapByte; sqInt mapByte1; - sqInt mcpc; - sqInt mcpc1; + usqInt mcpc; + usqInt mcpc1; sqInt result; sqInt result1; sqInt val; @@ -11516,7 +11516,7 @@ sqInt annotation; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; sqInt val; @@ -11856,7 +11856,7 @@ CogMethod *cogMethod; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; assert((((aCogMethod->cmType)) == CMMethod) @@ -11985,7 +11985,7 @@ sqInt isBackwardBranch; sqInt isInBlock; sqInt latestContinuation; - usqInt map; + sqInt map; sqInt mapByte; usqInt mcpc; sqInt nExts; @@ -12428,7 +12428,7 @@ printPCMapPairsFor(CogMethod *cogMethod) { sqInt annotation; - usqInt map; + sqInt map; unsigned char mapByte; usqInt mcpc; sqInt value; @@ -12602,7 +12602,7 @@ sqLong callDelta; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqLong refDelta; sqInt result; @@ -13161,7 +13161,7 @@ CogMethod *cogMethod; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; if (!(methodZoneBase)) { @@ -13602,7 +13602,7 @@ sqInt freedPIC; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; if (!(methodZoneBase)) { @@ -13677,7 +13677,7 @@ CogMethod *cogMethod; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt mustScanAndUnlink; sqInt result; @@ -13774,7 +13774,7 @@ CogMethod *cogMethod; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; if (!(methodZoneBase)) { @@ -13841,7 +13841,7 @@ sqInt freedPIC; sqInt map; sqInt mapByte; - sqInt mcpc; + usqInt mcpc; sqInt result; CogMethod *targetMethod; @@ -22032,7 +22032,7 @@ sqInt isBackwardBranch; sqInt isInBlock; sqInt latestContinuation; - usqInt map; + sqInt map; sqInt mapByte; usqInt mcpc; sqInt nExts; Modified: branches/Cog/nsspursrc/vm/cogitMIPSEL.c =================================================================== --- branches/Cog/nsspursrc/vm/cogitMIPSEL.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspursrc/vm/cogitMIPSEL.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e " __DATE__ ; +static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__cogitBuildInfo = __buildInfo; @@ -646,7 +646,7 @@ static AbstractInstruction * NoDbgRegParms gMoveMwrR(sqInt offset, sqInt baseReg, sqInt destReg); static AbstractInstruction * NoDbgRegParms gMoveRMwr(sqInt sourceReg, sqInt offset, sqInt baseReg); static AbstractInstruction * NoDbgRegParms gMoveRR(sqInt reg1, sqInt reg2); -static sqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); +static usqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); static sqInt NoDbgRegParms mapForperformUntilarg(CogMethod *cogMethod, sqInt (*functionSymbol)(sqInt annotation, char *mcpc, sqInt arg), sqInt arg); static sqInt NoDbgRegParms mapObjectReferencesInClosedPIC(CogMethod *cPIC); static void mapObjectReferencesInGeneratedRuntime(void); @@ -2643,7 +2643,7 @@ blockDispatchTargetsForperformarg(CogMethod *cogMethod, usqInt (*binaryFunction)(sqInt mcpc, sqInt arg), sqInt arg) { sqInt blockEntry; - sqInt end; + usqInt end; sqInt pc; sqInt result; usqInt targetpc; @@ -2687,12 +2687,12 @@ sqInt byte; BytecodeDescriptor *descriptor; sqInt distance; - sqInt endbcpc; + usqInt endbcpc; CogMethod *homeMethod; sqInt isBackwardBranch; sqInt isInBlock; sqInt latestContinuation; - sqInt map; + usqInt map; sqInt mapByte; usqInt mcpc1; sqInt nExts; @@ -4711,7 +4711,7 @@ static sqInt NoDbgRegParms cPICHasFreedTargets(CogMethod *cPIC) { - sqInt entryPoint; + usqInt entryPoint; sqInt i; sqInt pc; CogMethod *targetMethod; @@ -5096,9 +5096,9 @@ findMapLocationForMcpcinMethod(sqInt targetMcpc, CogMethod *cogMethod) { sqInt annotation; - sqInt map; + usqInt map; sqInt mapByte; - usqInt mcpc; + sqInt mcpc; mcpc = (0 ? (((usqInt)cogMethod)) + cbNoSwitchEntryOffset @@ -5180,7 +5180,7 @@ followForwardedLiteralsIn(CogMethod *cogMethod) { sqInt annotation; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -6990,10 +6990,10 @@ /* Answer the address of the null byte at the end of the method map. */ /* Cogit>>#mapEndFor: */ -static sqInt NoDbgRegParms +static usqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod) { - sqInt end; + usqInt end; end = ((((usqInt)cogMethod)) + ((cogMethod->blockSize))) - 1; while ((byteAt(end)) != MapEnd) { @@ -7011,7 +7011,7 @@ mapForperformUntilarg(CogMethod *cogMethod, sqInt (*functionSymbol)(sqInt annotation, char *mcpc, sqInt arg), sqInt arg) { sqInt annotation; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -7115,7 +7115,7 @@ sqInt freedPIC; sqInt hasYoungObj; sqInt hasYoungObjPtr; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt remappedMethod; @@ -7231,7 +7231,7 @@ { sqInt annotation; CogMethod *cogMethod; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -7309,7 +7309,7 @@ CogMethod *cogMethod; sqInt hasYoungObj; sqInt hasYoungObjPtr; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; usqInt pointer; @@ -7427,8 +7427,8 @@ sqInt annotation; sqInt annotation1; CogMethod *cogMethod; - sqInt map; - sqInt map1; + usqInt map; + usqInt map1; sqInt mapByte; sqInt mapByte1; sqInt mcpc; @@ -7583,7 +7583,7 @@ markAndTraceOrFreeCogMethodfirstVisit(CogMethod *cogMethod, sqInt firstVisit) { sqInt annotation; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -7923,7 +7923,7 @@ { sqInt annotation; CogMethod *cogMethod; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -8049,12 +8049,12 @@ sqInt byte; BytecodeDescriptor *descriptor; sqInt distance; - sqInt endbcpc; + usqInt endbcpc; CogMethod *homeMethod; sqInt isBackwardBranch; sqInt isInBlock; sqInt latestContinuation; - sqInt map; + usqInt map; sqInt mapByte; usqInt mcpc; sqInt nExts; @@ -8497,9 +8497,9 @@ printPCMapPairsFor(CogMethod *cogMethod) { sqInt annotation; - sqInt map; + usqInt map; unsigned char mapByte; - sqInt mcpc; + usqInt mcpc; sqInt value; mcpc = (0 @@ -8669,7 +8669,7 @@ { sqInt annotation; sqLong callDelta; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqLong refDelta; @@ -9229,7 +9229,7 @@ { sqInt annotation; CogMethod *cogMethod; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -9670,7 +9670,7 @@ sqInt annotation; CogMethod *cogMethod; sqInt freedPIC; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -9745,7 +9745,7 @@ { sqInt annotation; CogMethod *cogMethod; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt mustScanAndUnlink; @@ -9842,7 +9842,7 @@ { sqInt annotation; CogMethod *cogMethod; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -9909,7 +9909,7 @@ sqInt annotation; CogMethod *cogMethod; sqInt freedPIC; - sqInt map; + usqInt map; sqInt mapByte; sqInt mcpc; sqInt result; @@ -14758,7 +14758,7 @@ static AbstractInstruction * NoDbgRegParms relocateMethodReferenceBeforeAddressby(AbstractInstruction * self_in_relocateMethodReferenceBeforeAddressby, sqInt pc, sqInt delta) { - usqInt newValue; + sqInt newValue; usqInt oldValue; if (((opcodeAtAddress(self_in_relocateMethodReferenceBeforeAddressby, pc - 8)) == ADDIU) @@ -22249,13 +22249,13 @@ CogBlockMethod *cogMethod1; BytecodeDescriptor *descriptor; sqInt distance; - sqInt endbcpc; + usqInt endbcpc; sqInt errCode; CogMethod *homeMethod; sqInt isBackwardBranch; sqInt isInBlock; sqInt latestContinuation; - sqInt map; + usqInt map; sqInt mapByte; usqInt mcpc; sqInt nExts; Modified: branches/Cog/nsspursrc/vm/cointerp.c =================================================================== --- branches/Cog/nsspursrc/vm/cointerp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspursrc/vm/cointerp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2412,7 +2412,7 @@ /*560*/ -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, 0, 0, 0,-1,-1 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1856"; sqInt minBackwardJumpCountForCompile = MinBackwardJumpCountForCompile /* 40 */; volatile int sendTrace; @@ -28503,7 +28503,7 @@ sqInt ccIndex1; sqInt fmt; sqInt ok; - sqInt smallIntValue; + int smallIntValue; sqInt sz; usqLong value; @@ -40373,7 +40373,7 @@ sqInt oopRcvr; sqInt oopResult; usqLong result; - sqInt resultIsNegative; + int resultIsNegative; char *sp; oopArg = longAt(GIV(stackPointer) + (0 * BytesPerWord)); @@ -60296,7 +60296,7 @@ usqInt prevFree; usqInt prevFreeChunk; usqInt prevPrevFree; - usqInt prevPrevFreeChunk; + sqInt prevPrevFreeChunk; sqInt slotBytes; sqInt slotBytes1; usqInt there; @@ -66092,7 +66092,7 @@ bridgeFromto(SpurSegmentInfo *aSegment, SpurSegmentInfo *nextSegmentOrNil) { usqInt bridgeSpan; - usqInt clifton; + sqInt clifton; usqInt segEnd; segEnd = ((aSegment->segSize)) + ((aSegment->segStart)); @@ -66273,7 +66273,7 @@ static void postSnapshot(void) { DECL_MAYBE_SQ_GLOBAL_STRUCT - usqInt address; + sqInt address; sqInt bytes; usqInt freeChunk; sqInt i; @@ -66679,8 +66679,8 @@ { usqLong firstSavedBridgeWord; sqInt nWritten; - usqInt pier1; - usqInt pier2; + sqInt pier1; + sqInt pier2; usqLong secondSavedBridgeWord; pier1 = (((segment->segSize)) + ((segment->segStart))) - (2 * BaseHeaderSize); Modified: branches/Cog/nsspursrc/vm/cointerp.h =================================================================== --- branches/Cog/nsspursrc/vm/cointerp.h 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspursrc/vm/cointerp.h 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ Modified: branches/Cog/nsspursrc/vm/gcc3x-cointerp.c =================================================================== --- branches/Cog/nsspursrc/vm/gcc3x-cointerp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspursrc/vm/gcc3x-cointerp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -2,11 +2,11 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2415,7 +2415,7 @@ /*560*/ -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, 0, 0, 0,-1,-1 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine CoInterpreterPrimitives_VMMaker.oscog-eem.1856"; sqInt minBackwardJumpCountForCompile = MinBackwardJumpCountForCompile /* 40 */; volatile int sendTrace; @@ -28512,7 +28512,7 @@ sqInt ccIndex1; sqInt fmt; sqInt ok; - sqInt smallIntValue; + int smallIntValue; sqInt sz; usqLong value; @@ -40382,7 +40382,7 @@ sqInt oopRcvr; sqInt oopResult; usqLong result; - sqInt resultIsNegative; + int resultIsNegative; char *sp; oopArg = longAt(GIV(stackPointer) + (0 * BytesPerWord)); @@ -60305,7 +60305,7 @@ usqInt prevFree; usqInt prevFreeChunk; usqInt prevPrevFree; - usqInt prevPrevFreeChunk; + sqInt prevPrevFreeChunk; sqInt slotBytes; sqInt slotBytes1; usqInt there; @@ -66101,7 +66101,7 @@ bridgeFromto(SpurSegmentInfo *aSegment, SpurSegmentInfo *nextSegmentOrNil) { usqInt bridgeSpan; - usqInt clifton; + sqInt clifton; usqInt segEnd; segEnd = ((aSegment->segSize)) + ((aSegment->segStart)); @@ -66282,7 +66282,7 @@ static void postSnapshot(void) { DECL_MAYBE_SQ_GLOBAL_STRUCT - usqInt address; + sqInt address; sqInt bytes; usqInt freeChunk; sqInt i; @@ -66688,8 +66688,8 @@ { usqLong firstSavedBridgeWord; sqInt nWritten; - usqInt pier1; - usqInt pier2; + sqInt pier1; + sqInt pier2; usqLong secondSavedBridgeWord; pier1 = (((segment->segSize)) + ((segment->segStart))) - (2 * BaseHeaderSize); Modified: branches/Cog/nsspurstack64src/vm/gcc3x-interp.c =================================================================== --- branches/Cog/nsspurstack64src/vm/gcc3x-interp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspurstack64src/vm/gcc3x-interp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -2,11 +2,11 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2178,7 +2178,7 @@ /* 575 */ (void (*)(void))0, 0 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1856"; volatile int sendTrace; sqInt suppressHeartbeatFlag; Modified: branches/Cog/nsspurstack64src/vm/interp.c =================================================================== --- branches/Cog/nsspurstack64src/vm/interp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspurstack64src/vm/interp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2175,7 +2175,7 @@ /* 575 */ (void (*)(void))0, 0 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1856"; volatile int sendTrace; sqInt suppressHeartbeatFlag; Modified: branches/Cog/nsspurstacksrc/vm/gcc3x-interp.c =================================================================== --- branches/Cog/nsspurstacksrc/vm/gcc3x-interp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspurstacksrc/vm/gcc3x-interp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -2,11 +2,11 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2155,7 +2155,7 @@ /* 575 */ (void (*)(void))0, 0 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1856"; volatile int sendTrace; sqInt suppressHeartbeatFlag; Modified: branches/Cog/nsspurstacksrc/vm/interp.c =================================================================== --- branches/Cog/nsspurstacksrc/vm/interp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/nsspurstacksrc/vm/interp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "StackInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2152,7 +2152,7 @@ /* 575 */ (void (*)(void))0, 0 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1855"; +const char *interpreterVersion = "Newspeak Virtual Machine StackInterpreterPrimitives_VMMaker.oscog-eem.1856"; volatile int sendTrace; sqInt suppressHeartbeatFlag; Property changes on: branches/Cog/platforms/Cross/vm/sqSCCSVersion.h ___________________________________________________________________ Modified: checkindate - Sun May 1 22:11:41 PDT 2016 + Mon May 9 19:17:20 PDT 2016 Modified: branches/Cog/spur64src/vm/cogit.h =================================================================== --- branches/Cog/spur64src/vm/cogit.h 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/spur64src/vm/cogit.h 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ Modified: branches/Cog/spur64src/vm/cogitX64.c =================================================================== --- branches/Cog/spur64src/vm/cogitX64.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/spur64src/vm/cogitX64.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e " __DATE__ ; +static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__cogitBuildInfo = __buildInfo; @@ -584,7 +584,7 @@ static AbstractInstruction * NoDbgRegParms gMoveCwR(sqInt wordConstant, sqInt reg); static AbstractInstruction * NoDbgRegParms gMoveRMwr(sqInt sourceReg, sqInt offset, sqInt baseReg); static AbstractInstruction * NoDbgRegParms gMoveRR(sqInt reg1, sqInt reg2); -static sqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); +static usqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); static sqInt NoDbgRegParms mapForperformUntilarg(CogMethod *cogMethod, sqInt (*functionSymbol)(sqInt annotation, char *mcpc, sqInt arg), sqInt arg); static sqInt NoDbgRegParms mapObjectReferencesInClosedPIC(CogMethod *cPIC); static void mapObjectReferencesInGeneratedRuntime(void); @@ -2430,7 +2430,7 @@ blockDispatchTargetsForperformarg(CogMethod *cogMethod, usqInt (*binaryFunction)(sqInt mcpc, sqInt arg), sqInt arg) { sqInt blockEntry; - sqInt end; + usqInt end; sqInt pc; sqInt result; usqInt targetpc; @@ -2474,7 +2474,7 @@ sqInt byte; BytecodeDescriptor *descriptor; sqInt distance; - usqInt endbcpc; + sqInt endbcpc; CogMethod *homeMethod; sqInt isBackwardBranch; sqInt isInBlock; @@ -3255,7 +3255,7 @@ closedPICRefersToUnmarkedObject(CogMethod *cPIC) { sqInt i; - sqInt object; + usqInt object; sqInt pc; if (!((isImmediate((cPIC->selector))) @@ -4781,7 +4781,7 @@ sqInt annotation; usqInt map; sqInt mapByte; - usqInt mcpc; + sqInt mcpc; mcpc = (0 ? (((usqInt)cogMethod)) + cbNoSwitchEntryOffset @@ -6512,10 +6512,10 @@ /* Answer the address of the null byte at the end of the method map. */ /* Cogit>>#mapEndFor: */ -static sqInt NoDbgRegParms +static usqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod) { - sqInt end; + usqInt end; end = ((((usqInt)cogMethod)) + ((cogMethod->blockSize))) - 1; while ((byteAt(end)) != MapEnd) { @@ -7459,7 +7459,7 @@ sqInt byte; BytecodeDescriptor *descriptor; sqInt distance; - usqInt endbcpc; + sqInt endbcpc; CogMethod *homeMethod; sqInt isBackwardBranch; sqInt isInBlock; @@ -7907,9 +7907,9 @@ printPCMapPairsFor(CogMethod *cogMethod) { sqInt annotation; - sqInt map; + usqInt map; unsigned char mapByte; - usqInt mcpc; + sqInt mcpc; sqInt value; mcpc = (0 @@ -21003,7 +21003,7 @@ CogBlockMethod *cogMethod1; BytecodeDescriptor *descriptor; sqInt distance; - usqInt endbcpc; + sqInt endbcpc; sqInt errCode; CogMethod *homeMethod; sqInt isBackwardBranch; Modified: branches/Cog/spur64src/vm/cointerp.c =================================================================== --- branches/Cog/spur64src/vm/cointerp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/spur64src/vm/cointerp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2399,7 +2399,7 @@ /*560*/ -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, 0, 0, 0,-1,-1 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Croquet Closure Cog[Spur] VM [CoInterpreterPrimitives VMMaker.oscog-eem.1855]"; +const char *interpreterVersion = "Croquet Closure Cog[Spur] VM [CoInterpreterPrimitives VMMaker.oscog-eem.1856]"; sqInt minBackwardJumpCountForCompile = MinBackwardJumpCountForCompile /* 40 */; volatile int sendTrace; @@ -35179,7 +35179,7 @@ sqInt oopRcvr; sqInt oopResult; usqLong result; - sqInt resultIsNegative; + int resultIsNegative; char *sp; oopArg = longAt(GIV(stackPointer) + (0 * BytesPerWord)); @@ -36981,7 +36981,7 @@ sqInt fmt; usqInt instBytes; sqInt instFormat; - usqInt newFormat; + sqInt newFormat; sqInt normalizedInstFormat; usqInt numBytes; usqInt numSlots; @@ -55352,7 +55352,7 @@ usqInt prevFree; usqInt prevFreeChunk; usqInt prevPrevFree; - sqInt prevPrevFreeChunk; + usqInt prevPrevFreeChunk; sqInt slotBytes; sqInt slotBytes1; usqInt there; Modified: branches/Cog/spur64src/vm/cointerp.h =================================================================== --- branches/Cog/spur64src/vm/cointerp.h 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/spur64src/vm/cointerp.h 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ Modified: branches/Cog/spur64src/vm/gcc3x-cointerp.c =================================================================== --- branches/Cog/spur64src/vm/gcc3x-cointerp.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/spur64src/vm/gcc3x-cointerp.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -2,11 +2,11 @@ /* Automatically generated by - CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGeneratorGlobalStructure VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 " __DATE__ ; +static char __buildInfo[] = "CoInterpreter VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__interpBuildInfo = __buildInfo; @@ -2402,7 +2402,7 @@ /*560*/ -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, 0, 0, 0,-1,-1 }; char expensiveAsserts = 0; -const char *interpreterVersion = "Croquet Closure Cog[Spur] VM [CoInterpreterPrimitives VMMaker.oscog-eem.1855]"; +const char *interpreterVersion = "Croquet Closure Cog[Spur] VM [CoInterpreterPrimitives VMMaker.oscog-eem.1856]"; sqInt minBackwardJumpCountForCompile = MinBackwardJumpCountForCompile /* 40 */; volatile int sendTrace; @@ -35188,7 +35188,7 @@ sqInt oopRcvr; sqInt oopResult; usqLong result; - sqInt resultIsNegative; + int resultIsNegative; char *sp; oopArg = longAt(GIV(stackPointer) + (0 * BytesPerWord)); @@ -36990,7 +36990,7 @@ sqInt fmt; usqInt instBytes; sqInt instFormat; - usqInt newFormat; + sqInt newFormat; sqInt normalizedInstFormat; usqInt numBytes; usqInt numSlots; @@ -55361,7 +55361,7 @@ usqInt prevFree; usqInt prevFreeChunk; usqInt prevPrevFree; - sqInt prevPrevFreeChunk; + usqInt prevPrevFreeChunk; sqInt slotBytes; sqInt slotBytes1; usqInt there; Modified: branches/Cog/spursistasrc/vm/cogit.h =================================================================== --- branches/Cog/spursistasrc/vm/cogit.h 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/spursistasrc/vm/cogit.h 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,5 +1,5 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-eem.1855 uuid: d8e4a3c2-a3bf-4adc-b224-8012903a1ef4 + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ Modified: branches/Cog/spursistasrc/vm/cogitARMv5.c =================================================================== --- branches/Cog/spursistasrc/vm/cogitARMv5.c 2016-05-07 02:54:05 UTC (rev 3706) +++ branches/Cog/spursistasrc/vm/cogitARMv5.c 2016-05-10 02:18:53 UTC (rev 3707) @@ -1,9 +1,9 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + CCodeGenerator VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 from - SistaCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e + SistaCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 */ -static char __buildInfo[] = "SistaCogit VMMaker.oscog-nice.1853 uuid: 3ff63b2d-9dc9-4d6a-b3ff-fb6d37f1085e " __DATE__ ; +static char __buildInfo[] = "SistaCogit VMMaker.oscog-eem.1856 uuid: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 " __DATE__ ; char *__cogitBuildInfo = __buildInfo; @@ -97,7 +97,7 @@ #define DPFPReg2 2 #define EncounteredUnknownBytecode -6 #define EQ 0 -#define Extra0Reg 12 +#define Extra0Reg 9 #define Fill32 4 #define FirstAnnotation 64 #define FirstJump 11 @@ -260,7 +260,6 @@ #define PushCw 75 #define PushR 73 #define R0 0 -#define R12 12 #define ReceiverIndex 5 #define ReceiverResultReg 7 #define RetN 8 @@ -699,7 +698,7 @@ static AbstractInstruction * NoDbgRegParms gMoveMwrR(sqInt offset, sqInt baseReg, sqInt destReg); static AbstractInstruction * NoDbgRegParms gMoveRMwr(sqInt sourceReg, sqInt offset, sqInt baseReg); static AbstractInstruction * NoDbgRegParms gMoveRR(sqInt reg1, sqInt reg2); -static sqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); +static usqInt NoDbgRegParms mapEndFor(CogMethod *cogMethod); static sqInt NoDbgRegParms mapForperformUntilarg(CogMethod *cogMethod, sqInt (*functionSymbol)(sqInt annotation, char *mcpc, sqInt arg), sqInt arg); static sqInt NoDbgRegParms mapObjectReferencesInClosedPIC(CogMethod *cPIC); static void mapObjectReferencesInGeneratedRuntime(void); @@ -746,7 +745,6 @@ extern sqInt recordPrimTraceFunc(void); static void recordRunTimeObjectReferences(void); static sqInt NoDbgRegParms registerMaskFor(sqInt reg); -static sqInt NoDbgRegParms registerMaskForandandand(sqInt reg1, sqInt reg2, sqInt reg3, sqInt reg4); static void NoDbgRegParms relocateCallsAndSelfReferencesInMethod(CogMethod *cogMethod); @@ Diff output truncated at 50000 characters. @@

1 0

VM Maker: VMMaker.oscog-eem.1856.mcz
by commits＠source.squeak.org 10 May '16

10 May '16

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1856.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1856 Author: eem Time: 9 May 2016, 7:06:23.09895 pm UUID: ddc1d13f-a8de-4cb1-af85-65ca64ffbe34 Ancestors: VMMaker.oscog-eem.1855 Fix two regressions introduced into the ARM cogit in the register allocation changes made recently. a) getSave/RestoreRegs: should do nothing on ARM, and b) Extra0Reg must be distinct from the other registers (!!). Fix a speeling rorre. Simulation: Fix printing of the register map (a regression from the abstract register putsch of last year). Fix parsing invalid address traces in reporting the last N instructions. Improve printing of ClassBindings in disassembly. In 1856: Gregor Mendel starts his research on genetics. Kate Warne, the first female private detective, begins to work for the Pinkerton Detective Agency. Pre-human remains are found in the Neandertal valley in Germany. =============== Diff against VMMaker.oscog-eem.1855 =============== Item was changed: ----- Method: CogARMCompiler class>>initializeAbstractRegisters (in category 'class initialization') ----- initializeAbstractRegisters "Assign the abstract registers with the identities/indices of the relevant concrete registers." "N.B. According to BSABI, R0-R3 are caller-save, R4-R12 are callee save. Note that R9 might be a special register for the implementation. In some slides it is refered to as sb. R10 can contain the stack limit (sl), R11 the fp. R12 is an intra-procedure scratch instruction pointer for link purposes. It can also be used. R10 is used as temporary inside a single abstract opcode implementation" "R0-R3 are used when calling back to the interpreter. Using them would require saving and restoring their values, so they are omitted so far. R12 is the only scratch register at the moment.." super initializeAbstractRegisters. TempReg := R0. ClassReg := R8. ReceiverResultReg := R7. SendNumArgsReg := R6. + SPReg := SP. "a.k.a. R13" self assert: SP = 13. - SPReg := SP. "R13" FPReg := R11. Arg0Reg := R4. Arg1Reg := R5. + Extra0Reg := R9. + VarBaseReg := R10. "Must be callee saved" self assert: ConcreteVarBaseReg = R10. + RISCTempReg := R12. "a.k.a. IP" self assert: ConcreteIPReg = R12. - VarBaseReg := ConcreteVarBaseReg. "Must be callee saved" - RISCTempReg := ConcreteIPReg. "a.k.a. IP" - Extra0Reg := R12. LinkReg := LR. "R14" PCReg := PC. "R15" DPFPReg0 := D0. DPFPReg1 := D1. DPFPReg2 := D2. DPFPReg3 := D3. DPFPReg4 := D4. DPFPReg5 := D5. DPFPReg6 := D6. DPFPReg7 := D7 ! Item was changed: ----- Method: CogARMCompiler>>genRestoreRegs: (in category 'abi') ----- genRestoreRegs: regMask "Restore the registers in regMask as saved by genSaveRegs:. + Restore none, because the ARM ABI only defines callee saved registers, no caller-saved regs." - Restore none, because the ARM ABI only defines callee saved registers, no caller-saved regs. - But for the future..." - self assert: regMask = 0. - self deny: (regMask anyMask: (cogit registerMaskFor: SP and: FPReg and: LR and: PC)). - R0 to: R12 do: - [:reg| - (regMask anyMask: (cogit registerMaskFor: reg)) ifTrue: - [cogit PopR: reg]]. ^0! Item was changed: ----- Method: CogARMCompiler>>genSaveRegs: (in category 'abi') ----- genSaveRegs: regMask "Save the registers in regMask for a call into the C run-time from a trampoline. + Save none, because the ARM ABI only defines callee saved registers, no caller-saved regs." - Save none, because the ARM ABI only defines callee saved registers, no caller-saved regs. - But for the future..." - self assert: regMask = 0. - self deny: (regMask anyMask: (cogit registerMaskFor: SP and: FPReg and: LR and: PC)). - R12 to: R0 by: -1 do: - [:reg| - (regMask anyMask: (cogit registerMaskFor: reg)) ifTrue: - [cogit PushR: reg]]. ^0! Item was changed: ----- Method: CogX64Compiler>>genMarshallNArgs:arg:arg:arg:arg: (in category 'abi') ----- genMarshallNArgs: numArgs arg: regOrConst0 arg: regOrConst1 arg: regOrConst2 arg: regOrConst3 "Generate the code to pass up to four arguments in a C run-time call. Hack: each argument is either a negative number, which encodes a constant, or a non-negative number, that of a register. Run-time calls have no more than four arguments, so chosen so that on ARM, where in its C ABI the first four integer arguments are passed in registers, all arguments can be passed in registers. We defer to the back end to generate this code not so much that the back end knows whether it uses the stack or registers to pass arguments (it does, but...). In fact we defer for an extremely evil reason. Doing so allows the x64 (where up to 6 args are passed) to assign the register arguments in an order that allows some of the argument registers to be used for specific abstract registers, specifically ReceiverResultReg and ClassReg. This is evil, evil, evil, but also it's really nice to keep using the old register assignments the original author has grown accustomed to. How can this possibly work? Look at Cogit class>>runtime for a list of the run-time calls and their arguments, including which arguments are passed in which registers. Look at CogX64Compiler's + subclass implementations of initializeAbstractRegisters. There are no calls in which ReceiverResultReg - subclass implementations of initializeAbstractregisters. There are no calls in which ReceiverResultReg (RDX) and/or ClassReg (RCX) are passed along with Arg0Reg and Arg1Reg, and none in which the use of either ReceiverResultReg or ClassReg conflict for args 3 & 4. So if args are assigned in order, the + registers do not get overwritten. Yes, this is evil, but it's so nice to continue to use RCX & RDX. + + Argument registers for args 0 to 3 in SysV are RDI RSI RDX RCX, and in Win64 are RDI RSI R8 R9" - registers do not get overwritten. Yes, this is evil, but it's so nice to continue to use RCX & RDX." <inline: true> numArgs = 0 ifTrue: [^self]. (cogit isTrampolineArgConstant: regOrConst0) ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst0) R: RDI] ifFalse: [regOrConst0 ~= RDI ifTrue: [cogit MoveR: regOrConst0 R: RDI]]. numArgs = 1 ifTrue: [^self]. (cogit isTrampolineArgConstant: regOrConst1) ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst1) R: RSI] ifFalse: [regOrConst1 ~= RSI ifTrue: [cogit MoveR: regOrConst1 R: RSI]]. numArgs = 2 ifTrue: [^self]. self cppIf: ABI == #SysV ifTrue: [(cogit isTrampolineArgConstant: regOrConst2) ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst2) R: RDX] ifFalse: [regOrConst2 ~= RDX ifTrue: [cogit MoveR: regOrConst2 R: RDX]]. numArgs = 3 ifTrue: [^self]. (cogit isTrampolineArgConstant: regOrConst3) ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst3) R: RCX] ifFalse: [regOrConst3 ~= RCX ifTrue: [cogit MoveR: regOrConst3 R: RCX]]]. self cppIf: ABI == #MSVC ifTrue: [(cogit isTrampolineArgConstant: regOrConst2) ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst2) R: R8] ifFalse: [regOrConst2 ~= R8 ifTrue: [cogit MoveR: regOrConst2 R: R8]]. numArgs = 3 ifTrue: [^self]. (cogit isTrampolineArgConstant: regOrConst3) ifTrue: [cogit MoveCq: (cogit trampolineArgValue: regOrConst3) R: R9] ifFalse: [regOrConst3 ~= R9 ifTrue: [cogit MoveR: regOrConst3 R: R9]]]. self assert: numArgs <= 4! Item was changed: ----- Method: Cogit>>printRegisterMapOn: (in category 'disassembly') ----- printRegisterMapOn: aStream <doNotGenerate> | map n | map := backEnd generalPurposeRegisterMap. n := 0. map keys sort do: [:regName| | abstractName | + abstractName := CogAbstractRegisters nameForRegister: (map at: regName). - abstractName := CogRTLOpcodes nameForRegister: (map at: regName). aStream nextPutAll: abstractName; nextPutAll: ' => '; nextPutAll: regName] separatedBy: [(n := n + 1) \\ 4 = 0 ifTrue: [aStream cr] ifFalse: [aStream tab]]. aStream cr; flush! Item was changed: ----- Method: Cogit>>reportLastNInstructions (in category 'debugging') ----- reportLastNInstructions <doNotGenerate> | skipNext printInst | skipNext := false. printInst := [:inst| coInterpreter transcript nextPutAll: (EagerInstructionDecoration ifTrue: [inst] ifFalse: [processor decorateDisassembly: inst for: self + fromAddress: ((inst at: 3) = $r + ifTrue: [Integer readFrom: inst readStream] + ifFalse: [Integer readFrom: inst readStream base: 16])]); cr]. - fromAddress: (Integer readFrom: inst readStream base: 16)]); cr]. lastNInstructions withIndexDo: [:thing :idx| | next pc label | skipNext ifTrue: [skipNext := false] ifFalse: [thing isArray ifTrue: [thing first isString "i.e. { '(simulated return to '. processor retpcIn: coInterpreter memory. ')'}" ifTrue: [thing do: [:stringOrNumber| coInterpreter transcript nextPutAll: (stringOrNumber isString ifTrue: [stringOrNumber] ifFalse: [stringOrNumber hex])]. coInterpreter transcript cr] ifFalse: "if possible, add the label to the instruction line to condense the output" [coInterpreter transcript cr. pc := thing at: processor registerStatePCIndex. label := self relativeLabelForPC: pc. ((next := lastNInstructions at: idx + 1 ifAbsent: []) notNil and: [next isString and: [(Integer readFrom: next readStream radix: 16) = pc]]) ifTrue: "Decorate instruction and eliminate pc line" [skipNext := true. processor printRegisterStateExceptPC: thing on: coInterpreter transcript. label ifNotNil: [coInterpreter transcript nextPutAll: label; space]. printInst value: next] ifFalse: [label ifNotNil: [coInterpreter transcript nextPutAll: label; nextPut: $:; cr]. processor printRegisterState: thing on: coInterpreter transcript]]] ifFalse: [printInst value: thing]]]. coInterpreter transcript flush! Item was changed: ----- Method: SpurMemoryManager>>lookupAddress: (in category 'simulation only') ----- lookupAddress: address "If address appears to be that of a Symbol or a few well-known objects (such as classes) answer it, otherwise answer nil. For code disassembly" <doNotGenerate> | fmt size string class classSize maybeThisClass classNameIndex thisClassIndex | ((self addressCouldBeObj: address) and: [(thisClassIndex := self classIndexOf: address) > 0]) ifFalse: [^address = scavengeThreshold ifTrue: ['scavengeThreshold']]. address - self baseHeaderSize = hiddenRootsObj ifTrue: [^'(hiddenRootsObj+baseHeaderSize)']. fmt := self formatOf: address. size := self lengthOf: address baseHeader: (self baseHeader: address) format: fmt. size = 0 ifTrue: [^address caseOf: { [nilObj] -> ['nil']. [trueObj] -> ['true']. [falseObj] -> ['false'] } otherwise: []]. ((fmt between: self firstByteFormat and: self firstCompiledMethodFormat - 1) "indexable byte fields" and: [(size between: 1 and: 64) and: [(Scanner isLiteralSymbol: (string := (0 to: size - 1) collect: [:i| Character value: (self fetchByte: i ofObject: address)])) or: [NewspeakVM and: [string noneSatisfy: [:c| c isSeparator or: [c asInteger > 126]]]]]]) ifTrue: [^'#', (ByteString withAll: string)]. class := self noCheckClassAtIndex: thisClassIndex. (class isNil or: [class = nilObj]) ifTrue: [^nil]. "address is either a class or a metaclass, or an instance of a class or invalid. determine which." classNameIndex := coInterpreter classNameIndex. thisClassIndex := coInterpreter thisClassIndex. ((classSize := self numSlotsOf: class) <= (classNameIndex max: thisClassIndex) or: [classSize > 255]) ifTrue: [^nil]. "Address could be a class or a metaclass" (fmt = 1 and: [size > classNameIndex]) ifTrue: ["Is address a class? If so class's thisClass is address." (self lookupAddress: (self fetchPointer: classNameIndex ofObject: address)) ifNotNil: [:maybeClassName| (self fetchPointer: thisClassIndex ofObject: class) = address ifTrue: [^maybeClassName allButFirst]]. "Is address a Metaclass? If so class's name is Metaclass and address's thisClass holds the class name" ((self isBytes: (self fetchPointer: classNameIndex ofObject: class)) and: [(self lookupAddress: (self fetchPointer: classNameIndex ofObject: class)) = '#Metaclass' and: [size >= thisClassIndex]]) ifTrue: [maybeThisClass := self fetchPointer: thisClassIndex ofObject: address. (self lookupAddress: (self fetchPointer: classNameIndex ofObject: maybeThisClass)) ifNotNil: [:maybeThisClassName| ^maybeThisClassName allButFirst, ' class']]]. ^(self lookupAddress: (self fetchPointer: classNameIndex ofObject: class)) ifNotNil: + [:maybeClassName| + (size = 2 + and: [fmt = self nonIndexablePointerFormat + and: ['#ClassBinding' = maybeClassName]]) ifTrue: + [^'a ClassBinding ' + , ((self lookupAddress: (self fetchPointer: KeyIndex ofObject: address)) ifNil: ['']) + , ((self lookupAddress: (self fetchPointer: ValueIndex ofObject: address)) ifNil: [''] ifNotNil: [:val| ' -> ', val])]. + 'a(n) ', maybeClassName allButFirst]! - [:maybeClassName| 'a(n) ', maybeClassName allButFirst]!

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Re: Borked unix displaying in vm3692 (wasRe: [squeak-dev] International text input on X11)
by Eliot Miranda 09 May '16

09 May '16

Hi Tim, Hi Yoshiki, we made some changes to register allocation in recent weeks and we've broken register saving from machine-code to run-time callouts on ARM. It shows up in the simulator and I'm looking at it now. I suspect VMMaker.oscog-eem.1756. Anyway, apologies, and I'm trying to fix it now. The symptom is that the first assert in the following fails when generating the run-time trampoline calls at start-up: CogARMCompiler>>genSaveRegs: regMask "Save the registers in regMask for a call into the C run-time from a trampoline. Save none, because the ARM ABI only defines callee saved registers, no caller-saved regs. But for the future..." self assert: regMask = 0. self deny: (regMask anyMask: (cogit registerMaskFor: SP and: FPReg and: LR and: PC)). R12 to: R0 by: -1 do: [:reg| (regMask anyMask: (cogit registerMaskFor: reg)) ifTrue: [cogit PushR: reg]]. ^0 I should have it fixed quickly. On Mon, May 9, 2016 at 11:53 AM, tim Rowledge <tim(a)rowledge.org> wrote: > > > On 09-05-2016, at 11:24 AM, tim Rowledge <tim(a)rowledge.org> wrote: > > > > > >> On 09-05-2016, at 11:16 AM, tim Rowledge <tim(a)rowledge.org> wrote: > >> > >> > >>> On 09-05-2016, at 11:05 AM, tim Rowledge <tim(a)rowledge.org> wrote: > >>> > >>> An svn diff -r 3663:3692 in platforms/unix shows only some (to me) > innocuous changes in vm/aio.c > >>> > >>> More unixy expertise required to say if that has anything to do with > it. > >> > >> Building with the older version makes no difference for me. Let’s try > an older tree. > > > > 3680 fails, let’s try 3670 > > Per the X11 input thread for those not paying attention to everything, > 3671 is the last one I can get a display displaying on a Pi. > > > tim > -- > tim Rowledge; tim(a)rowledge.org; http://www.rowledge.org/tim > Klingon Code Warrior:- 6) "Our competitors are without honor!" > > > > -- _,,,^..^,,,_ best, Eliot

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Vm-dev May 2016