Vm-dev February 2018

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VM Maker: VMMaker.oscog-eem.2333.mcz
by commits＠source.squeak.org 10 Feb '18

10 Feb '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2333.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2333 Author: eem Time: 9 February 2018, 6:01:54.490829 pm UUID: c1d6776d-bdb0-415a-8e2b-8251cde78de0 Ancestors: VMMaker.oscog-eem.2332 RegisterAllocatingCogit: Fix mistakes in reconcileWith:spillOffset:onSpillOrUnspill: when merging with a volatile entry that has a register. The current entry must morph into an SSRegister, /not/ an SSSpill, and it must answer that it has merged a register. mergeCurrentSimStackWith: must deassign the target's reguster, /not/ current's. And it must actually update current's spill status on (un)spill. Fix slip in genForwardersInlinedIdenticalOrNotIf:. Fix new case in simStackMergeCompatibleWith:. With these changes the bootstrap gets beyond saving the image, > 18000 jitted methods, before hitting an assert fail due to a bad reguster assignment for simSelf in TransformMorph>>invalidRect:from:. Progress! Simulator: Have the break selector dialog allow setting an MNU break selector. =============== Diff against VMMaker.oscog-eem.2332 =============== Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileWith:spillOffset:onSpillOrUnspill: (in category 'compile abstract instructions') ----- reconcileWith: targetEntry spillOffset: spillOffset onSpillOrUnspill: spillOrUnspillBlock "Make the state of a targetEntry, a stack entry following a non-inlined special selector send, the same as the corresponding entry (the receiver) along the inlined path. spillOffset is zero for non-spill locations (self & temps), and the offset of the spill for volatile stack entries. spillOrUnspillBlock is a block evaluated with the target's registerOrNone if the receiver and target have different spilledness. Answer if the reconciliation merged a register; merged registers must be deassigned." <var: #targetEntry type: #'SimStackEntry *'> <inline: true> | targetReg mergedRegister | spilled = targetEntry spilled ifTrue: [self assert: ((self isSameEntryAs: targetEntry) or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). (targetReg := targetEntry registerOrNone) = NoReg ifTrue: [liveRegister := NoReg. ^false]. mergedRegister := false. type caseOf: { [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: [cogit MoveMw: offset r: register R: targetReg. mergedRegister := true]. targetEntry type caseOf: { [SSBaseOffset] -> [liveRegister := targetReg. (self isSameEntryAs: targetEntry) ifFalse: [type := SSSpill. offset := spillOffset]]. [SSSpill] -> [liveRegister := targetReg. type := SSSpill. offset := spillOffset]. [SSConstant] -> [liveRegister := targetReg. type := SSSpill. offset := spillOffset]. [SSRegister] -> [register := targetReg. type := SSRegister] }]. [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. liveRegister := targetReg. mergedRegister := true]. [SSConstant] -> [liveRegister = NoReg ifTrue: [cogit genMoveConstant: constant R: targetReg] ifFalse: [cogit MoveR: liveRegister R: targetReg]. type := SSRegister. register := targetReg. liveRegister := NoReg. mergedRegister := true]. [SSRegister] -> [targetReg ~= register ifTrue: [cogit MoveR: register R: targetReg. register := targetReg. mergedRegister := true]] }. ^mergedRegister]. targetReg := targetEntry registerOrNone. spillOrUnspillBlock value: targetReg. (type = SSConstant and: [targetEntry type ~= SSConstant or: [targetEntry constant ~= constant]]) ifTrue: [type := SSSpill. offset := spillOffset. register := FPReg]. + (spilled not and: [type = SSSpill]) ifTrue: + [self assert: targetReg ~= NoReg. type := SSRegister. register := targetReg]. liveRegister ~= targetReg ifTrue: + [liveRegister := NoReg. + ^true]. - [liveRegister := NoReg]. ^false! Item was changed: ----- Method: CogVMSimulator>>codeGeneratorToComputeAccessorDepth (in category 'primitive support') ----- codeGeneratorToComputeAccessorDepth + ^(VMMaker new - ^VMMaker new buildCodeGeneratorForInterpreter: CoInterpreterPrimitives includeAPIMethods: false + initializeClasses: false) + logger: self transcript; + yourself! - initializeClasses: false! Item was changed: ----- Method: CogVMSimulator>>utilitiesMenu: (in category 'UI') ----- utilitiesMenu: aMenuMorph aMenuMorph add: 'toggle transcript' action: #toggleTranscript; add: 'clone VM' action: #cloneSimulationWindow; addLine; add: 'print ext head frame' action: #printExternalHeadFrame; add: 'print int head frame' action: #printHeadFrame; add: 'print mc/cog head frame' action: [self printFrame: cogit processor fp WithSP: cogit processor sp]; add: 'short print ext head frame & callers' action: [self shortPrintFrameAndCallers: framePointer]; add: 'short print int head frame & callers' action: [self shortPrintFrameAndCallers: localFP]; add: 'short print mc/cog head frame & callers' action: [self shortPrintFrameAndCallers: cogit processor fp]; add: 'long print ext head frame & callers' action: [self printFrameAndCallers: framePointer SP: stackPointer]; add: 'long print int head frame & callers' action: [self printFrameAndCallers: localFP SP: localSP]; add: 'long print mc/cog head frame & callers' action: [self printFrameAndCallers: cogit processor fp SP: cogit processor sp]; add: 'print frame...' action: [(self promptHex: 'print frame') ifNotNil: [:fp| self printFrame: fp]]; add: 'print call stack' action: #printCallStack; add: 'print stack call stack' action: #printStackCallStack; add: 'print stack call stack of...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printStackCallStackOf: fp]]; add: 'print call stack of...' action: [(self promptHex: 'context or process oop') ifNotNil: [:obj| self printCallStackOf: obj]]; add: 'print call stack of frame...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printCallStackFP: fp]]; add: 'print all stacks' action: #printAllStacks; add: 'write back local ptrs' action: [stackPointer := localSP. framePointer := localFP. instructionPointer := localIP. self writeBackHeadFramePointers]; add: 'write back mc ptrs' action: [stackPointer := cogit processor sp. framePointer := cogit processor fp. instructionPointer := cogit processor pc. self externalWriteBackHeadFramePointers]; addLine; add: 'print rump C stack' action: [objectMemory printMemoryFrom: cogit processor sp to: cogit getCStackPointer]; add: 'print registers' action: [cogit processor printRegistersOn: transcript]; add: 'print register map' action: [cogit printRegisterMapOn: transcript]; add: 'disassemble method/trampoline...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit disassembleCodeAt: pc]]; add: 'disassemble method/trampoline at pc' action: [cogit disassembleCodeAt: (((cogit codeEntryFor: cogit processor pc) isNil and: [(cogit methodZone methodFor: cogit processor pc) = 0]) ifTrue: [instructionPointer] ifFalse: [cogit processor pc])]; add: 'disassemble ext head frame method' action: [cogit disassembleMethod: (self frameMethod: framePointer)]; add: 'print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self printOop: oop]]; add: 'long print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self longPrintOop: oop]]; add: 'print context...' action: [(self promptHex: 'print context') ifNotNil: [:oop| self printContext: oop]]; add: 'symbolic method...' action: [(self promptHex: 'method bytecodes') ifNotNil: [:oop| self symbolicMethod: oop]]; addLine; add: 'inspect object memory' target: objectMemory action: #inspect; add: 'run leak checker' action: [Cursor execute showWhile: [self runLeakChecker]]; add: 'inspect cointerpreter' action: #inspect; add: 'inspect cogit' target: cogit action: #inspect; add: 'inspect method zone' target: cogit methodZone action: #inspect. self isThreadedVM ifTrue: [aMenuMorph add: 'inspect thread manager' target: self threadManager action: #inspect]. aMenuMorph addLine; add: 'print cog methods' target: cogMethodZone action: #printCogMethods; add: 'print cog methods with prim...' action: [(self promptNum: 'prim index') ifNotNil: [:pix| cogMethodZone printCogMethodsWithPrimitive: pix]]; add: 'print cog methods with selector...' action: [|s| s := UIManager default request: 'selector'. s notEmpty ifTrue: [s = 'nil' ifTrue: [s := nil]. cogMethodZone methodsDo: [:m| (s ifNil: [m selector = objectMemory nilObject] ifNotNil: [(objectMemory numBytesOf: m selector) = s size and: [(self str: s n: (m selector + objectMemory baseHeaderSize) cmp: (objectMemory numBytesOf: m selector)) = 0]]) ifTrue: [cogit printCogMethod: m]]]]; add: 'print cog methods with method...' action: [(self promptHex: 'method') ifNotNil: [:methodOop| cogMethodZone methodsDo: [:m| m methodObject = methodOop ifTrue: [cogit printCogMethod: m]]]]; add: 'print cog method for...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit printCogMethodFor: pc]]; add: 'print cog method header for...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit printCogMethodHeaderFor: pc]]; add: 'print trampoline table' target: cogit action: #printTrampolineTable; add: 'print prim trace log' action: #dumpPrimTraceLog; add: 'report recent instructions' target: cogit action: #reportLastNInstructions; add: (cogit printRegisters ifTrue: ['no print registers each instruction'] ifFalse: ['print registers each instruction']) action: [cogit printRegisters: cogit printRegisters not]; add: (cogit printInstructions ifTrue: ['no print instructions each instruction'] ifFalse: ['print instructions each instruction']) action: [cogit printInstructions: cogit printInstructions not]; addLine; add: (cogit singleStep ifTrue: ['no single step'] ifFalse: ['single step']) action: [cogit singleStep: cogit singleStep not]; add: 'click step' action: [cogit setClickStepBreakBlock]; add: 'set break pc', cogit breakPC menuPrompt, '...-ve to disable or remove' action: [cogit promptForBreakPC]; add: 'set break count...' action: [|s| s := UIManager default request: 'break count (dec)'. s notEmpty ifTrue: [breakCount := Integer readFrom: s readStream]]; + add: 'set break selector...' action: [|s| s := UIManager default request: 'break selector (MNU:foo for MNU)'. + s notEmpty ifTrue: + [(s size > 4 and: [s beginsWith: 'MNU:']) + ifTrue: [self setBreakMNUSelector: (s allButFirst: 4)] + ifFalse: [self setBreakSelector: s]]]; - add: 'set break selector...' action: [|s| s := UIManager default request: 'break selector'. - s notEmpty ifTrue: [self setBreakSelector: s]]; add: 'set break block...' action: [|s| s := UIManager default request: 'break block' initialAnswer: '[:theCogit| false]'. s notEmpty ifTrue: [self setBreakBlockFromString: s]]; add: 'set cogit break method...' action: [(self promptHex: 'cogit breakMethod') ifNotNil: [:bm| cogit setBreakMethod: bm]]; add: (printBytecodeAtEachStep ifTrue: ['no print bytecode each bytecode'] ifFalse: ['print bytecode each bytecode']) action: [self ensureDebugAtEachStepBlock. printBytecodeAtEachStep := printBytecodeAtEachStep not]; add: (printFrameAtEachStep ifTrue: ['no print frame each bytecode'] ifFalse: ['print frame each bytecode']) action: [self ensureDebugAtEachStepBlock. printFrameAtEachStep := printFrameAtEachStep not]. ^aMenuMorph! Item was changed: ----- Method: Cogit>>cog:selector: (in category 'jit - api') ----- cog: aMethodObj selector: aSelectorOop "Attempt to produce a machine code method for the bytecode method object aMethodObj. N.B. If there is no code memory available do *NOT* attempt to reclaim the method zone. Certain clients (e.g. ceSICMiss:) depend on the zone remaining constant across method generation." <api> <returnTypeC: #'CogMethod *'> + | selector cogMethod | - | cogMethod | <var: #cogMethod type: #'CogMethod *'> (self exclude: aMethodObj selector: aSelectorOop) ifTrue: [^nil]. "In Newspeak we support anonymous accessors and hence tolerate the same method being cogged multiple times. But only if the method class association is nil." NewspeakVM ifTrue: [(coInterpreter methodHasCogMethod: aMethodObj) ifTrue: [cogMethod := coInterpreter cogMethodOf: aMethodObj. self deny: cogMethod selector = aSelectorOop. cogMethod selector = aSelectorOop ifTrue: [^cogMethod]. (coInterpreter methodClassAssociationOf: aMethodObj) ~= objectMemory nilObject ifTrue: [self cCode: 'extern void *firstIndexableField(sqInt)'. "Slang, au natural" self warnMultiple: cogMethod selectors: aSelectorOop. ^nil]]] ifFalse: [self deny: (coInterpreter methodHasCogMethod: aMethodObj)]. self deny: (objectMemory isOopCompiledMethod: (coInterpreter ultimateLiteralOf: aMethodObj)). + selector := aSelectorOop = objectMemory nilObject + ifTrue: [coInterpreter maybeSelectorOfMethod: aMethodObj] + ifFalse: [aSelectorOop]. + "coInterpreter stringOf: selector" - "coInterpreter stringOf: aSelectorOop" coInterpreter + compilationBreak: selector + point: (objectMemory lengthOf: selector) - compilationBreak: aSelectorOop - point: (objectMemory lengthOf: aSelectorOop) isMNUCase: false. aMethodObj = breakMethod ifTrue: [self halt: 'Compilation of breakMethod']. NewspeakVM ifTrue: [cogMethod := methodZone findPreviouslyCompiledVersionOf: aMethodObj with: aSelectorOop. cogMethod ifNotNil: [(coInterpreter methodHasCogMethod: aMethodObj) not ifTrue: [self assert: (coInterpreter rawHeaderOf: aMethodObj) = cogMethod methodHeader. cogMethod methodObject: aMethodObj. coInterpreter rawHeaderOf: aMethodObj put: cogMethod asInteger]. ^cogMethod]]. "If the generators for the alternate bytecode set are missing then interpret." (coInterpreter methodUsesAlternateBytecodeSet: aMethodObj) ifTrue: [(self numElementsIn: generatorTable) <= 256 ifTrue: [^nil]. bytecodeSetOffset := 256] ifFalse: [bytecodeSetOffset := 0]. objectRepresentation ensureNoForwardedLiteralsIn: aMethodObj. methodObj := aMethodObj. methodHeader := objectMemory methodHeaderOf: aMethodObj. receiverTags := objectMemory receiverTagBitsForMethod: methodObj. cogMethod := self compileCogMethod: aSelectorOop. (cogMethod asInteger between: MaxNegativeErrorCode and: -1) ifTrue: [cogMethod asInteger = InsufficientCodeSpace ifTrue: [coInterpreter callForCogCompiledCodeCompaction]. self maybeFreeCounters. "Right now no errors should be reported, so nothing more to do." "self reportError: (self cCoerceSimple: cogMethod to: #sqInt)." ^nil]. "self cCode: '' inSmalltalk: [coInterpreter printCogMethod: cogMethod. ""coInterpreter symbolicMethod: aMethodObj."" self assertValidMethodMap: cogMethod." "self disassembleMethod: cogMethod." "printInstructions := clickConfirm := true""]." ^cogMethod! Item was changed: ----- Method: RegisterAllocatingCogit>>genForwardersInlinedIdenticalOrNotIf: (in category 'bytecode generators') ----- genForwardersInlinedIdenticalOrNotIf: orNot | nextPC branchDescriptor unforwardRcvr argReg targetPC unforwardArg rcvrReg postBranchPC retry fixup comparison needMergeToTarget needMergeToContinue | <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #toContinueLabel type: #'AbstractInstruction *'> <var: #toTargetLabel type: #'AbstractInstruction *'> <var: #comparison type: #'AbstractInstruction *'> <var: #retry type: #'AbstractInstruction *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ]. "If an operand is an annotable constant, it may be forwarded, so we need to store it into a register so the forwarder check can jump back to the comparison after unforwarding the constant. However, if one of the operand is an unnanotable constant, does not allocate a register for it (machine code will use operations on constants) and does not generate forwarder checks." unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. self allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg rcvrNeedsReg: unforwardRcvr into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^self genIdenticalNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg orNotIf: orNot]. self assert: (unforwardArg or: [unforwardRcvr]). self ssPop: 2. "If we had moveAllButTop: 2 volatileSimStackEntriesToRegistersPreserving: we could avoid the extra ssPop:s" self moveVolatileSimStackEntriesToRegistersPreserving: (self allocatedRegisters bitOr: (argReg = NoReg ifTrue: [self registerMaskFor: rcvrReg] + ifFalse: + [rcvrReg = NoReg + ifTrue: [self registerMaskFor: argReg] + ifFalse: [self registerMaskFor: rcvrReg and: argReg]])). - ifFalse: [self registerMaskFor: rcvrReg and: argReg])). retry := self Label. self ssPop: -2. self genCmpArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. (self fixupAt: nextPC) notAFixup "The next instruction is dead. we can skip it." ifTrue: [deadCode := true] ifFalse: [self deny: deadCode]. "push dummy value below" "self printSimStack; printSimStack: (self fixupAt: postBranchPC) mergeSimStack" "If there are merges to be performed on the forward branches we have to execute the merge code only along the path requiring that merge, and exactly once." needMergeToTarget := self mergeRequiredForJumpTo: targetPC. needMergeToContinue := self mergeRequiredForJumpTo: postBranchPC. orNot == branchDescriptor isBranchTrue ifFalse: "a == b ifTrue: ... or a ~~ b ifFalse: ... jump on equal to target pc" [fixup := needMergeToContinue ifTrue: [0] "jumps will fall-through to to-continue merge code" ifFalse: [self ensureFixupAt: postBranchPC]. comparison := self JumpZero: (needMergeToTarget ifTrue: [0] "comparison will be fixed up to to-target merge code" ifFalse: [self ensureFixupAt: targetPC])] ifTrue: "a == b ifFalse: ... or a ~~ b ifTrue: ... jump on equal to post-branch pc" [fixup := needMergeToTarget ifTrue: [0] "jumps will fall-through to to-target merge code" ifFalse: [self ensureFixupAt: targetPC]. comparison := self JumpZero: (needMergeToContinue ifTrue: [0] "comparison will be fixed up to to-continue merge code" ifFalse: [self ensureFixupAt: postBranchPC])]. "The forwarders check(s) need(s) to jump back to the comparison (retry) if a forwarder is found, else jump forward either to the next forwarder check or to the postBranch or branch target (fixup). But if there is merge code along a path, the jump must be to the merge code." (unforwardArg and: [unforwardRcvr]) ifTrue: [objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: retry]. objectRepresentation genEnsureOopInRegNotForwarded: (unforwardRcvr ifTrue: [rcvrReg] ifFalse: [argReg]) scratchReg: TempReg ifForwarder: retry ifNotForwarder: fixup. "If fixup is zero then the ifNotForwarder path falls through to a Label which is interpreted as either to-continue or to-target, depending on orNot == branchDescriptor isBranchTrue." orNot == branchDescriptor isBranchTrue ifFalse: "a == b ifTrue: ... or a ~~ b ifFalse: ... jump on equal to target pc" [needMergeToContinue ifTrue: "fall-through to to-continue merge code" [self Jump: (self ensureFixupAt: postBranchPC)]. needMergeToTarget ifTrue: "fixup comparison to to-target merge code" [comparison jmpTarget: self Label. self Jump: (self ensureFixupAt: targetPC)]] ifTrue: "a == b ifFalse: ... or a ~~ b ifTrue: ... jump on equal to post-branch pc" [needMergeToTarget ifTrue: "fall-through to to-target merge code" [self Jump: (self ensureFixupAt: targetPC)]. needMergeToContinue ifTrue: "fixup comparison to to-continue merge code" [comparison jmpTarget: self Label. self Jump: (self ensureFixupAt: postBranchPC)]]. deadCode ifFalse: "duplicate the merge fixup's top of stack so as to avoid a false confict." [self ssPushDesc: ((self fixupAt: nextPC) mergeSimStack at: simStackPtr + 1)]. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup "At a merge point the cogit expects the stack to be in the same state as fixup's mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible." "self printSimStack; printSimStack: fixup mergeSimStack" "self simStackPrintString-> fixup simStackPrintString" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> | currentRegisters targetRegisters mergeSimStack current target spillOffset | (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. self assert: simStackPtr = fixup simStackPtr. currentRegisters := self liveRegistersFrom: 0 to: simStackPtr in: simStack. targetRegisters := self liveRegistersFrom: 0 to: simStackPtr in: mergeSimStack. self resolveConflicts: (currentRegisters bitAnd: targetRegisters) with: fixup mergeSimStack to: fixup simStackPtr. self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack). (self pushForMergeWith: mergeSimStack) ifTrue: [0 to: simStackPtr do: [:i| spillOffset := i > methodOrBlockNumTemps ifTrue: [self frameOffsetOfTemporary: i - 1] ifFalse: [0]. ((current := self simStack: simStack at: i) reconcileWith: (target := self simStack: mergeSimStack at: i) spillOffset: spillOffset onSpillOrUnspill: [:targetReg| self deny: current spilled. self assert: spillOffset ~= 0. + current ensureSpilledAt: spillOffset from: FPReg. + simSpillBase <= i ifTrue: + [simSpillBase := i + 1]]) ifTrue: + [| targetReg | + (i > methodOrBlockNumTemps and: [(targetReg := target registerOrNone) ~= NoReg]) ifTrue: + [self deassignRegister: targetReg in: simStack. + self deassignRegister: targetReg in: mergeSimStack. + self deny: (self register: targetReg isInMask: self liveRegistersInSelfAndTemps)]]]] - current ensureSpilledAt: spillOffset from: FPReg]) ifTrue: - [i > methodOrBlockNumTemps ifTrue: - [self deassignRegister: current registerOrNone in: mergeSimStack. - self deassignRegister: current registerOrNone in: simStack. - self deny: (self register: current registerOrNone - isInMask: self liveRegistersInSelfAndTemps)]]]] ifFalse: [simStackPtr to: 0 by: -1 do: [:i| spillOffset := i > methodOrBlockNumTemps ifTrue: [self frameOffsetOfTemporary: i - 1] ifFalse: [0]. ((current := self simStack: simStack at: i) reconcileWith: (target := self simStack: mergeSimStack at: i) spillOffset: spillOffset onSpillOrUnspill: [:targetReg| self assert: current spilled. self assert: spillOffset ~= 0. targetReg ~= NoReg ifTrue: [self PopR: targetReg] ifFalse: [self AddCq: objectRepresentation wordSize R: SPReg]. + current spilled: false. + simSpillBase > i ifTrue: + [simSpillBase := i]]) ifTrue: + [| targetReg | + (i > methodOrBlockNumTemps and: [(targetReg := target registerOrNone) ~= NoReg]) ifTrue: + [self deassignRegister: targetReg in: simStack. + self deassignRegister: targetReg in: mergeSimStack. + self deny: (self register: targetReg isInMask: self liveRegistersInSelfAndTemps)]]]]. - current type ~= SSSpill ifTrue: - [current spilled: false. - simSpillBase > i ifTrue: - [simSpillBase := i]]]) ifTrue: - [i > methodOrBlockNumTemps ifTrue: - [self deassignRegister: current registerOrNone in: mergeSimStack. - self deassignRegister: current registerOrNone in: simStack. - self deny: (self register: current registerOrNone - isInMask: self liveRegistersInSelfAndTemps)]]]]. self updateSimSpillBase! Item was changed: ----- Method: RegisterAllocatingCogit>>simStackMergeCompatibleWith: (in category 'bytecode generator support') ----- simStackMergeCompatibleWith: fixup simStackPtr = fixup simStackPtr ifFalse: [^false]. simStackPtr to: 0 by: -1 do: [:i| | target current | target := self simStack: fixup mergeSimStack at: i. current := self simStack: simStack at: i. (target isSameEntryAs: current) ifFalse: [^current type caseOf: { + [SSBaseOffset] -> [(current offset = (self frameOffsetOfTemporary: i - 1) + and: [current register = FPReg]) + ifTrue: [true] "current has been spilled virtually" + ifFalse: + [target type caseOf: { + [SSBaseOffset] -> [false]. + [SSSpill] -> [false]. + [SSConstant] -> [false]. + [SSRegister] -> [false] }]]. - [SSBaseOffset] -> [target type caseOf: { - [SSBaseOffset] -> [false]. - [SSSpill] -> [false]. - [SSConstant] -> [false]. - [SSRegister] -> [false] }]. [SSSpill] -> [target type caseOf: { [SSBaseOffset] -> [true]. [SSSpill] -> [true]. [SSConstant] -> [true]. [SSRegister] -> [true] }]. [SSConstant] -> [target type caseOf: { [SSBaseOffset] -> [false]. [SSSpill] -> [false]. [SSConstant] -> [current constant = target constant]. [SSRegister] -> [false] }]. [SSRegister] -> [target type caseOf: { [SSBaseOffset] -> [current register = target liveRegister]. [SSSpill] -> [current register = target liveRegister]. [SSConstant] -> [current register = target liveRegister]. [SSRegister] -> [current register = target register] }] }]]. ^true! Item was changed: ----- Method: StackInterpreter>>codeGeneratorToComputeAccessorDepth (in category 'primitive support') ----- codeGeneratorToComputeAccessorDepth + ^(VMMaker new - ^VMMaker new buildCodeGeneratorForInterpreter: self class primitivesClass includeAPIMethods: false + initializeClasses: false) + logger: self transcript; + yourself! - initializeClasses: false! Item was changed: ----- Method: StackInterpreterSimulator>>utilitiesMenu: (in category 'UI') ----- utilitiesMenu: aMenuMorph aMenuMorph add: 'toggle transcript' action: #toggleTranscript; add: 'clone VM' action: #cloneSimulationWindow; addLine; add: 'print ext head frame' action: #printExternalHeadFrame; add: 'print int head frame' action: #printHeadFrame; add: 'short print ext frame & callers' action: [self shortPrintFrameAndCallers: framePointer]; add: 'short print int frame & callers' action: [self shortPrintFrameAndCallers: localFP]; add: 'long print ext frame & callers' action: [self printFrameAndCallers: framePointer SP: stackPointer]; add: 'long print int frame & callers' action: [self printFrameAndCallers: localFP SP: localSP]; add: 'print frame...' action: [(self promptHex: 'print frame') ifNotNil: [:fp| self printFrame: fp]]; add: 'print call stack' action: #printCallStack; add: 'print stack call stack' action: #printStackCallStack; add: 'print stack call stack of...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printStackCallStackOf: fp]]; add: 'print call stack of...' action: [(self promptHex: 'context or process oop') ifNotNil: [:obj| self printCallStackOf: obj]]; add: 'print call stack of frame...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printCallStackFP: fp]]; add: 'print all stacks' action: #printAllStacks; add: 'write back local ptrs' action: [stackPointer := localSP. framePointer := localFP. instructionPointer := localIP. self writeBackHeadFramePointers]; add: 'print prim trace log' action: #dumpPrimTraceLog; addLine; add: 'print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self printOop: oop]]; add: 'long print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self longPrintOop: oop]]; add: 'print context...' action: [(self promptHex: 'print context') ifNotNil: [:oop| self printContext: oop]]; addLine; add: 'inspect object memory' target: objectMemory action: #inspect; add: 'run leak checker' action: [Cursor execute showWhile: [self runLeakChecker]]; add: 'inspect interpreter' action: #inspect; addLine; add: 'set break count...' action: [|s| s := UIManager default request: 'break count (dec)'. s notEmpty ifTrue: [breakCount := Integer readFrom: s readStream]]; + add: 'set break selector...' action: [|s| s := UIManager default request: 'break selector (MNU:foo for MNU)'. + s notEmpty ifTrue: + [(s size > 4 and: [s beginsWith: 'MNU:']) + ifTrue: [self setBreakMNUSelector: (s allButFirst: 4)] + ifFalse: [self setBreakSelector: s]]]; - add: 'set break selector...' action: [|s| s := UIManager default request: 'break selector'. - s notEmpty ifTrue: [self setBreakSelector: s]]; add: 'turn valid exec ptrs assert o', (assertVEPAES ifTrue: ['ff'] ifFalse: ['n']) action: [assertVEPAES := assertVEPAES not]; add: 'click step' action: [self setClickStepBreakBlock]; add: (printSends ifTrue: ['no print sends'] ifFalse: ['print sends']) action: [self ensureDebugAtEachStepBlock. printSends := printSends not]; "currently printReturns does nothing" "add: (printReturns ifTrue: ['no print returns'] ifFalse: ['print returns']) action: [self ensureDebugAtEachStepBlock. printReturns := printReturns not];" add: (printBytecodeAtEachStep ifTrue: ['no print bytecode each bytecode'] ifFalse: ['print bytecode each bytecode']) action: [self ensureDebugAtEachStepBlock. printBytecodeAtEachStep := printBytecodeAtEachStep not]; add: (printFrameAtEachStep ifTrue: ['no print frame each bytecode'] ifFalse: ['print frame each bytecode']) action: [self ensureDebugAtEachStepBlock. printFrameAtEachStep := printFrameAtEachStep not]. ^aMenuMorph!

1 0

VM Maker: VMMaker.oscog-eem.2332.mcz
by commits＠source.squeak.org 09 Feb '18

09 Feb '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2332.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2332 Author: eem Time: 8 February 2018, 6:01:54.68433 pm UUID: f17f3408-e209-439f-b78c-6af70bf7cdd0 Ancestors: VMMaker.oscog-eem.2331 RegisterAllocatingCogit: Moving volatile stack contents to registers should happen once before each jump, not potentially multiple times in ensureFixupAt:. Refactor moveVolatileSimStackEntriesToRegisters into moveVolatileSimStackEntriesToRegistersPreserving:, allowing easier use by the sopecial selecrtor generators, which have allocated registers before they're ready to move volatile contents to registers. When reconciling, if a constant is in a register, use the register. =============== Diff against VMMaker.oscog-eem.2331 =============== Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileWith:spillOffset:onSpillOrUnspill: (in category 'compile abstract instructions') ----- reconcileWith: targetEntry spillOffset: spillOffset onSpillOrUnspill: spillOrUnspillBlock "Make the state of a targetEntry, a stack entry following a non-inlined special selector send, the same as the corresponding entry (the receiver) along the inlined path. spillOffset is zero for non-spill locations (self & temps), and the offset of the spill for volatile stack entries. spillOrUnspillBlock is a block evaluated with the target's registerOrNone if the receiver and target have different spilledness. Answer if the reconciliation merged a register; merged registers must be deassigned." <var: #targetEntry type: #'SimStackEntry *'> <inline: true> | targetReg mergedRegister | spilled = targetEntry spilled ifTrue: [self assert: ((self isSameEntryAs: targetEntry) or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). (targetReg := targetEntry registerOrNone) = NoReg ifTrue: [liveRegister := NoReg. ^false]. mergedRegister := false. type caseOf: { [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: [cogit MoveMw: offset r: register R: targetReg. mergedRegister := true]. targetEntry type caseOf: { [SSBaseOffset] -> [liveRegister := targetReg. (self isSameEntryAs: targetEntry) ifFalse: [type := SSSpill. offset := spillOffset]]. [SSSpill] -> [liveRegister := targetReg. type := SSSpill. offset := spillOffset]. [SSConstant] -> [liveRegister := targetReg. type := SSSpill. offset := spillOffset]. [SSRegister] -> [register := targetReg. type := SSRegister] }]. [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. liveRegister := targetReg. mergedRegister := true]. + [SSConstant] -> [liveRegister = NoReg + ifTrue: [cogit genMoveConstant: constant R: targetReg] + ifFalse: [cogit MoveR: liveRegister R: targetReg]. - [SSConstant] -> [cogit genMoveConstant: constant R: targetReg. type := SSRegister. register := targetReg. liveRegister := NoReg. mergedRegister := true]. [SSRegister] -> [targetReg ~= register ifTrue: [cogit MoveR: register R: targetReg. register := targetReg. mergedRegister := true]] }. ^mergedRegister]. targetReg := targetEntry registerOrNone. spillOrUnspillBlock value: targetReg. (type = SSConstant and: [targetEntry type ~= SSConstant or: [targetEntry constant ~= constant]]) ifTrue: [type := SSSpill. offset := spillOffset. register := FPReg]. liveRegister ~= targetReg ifTrue: [liveRegister := NoReg]. ^false! Item was changed: ----- Method: RegisterAllocatingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- assertCorrectSimStackPtr <inline: true> "generates nothing anyway" "self simStackPrintString" self cCode: '' inSmalltalk: [deadCode ifFalse: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) + = (self debugStackPointerFor: bytecodePC). + self assert: (simSpillBase >= methodOrBlockNumTemps + or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil and: [simSpillBase > methodOrBlockNumArgs]]). + (needsFrame and: [simSpillBase > 0]) ifTrue: + [self assert: (self simStackAt: simSpillBase - 1) spilled == true. + self assert: (simSpillBase > simStackPtr or: [(self simStackAt: simSpillBase) spilled == false])]]. - = (self debugStackPointerFor: bytecodePC)]. self deny: self duplicateRegisterAssignmentsInTemporaries]! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureFixupAt: (in category 'bytecode generator support') ----- ensureFixupAt: targetPC "Make sure there's a flagged fixup at the target pc in fixups. Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction. Override to generate stack merging code if required." | fixup | <var: #fixup type: #'BytecodeFixup *'> self assert: targetPC > bytecodePC. self cCode: '' inSmalltalk: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) = (self debugStackPointerFor: targetPC)]. fixup := self fixupAt: targetPC. "If a non-merge fixup has already been defined then where-ever that was done didn't realise there needed to be a merge and forgot to save the stack state for that merge." self deny: fixup isNonMergeFixup. fixup needsFixup ifTrue: [fixup mergeSimStack ifNil: [self setMergeSimStackOf: fixup] ifNotNil: [self copySimStackToScratch: simSpillBase. self mergeCurrentSimStackWith: fixup. self restoreSimStackFromScratch]] ifFalse: [self assert: (fixup mergeSimStack isNil or: [compilationPass = 2]). fixup mergeSimStack ifNil: [self setMergeSimStackOf: fixup] ifNotNil: + [self assert: (self simStack: simStack isIdenticalTo: fixup mergeSimStack)]]. - [self moveVolatileSimStackEntriesToRegisters. - self assert: (self simStack: simStack isIdenticalTo: fixup mergeSimStack)]]. ^super ensureFixupAt: targetPC! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureNonMergeFixupAt: (in category 'compile abstract instructions') ----- ensureNonMergeFixupAt: targetPC + "RegisterAllocatingCogit insists on merging." + self shouldNotImplement! - "Make sure there's a flagged fixup at the target pc in fixups. - Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction. - Override to remember the simStack state at the target, if not already there." - "self printSimStack; printSimStack: fixup mergeSimStack" - true - ifTrue: [self shouldNotImplement] - ifFalse: - [| fixup | - fixup := super ensureNonMergeFixupAt: targetPC. - fixup mergeSimStack - ifNil: [self setMergeSimStackOf: fixup] - ifNotNil: - [self assert: simStackPtr = fixup simStackPtr. - self deny: (self mergeRequiredToTarget: fixup mergeSimStack)]. - ^fixup]! Item was changed: ----- Method: RegisterAllocatingCogit>>genForwardersInlinedIdenticalOrNotIf: (in category 'bytecode generators') ----- genForwardersInlinedIdenticalOrNotIf: orNot | nextPC branchDescriptor unforwardRcvr argReg targetPC unforwardArg rcvrReg postBranchPC retry fixup comparison needMergeToTarget needMergeToContinue | <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #toContinueLabel type: #'AbstractInstruction *'> <var: #toTargetLabel type: #'AbstractInstruction *'> <var: #comparison type: #'AbstractInstruction *'> <var: #retry type: #'AbstractInstruction *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ]. "If an operand is an annotable constant, it may be forwarded, so we need to store it into a register so the forwarder check can jump back to the comparison after unforwarding the constant. However, if one of the operand is an unnanotable constant, does not allocate a register for it (machine code will use operations on constants) and does not generate forwarder checks." unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. self allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg rcvrNeedsReg: unforwardRcvr into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^self genIdenticalNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg orNotIf: orNot]. self assert: (unforwardArg or: [unforwardRcvr]). + self ssPop: 2. "If we had moveAllButTop: 2 volatileSimStackEntriesToRegistersPreserving: we could avoid the extra ssPop:s" + self moveVolatileSimStackEntriesToRegistersPreserving: + (self allocatedRegisters bitOr: (argReg = NoReg + ifTrue: [self registerMaskFor: rcvrReg] + ifFalse: [self registerMaskFor: rcvrReg and: argReg])). - retry := self Label. + self ssPop: -2. self genCmpArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. (self fixupAt: nextPC) notAFixup "The next instruction is dead. we can skip it." ifTrue: [deadCode := true] ifFalse: [self deny: deadCode]. "push dummy value below" "self printSimStack; printSimStack: (self fixupAt: postBranchPC) mergeSimStack" "If there are merges to be performed on the forward branches we have to execute the merge code only along the path requiring that merge, and exactly once." needMergeToTarget := self mergeRequiredForJumpTo: targetPC. needMergeToContinue := self mergeRequiredForJumpTo: postBranchPC. orNot == branchDescriptor isBranchTrue ifFalse: "a == b ifTrue: ... or a ~~ b ifFalse: ... jump on equal to target pc" [fixup := needMergeToContinue ifTrue: [0] "jumps will fall-through to to-continue merge code" ifFalse: [self ensureFixupAt: postBranchPC]. comparison := self JumpZero: (needMergeToTarget ifTrue: [0] "comparison will be fixed up to to-target merge code" ifFalse: [self ensureFixupAt: targetPC])] ifTrue: "a == b ifFalse: ... or a ~~ b ifTrue: ... jump on equal to post-branch pc" [fixup := needMergeToTarget ifTrue: [0] "jumps will fall-through to to-target merge code" ifFalse: [self ensureFixupAt: targetPC]. comparison := self JumpZero: (needMergeToContinue ifTrue: [0] "comparison will be fixed up to to-continue merge code" ifFalse: [self ensureFixupAt: postBranchPC])]. "The forwarders check(s) need(s) to jump back to the comparison (retry) if a forwarder is found, else jump forward either to the next forwarder check or to the postBranch or branch target (fixup). But if there is merge code along a path, the jump must be to the merge code." (unforwardArg and: [unforwardRcvr]) ifTrue: [objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: retry]. objectRepresentation genEnsureOopInRegNotForwarded: (unforwardRcvr ifTrue: [rcvrReg] ifFalse: [argReg]) scratchReg: TempReg ifForwarder: retry ifNotForwarder: fixup. "If fixup is zero then the ifNotForwarder path falls through to a Label which is interpreted as either to-continue or to-target, depending on orNot == branchDescriptor isBranchTrue." orNot == branchDescriptor isBranchTrue ifFalse: "a == b ifTrue: ... or a ~~ b ifFalse: ... jump on equal to target pc" [needMergeToContinue ifTrue: "fall-through to to-continue merge code" [self Jump: (self ensureFixupAt: postBranchPC)]. needMergeToTarget ifTrue: "fixup comparison to to-target merge code" [comparison jmpTarget: self Label. self Jump: (self ensureFixupAt: targetPC)]] ifTrue: "a == b ifFalse: ... or a ~~ b ifTrue: ... jump on equal to post-branch pc" [needMergeToTarget ifTrue: "fall-through to to-target merge code" [self Jump: (self ensureFixupAt: targetPC)]. needMergeToContinue ifTrue: "fixup comparison to to-continue merge code" [comparison jmpTarget: self Label. self Jump: (self ensureFixupAt: postBranchPC)]]. deadCode ifFalse: "duplicate the merge fixup's top of stack so as to avoid a false confict." [self ssPushDesc: ((self fixupAt: nextPC) mergeSimStack at: simStackPtr + 1)]. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genJumpIf:to: (in category 'bytecode generator support') ----- genJumpIf: boolean to: targetBytecodePC <inline: false> | eventualTarget desc reg fixup ok mbb noMustBeBoolean | <var: #fixup type: #'BytecodeFixup *'> <var: #ok type: #'AbstractInstruction *'> <var: #desc type: #'CogSimStackEntry *'> <var: #mbb type: #'AbstractInstruction *'> eventualTarget := self eventualTargetOf: targetBytecodePC. desc := self ssTop. self ssPop: 1. noMustBeBoolean := self extASpecifiesNoMustBeBoolean. extA := 0. + self moveVolatileSimStackEntriesToRegisters. + (self stackEntryIsBoolean: desc) ifTrue: ["Must annotate the bytecode for correct pc mapping." desc constant = boolean ifTrue: [deadCode := true. "Can't fall through." fixup := self ensureFixupAt: eventualTarget. self annotateBytecode: (self Jump: fixup)] ifFalse: [self annotateBytecode: (self prevInstIsPCAnnotated ifTrue: [self Nop] ifFalse: [self Label])]. ^0]. "try and use the top entry's register if any, but only if it can be destroyed." reg := (desc type ~= SSRegister or: [(self anyReferencesToRegister: desc register inAllButTopNItems: 0) or: [(desc register = ReceiverResultReg and: [self receiverIsInReceiverResultReg])]]) ifTrue: [TempReg] ifFalse: [desc register]. desc popToReg: reg. "Cunning trick by LPD. If true and false are contiguous subtract the smaller. Correct result is either 0 or the distance between them. If result is not 0 or their distance send mustBeBoolean." self assert: (objectMemory objectAfter: objectMemory falseObject) = objectMemory trueObject. "Merge required; must not generate merge code along untaken branch, so flip the order." (self mergeRequiredForJumpTo: eventualTarget) ifTrue: [self genSubConstant: (boolean = objectMemory trueObject ifTrue: [objectMemory falseObject] ifFalse: [objectMemory trueObject]) R: reg. ok := self JumpZero: 0. self CmpCq: (boolean = objectMemory trueObject ifTrue: [objectMemory trueObject - objectMemory falseObject] ifFalse: [objectMemory falseObject - objectMemory trueObject]) R: reg. noMustBeBoolean ifTrue: [self JumpZero: (self ensureFixupAt: eventualTarget). "generates merge code" ok jmpTarget: (self annotateBytecode: self lastOpcode). ^0]. mbb := self JumpNonZero: 0. self Jump: (self ensureFixupAt: eventualTarget). "generates merge code" mbb jmpTarget: self Label] ifFalse: [self genSubConstant: boolean R: reg. self JumpZero: (self ensureFixupAt: eventualTarget). noMustBeBoolean ifTrue: [self annotateBytecode: self lastOpcode. ^0]. self CmpCq: (boolean = objectMemory falseObject ifTrue: [objectMemory trueObject - objectMemory falseObject] ifFalse: [objectMemory falseObject - objectMemory trueObject]) R: reg. ok := self JumpZero: 0]. reg ~= TempReg ifTrue: [self MoveR: reg R: TempReg]. self copySimStackToScratch: simSpillBase. self ssFlushTo: simStackPtr. self genCallMustBeBooleanFor: boolean. "NOTREACHED" ok jmpTarget: (self annotateBytecode: self Label). self restoreSimStackFromScratch. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genJumpTo: (in category 'bytecode generator support') ----- genJumpTo: targetBytecodePC "Overriden to avoid the flush because in this cogit stack state is merged at merge point." | eventualTarget generator fixup | + self moveVolatileSimStackEntriesToRegisters. eventualTarget := self eventualTargetOf: targetBytecodePC. (eventualTarget > bytecodePC and: [self stackTopIsBoolean and: [(generator := self generatorForPC: eventualTarget) isConditionalBranch]]) ifTrue: [eventualTarget := eventualTarget + generator numBytes + (generator isBranchTrue == (self ssTop constant = objectMemory trueObject) ifTrue: [self spanFor: generator at: eventualTarget exts: 0 in: methodObj] ifFalse: [0]). self ssPop: 1. fixup := self ensureFixupAt: eventualTarget. self ssPop: -1] ifFalse: [fixup := self ensureFixupAt: eventualTarget]. deadCode := true. "can't fall through" self Jump: fixup. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison | nextPC postBranchPC targetPC primDescriptor branchDescriptor rcvrIsInt rcvrIsConst argIsIntConst argInt jumpNotSmallInts inlineCAB index rcvrReg argReg branchToTarget needMergeToContinue needMergeToTarget | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> primDescriptor := self generatorAt: byte0. argIsIntConst := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := ((rcvrIsConst := (self ssValue: 1) type = SSConstant) and: [objectMemory isIntegerObject: (self ssValue: 1) constant]) or: [self mclassIsSmallInteger and: [(self ssValue: 1) isSameEntryAs: self simSelf]]. (argIsIntConst and: [rcvrIsInt and: [rcvrIsConst]]) ifTrue: [^self genStaticallyResolvedSpecialSelectorComparison]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetPC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsIntConst or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. "In-line the comparison and the jump, but if the types are not SmallInteger then we will need to do a send and fall through to the following conditional branch. Since we're allocating values in registers we would like to keep those registers live on the inlined path and reload registers along the non-inlined send path. The merge logic at the branch destinations handles this." argIsIntConst ifTrue: [rcvrReg := self allocateRegForStackEntryAt: 1. (self ssValue: 1) popToReg: rcvrReg. argReg := NoReg] ifFalse: [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue: 1) popToReg: rcvrReg]. self ssPop: 2. + self moveVolatileSimStackEntriesToRegistersPreserving: + (self allocatedRegisters bitOr: (argReg = NoReg + ifTrue: [self registerMaskFor: rcvrReg] + ifFalse: [self registerMaskFor: rcvrReg and: argReg])). + jumpNotSmallInts := (rcvrIsInt and: [argIsIntConst]) ifFalse: [argIsIntConst ifTrue: [objectRepresentation genJumpNotSmallInteger: rcvrReg] ifFalse: [rcvrIsInt ifTrue: [objectRepresentation genJumpNotSmallInteger: argReg] ifFalse: [objectRepresentation genJumpNotSmallIntegersIn: rcvrReg and: argReg scratch: TempReg]]]. argIsIntConst ifTrue: [self CmpCq: argInt R: rcvrReg] ifFalse: [self CmpR: argReg R: rcvrReg]. "self printSimStack; printSimStack: (self fixupAt: postBranchPC) mergeSimStack; printSimStack: (self fixupAt: targetPC) mergeSimStack" "If there are merges to be performed on the forward branches we have to execute the merge code only along the path requiring that merge, and exactly once." needMergeToTarget := self mergeRequiredForJumpTo: targetPC. needMergeToContinue := self mergeRequiredForJumpTo: postBranchPC. "Cmp is weird/backwards so invert the comparison." (needMergeToTarget and: [needMergeToContinue]) ifTrue: [branchToTarget := self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: 0. self Jump: (self ensureFixupAt: postBranchPC). branchToTarget jmpTarget: self Label. self Jump: (self ensureFixupAt: targetPC)]. (needMergeToTarget and: [needMergeToContinue not]) ifTrue: [self genConditionalBranch: (branchDescriptor isBranchFalse ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: postBranchPC) asUnsignedInteger. self Jump: (self ensureFixupAt: targetPC)]. (needMergeToTarget not and: [needMergeToContinue]) ifTrue: [self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: targetPC) asUnsignedInteger. self Jump: (self ensureFixupAt: postBranchPC)]. (needMergeToTarget or: [needMergeToContinue]) ifFalse: [self genConditionalBranch: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureFixupAt: targetPC) asUnsignedInteger. self Jump: (self ensureFixupAt: postBranchPC)]. jumpNotSmallInts ifNil: [self annotateInstructionForBytecode. deadCode := true. ^0]. jumpNotSmallInts jmpTarget: self Label. self ssFlushTo: simStackPtr. rcvrReg = Arg0Reg ifTrue: [argReg = ReceiverResultReg ifTrue: [self SwapR: Arg0Reg R: Arg0Reg Scratch: TempReg. argReg := Arg0Reg] ifFalse: [self MoveR: rcvrReg R: ReceiverResultReg]. rcvrReg := ReceiverResultReg]. argIsIntConst ifTrue: [self MoveCq: argInt R: Arg0Reg] ifFalse: [argReg ~= Arg0Reg ifTrue: [self MoveR: argReg R: Arg0Reg]]. rcvrReg ~= ReceiverResultReg ifTrue: [self MoveR: rcvrReg R: ReceiverResultReg]. index := byte0 - self firstSpecialSelectorBytecodeOffset. ^self genMarshalledSend: index negated - 1 numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: RegisterAllocatingCogit>>genVanillaInlinedIdenticalOrNotIf: (in category 'bytecode generators') ----- genVanillaInlinedIdenticalOrNotIf: orNot | nextPC postBranchPC targetBytecodePC branchDescriptor rcvrReg argReg argIsConstant rcvrIsConstant | <var: #branchDescriptor type: #'BytecodeDescriptor *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. argIsConstant := self ssTop type = SSConstant. "They can't be both constants to use correct machine opcodes. However annotable constants can't be resolved statically, hence we need to careful." rcvrIsConstant := argIsConstant not and: [(self ssValue: 1) type = SSConstant]. self allocateEqualsEqualsRegistersArgNeedsReg: argIsConstant not rcvrNeedsReg: rcvrIsConstant not into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genIdenticalNoBranchArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg orNotIf: orNot]. - self genCmpArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. + self moveVolatileSimStackEntriesToRegistersPreserving: + (self allocatedRegisters bitOr: (argReg = NoReg + ifTrue: [self registerMaskFor: rcvrReg] + ifFalse: [self registerMaskFor: rcvrReg and: argReg])). + self genCmpArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg. + "For now just deny we're in the situation we have yet to implement ;-)" self deny: (self mergeRequiredForJumpTo: targetBytecodePC). self deny: (self mergeRequiredForJumpTo: postBranchPC). "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." (self fixupAt: nextPC) notAFixup ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC. self ensureFixupAt: postBranchPC] ifFalse: [self deny: deadCode]. "push dummy value below" self genConditionalBranch: (orNot == branchDescriptor isBranchTrue ifTrue: [JumpNonZero] ifFalse: [JumpZero]) operand: (self ensureNonMergeFixupAt: targetBytecodePC) asUnsignedInteger. "If the branch is dead, then we can just fall through postBranchPC (only a nop in-between), else we need to jump over the code of the branch" deadCode ifFalse: [self Jump: (self ensureNonMergeFixupAt: postBranchPC). "duplicate the merge fixup's top of stack so as to avoid a false confict." self ssPushDesc: ((self fixupAt: nextPC) mergeSimStack at: simStackPtr + 1)]. ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup "At a merge point the cogit expects the stack to be in the same state as fixup's mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible." "self printSimStack; printSimStack: fixup mergeSimStack" "self simStackPrintString-> fixup simStackPrintString" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> | currentRegisters targetRegisters mergeSimStack current target spillOffset | (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. self assert: simStackPtr = fixup simStackPtr. currentRegisters := self liveRegistersFrom: 0 to: simStackPtr in: simStack. targetRegisters := self liveRegistersFrom: 0 to: simStackPtr in: mergeSimStack. self resolveConflicts: (currentRegisters bitAnd: targetRegisters) with: fixup mergeSimStack to: fixup simStackPtr. self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack). (self pushForMergeWith: mergeSimStack) ifTrue: [0 to: simStackPtr do: [:i| spillOffset := i > methodOrBlockNumTemps ifTrue: [self frameOffsetOfTemporary: i - 1] ifFalse: [0]. ((current := self simStack: simStack at: i) reconcileWith: (target := self simStack: mergeSimStack at: i) spillOffset: spillOffset onSpillOrUnspill: [:targetReg| self deny: current spilled. self assert: spillOffset ~= 0. current ensureSpilledAt: spillOffset from: FPReg]) ifTrue: [i > methodOrBlockNumTemps ifTrue: [self deassignRegister: current registerOrNone in: mergeSimStack. self deassignRegister: current registerOrNone in: simStack. self deny: (self register: current registerOrNone isInMask: self liveRegistersInSelfAndTemps)]]]] ifFalse: [simStackPtr to: 0 by: -1 do: [:i| spillOffset := i > methodOrBlockNumTemps ifTrue: [self frameOffsetOfTemporary: i - 1] ifFalse: [0]. ((current := self simStack: simStack at: i) reconcileWith: (target := self simStack: mergeSimStack at: i) spillOffset: spillOffset onSpillOrUnspill: [:targetReg| self assert: current spilled. self assert: spillOffset ~= 0. targetReg ~= NoReg ifTrue: [self PopR: targetReg] + ifFalse: [self AddCq: objectRepresentation wordSize R: SPReg]. + current type ~= SSSpill ifTrue: + [current spilled: false. + simSpillBase > i ifTrue: + [simSpillBase := i]]]) ifTrue: - ifFalse: [self AddCq: objectRepresentation wordSize R: SPReg]]) ifTrue: [i > methodOrBlockNumTemps ifTrue: [self deassignRegister: current registerOrNone in: mergeSimStack. self deassignRegister: current registerOrNone in: simStack. self deny: (self register: current registerOrNone isInMask: self liveRegistersInSelfAndTemps)]]]]. self updateSimSpillBase! Item was changed: ----- Method: RegisterAllocatingCogit>>moveVolatileSimStackEntriesToRegisters (in category 'bytecode generator support') ----- moveVolatileSimStackEntriesToRegisters + self moveVolatileSimStackEntriesToRegistersPreserving: self allocatedRegisters! - "When jumping forward to a merge point the stack must be reconcilable with the state that falls through to the merge point. - We cannot easily arrange that later we add code to the branch, e.g. to spill values. Instead, any volatile contents must be - moved to registers. - [In fact, that's not exactly true, consider these two code sequences: - self at: (expr ifTrue: [1] ifFalse: [2]) put: a - self at: 1 put: (expr ifTrue: [a] ifFalse: [b]) - The first one needs 1 saving to a register to reconcile with 2. - The second one has 1 on both paths, but we're not clever enough to spot this case yet. - First of all, if the constant requires an annotation then it is difficult to deal with. But if the constant - does not require an annotation one way would be for a SimStackEntry for an SSConstant to refer to - the loading instruction and then at the merge simply change the loading instruction to a Label if the - constant is the same on both branches]. - Volatile contents are anything not spilled to the stack, because as yet we can only merge registers." - <inline: true> - | allocatedRegs | - <var: #desc type: #'SimStackEntry *'> - allocatedRegs := self allocatedRegisters. - self assert: simSpillBase >= 0. - simSpillBase to: simStackPtr do: - [:i| | desc reg | - desc := self simStackAt: i. - desc spilled - ifTrue: [simSpillBase := i] - ifFalse: - [desc registerOrNone = NoReg ifTrue: - [reg := self allocateRegNotConflictingWith: allocatedRegs. - reg = NoReg - ifTrue: [self halt] "have to spill" - ifFalse: - [desc storeToReg: reg. - allocatedRegs := allocatedRegs bitOr: (self registerMaskFor: reg)]]]]. - self deny: self duplicateRegisterAssignmentsInTemporaries! Item was added: + ----- Method: RegisterAllocatingCogit>>moveVolatileSimStackEntriesToRegistersPreserving: (in category 'bytecode generator support') ----- + moveVolatileSimStackEntriesToRegistersPreserving: registerSet + "When jumping forward to a merge point the stack must be reconcilable with the state that falls through to the merge point. + We cannot easily arrange that later we add code to the branch, e.g. to spill values. Instead, any volatile contents must be + moved to registers. + [In fact, that's not exactly true, consider these two code sequences: + self at: (expr ifTrue: [1] ifFalse: [2]) put: a + self at: 1 put: (expr ifTrue: [a] ifFalse: [b]) + The first one needs 1 saving to a register to reconcile with 2. + The second one has 1 on both paths, but we're not clever enough to spot this case yet. + First of all, if the constant requires an annotation then it is difficult to deal with. But if the constant + does not require an annotation one way would be for a SimStackEntry for an SSConstant to refer to + the loading instruction and then at the merge simply change the loading instruction to a Label if the + constant is the same on both branches]. + Volatile contents are anything not spilled to the stack, because as yet we can only merge registers." + <inline: true> + | allocatedRegs | + <var: #desc type: #'SimStackEntry *'> + allocatedRegs := registerSet. + self assert: simSpillBase >= 0. + simSpillBase to: simStackPtr do: + [:i| | desc reg | + desc := self simStackAt: i. + desc spilled + ifTrue: [simSpillBase := i] + ifFalse: + [desc registerOrNone = NoReg ifTrue: + [reg := self allocateRegNotConflictingWith: allocatedRegs. + reg = NoReg + ifTrue: [self halt] "have to spill" + ifFalse: + [desc storeToReg: reg. + allocatedRegs := allocatedRegs bitOr: (self registerMaskFor: reg)]]]]. + self deny: self duplicateRegisterAssignmentsInTemporaries! Item was changed: ----- Method: RegisterAllocatingCogit>>setMergeSimStackOf: (in category 'bytecode generator support') ----- setMergeSimStackOf: fixup <var: #fixup type: #'BytecodeFixup *'> - self moveVolatileSimStackEntriesToRegisters. fixup mergeSimStack ifNil: [self assert: nextFixup <= numFixups. self cCode: [fixup mergeSimStack: mergeSimStacksBase + (nextFixup * self simStackSlots * (self sizeof: CogSimStackEntry))]. nextFixup := nextFixup + 1] ifNotNil: [self assert: fixup simStackPtr = simStackPtr. 0 to: simStackPtr do: [:i| self assert: ((self simStackAt: i) isSameEntryAs: (self addressOf: (fixup mergeSimStack at: i))). (self simStackAt: i) liveRegister ~= (self addressOf: (fixup mergeSimStack at: i)) liveRegister ifTrue: [(self simStackAt: i) liveRegister: NoReg]]]. fixup simStackPtr: simStackPtr. self cCode: [self mem: fixup mergeSimStack cp: simStack y: self simStackSlots * (self sizeof: CogSimStackEntry)] inSmalltalk: [fixup mergeSimStack: self copySimStack]!

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Re: [Vm-dev] [OpenSmalltalk/opensmalltalk-vm] Crashes while typing on macOS Sierra (#141)
by Tobias Pape 08 Feb '18

08 Feb '18

Closed #141 via ecd41af43d43ace633ccf2d53f3774161a793792. -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/141#event-14600246…

3 3

VM Maker: VMMaker.oscog-eem.2331.mcz
by commits＠source.squeak.org 08 Feb '18

08 Feb '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2331.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2331 Author: eem Time: 7 February 2018, 4:29:40.345022 pm UUID: d0e828c3-358c-4ff1-9762-3bcbe3306514 Ancestors: VMMaker.oscog-eem.2330 RegisterAllocatingCogit: Refactor to allow RegisterAllocatingCogit to deal with the push initial nils hack, i.e. move the two pass loop mechanism out of compileAbstractInstructionsFrom:through: into compileMethodBody & compileBlockBodies. Ensure a few loops using simSpillBase compyte a rahge that is between 0 and simStackPtr. Make several asserts use maybeCompilingFirstPassOfBlockWithInitialPushNil instead of open coding the expression. Execution appears to be correct until nextPutAll: is sent to a SmallInteger evaluating "aStream nextPutAll: (m < 10 ifTrue: [':0'] ifFalse: [':'])." in Time>>#print24:showSeconds:showSubseconds:on: =============== Diff against VMMaker.oscog-eem.2330 =============== Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileWith:spillOffset:onSpillOrUnspill: (in category 'compile abstract instructions') ----- reconcileWith: targetEntry spillOffset: spillOffset onSpillOrUnspill: spillOrUnspillBlock "Make the state of a targetEntry, a stack entry following a non-inlined special selector send, the same as the corresponding entry (the receiver) along the inlined path. spillOffset is zero for non-spill locations (self & temps), and the offset of the spill for volatile stack entries. spillOrUnspillBlock is a block evaluated with the target's registerOrNone if the receiver and target have different spilledness. Answer if the reconciliation merged a register; merged registers must be deassigned." <var: #targetEntry type: #'SimStackEntry *'> <inline: true> | targetReg mergedRegister | spilled = targetEntry spilled ifTrue: [self assert: ((self isSameEntryAs: targetEntry) or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). (targetReg := targetEntry registerOrNone) = NoReg ifTrue: [liveRegister := NoReg. ^false]. mergedRegister := false. type caseOf: { [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: [cogit MoveMw: offset r: register R: targetReg. mergedRegister := true]. targetEntry type caseOf: { [SSBaseOffset] -> [liveRegister := targetReg. (self isSameEntryAs: targetEntry) ifFalse: [type := SSSpill. offset := spillOffset]]. [SSSpill] -> [liveRegister := targetReg. type := SSSpill. offset := spillOffset]. [SSConstant] -> [liveRegister := targetReg. type := SSSpill. offset := spillOffset]. [SSRegister] -> [register := targetReg. type := SSRegister] }]. [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. liveRegister := targetReg. mergedRegister := true]. [SSConstant] -> [cogit genMoveConstant: constant R: targetReg. + type := SSRegister. register := targetReg. liveRegister := NoReg. - type := SSRegister. register := targetReg. mergedRegister := true]. [SSRegister] -> [targetReg ~= register ifTrue: [cogit MoveR: register R: targetReg. register := targetReg. mergedRegister := true]] }. ^mergedRegister]. targetReg := targetEntry registerOrNone. spillOrUnspillBlock value: targetReg. + (type = SSConstant + and: [targetEntry type ~= SSConstant or: [targetEntry constant ~= constant]]) ifTrue: + [type := SSSpill. offset := spillOffset. register := FPReg]. liveRegister ~= targetReg ifTrue: [liveRegister := NoReg]. ^false! Item was changed: ----- Method: RegisterAllocatingCogit>>compileAbstractInstructionsFrom:through: (in category 'compile abstract instructions') ----- compileAbstractInstructionsFrom: start through: end "Loop over bytecodes, dispatching to the generator for each bytecode, handling fixups in due course. + Override to recompile after a loop requiring a merge is detected." - Override to provide a development-time only escape for failed merges due to partially implemented - parallel move. Override to recompile after a loop requiring a merge is detected." - | result initialOpcodeIndex initialCounterIndex initialIndexOfIRC | - compilationPass := 1. scratchBytecodePC := nil. + ^super compileAbstractInstructionsFrom: start through: end! - initialOpcodeIndex := opcodeIndex. - initialCounterIndex := self maybeCounterIndex."for SistaCogit" - literalsManager saveForRecompile. - NewspeakVM ifTrue: - [initialIndexOfIRC := indexOfIRC]. - [recompileForLoopRegisterAssignments := false. - result := super compileAbstractInstructionsFrom: start through: end. - result = 0 and: [recompileForLoopRegisterAssignments]] - whileTrue: - [self assert: compilationPass <= 2. - self reinitializeAllButBackwardFixupsFrom: start through: end. - self resetSimStack: start. - self reinitializeOpcodesFrom: initialOpcodeIndex to: opcodeIndex - 1. - compilationPass := compilationPass + 1. - nextFixup := 0. - opcodeIndex := initialOpcodeIndex. - self maybeSetCounterIndex: initialCounterIndex. "For SistaCogit" - literalsManager resetForRecompile. - NewspeakVM ifTrue: - [indexOfIRC := initialIndexOfIRC]]. - ^result! Item was added: + ----- Method: RegisterAllocatingCogit>>compileBlockBodies (in category 'compile abstract instructions') ----- + compileBlockBodies + <inline: false> + | result compiledBlocksCount blockStart savedNeedsFrame savedNumArgs savedNumTemps + initialStackPtr initialOpcodeIndex initialIndexOfIRC initialCounterIndex | + <var: #blockStart type: #'BlockStart *'> + self assert: blockCount > 0. + "scanBlock: in compileBlockEntry: sets both of these appropriately for each block." + savedNeedsFrame := needsFrame. + savedNumArgs := methodOrBlockNumArgs. + savedNumTemps := methodOrBlockNumTemps. + inBlock := InVanillaBlock. + compiledBlocksCount := 0. + [compiledBlocksCount < blockCount] whileTrue: + [blockStart := self blockStartAt: compiledBlocksCount. + (result := self scanBlock: blockStart) < 0 ifTrue: [^result]. + compilationPass := 1. + scratchBytecodePC := nil. + initialOpcodeIndex := opcodeIndex. + initialCounterIndex := self maybeCounterIndex."for SistaCogit" + literalsManager saveForRecompile. + NewspeakVM ifTrue: + [initialIndexOfIRC := indexOfIRC]. + [recompileForLoopRegisterAssignments := false. + self compileBlockEntry: blockStart. + initialStackPtr := simStackPtr. + (result := self compileAbstractInstructionsFrom: blockStart startpc + (self pushNilSize: methodObj numInitialNils: blockStart numInitialNils) + through: blockStart startpc + blockStart span - 1) < 0 ifTrue: + [^result]. + "If the final simStackPtr is less than the initial simStackPtr then scanBlock: over- + estimated the number of initial nils (because it assumed one or more pushNils to + produce an operand were pushNils to initialize temps. This is very rare, so + compensate by checking, adjusting numInitialNils and recompiling the block body. + N.B. No need to reinitialize the literalsManager because it answers existing literals." + initialStackPtr ~= simStackPtr or: [recompileForLoopRegisterAssignments]] + whileTrue: + [self assert: (initialStackPtr > simStackPtr or: [deadCode]). + self assert: compilationPass = 1. + compilationPass := compilationPass + 1. "for asserts" + blockStart numInitialNils: blockStart numInitialNils + simStackPtr - initialStackPtr. + blockStart fakeHeader dependent: nil. + self reinitializeAllButBackwardFixupsFrom: blockStart startpc + blockStart numInitialNils through: blockStart startpc + blockStart span - 1. + nextFixup := 0. + self resetSimStack: blockStart startpc. + self reinitializeOpcodesFrom: initialOpcodeIndex to: opcodeIndex - 1. + opcodeIndex := initialOpcodeIndex. + self maybeSetCounterIndex: initialCounterIndex. "For SistaCogit" + literalsManager resetForRecompile. + NewspeakVM ifTrue: + [indexOfIRC := initialIndexOfIRC]]. + compiledBlocksCount := compiledBlocksCount + 1]. + needsFrame := savedNeedsFrame. + methodOrBlockNumArgs := savedNumArgs. + methodOrBlockNumTemps := savedNumTemps. + ^0! Item was added: + ----- Method: RegisterAllocatingCogit>>compileMethodBody (in category 'compile abstract instructions') ----- + compileMethodBody + "Compile the top-level method body." + <inline: true> + | result initialOpcodeIndex initialCounterIndex initialIndexOfIRC start | + endPC < initialPC ifTrue: [^0]. "quick primitives" + "When compiling, skip any initial CallPrimitive and optional StorePrimErrCode bytecodes. + These are dealt with in compileFrameBuild." + compilationPass := 1. + scratchBytecodePC := nil. + initialOpcodeIndex := opcodeIndex. + initialCounterIndex := self maybeCounterIndex."for SistaCogit" + literalsManager saveForRecompile. + NewspeakVM ifTrue: + [initialIndexOfIRC := indexOfIRC]. + [recompileForLoopRegisterAssignments := false. + start := initialPC + (self deltaToSkipPrimAndErrorStoreIn: methodObj header: methodHeader). + result := self compileAbstractInstructionsFrom: start through: endPC. + result = 0 + and: [recompileForLoopRegisterAssignments]] + whileTrue: + [self assert: compilationPass <= 2. + self reinitializeAllButBackwardFixupsFrom: start through: endPC. + self resetSimStack: start. + self reinitializeOpcodesFrom: initialOpcodeIndex to: opcodeIndex - 1. + compilationPass := compilationPass + 1. + nextFixup := 0. + opcodeIndex := initialOpcodeIndex. + self maybeSetCounterIndex: initialCounterIndex. "For SistaCogit" + literalsManager resetForRecompile. + NewspeakVM ifTrue: + [indexOfIRC := initialIndexOfIRC]]. + ^result! Item was changed: ----- Method: RegisterAllocatingCogit>>copySimStackToScratch: (in category 'bytecode generator support') ----- copySimStackToScratch: spillBase <inline: true> + self assert: (spillBase > methodOrBlockNumTemps + or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil and: [spillBase > methodOrBlockNumArgs]]). - self assert: spillBase > methodOrBlockNumTemps. scratchBytecodePC = bytecodePC ifTrue: [^self]. scratchBytecodePC := bytecodePC. self cCode: [self mem: scratchSimStack cp: simStack y: self simStackSlots * (self sizeof: CogSimStackEntry)] inSmalltalk: [0 to: simStackPtr do: [:i| scratchSimStack at: i put: (simStack at: i) copy]]. scratchSpillBase := spillBase! Item was changed: ----- Method: RegisterAllocatingCogit>>duplicateRegisterAssignmentsInTemporaries (in category 'debugging') ----- duplicateRegisterAssignmentsInTemporaries | liveRegisters | liveRegisters := 0. + 0 to: (methodOrBlockNumTemps min: (simStackPtr min: simSpillBase - 1)) do: "The min:s are for the initial push nil hack" + [:i| | current liveRegister | + liveRegister := (current := self simStackAt: i) liveRegister. - 0 to: methodOrBlockNumTemps do: - [:i| | liveRegister | - liveRegister := (self simStackAt: i) liveRegister. liveRegister ~= NoReg ifTrue: [(self register: liveRegister isInMask: liveRegisters) ifTrue: + ["Filter out pushed temps in first-pass vanilla blocks" + (self maybeCompilingFirstPassOfBlockWithInitialPushNil + and: [current type = SSBaseOffset + and: [current offset ~= (self frameOffsetOfTemporary: i - 1)]]) ifFalse: + [^true]]. + liveRegisters := liveRegisters bitOr: (self registerMaskFor: liveRegister)]]. - [^true]. - liveRegisters := liveRegisters bitOr: 1 << liveRegister]]. ^false! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup "At a merge point the cogit expects the stack to be in the same state as fixup's mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible." "self printSimStack; printSimStack: fixup mergeSimStack" "self simStackPrintString-> fixup simStackPrintString" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> | currentRegisters targetRegisters mergeSimStack current target spillOffset | (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. self assert: simStackPtr = fixup simStackPtr. currentRegisters := self liveRegistersFrom: 0 to: simStackPtr in: simStack. targetRegisters := self liveRegistersFrom: 0 to: simStackPtr in: mergeSimStack. self resolveConflicts: (currentRegisters bitAnd: targetRegisters) with: fixup mergeSimStack to: fixup simStackPtr. self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack). (self pushForMergeWith: mergeSimStack) ifTrue: [0 to: simStackPtr do: [:i| spillOffset := i > methodOrBlockNumTemps ifTrue: [self frameOffsetOfTemporary: i - 1] ifFalse: [0]. ((current := self simStack: simStack at: i) reconcileWith: (target := self simStack: mergeSimStack at: i) spillOffset: spillOffset onSpillOrUnspill: [:targetReg| self deny: current spilled. self assert: spillOffset ~= 0. current ensureSpilledAt: spillOffset from: FPReg]) ifTrue: [i > methodOrBlockNumTemps ifTrue: [self deassignRegister: current registerOrNone in: mergeSimStack. + self deassignRegister: current registerOrNone in: simStack. self deny: (self register: current registerOrNone isInMask: self liveRegistersInSelfAndTemps)]]]] ifFalse: [simStackPtr to: 0 by: -1 do: [:i| spillOffset := i > methodOrBlockNumTemps ifTrue: [self frameOffsetOfTemporary: i - 1] ifFalse: [0]. ((current := self simStack: simStack at: i) reconcileWith: (target := self simStack: mergeSimStack at: i) spillOffset: spillOffset onSpillOrUnspill: [:targetReg| self assert: current spilled. self assert: spillOffset ~= 0. targetReg ~= NoReg ifTrue: [self PopR: targetReg] ifFalse: [self AddCq: objectRepresentation wordSize R: SPReg]]) ifTrue: [i > methodOrBlockNumTemps ifTrue: [self deassignRegister: current registerOrNone in: mergeSimStack. + self deassignRegister: current registerOrNone in: simStack. self deny: (self register: current registerOrNone isInMask: self liveRegistersInSelfAndTemps)]]]]. self updateSimSpillBase! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeWithFixupIfRequired: (in category 'simulation stack') ----- mergeWithFixupIfRequired: fixup "If this bytecode has a fixup, some kind of merge needs to be done. There are 4 cases: 1) the bytecode has no fixup (fixup isNotAFixup) do nothing 2) the bytecode has a non merge fixup the fixup has needsNonMergeFixup. The code generating non merge fixup (currently only special selector code) is responsible for the merge so no need to do it. We set deadCode to false as the instruction can be reached from jumps. 3) the bytecode has a merge fixup, but execution flow *cannot* fall through to the merge point. the fixup has needsMergeFixup and deadCode = true. ignores the current simStack as it does not mean anything restores the simStack to the state the jumps to the merge point expects it to be. 4) the bytecode has a merge fixup and execution flow *can* fall through to the merge point. the fixup has needsMergeFixup and deadCode = false. Merge the state into the fixup's state via mergeCurrentSimStackWith:forwards:. In addition, if this is a backjump merge point, we patch the fixup to hold the current simStackPtr for later assertions. self printSimStack: fixup mergeSimStack" <var: #fixup type: #'BytecodeFixup *'> deadCode ifFalse: [self assertCorrectSimStackPtr]. "case 1" fixup notAFixup ifTrue: [^0]. "case 2" fixup isNonMergeFixup ifTrue: [deadCode ifTrue: [self deny: fixup simStackPtr isNil. simStackPtr := fixup simStackPtr. self restoreSimStackAtMergePoint: fixup. deadCode := false. self assertCorrectSimStackPtr] ifFalse: [self flushRegistersOnlyLiveOnFallThrough: fixup]. ^0]. "cases 3 and 4" self assert: fixup isMergeFixup. self traceMerge: fixup. deadCode ifTrue: "case 3" [simStackPtr := fixup simStackPtr. self restoreSimStackAtMergePoint: fixup. + deadCode := false] - deadCode := false.] ifFalse: "case 4" [(fixup isBackwardBranchFixup and: [compilationPass > 1]) ifTrue: [fixup simStackPtr: simStackPtr. self mergeCurrentSimStackWith: fixup. self copySimStackToFixup: fixup] ifFalse: [self mergeCurrentSimStackWith: fixup]]. "cases 3 and 4" fixup isBackwardBranchFixup ifTrue: [fixup mergeSimStack ifNil: [self assert: compilationPass = 1. self setMergeSimStackOf: fixup]]. fixup targetInstruction: self Label. self assertCorrectSimStackPtr. self assert: (self simStackMergeCompatibleWith: fixup). + "self simStackPrintString, fixup simStackPrintString" - "self simStackPrintString""fixup simStackPrintString" ^0! Item was changed: ----- Method: RegisterAllocatingCogit>>reinitializeAllButBackwardFixupsFrom:through: (in category 'compile abstract instructions') ----- reinitializeAllButBackwardFixupsFrom: start through: end "When a method must be recompiled due to moving a loop's register assignments to the head of a loop, backward fixups must be marked as such, and all but backward fixups must be reinitialized." - <inline: true> | descriptor nExts pc distance targetPC | <var: #descriptor type: #'BytecodeDescriptor *'> pc := start. nExts := 0. [pc <= end] whileTrue: [byte0 := (objectMemory fetchByte: pc ofObject: methodObj) + bytecodeSetOffset. descriptor := self generatorAt: byte0. (descriptor isBranch and: [self isBackwardBranch: descriptor at: pc exts: nExts in: methodObj]) ifTrue: [distance := self spanFor: descriptor at: pc exts: nExts in: methodObj. targetPC := pc + descriptor numBytes + distance. self initializeFixupAt: targetPC]. descriptor isBlockCreation ifTrue: [distance := self spanFor: descriptor at: pc exts: nExts in: methodObj. pc := pc + descriptor numBytes + distance] ifFalse: [pc := pc + descriptor numBytes]. nExts := descriptor isExtension ifTrue: [nExts + 1] ifFalse: [0]]. start to: end do: [:i| | fixup | fixup := self fixupAt: i. (fixup notAFixup or: [fixup isBackwardBranchFixup]) ifFalse: [fixup reinitialize]]! Item was changed: ----- Method: RegisterAllocatingCogit>>resetSimStack: (in category 'bytecode generator support') ----- resetSimStack: startPC <inline: true> simSpillBase := methodOrBlockNumTemps + 1. simStackPtr := methodOrBlockNumTemps. + 0 to: simStackPtr do: + [:i| + (self simStackAt: i) liveRegister: NoReg. + self cCode: '' inSmalltalk: [(self simStackAt: i) bcptr: startPC]]! - self flushLiveRegistersForSend. - self cCode: '' inSmalltalk: - [0 to: methodOrBlockNumTemps do: - [:i| - (self simStackAt: i) bcptr: startPC]]! Item was changed: ----- Method: RegisterAllocatingCogit>>restoreSimStackAtMergePoint: (in category 'simulation stack') ----- restoreSimStackAtMergePoint: fixup <inline: true> "All the execution paths reaching a merge point expect everything to be spilled on stack and the optStatus is unknown. If the merge point follows a return, it isn't a merge, but a skip past a return. If it is a real merge point then throw away all simStack optimization state." fixup mergeSimStack ifNotNil: [simSpillBase := methodOrBlockNumTemps + 1. 0 to: simStackPtr do: [:i| self cCode: [simStack at: i put: (fixup mergeSimStack at: i)] + inSmalltalk: [(simStack at: i) copyFrom: (fixup mergeSimStack at: i)]]. + self updateSimSpillBase]. - inSmalltalk: [(simStack at: i) copyFrom: (fixup mergeSimStack at: i)]]]. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>assertCorrectSimStackPtr (in category 'compile abstract instructions') ----- assertCorrectSimStackPtr <inline: true> "Would like to assert simply simSpillBase > methodOrBlockNumTemps but can't because of the initialNils hack for nested blocks in SqueakV3PlusClosures" self assert: (simSpillBase >= methodOrBlockNumTemps + or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil and: [simSpillBase > methodOrBlockNumArgs]]). - or: [inBlock = InVanillaBlock and: [simSpillBase >= 0]]). (needsFrame and: [simSpillBase > 0]) ifTrue: [self assert: (self simStackAt: simSpillBase - 1) spilled == true. self assert: (simSpillBase > simStackPtr or: [(self simStackAt: simSpillBase) spilled == false])]. self cCode: '' inSmalltalk: [deadCode ifFalse: [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) = (self debugStackPointerFor: bytecodePC)]].! Item was changed: ----- Method: StackToRegisterMappingCogit>>mergeWithFixupIfRequired: (in category 'simulation stack') ----- mergeWithFixupIfRequired: fixup "If this bytecode has a fixup, some kind of merge needs to be done. There are 4 cases: 1) the bytecode has no fixup (fixup isNotAFixup) do nothing 2) the bytecode has a non merge fixup the fixup has needsNonMergeFixup. The code generating non merge fixup (currently only special selector code) is responsible for the merge so no need to do it. We set deadCode to false as the instruction can be reached from jumps. 3) the bytecode has a merge fixup, but execution flow *cannot* fall through to the merge point. the fixup has needsMergeFixup and deadCode = true. ignores the current simStack as it does not mean anything restores the simStack to the state the jumps to the merge point expects it to be. 4) the bytecode has a merge fixup and execution flow *can* fall through to the merge point. the fixup has needsMergeFixup and deadCode = false. flushes the stack to the stack pointer so the fall through execution path simStack is in the state the merge point expects it to be. restores the simStack to the state the jumps to the merge point expects it to be. In addition, if this is a backjump merge point, we patch the fixup to hold the current simStackPtr for later assertions." <var: #fixup type: #'BytecodeFixup *'> self assertCorrectSimStackPtr. "case 1" fixup notAFixup ifTrue: [^0]. "case 2" fixup isNonMergeFixup ifTrue: [deadCode := false. ^0]. "cases 3 and 4" self assert: fixup isMergeFixup. self traceMerge: fixup. deadCode ifTrue: "case 3" ["Would like to assert fixup simStackPtr >= methodOrBlockNumTemps but can't because of the initialNils hack." self assert: (fixup simStackPtr >= methodOrBlockNumTemps + or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil]). - or: [inBlock = InVanillaBlock]). simStackPtr := fixup simStackPtr. LowcodeVM ifTrue: [simNativeStackPtr := fixup simNativeStackPtr. simNativeStackSize := fixup simNativeStackSize]] ifFalse: "case 4" [self ssFlushTo: simStackPtr]. "cases 3 and 4" deadCode := false. fixup isBackwardBranchFixup ifTrue: [fixup simStackPtr: simStackPtr. LowcodeVM ifTrue: [fixup simNativeStackPtr: simNativeStackPtr. fixup simNativeStackSize: simNativeStackSize]]. fixup targetInstruction: self Label. self assert: simStackPtr = fixup simStackPtr. LowcodeVM ifTrue: [self assert: simNativeStackPtr = fixup simNativeStackPtr. self assert: simNativeStackSize = fixup simNativeStackSize]. self cCode: '' inSmalltalk: [self assert: fixup simStackPtr = (self debugStackPointerFor: bytecodePC)]. self restoreSimStackAtMergePoint: fixup. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssAllocateCallReg:and:and: (in category 'simulation stack') ----- ssAllocateCallReg: requiredReg1 and: requiredReg2 and: requiredReg3 "Allocate registers needed in a run-time call (i.e. flush uses of the registers to the real stack). Since the run-time can smash any and all caller-saved registers also flush all caller-saved registers." + self ssAllocateRequiredRegMask: (CallerSavedRegisterMask bitOr: + (self registerMaskFor: requiredReg1 and: requiredReg2 and: requiredReg3)) - self ssAllocateRequiredRegMask: (CallerSavedRegisterMask - bitOr: ((self registerMaskFor: requiredReg1) - bitOr: ((self registerMaskFor: requiredReg2) - bitOr: (self registerMaskFor: requiredReg3)))) upThrough: simStackPtr! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssAllocateRequiredRegMask:upThrough:upThroughNative: (in category 'simulation stack') ----- ssAllocateRequiredRegMask: requiredRegsMask upThrough: stackPtr upThroughNative: nativeStackPtr | lastRequired lastRequiredNative liveRegs | lastRequired := -1. lastRequiredNative := -1. "compute live regs while noting the last occurrence of required regs. If these are not free we must spill from simSpillBase to last occurrence. Note we are conservative here; we could allocate FPReg in frameless methods." liveRegs := self registerMaskFor: FPReg and: SPReg. (simSpillBase max: 0) to: stackPtr do: [:i| liveRegs := liveRegs bitOr: (self simStackAt: i) registerMask. + ((self simStackAt: i) registerMask anyMask: requiredRegsMask) ifTrue: - ((self simStackAt: i) registerMask bitAnd: requiredRegsMask) ~= 0 ifTrue: [lastRequired := i]]. LowcodeVM ifTrue: [self assert: nativeStackPtr = simNativeStackPtr. (simNativeSpillBase max: 0) to: nativeStackPtr do: [:i| liveRegs := liveRegs bitOr: (self simNativeStackAt: i) nativeRegisterMask. ((self simNativeStackAt: i) nativeRegisterMask anyMask: requiredRegsMask) ifTrue: [lastRequiredNative := i]]]. "If any of requiredRegsMask are live we must spill." (liveRegs anyMask: requiredRegsMask) ifTrue: [self ssFlushTo: lastRequired. self deny: (self liveRegisters anyMask: requiredRegsMask)]! Item was changed: ----- Method: StackToRegisterMappingCogit>>ssFlushTo: (in category 'simulation stack') ----- ssFlushTo: index <inline: true> self assert: self tempsValidAndVolatileEntriesSpilled. LowcodeVM ifTrue: [self ssNativeFlushTo: simNativeStackPtr]. simSpillBase <= index ifTrue: + [((simSpillBase max: methodOrBlockNumTemps + 1) min: simStackPtr) to: index do: - [(simSpillBase max: methodOrBlockNumTemps + 1) to: index do: [:i| self assert: needsFrame. (self simStackAt: i) ensureSpilledAt: (self frameOffsetOfTemporary: i - 1) "frameOffsetOfTemporary: is 0-relative" from: FPReg]. simSpillBase := index + 1]! Item was changed: ----- Method: StackToRegisterMappingCogit>>updateSimSpillBase (in category 'simulation stack') ----- updateSimSpillBase "Something volatile has been pushed on the stack; update simSpillBase accordingly." <inline: true> self assert: ((simSpillBase > methodOrBlockNumTemps and: [simStackPtr >= methodOrBlockNumTemps]) + or: [self maybeCompilingFirstPassOfBlockWithInitialPushNil]). - or: [inBlock = InVanillaBlock and: [compilationPass = 1]]). simSpillBase > simStackPtr ifTrue: [simSpillBase := simStackPtr + 1. [simSpillBase - 1 > methodOrBlockNumTemps and: [(self simStackAt: simSpillBase - 1) spilled not]] whileTrue: [simSpillBase := simSpillBase - 1]] ifFalse: [[(self simStackAt: simSpillBase) spilled and: [simSpillBase <= simStackPtr]] whileTrue: [simSpillBase := simSpillBase + 1]]. methodOrBlockNumTemps + 1 to: (simSpillBase - 1 min: simStackPtr) do: [:i| self assert: (self simStackAt: i) spilled == true]!

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[OpenSmalltalk/opensmalltalk-vm] 997e64: Mac OS X: Eliminate compiler warnings for the prin...
by GitHub 07 Feb '18

07 Feb '18

Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 997e64442453a6945ae531d4220b3a288364f14e https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/997e64442453a6945a… Author: Eliot Miranda <eliot.miranda(a)gmail.com> Date: 2018-02-07 (Wed, 07 Feb 2018) Changed paths: M platforms/iOS/vm/Common/Classes/sqSqueakMainApp.m Log Message: ----------- Mac OS X: Eliminate compiler warnings for the printf that dumps the registers on a crash.

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[OpenSmalltalk/opensmalltalk-vm] Re-enable code signing on macOS for Pharo (#207)
by Fabio Niephaus 06 Feb '18

06 Feb '18

-- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/207

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[OpenSmalltalk/opensmalltalk-vm] pharo.cog.spur configure error: C compiler cannot generate executables (#211)
by Javier Pimas 06 Feb '18

06 Feb '18

When building for linux32x86 on ubuntu17.04/64-bits. I _do_ have a cross compiler and can generate 32bit binaries with -m32 --- [...]/opensmalltalk-vm/spursrc [...]/opensmalltalk-vm/src/plugins checking sanity of generated src directory... okay checking build system type... i686-pc-linux-gnu checking host system type... i686-pc-linux-gnu checking target system type... i686-pc-linux-gnu Configuring Squeak (.-) for i686-pc-linux-gnu checking whether make sets $(MAKE)... yes checking for gcc... gcc -m32 checking for C compiler default output file name... configure: error: C compiler cannot create executables -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/211

3 3

VM Maker: VMMaker.oscog-eem.2330.mcz
by commits＠source.squeak.org 06 Feb '18

06 Feb '18

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2330.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.2330 Author: eem Time: 6 February 2018, 11:44:42.955827 am UUID: 90c31ff5-bcbb-46e4-b6ca-e14c79d71d80 Ancestors: VMMaker.oscog-eem.2329 RegisterAllocatingCogit: Refactor reconcilePushingWith: & reconcilePoppingWith: into reconcileWith:spillOffset:onSpillOrUnspill:. Delete several now obsolete methods. Fix a slip in attemptToComputeTempNamesFor: =============== Diff against VMMaker.oscog-eem.2329 =============== Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>ensureSpilledAt:from: (in category 'compile abstract instructions') ----- ensureSpilledAt: baseOffset from: baseRegister spilled ifTrue: [type = SSSpill ifTrue: [self assert: ((offset = baseOffset and: [register = baseRegister]) or: [cogit violatesEnsureSpilledSpillAssert]). liveRegister := NoReg. ^self]]. self assert: type ~= SSSpill. cogit traceSpill: self. "N.B. Keep the type of SSConstant spills as SSConstant so that when joins occur as a result of expressions with constants on the stack, the constant on stack can be recovered. e.g. as in self at: 1 put: (self foo ifTrue: [self bar] ifFalse: [self baz])." type = SSConstant ifTrue: + [liveRegister = NoReg + ifTrue: [cogit genPushConstant: constant] + ifFalse: [cogit PushR: liveRegister]] - [cogit genPushConstant: constant] ifFalse: [type = SSBaseOffset ifTrue: [liveRegister = NoReg ifTrue: [cogit MoveMw: offset r: register R: TempReg. cogit PushR: TempReg] ifFalse: [cogit PushR: liveRegister]] ifFalse: [self assert: type = SSRegister. cogit PushR: register]. type := SSSpill]. liveRegister := NoReg. spilled := true. offset := baseOffset. register := baseRegister! Item was changed: ----- Method: CogRegisterAllocatingSimStackEntry>>popToReg: (in category 'compile abstract instructions') ----- popToReg: reg liveRegister ~= NoReg ifTrue: [self deny: (type = SSRegister and: [register ~= liveRegister and: [cogit needsFrame]]). spilled ifTrue: "This is rare, and in some cases it isn't even needed (e.g. frameful return) but we can't tell as yet." [cogit AddCq: objectRepresentation wordSize R: SPReg]. reg ~= liveRegister ifTrue: [cogit MoveR: liveRegister R: reg] ifFalse: [cogit Label]] ifFalse: [spilled ifTrue: [cogit PopR: reg] ifFalse: [type caseOf: { [SSBaseOffset] -> [cogit MoveMw: offset r: register R: reg]. + [SSSpill] -> [cogit MoveMw: offset r: register R: reg]. [SSConstant] -> [cogit genMoveConstant: constant R: reg]. [SSRegister] -> [reg ~= register ifTrue: [cogit MoveR: register R: reg] ifFalse: [cogit Label]] }]]. (reg ~= TempReg and: [liveRegister = NoReg and: [type ~= SSRegister]]) ifTrue: [liveRegister := reg. cogit copyLiveRegisterToCopiesOf: self]! Item was removed: - ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileBackwardsWith: (in category 'compile abstract instructions') ----- - reconcileBackwardsWith: targetEntry - "Make the state of the receiver, a stack entry at a backward jump, - the same as the corresponding simStackEntry at the target of the jump" - <var: #targetEntry type: #'SimStackEntry *'> - | targetReg | - (targetReg := targetEntry registerOrNone) = NoReg ifTrue: - [^self]. - targetEntry type = SSConstant ifTrue: - [self assert: (type = SSConstant and: [constant = targetEntry constant]). - ^self]. - liveRegister ~= NoReg ifTrue: - [liveRegister ~= targetReg ifTrue: - [cogit MoveR: liveRegister R: targetReg]. - ^self]. - type caseOf: { - [SSBaseOffset] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSConstant] -> [cogit genMoveConstant: constant R: targetReg]. - [SSRegister] -> [register ~= targetReg ifTrue: - [cogit MoveR: register R: targetReg]] }! Item was removed: - ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileForwardsWith: (in category 'compile abstract instructions') ----- - reconcileForwardsWith: targetEntry - "Make the state of the receiver, a stack entry at the end of a basic block, - the same as the corresponding simStackEntry at the target of a preceding - jump to the beginning of the next basic block. Make sure targetEntry - reflects the state of the merged simStack; it will be installed as the current - entry by restoreSimStackAtMergePoint: in mergeWithFixupIfRequired:. - - Answer if the liveRegister for the targetEntry (if any) should be deassigned; - this is because if merging a non-temp with a temp that has a live register we - can assign to the register, but must unassign the register from the temp, - otherwise the temp will acquire the merged value without an assignment." - <var: #targetEntry type: #'SimStackEntry *'> - | targetReg | - (targetReg := targetEntry registerOrNone) = NoReg ifTrue: - [| reg | - self assert: targetEntry spilled. - (self isSameEntryAs: targetEntry) ifTrue: - [self assert: spilled. - ^false]. - (reg := self registerOrNone) = NoReg ifTrue: [reg := TempReg]. - self storeToReg: reg. - spilled - ifTrue: [cogit MoveR: reg Mw: targetEntry offset r: targetEntry register] - ifFalse: [cogit PushR: reg]. - ^false]. - liveRegister ~= NoReg ifTrue: - [liveRegister ~= targetReg ifTrue: - [cogit MoveR: liveRegister R: targetReg]. - (spilled and: [targetEntry spilled not]) ifTrue: - [cogit AddCq: objectRepresentation wordSize R: SPReg]. - ^false]. - spilled - ifTrue: - [targetEntry spilled ifFalse: - [cogit PopR: targetReg. "KISS; generate the least number of instructions..." - ^false]] - ifFalse: - [targetEntry spilled ifTrue: - [cogit SubCq: objectRepresentation wordSize R: SPReg]]. - type caseOf: { - [SSBaseOffset] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg]. - [SSConstant] -> [cogit genMoveConstant: constant R: targetReg]. - [SSRegister] -> [register ~= targetReg ifTrue: - [cogit MoveR: register R: targetReg]] }. - (targetEntry type = SSConstant - and: [type ~= SSConstant or: [constant ~= targetEntry constant]]) ifTrue: - [targetEntry - register: targetReg; - type: SSRegister]. - "If merging a constant with a constant assigned to a register, then the register must be deassigned from any temps." - ^targetEntry type = SSConstant - "If merging a non-temp with a temp that has a live register we can assign - to the register, but must unassign the register from the temp, otherwise - the temp will acquire the merged value without an assignment." - or: [targetEntry isFrameTempVar and: [(self isSameEntryAs: targetEntry) not]]! Item was removed: - ----- Method: CogRegisterAllocatingSimStackEntry>>reconcilePoppingWith: (in category 'compile abstract instructions') ----- - reconcilePoppingWith: targetEntry - "Make the state of a targetEntry, a stack entry following a non-inlined special selector - send, the same as the corresponding entry (the receiver) along the inlined path." - <var: #targetEntry type: #'SimStackEntry *'> - | targetReg | - spilled = targetEntry spilled ifTrue: - [self assert: ((self isSameEntryAs: targetEntry) - or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) - or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). - (targetReg := targetEntry registerOrNone) = NoReg ifTrue: - [liveRegister := NoReg. - ^self]. - type caseOf: { - [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: - [cogit MoveMw: offset r: register R: targetReg]. - targetEntry type caseOf: { - [SSBaseOffset] -> [liveRegister := targetReg. - (self isSameEntryAs: targetEntry) ifFalse: - [type := SSSpill]]. - [SSSpill] -> [liveRegister := targetReg. type := SSSpill]. - [SSConstant] -> [liveRegister := targetReg. type := SSSpill]. - [SSRegister] -> [register := targetReg. type := SSRegister] }]. - [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. - liveRegister := targetReg]. - [SSConstant] -> [cogit genMoveConstant: constant R: targetReg. - type := SSRegister. register := targetReg]. - [SSRegister] -> [targetReg ~= register ifTrue: - [cogit MoveR: register R: targetReg. - register := targetReg]] }. - ^self]. - self assert: spilled. - (targetReg := targetEntry registerOrNone) ~= NoReg - ifTrue: [cogit PopR: targetReg] - ifFalse: [cogit AddCq: objectRepresentation wordSize R: SPReg]. - liveRegister ~= targetReg ifTrue: - [liveRegister := NoReg]! Item was removed: - ----- Method: CogRegisterAllocatingSimStackEntry>>reconcilePushingWith: (in category 'compile abstract instructions') ----- - reconcilePushingWith: targetEntry - "Make the state of the receiver, a stack entry at the end of a basic block, - the same as the corresponding simStackEntry at the target of a preceding - jump to the beginning of the next basic block. Make sure targetEntry - reflects the state of the merged simStack; it will be installed as the current - entry by restoreSimStackAtMergePoint: in mergeWithFixupIfRequired:." - <var: #targetEntry type: #'SimStackEntry *'> - | targetReg | - spilled = targetEntry spilled ifTrue: - [self assert: ((self isSameEntryAs: targetEntry) - or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) - or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). - (targetReg := targetEntry registerOrNone) = NoReg ifTrue: - [liveRegister := NoReg. - ^self]. - type caseOf: { - [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: - [cogit MoveMw: offset r: register R: targetReg]. - targetEntry type caseOf: { - [SSBaseOffset] -> [liveRegister := targetReg. - (self isSameEntryAs: targetEntry) ifFalse: - [type := SSSpill]]. - [SSSpill] -> [liveRegister := targetReg. type := SSSpill]. - [SSConstant] -> [liveRegister := targetReg. type := SSSpill]. - [SSRegister] -> [register := targetReg. type := SSRegister] }]. - [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. - liveRegister := targetReg]. - [SSConstant] -> [cogit genMoveConstant: constant R: targetReg. - type := SSRegister. register := targetReg]. - [SSRegister] -> [targetReg ~= register ifTrue: - [cogit MoveR: register R: targetReg. - register := targetReg]] }. - ^self]. - self assert: spilled. - (targetReg := targetEntry registerOrNone) ~= NoReg - ifTrue: [cogit PopR: targetReg] - ifFalse: [cogit AddCq: objectRepresentation wordSize R: SPReg]. - liveRegister ~= targetReg ifTrue: - [liveRegister := NoReg]! Item was added: + ----- Method: CogRegisterAllocatingSimStackEntry>>reconcileWith:spillOffset:onSpillOrUnspill: (in category 'compile abstract instructions') ----- + reconcileWith: targetEntry spillOffset: spillOffset onSpillOrUnspill: spillOrUnspillBlock + "Make the state of a targetEntry, a stack entry following a non-inlined special selector + send, the same as the corresponding entry (the receiver) along the inlined path. + spillOffset is zero for non-spill locations (self & temps), and the offset of the spill for + volatile stack entries. spillOrUnspillBlock is a block evaluated with the target's + registerOrNone if the receiver and target have different spilledness. + Answer if the reconciliation merged a register; merged registers must be deassigned." + <var: #targetEntry type: #'SimStackEntry *'> + <inline: true> + | targetReg mergedRegister | + spilled = targetEntry spilled ifTrue: + [self assert: ((self isSameEntryAs: targetEntry) + or: [(targetEntry spilled not and: [targetEntry registerOrNone ~= NoReg]) + or: [spilled and: [type = SSConstant and: [offset = targetEntry offset]]]]). + (targetReg := targetEntry registerOrNone) = NoReg ifTrue: + [liveRegister := NoReg. + ^false]. + mergedRegister := false. + type caseOf: { + [SSBaseOffset] -> [liveRegister ~= targetReg ifTrue: + [cogit MoveMw: offset r: register R: targetReg. + mergedRegister := true]. + targetEntry type caseOf: { + [SSBaseOffset] -> [liveRegister := targetReg. + (self isSameEntryAs: targetEntry) ifFalse: + [type := SSSpill. + offset := spillOffset]]. + [SSSpill] -> [liveRegister := targetReg. type := SSSpill. + offset := spillOffset]. + [SSConstant] -> [liveRegister := targetReg. type := SSSpill. + offset := spillOffset]. + [SSRegister] -> [register := targetReg. type := SSRegister] }]. + [SSSpill] -> [cogit MoveMw: offset r: register R: targetReg. + liveRegister := targetReg. + mergedRegister := true]. + [SSConstant] -> [cogit genMoveConstant: constant R: targetReg. + type := SSRegister. register := targetReg. + mergedRegister := true]. + [SSRegister] -> [targetReg ~= register ifTrue: + [cogit MoveR: register R: targetReg. + register := targetReg. + mergedRegister := true]] }. + ^mergedRegister]. + targetReg := targetEntry registerOrNone. + spillOrUnspillBlock value: targetReg. + liveRegister ~= targetReg ifTrue: + [liveRegister := NoReg]. + ^false! Item was changed: ----- Method: Cogit class>>attemptToComputeTempNamesFor: (in category 'in-image compilation support') ----- attemptToComputeTempNamesFor: aCompiledMethod (aCompiledMethod respondsTo: #tempNames) ifTrue: [| blocks | blocks := aCompiledMethod embeddedBlockClosures. initializationOptions at: #tempNames put: (Dictionary withAll: {aCompiledMethod initialPC -> ([aCompiledMethod tempNames] on: MessageNotUnderstood do: [:ex| (self isSistaMessage: ex message unimplementedIn: Decompiler) ifTrue: [^self]. (Smalltalk classNamed: #AssemblerAbsentClassImport) ifNotNil: [:aaciClass| (ex receiver isKindOf: aaciClass) ifTrue: [^self]]. ex pass])}, (blocks ifEmpty: [#()] ifNotEmpty: [aCompiledMethod embeddedBlockClosures with: ((aCompiledMethod methodNode schematicTempNamesString allButFirst: (aCompiledMethod methodNode schematicTempNamesString indexOf: $[)) piecesCutWhere: [:a :b| b = $[]) + collect: [:c :s| c startpc -> (s substrings collect: [:ea| ea copyWithout: $] ])]]))]! - collect: [:c :s| c startpc -> s substrings]]))]! Item was changed: ----- Method: Cogit>>promptForBreakPC (in category 'simulation only') ----- promptForBreakPC <doNotGenerate> | s first pc | + s := UIManager default request: 'Break pc (hex, + to add, - to remove)'. - s := UIManager default request: 'Break pc (hex)'. s := s withBlanksTrimmed. s isEmpty ifTrue: [^self]. ('+-' includes: s first) ifTrue: [first := s first. s := s allButFirst]. (s isEmpty and: [first = $-]) ifTrue: [^self breakPC: nil]. pc := (s includes: $r) ifTrue: [Number readFrom: s readStream] ifFalse: [(#('0x' '-0x') detect: [:prefix| s beginsWith: prefix] ifNone: []) ifNotNil: [:prefix| s := s allButFirst: prefix size. prefix first = $- ifTrue: [s := '-', s]]. Integer readFrom: s readStream base: 16]. first = $+ ifTrue: [^self breakPC: (breakPC addBreakpoint: pc)]. first = $- ifTrue: [^self breakPC: (breakPC removeBreakpoint: pc)]. self breakPC: pc! Item was added: + ----- Method: RegisterAllocatingCogit>>deassignRegister:in: (in category 'bytecode generator support') ----- + deassignRegister: register in: aSimStack + "When a merge has assigned a register to a volatile stack entry + deassign that register from any temporaries." + self assert: register ~= NoReg. + 0 to: methodOrBlockNumTemps do: + [:i| + (self simStack: aSimStack at: i) liveRegister = register ifTrue: + [(self simStack: aSimStack at: i) liveRegister: NoReg]]! Item was removed: - ----- Method: RegisterAllocatingCogit>>deassignRegisterForTempVar:in: (in category 'bytecode generator support') ----- - deassignRegisterForTempVar: targetEntry in: mergeSimStack - "If merging a non-temp with a temp that has a live register we can assign - to the register, but must unassign the register from the temp, otherwise - the temp will acquire the merged value without an assignment. The targetEntry - must also be transmogrified into an SSRegister entry, which is done in the caller." - <var: #targetEntry type: #'SimStackEntry *'> - <var: #duplicateEntry type: #'SimStackEntry *'> - <var: #mergeSimStack type: #'SimStackEntry *'> - <inline: true> - | reg | - self halt. "Clément and I hope this shouldn't happen as of the new merge code in reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn:" - reg := targetEntry liveRegister. - self assert: (reg ~= NoReg and: [targetEntry type = SSConstant or: [targetEntry isFrameTempVar]]). - targetEntry type = SSConstant - ifTrue: - [simStackPtr to: 1 by: -1 do: - [:j| | duplicateEntry | - duplicateEntry := self simStack: mergeSimStack at: j. - (duplicateEntry registerOrNone = reg - and: [duplicateEntry type = SSBaseOffset or: [duplicateEntry type = SSSpill]]) ifTrue: - [duplicateEntry liveRegister: NoReg]]] - ifFalse: - [simStackPtr to: 1 by: -1 do: - [:j| | duplicateEntry | - duplicateEntry := self simStack: mergeSimStack at: j. - (targetEntry isSameEntryAs: duplicateEntry) ifTrue: - [j <= methodOrBlockNumTemps - ifTrue: [duplicateEntry liveRegister: NoReg] - ifFalse: [duplicateEntry type: SSRegister; register: reg]]]]! Item was changed: ----- Method: RegisterAllocatingCogit>>ensureFixupAt: (in category 'bytecode generator support') ----- ensureFixupAt: targetPC "Make sure there's a flagged fixup at the target pc in fixups. Initially a fixup's target is just a flag. Later on it is replaced with a proper instruction. Override to generate stack merging code if required." | fixup | <var: #fixup type: #'BytecodeFixup *'> self assert: targetPC > bytecodePC. + self cCode: '' inSmalltalk: + [self assert: simStackPtr + (needsFrame ifTrue: [0] ifFalse: [1]) + = (self debugStackPointerFor: targetPC)]. fixup := self fixupAt: targetPC. "If a non-merge fixup has already been defined then where-ever that was done didn't realise there needed to be a merge and forgot to save the stack state for that merge." self deny: fixup isNonMergeFixup. fixup needsFixup ifTrue: [fixup mergeSimStack ifNil: [self setMergeSimStackOf: fixup] ifNotNil: [self copySimStackToScratch: simSpillBase. + self mergeCurrentSimStackWith: fixup. - self mergeCurrentSimStackWith: fixup forwards: true. self restoreSimStackFromScratch]] ifFalse: [self assert: (fixup mergeSimStack isNil or: [compilationPass = 2]). fixup mergeSimStack ifNil: [self setMergeSimStackOf: fixup] ifNotNil: [self moveVolatileSimStackEntriesToRegisters. self assert: (self simStack: simStack isIdenticalTo: fixup mergeSimStack)]]. ^super ensureFixupAt: targetPC! Item was removed: - ----- Method: RegisterAllocatingCogit>>initOptStatus: (in category 'simulation stack') ----- - initOptStatus: receiverResultRegLive - <inline: true>! Item was added: + ----- Method: RegisterAllocatingCogit>>liveRegistersInSelfAndTemps (in category 'debugging') ----- + liveRegistersInSelfAndTemps + ^self liveRegistersFrom: 0 to: methodOrBlockNumTemps in: simStack! Item was changed: ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith: (in category 'bytecode generator support') ----- mergeCurrentSimStackWith: fixup "At a merge point the cogit expects the stack to be in the same state as fixup's mergeSimStack. mergeSimStack is the state as of some jump forward or backward to this point. So make simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). Values may have to be assigned to registers. Registers may have to be swapped. Generate code to merge the current simStack with that of the target fixup, the goal being to keep as many registers live as possible." "self printSimStack; printSimStack: fixup mergeSimStack" "self simStackPrintString-> fixup simStackPrintString" "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" <var: #fixup type: #'BytecodeFixup *'> + | currentRegisters targetRegisters mergeSimStack current target spillOffset | - | currentRegisters targetRegisters mergeSimStack current target | (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. self assert: simStackPtr = fixup simStackPtr. currentRegisters := self liveRegistersFrom: 0 to: simStackPtr in: simStack. targetRegisters := self liveRegistersFrom: 0 to: simStackPtr in: mergeSimStack. self resolveConflicts: (currentRegisters bitAnd: targetRegisters) with: fixup mergeSimStack to: fixup simStackPtr. self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack). - "if we simply compare spill bases it is trivial here to decide whether to push or pop. - Otherwise we have to determine the spill base in fixup's mergeSimStack." (self pushForMergeWith: mergeSimStack) ifTrue: [0 to: simStackPtr do: [:i| + spillOffset := i > methodOrBlockNumTemps + ifTrue: [self frameOffsetOfTemporary: i - 1] + ifFalse: [0]. + ((current := self simStack: simStack at: i) + reconcileWith: (target := self simStack: mergeSimStack at: i) + spillOffset: spillOffset + onSpillOrUnspill: + [:targetReg| + self deny: current spilled. + self assert: spillOffset ~= 0. + current ensureSpilledAt: spillOffset from: FPReg]) ifTrue: + [i > methodOrBlockNumTemps ifTrue: + [self deassignRegister: current registerOrNone in: mergeSimStack. + self deny: (self register: current registerOrNone + isInMask: self liveRegistersInSelfAndTemps)]]]] - current := self simStack: simStack at: i. - target := self simStack: mergeSimStack at: i. - current reconcilePushingWith: target]] ifFalse: [simStackPtr to: 0 by: -1 do: [:i| + spillOffset := i > methodOrBlockNumTemps + ifTrue: [self frameOffsetOfTemporary: i - 1] + ifFalse: [0]. + ((current := self simStack: simStack at: i) + reconcileWith: (target := self simStack: mergeSimStack at: i) + spillOffset: spillOffset + onSpillOrUnspill: + [:targetReg| + self assert: current spilled. + self assert: spillOffset ~= 0. + targetReg ~= NoReg + ifTrue: [self PopR: targetReg] + ifFalse: [self AddCq: objectRepresentation wordSize R: SPReg]]) ifTrue: + [i > methodOrBlockNumTemps ifTrue: + [self deassignRegister: current registerOrNone in: mergeSimStack. + self deny: (self register: current registerOrNone + isInMask: self liveRegistersInSelfAndTemps)]]]]. + self updateSimSpillBase! - current := self simStack: simStack at: i. - target := self simStack: mergeSimStack at: i. - current reconcilePoppingWith: target]]. - self assertCorrectSimStackPtr! Item was removed: - ----- Method: RegisterAllocatingCogit>>mergeCurrentSimStackWith:forwards: (in category 'bytecode generator support') ----- - mergeCurrentSimStackWith: fixup forwards: forwards - "At a merge point the cogit expects the stack to be in the same state as mergeSimStack. - mergeSimStack is the state as of some jump forward or backward to this point. So make - simStack agree with mergeSimStack (it is, um, problematic to plant code at the jump). - Values may have to be assigned to registers. Registers may have to be swapped. - The state of optStatus must agree. - Generate code to merge the current simStack with that of the target fixup, - the goal being to keep as many registers live as possible. If the merge is forwards - registers can be deassigned (since registers are always written to temp vars). - But if backwards, nothing can be deassigned, and the state /must/ reflect the target." - "self printSimStack; printSimStack: fixup mergeSimStack" - "abstractOpcodes object copyFrom: startIndex to: opcodeIndex" - <var: #fixup type: #'BytecodeFixup *'> - | startIndex mergeSimStack | - <var: #mergeSimStack type: #'SimStackEntry *'> - <var: #targetEntry type: #'SimStackEntry *'> - <var: #currentEntry type: #'SimStackEntry *'> - (mergeSimStack := fixup mergeSimStack) ifNil: [^self]. - startIndex := opcodeIndex. "for debugging" - "Assignments amongst the registers must be made in order to avoid overwriting. - If necessary exchange registers amongst simStack's entries to resolve any conflicts." - self reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn: mergeSimStack. - (self asserta: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack)) ifFalse: - [Notification new tag: #failedMerge; signal]. - (self pushForMergeWith: mergeSimStack) - ifTrue: - [methodOrBlockNumTemps + 1 to: simStackPtr do: - [:i| self mergePushingWithEntryInTargetSimStack: mergeSimStack at: i]] - ifFalse: - [simStackPtr to: methodOrBlockNumTemps + 1 by: -1 do: - [:i| self mergePoppingWithEntryInTargetSimStack: mergeSimStack at: i]]. - "Still haven't handled simSpillBase." - self assert: (simSpillBase > simStackPtr - or: [simSpillBase > methodOrBlockNumTemps - and: [(self simStack: mergeSimStack at: simSpillBase - 1) spilled]])! Item was removed: - ----- Method: RegisterAllocatingCogit>>mergePoppingWithEntryInTargetSimStack:at: (in category 'bytecode generator support') ----- - mergePoppingWithEntryInTargetSimStack: mergeSimStack at: i - "Merge an intermediate result on currentSimStack with the corresponding one in target's mergeSimStack. - Depending on spilledness, the stack may need to be pushed or popped, or simply a register assignment made." - | currentEntry targetEntry | - <inline: true> - currentEntry := self simStack: simStack at: i. - targetEntry := self simStack: mergeSimStack at: i. - currentEntry reconcilePoppingWith: targetEntry. - "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: - spilled ifFalse: - [simSpillBase := i - 1]. - simStack - at: i - put: (self - cCode: [mergeSimStack at: i] - inSmalltalk: [(mergeSimStack at: i) copy])"! Item was removed: - ----- Method: RegisterAllocatingCogit>>mergePushingWithEntryInTargetSimStack:at: (in category 'bytecode generator support') ----- - mergePushingWithEntryInTargetSimStack: mergeSimStack at: i - "Merge an intermediate result on currentSimStack with the corresponding one in target's mergeSimStack. - Depending on spilledness, the stack may need to be pushed or popped, or simply a register assignment made." - | currentEntry targetEntry | - <inline: true> - currentEntry := self simStack: simStack at: i. - targetEntry := self simStack: mergeSimStack at: i. - (currentEntry reconcilePushingWith: targetEntry) ifTrue: - [self assert: i > methodOrBlockNumTemps. - self deassignRegisterForTempVar: targetEntry in: mergeSimStack. - targetEntry - type: SSRegister; - register: targetEntry liveRegister]. - "Note, we could update the simStack and spillBase here but that is done in restoreSimStackAtMergePoint: - spilled ifFalse: - [simSpillBase := i - 1]. - simStack - at: i - put: (self - cCode: [mergeSimStack at: i] - inSmalltalk: [(mergeSimStack at: i) copy])"! Item was changed: ----- Method: RegisterAllocatingCogit>>reconcileRegisterStateForJoinAfterSpecialSelectorSend (in category 'bytecode generator support') ----- reconcileRegisterStateForJoinAfterSpecialSelectorSend "When the control flow from the inlined special selector code (e.g. add or comparison) joins the control flow from the send, taken when the inlined code fails, we should decide whether to reload any registers known to contain useful values or mark them as dead." "Restore the simStack to that in scratchSimStack, popping any spilled state back into allocated registers." + | current spillOffset target | simSpillBase := scratchSpillBase. simStackPtr to: 0 by: -1 do: [:i| + spillOffset := i > methodOrBlockNumTemps + ifTrue: [self frameOffsetOfTemporary: i - 1] + ifFalse: [0]. + (current := self simStack: simStack at: i) + reconcileWith: (target := self simStack: scratchSimStack at: i) + spillOffset: spillOffset + onSpillOrUnspill: + [:targetReg| + self assert: current spilled. + self assert: spillOffset ~= 0. + targetReg ~= NoReg + ifTrue: [self PopR: targetReg] + ifFalse: [self AddCq: objectRepresentation wordSize R: SPReg]]. - self assert: (i = simStackPtr - ifTrue: [(self simStackAt: i) type = SSRegister] - ifFalse: [(self simStackAt: i) spilled]). - (self simStackAt: i) reconcilePoppingWith: (self simStack: scratchSimStack at: i). simStack at: i put: (self cCode: [scratchSimStack at: i] inSmalltalk: [(scratchSimStack at: i) copy])]! Item was removed: - ----- Method: RegisterAllocatingCogit>>reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn: (in category 'bytecode generator support') ----- - reconcileRegistersInTempVarsInCurrentSimStackWithThoseIn: mergeSimStack - <var: #mergeSimStack type: #'SimStackEntry *'> - 0 to: methodOrBlockNumTemps do: - [ :i | | current target | - current := self simStack: simStack at: i. - target := self simStack: mergeSimStack at: i. - target registerMaskOrNone ~= 0 - ifTrue: - [ target registerMaskOrNone ~= current registerMaskOrNone ifTrue: - [ self swap: target with: current at: i]] - ifFalse: [current liveRegister: NoReg]]. - ^0! Item was removed: - ----- Method: RegisterAllocatingCogit>>swap:with:at: (in category 'bytecode generator support') ----- - swap: target with: current at: index - "Swaps the registers between target and current. - target is guaranteed to be in a register. Current is not. - If current is in a register, just perform a register swap and update the simStack. - If current is not in a register, free the target register and use it. - Invariant: - items in current's simStack up to index have been resolved with target because we are visiting the stack in order 0 to siumStackPtr. - Strategy: - since the target simStack is valid (it has a unique disposition of temps) we can - spill to obtain registers (since once an entry is written to ther stack its register, if any, can be freed) - pop to assign after fully spilling (if necessary)" - | currentLiveRegisters | - self assert: target registerMaskOrNone ~= 0. - current registerMaskOrNone ~= 0 ifTrue: - [ self SwapR: target liveRegister R: current liveRegister Scratch: RISCTempReg. - methodOrBlockNumTemps + 1 to: simStackPtr do: - [:i| | localCurrent | - localCurrent := self simStack: simStack at: i. - localCurrent liveRegister = current liveRegister - ifTrue: [ localCurrent liveRegister: target liveRegister ] - ifFalse: [ localCurrent liveRegister = target liveRegister - ifTrue: [ localCurrent liveRegister: current liveRegister ] ] ]. - current liveRegister: target liveRegister. - ^ 0 ]. - 0 to: index - 1 do: [:j | self assert: (self simStack: simStack at: j) liveRegister ~= target liveRegister]. - - currentLiveRegisters := self liveRegistersExceptingTopNItems: 0 in: simStack. - (self register: target liveRegister isInMask: currentLiveRegisters) ifTrue: - [self ssAllocateRequiredReg: target liveRegister]. - "Now target liveRegister is available. we set it." - current storeToReg: target liveRegister. - ^0!

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[OpenSmalltalk/opensmalltalk-vm] 201802061430
by Fabio Niephaus 06 Feb '18

06 Feb '18

-- You are receiving this because you are subscribed to this thread. View it on GitHub: https://github.com/OpenSmalltalk/opensmalltalk-vm/releases/tag/201802061430

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[OpenSmalltalk/opensmalltalk-vm]
by GitHub 06 Feb '18

06 Feb '18

Branch: refs/tags/201802061430 Home: https://github.com/OpenSmalltalk/opensmalltalk-vm

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Vm-dev February 2018