On 2022-06-14 06:37, Gerald Klix via Cuis-dev wrote:
I did not ask a specific enough question: "Wasn't there a RiscV JIT VM? AFAIR Eliott wrote something about that one."
No. MIPS, ARM, and RISCV are all RISC architectures, and there is a RiscOS which runs on ARM. https://www.riscosopen.org/content/
Right now the image is running well, but I get an error PNGReaderWriter crc error in chunk IHDR
But this does come up in the debugger! Not by crashing.
Probably an edge case with passing structs. Callouts and FFI need more testing.
But, hey, celebrate success! Ran the first time I got everything to compile. Wow! Bless the OpenSmalltalk crew! :)
Note that Allwinner D1 is a slow chip. One core. LicheeRV is finiky. No graphics acceleration. Early days Debian Linux. You have to be comfortable with Linux and SD cards to attempt it.
I wrote up basics at
https://github.com/KenDickey/opensmalltalk-vm-rv64/blob/Cog/building/linux64...
You probably want to read that first.
But, we are supposed to get fast, relatively cheap risc boards later this year. Perhaps BeagleV? We have to be ready! ;^)
Good on ya, -KenD
On 2022-06-14, at 7:26 AM, ken.dickey@whidbey.com wrote:
On 2022-06-14 06:37, Gerald Klix via Cuis-dev wrote:
I did not ask a specific enough question: "Wasn't there a RiscV JIT VM? AFAIR Eliott wrote something about that one."
No. MIPS, ARM, and RISCV are all RISC architectures,
Over the years I have noticed that a very large number of people seem to think that 'RISC architecture' maps to 'all RISC chips have the same instruction set'. It makes me shake my head sadly every time.
tim -- tim Rowledge; tim@rowledge.org; http://www.rowledge.org/tim "Virtual Memory" means never knowing where your next byte is coming from.
vm-dev@lists.squeakfoundation.org