Lars Wassermann uploaded a new version of Cog to project VM Maker: http://source.squeak.org/VMMaker/Cog-lw.52.mcz
==================== Summary ====================
Name: Cog-lw.52 Author: lw Time: 8 August 2012, 2:38:07.331 pm UUID: 034b9ff8-a7b0-6449-b4cb-b173a85473e0 Ancestors: Cog-lw.51
refactored smashRegisterAccessors to allow plugging in different register names to be smashed.
added proper #printOn: to ARMAlien
=============== Diff against Cog-lw.51 ===============
Item was added: + ----- Method: BochsIA32Alien>>smashRegisterAccessors (in category 'accessing-abstract') ----- + smashRegisterAccessors + ^#(eax: ebx: ecx: edx: esi: edi:)!
Item was removed: - ----- Method: BochsIA32Alien>>smashRegistersWithValuesFrom:by: (in category 'accessing-abstract') ----- - smashRegistersWithValuesFrom: base by: step - #(eax: ebx: ecx: edx: esi: edi:) - withIndexDo: - [:accessor :index| - self perform: accessor with: index - 1 * step + base]!
Item was changed: ----- Method: CogProcessorAlien>>disassembleFrom:to:in:on: (in category 'disassembly') ----- disassembleFrom: startAddress to: endAddress in: memory on: aStream | address | address := startAddress. [address < endAddress] whileTrue: [[:size :string| + aStream nextPutAll: (address printStringBase: 16 length: 8 padded: true); nextPut: $:; tab; nextPutAll: string; cr; flush. - aStream nextPutAll: string; cr; flush. address := address + size] valueWithArguments: (self primitiveDisassembleAt: address inMemory: memory)]!
Item was added: + ----- Method: CogProcessorAlien>>smashRegisterAccessors (in category 'accessing-abstract') ----- + smashRegisterAccessors + self subclassResponsibility!
Item was added: + ----- Method: CogProcessorAlien>>smashRegistersWithValuesFrom:by: (in category 'accessing-abstract') ----- + smashRegistersWithValuesFrom: base by: step + self smashRegisterAccessors + withIndexDo: + [:accessor :index| + self perform: accessor with: index - 1 * step + base]!
Item was changed: ----- Method: GdbARMAlien>>nopOpcode (in category 'opcodes') ----- nopOpcode "mov r0, r0" + ^ 16rE1A00000! - ^ 16rE1A01001!
Item was added: + ----- Method: GdbARMAlien>>printOn: (in category 'printing') ----- + printOn: aStream + aStream nextPutAll: 'an ARMAlien('. + self registerState allButLast with: self registerStateNames allButLast do: [ :state :i | + aStream + << i << ': ' + << (state abs > 15 ifTrue: [state hex] ifFalse: [state asString]) + << ', ']. + aStream << 'NZCVIF: ' + << (self registerState last printStringBase: 2 length: 6 padded: true) << ')'.!
Item was added: + ----- Method: GdbARMAlien>>registerStateNames (in category 'accessing-abstract') ----- + registerStateNames + ^#( r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc eflags)!
Item was changed: ----- Method: GdbARMAlien>>retOpcode (in category 'opcodes') ----- retOpcode "the ret command does not generally exist. the most similar would be mov pc, lr" + ^ self notYetImplemented! - ^ self halt.!
Item was added: + ----- Method: GdbARMAlien>>simulateLeafCallOf:nextpc:memory: (in category 'execution') ----- + simulateLeafCallOf: address nextpc: nextpc memory: aMemory + self lr: nextpc. + self pc: address!
Item was added: + ----- Method: GdbARMAlien>>smashRegisterAccessors (in category 'accessing-abstract') ----- + smashRegisterAccessors + ^#(r0: r1: r2: r3: r4: r5: r6: r7: r8:)!
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