Ryan Macnak uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-rmacnak.1616.mcz
==================== Summary ====================
Name: VMMaker.oscog-rmacnak.1616
Author: rmacnak
Time: 30 December 2015, 9:52:25.92 pm
UUID: f9ab8d82-c5d7-4710-98be-572dd35495a9
Ancestors: VMMaker.oscog-cb.1615
MIPS: Implement I-cache flush with <asm/cachectl.h>.
Explicitly initialize scratch and floating point abstract registers to NoReg to make the translated VM compile again.
Use signed shift when generating I-type instructions.
=============== Diff against VMMaker.oscog-cb.1615 ===============
Item was removed:
- ----- Method: CogAbstractInstruction>>isLongJump (in category 'testing') -----
- isLongJump
- ^opcode between: FirstJump and: FirstShortJump - 1!
Item was added:
+ ----- Method: CogMIPSELCompiler class>>declareCVarsIn: (in category 'translation') -----
+ declareCVarsIn: aCCodeGenerator
+ super declareCVarsIn: aCCodeGenerator.
+ aCCodeGenerator addHeaderFile: '<asm/cachectl.h>'. "For cacheflush"!
Item was changed:
----- Method: CogMIPSELCompiler class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"See MIPSConstants>>initializeRegisters for a description of the C ABI."
"Note we can fit all of the abstract registers in C preserved registers, and
not need to save or restore them at runtime calls."
-
super initializeAbstractRegisters.
ReceiverResultReg := S0.
Arg0Reg := S1.
Arg1Reg := S2.
ClassReg := S3.
SendNumArgsReg := S4.
TempReg := S5.
VarBaseReg := S6. "Must be callee saved"
SPReg := SP.
FPReg := FP.
RISCTempReg := AT.
+ LinkReg := RA.
+
+ self flag: #todo.
+ Scratch0Reg := NoReg.
+ Scratch1Reg := NoReg.
+ Scratch2Reg := NoReg.
+ Scratch3Reg := NoReg.
+ Scratch4Reg := NoReg.
+ Scratch5Reg := NoReg.
+ Scratch6Reg := NoReg.
+ Scratch7Reg := NoReg.
+
+ self flag: #todo.
+ DPFPReg0 := NoReg.
+ DPFPReg1 := NoReg.
+ DPFPReg2 := NoReg.
+ DPFPReg3 := NoReg.
+ DPFPReg4 := NoReg.
+ DPFPReg5 := NoReg.
+ DPFPReg6 := NoReg.
+ DPFPReg7 := NoReg.
+ DPFPReg8 := NoReg.
+ DPFPReg9 := NoReg.
+ DPFPReg10 := NoReg.
+ DPFPReg11 := NoReg.
+ DPFPReg12 := NoReg.
+ DPFPReg13 := NoReg.
+ DPFPReg14 := NoReg.
+ DPFPReg15 := NoReg.
+
+ !
- LinkReg := RA!
Item was changed:
----- Method: CogMIPSELCompiler>>beqR:R:offset: (in category 'encoding - control') -----
beqR: leftReg R: rightReg offset: offset
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
+ ^self itype: BEQ rs: leftReg rt: rightReg signedImmediate: offset >>> 2!
- ^self itype: BEQ rs: leftReg rt: rightReg signedImmediate: offset >> 2!
Item was changed:
----- Method: CogMIPSELCompiler>>bgezR:offset: (in category 'encoding - control') -----
bgezR: cmpReg offset: offset
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
+ ^self itype: REGIMM rs: cmpReg rt: BGEZ signedImmediate: offset >>> 2!
- ^self itype: REGIMM rs: cmpReg rt: BGEZ signedImmediate: offset >> 2!
Item was changed:
----- Method: CogMIPSELCompiler>>bgtzR:offset: (in category 'encoding - control') -----
bgtzR: cmpReg offset: offset
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
+ ^self itype: BGTZ rs: cmpReg rt: 0 signedImmediate: offset >>> 2!
- ^self itype: BGTZ rs: cmpReg rt: 0 signedImmediate: offset >> 2!
Item was changed:
----- Method: CogMIPSELCompiler>>blezR:offset: (in category 'encoding - control') -----
blezR: cmpReg offset: offset
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
+ ^self itype: BLEZ rs: cmpReg rt: 0 signedImmediate: offset >>> 2!
- ^self itype: BLEZ rs: cmpReg rt: 0 signedImmediate: offset >> 2!
Item was changed:
----- Method: CogMIPSELCompiler>>bltzR:offset: (in category 'encoding - control') -----
bltzR: cmpReg offset: offset
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
+ ^self itype: REGIMM rs: cmpReg rt: BLTZ signedImmediate: offset >>> 2!
- ^self itype: REGIMM rs: cmpReg rt: BLTZ signedImmediate: offset >> 2!
Item was changed:
----- Method: CogMIPSELCompiler>>bneR:R:offset: (in category 'encoding - control') -----
bneR: leftReg R: rightReg offset: offset
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
+ ^self itype: BNE rs: leftReg rt: rightReg signedImmediate: offset >>> 2!
- ^self itype: BNE rs: leftReg rt: rightReg signedImmediate: offset >> 2!
Item was changed:
----- Method: CogMIPSELCompiler>>callerSavedRegisterMask (in category 'accessing') -----
callerSavedRegisterMask
+ "Volatile"
"See MIPSConstants initializeRegisters."
self flag: #OABI.
^cogit
+ registerMaskFor: T0
+ and: T1
+ and: T2
+ and: T3
+ and: T4
+ and: T5
+ and: T6
+ and: T7
+ and: T8
+ and: T9!
- registerMaskFor: S0
- and: S1
- and: S2
- and: S3
- and: S4
- and: S5
- and: S6
- and: S7!
Item was changed:
----- Method: CogMIPSELCompiler>>flushICacheFrom:to: (in category 'inline cacheing') -----
flushICacheFrom: startAddress "<Integer>" to: endAddress "<Integer>"
+ <cmacro: '(me,startAddress,endAddress) cacheflush((char*) startAddress, endAddress - startAddress, ICACHE)'>
+ "See http://www.linux-mips.org/wiki/Cacheflush_Syscall"
- <cmacro: '(me,startAddress,endAddress) __clear_cache((char*) startAddress, (char*) (endAddress ))'>
- "On ARM we almost certainly need to flush and wash hands. On linux we use __clear_cache (see http://community.arm.com/groups/processors/blog/2010/02/17/caches-and-self-… for a decent example) and remember that the end address is *exclusive* so we can just use the end address passed in since it is always the byte after the actual last one needing flushing"
self halt: #ceFlushICache!
Item was changed:
----- Method: CogMIPSELCompiler>>high16BitsOf: (in category 'encoding') -----
high16BitsOf: word
+ <var: #word type: #usqInt>
^word >> 16!
Item was changed:
----- Method: CogMIPSELCompiler>>itype:rs:rt:eitherImmediate: (in category 'encoding') -----
+ itype: op rs: rs rt: rt eitherImmediate: immediate
- itype: op rs: rs rt: rt eitherImmediate: signedImmediate
- | unsignedImmediate |
self assert: (op between: 0 and: 63).
self assert: (rs between: 0 and: 31).
self assert: (rt between: 0 and: 31).
+ "signedImmediate < 0
- signedImmediate < 0
ifTrue: [unsignedImmediate := signedImmediate + 16r10000]
ifFalse: [unsignedImmediate := signedImmediate].
+ self assert: (unsignedImmediate between: 0 and: 16rFFFF)."
+ ^(((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: (immediate bitAnd: 16rFFFF)!
- self assert: (unsignedImmediate between: 0 and: 16rFFFF).
- ^(((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: unsignedImmediate!
Item was changed:
----- Method: CogMIPSELCompiler>>itype:rs:rt:signedImmediate: (in category 'encoding') -----
+ itype: op rs: rs rt: rt signedImmediate: immediate
- itype: op rs: rs rt: rt signedImmediate: signedImmediate
- | unsignedImmediate |
self assert: (op between: 0 and: 63).
self assert: (rs between: 0 and: 31).
self assert: (rt between: 0 and: 31).
+ self assert: (immediate between: -16r8000 and: 16r7FFF).
+ "signedImmediate < 0
- self assert: (signedImmediate between: -16r8000 and: 16r7FFF).
- signedImmediate < 0
ifTrue: [unsignedImmediate := signedImmediate + 16r10000]
ifFalse: [unsignedImmediate := signedImmediate].
+ self assert: (unsignedImmediate between: 0 and: 16rFFFF)."
+ ^(((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: (immediate bitAnd: 16rFFFF)!
- self assert: (unsignedImmediate between: 0 and: 16rFFFF).
- ^(((op << 26) bitOr: (rs << 21)) bitOr: (rt << 16)) bitOr: unsignedImmediate!
Item was changed:
----- Method: CogMIPSELCompiler>>literalAtAddress: (in category 'inline cacheing') -----
literalAtAddress: mcpc
+ <var: #high type: #usqInt>
+ <var: #low type: #usqInt>
| high low |
self assert: (self opcodeAtAddress: mcpc) = ORI.
self assert: (self opcodeAtAddress: mcpc - 4) = LUI.
low := (objectMemory longAt: mcpc) bitAnd: 16rFFFF.
high := (objectMemory longAt: mcpc - 4) bitAnd: 16rFFFF.
^high << 16 bitOr: low
!
Item was changed:
----- Method: CogMIPSELCompiler>>literalAtAddress:put: (in category 'inline cacheing') -----
literalAtAddress: mcpc put: newLiteral
+ <var: #oldUpper type: #usqInt>
+ <var: #newUpper type: #usqInt>
+ <var: #oldLower type: #usqInt>
+ <var: #newLower type: #usqInt>
| oldUpper newUpper oldLower newLower |
self assert: (self opcodeAtAddress: mcpc - 4) = LUI.
self assert: (self opcodeAtAddress: mcpc) = ORI.
oldUpper := objectMemory longAt: mcpc - 4.
newUpper := (oldUpper bitAnd: 16rFFFF0000) bitOr: (self high16BitsOf: newLiteral).
objectMemory longAt: mcpc - 4 put: newUpper.
oldLower := objectMemory longAt: mcpc.
newLower := (oldLower bitAnd: 16rFFFF0000) bitOr: (self low16BitsOf: newLiteral).
objectMemory longAt: mcpc put: newLower.
self assert: (self opcodeAtAddress: mcpc - 4) = LUI.
self assert: (self opcodeAtAddress: mcpc) = ORI.
self assert: (self literalAtAddress: mcpc) = newLiteral.
^newLiteral!
Item was changed:
----- Method: CogMIPSELCompiler>>low16BitsOf: (in category 'encoding') -----
low16BitsOf: word
+ <var: #word type: #usqInt>
^word bitAnd: 16rFFFF!
Item was changed:
----- Method: CogMIPSELCompiler>>rewriteITypeBranchAtAddress:target: (in category 'inline cacheing') -----
rewriteITypeBranchAtAddress: mcpc target: newTarget
| newDisplacement oldInstruction newInstruction |
newDisplacement := newTarget - (mcpc + 4). "Displacement is relative to delay slot."
+ newDisplacement := newDisplacement >>> 2. "Displacement is in words."
+ newDisplacement := (newDisplacement bitAnd: 16rFFFF).
- newDisplacement := newDisplacement >> 2. "Displacement is in words."
-
- self assert: (newDisplacement between: -16r8000 and: 16r7FFF).
- newDisplacement < 0
- ifTrue: [newDisplacement := newDisplacement + 16r10000]
- ifFalse: [newDisplacement := newDisplacement].
- self assert: (newDisplacement between: 0 and: 16rFFFF).
oldInstruction := objectMemory longAt: mcpc.
newInstruction := (oldInstruction bitAnd: 16rFFFF0000) bitOr: newDisplacement.
objectMemory longAt: mcpc put: newInstruction.!
Item was changed:
----- Method: CogMIPSELCompiler>>targetFromITypeAtAddress: (in category 'inline cacheing') -----
targetFromITypeAtAddress: mcpc
+ <var: #offset type: #usqInt>
+ <var: #mcpc type: #usqInt>
+ <returnTypeC: #usqInt>
| offset |
offset := (objectMemory longAt: mcpc) bitAnd: 16rFFFF.
+ self cCode: '' inSmalltalk: [offset >= 16r8000 ifTrue: [offset := offset - 16r10000]].
- offset >= 16r8000 ifTrue: [offset := offset - 16r10000].
offset := offset << 2.
^mcpc + offset + OneInstruction. "Offset is relative to the delay slot"!
Item was changed:
----- Method: CogMIPSELCompiler>>targetFromJTypeAtAddress: (in category 'inline cacheing') -----
targetFromJTypeAtAddress: mcpc
+ <var: #mcpc type: #usqInt>
+ <returnTypeC: #usqInt>
| targetLow |
targetLow := (objectMemory longAt: mcpc) bitAnd: 16r3FFFFFF.
"mcpc + 4: relative to delay slot not j"
^((mcpc + 4) bitAnd: 16rF0000000) + (targetLow << 2) !
Item was added:
+ ----- Method: Cogit>>registerMaskFor:and:and:and:and:and:and:and:and:and: (in category 'register management') -----
+ registerMaskFor: reg1 and: reg2 and: reg3 and: reg4 and: reg5 and: reg6 and: reg7 and: reg8 and: reg9 and: reg10
+ ^((((((((1 << reg1 bitOr: 1 << reg2) bitOr: 1 << reg3) bitOr: 1 << reg4) bitOr: 1 << reg5) bitOr: 1 << reg6) bitOr: 1 << reg7) bitOr: 1 << reg8) bitOr: 1 << reg9) bitOr: 1 << reg10!
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Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1615.mcz
==================== Summary ====================
Name: VMMaker.oscog-cb.1615
Author: cb
Time: 29 December 2015, 10:30:37.779 am
UUID: 712a0115-a780-4d2c-b4f8-c0bc78031889
Ancestors: VMMaker.oscog-eem.1614, VMMaker.oscog-cb.1579
Made a new version of immutability with Eliot's remarks:
- control flow maintained for the simulator
- option pragma everywhere needed
- removed duplication in extStore bytecodes
- removed useless instruction in primitiveClone.
I tried to use it, it does not work, but it seems the bleeding edge is not stable.
The only thing I noticed is that some assertion may fail in #maybeCheckStackDepth:sp:pc: .
=============== Diff against VMMaker.oscog-eem.1614 ===============
Item was added:
+ ----- Method: CoInterpreter>>ceCannotAssignTo:withIndex:valueToAssign: (in category 'trampolines') -----
+ ceCannotAssignTo: immutableObject withIndex: index valueToAssign: valueToAssign
+ "index is unboxed."
+ <api>
+ <option: #IMMUTABILITY>
+ instructionPointer := self popStack.
+ self push: immutableObject.
+ self push: valueToAssign.
+ self push: (objectMemory integerObjectOf: index).
+ self push: instructionPointer.
+ ^ self
+ ceSendAbort: (objectMemory splObj: SelectorAttemptToAssign)
+ to: immutableObject
+ numArgs: 2!
Item was removed:
- ----- Method: CoInterpreter>>extendedStoreBytecode (in category 'stack bytecodes') -----
- extendedStoreBytecode
- "Override to use itemporary:in:put:"
- | descriptor variableType variableIndex |
- <inline: true>
- descriptor := self fetchByte.
- self fetchNextBytecode.
- variableType := descriptor >> 6 bitAnd: 3.
- variableIndex := descriptor bitAnd: 63.
- variableType = 0 ifTrue:
- [^objectMemory storePointer: variableIndex ofObject: self receiver withValue: self internalStackTop].
- variableType = 1 ifTrue:
- [^self itemporary: variableIndex in: localFP put: self internalStackTop].
- variableType = 3 ifTrue:
- [^self storeLiteralVariable: variableIndex withValue: self internalStackTop].
- self error: 'illegal store'!
Item was added:
+ ----- Method: CoInterpreter>>extendedStoreBytecodePop: (in category 'stack bytecodes') -----
+ extendedStoreBytecodePop: popBoolean
+ "Override to use itemporary:in:put:"
+ | descriptor variableType variableIndex value |
+ <inline: true>
+ descriptor := self fetchByte.
+ self fetchNextBytecode.
+ variableType := descriptor >> 6 bitAnd: 3.
+ variableIndex := descriptor bitAnd: 63.
+ value := self internalStackTop.
+ popBoolean ifTrue: [ self internalPop: 1 ].
+ variableType = 0 ifTrue:
+ [^objectMemory storePointerImmutabilityCheck: variableIndex ofObject: self receiver withValue: value].
+ variableType = 1 ifTrue:
+ [^self itemporary: variableIndex in: localFP put: value].
+ variableType = 3 ifTrue:
+ [^self storeLiteralVariable: variableIndex withValue: value].
+ self error: 'illegal store'!
Item was changed:
----- Method: CoInterpreterPrimitives>>primitiveObjectAtPut (in category 'object access primitives') -----
primitiveObjectAtPut
"Store a literal into a CompiledMethod at the given index. Defined for CompiledMethods only."
| thisReceiver rawHeader realHeader index newValue |
newValue := self stackValue: 0.
index := self stackValue: 1.
(objectMemory isNonIntegerObject: index) ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
index := objectMemory integerValueOf: index.
thisReceiver := self stackValue: 2.
+ self cppIf: IMMUTABILITY
+ ifTrue: [ (objectMemory isImmutable: thisReceiver) ifTrue: [ ^self primitiveFailFor: PrimErrInappropriate ] ].
rawHeader := self rawHeaderOf: thisReceiver.
realHeader := (self isCogMethodReference: rawHeader)
ifTrue: [(self cCoerceSimple: rawHeader to: #'CogMethod *') methodHeader]
ifFalse: [rawHeader].
(index > 0
and: [index <= ((objectMemory literalCountOfMethodHeader: realHeader) + LiteralStart)]) ifFalse:
[^self primitiveFailFor: PrimErrBadIndex].
index = 1
ifTrue:
[((objectMemory isNonIntegerObject: newValue)
or: [(objectMemory literalCountOfMethodHeader: newValue) ~= (objectMemory literalCountOfMethodHeader: realHeader)]) ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
(self isCogMethodReference: rawHeader)
ifTrue: [(self cCoerceSimple: rawHeader to: #'CogMethod *') methodHeader: newValue]
ifFalse: [objectMemory storePointerUnchecked: 0 ofObject: thisReceiver withValue: newValue]]
ifFalse:
[objectMemory storePointer: index - 1 ofObject: thisReceiver withValue: newValue].
self pop: 3 thenPush: newValue!
Item was added:
+ ----- Method: CogObjectRepresentation>>genStoreSourceReg:slotIndex:destReg:scratchReg:inFrame: (in category 'compile abstract instructions') -----
+ genStoreSourceReg: sourceReg slotIndex: index destReg: destReg scratchReg: scratchReg inFrame: inFrame
+ ^ self
+ genStoreSourceReg: sourceReg
+ slotIndex: index
+ destReg: destReg
+ scratchReg: scratchReg
+ inFrame: inFrame
+ needsStoreCheck: true!
Item was changed:
----- Method: CogObjectRepresentationFor32BitSpur>>genInnerPrimitiveAtPut: (in category 'primitive generators') -----
genInnerPrimitiveAtPut: retNoffset
"Implement the guts of primitiveAtPut"
+ | formatReg jumpImmediate jumpBadIndex jumpImmutable
- | formatReg jumpImmediate jumpBadIndex
jumpNotIndexablePointers jumpNotIndexableBits
jumpIsContext jumpIsCompiledMethod jumpIsBytes jumpHasFixedFields
jumpArrayOutOfBounds jumpFixedFieldsOutOfBounds
jumpWordsOutOfBounds jumpBytesOutOfBounds jumpBytesOutOfRange
jumpNonSmallIntegerValue jumpNegative jumpShortsUnsupported jumpNotPointers
|
<inline: true>
"c.f. StackInterpreter>>stSizeOf: SpurMemoryManager>>lengthOf:format: fixedFieldsOf:format:length:"
<var: #jumpIsBytes type: #'AbstractInstruction *'>
<var: #jumpNegative type: #'AbstractInstruction *'>
<var: #jumpBadIndex type: #'AbstractInstruction *'>
<var: #jumpIsContext type: #'AbstractInstruction *'>
<var: #jumpImmediate type: #'AbstractInstruction *'>
<var: #jumpHasFixedFields type: #'AbstractInstruction *'>
<var: #jumpNotIndexableBits type: #'AbstractInstruction *'>
<var: #jumpArrayOutOfBounds type: #'AbstractInstruction *'>
<var: #jumpBytesOutOfBounds type: #'AbstractInstruction *'>
<var: #jumpShortsUnsupported type: #'AbstractInstruction *'>
<var: #jumpWordsOutOfBounds type: #'AbstractInstruction *'>
<var: #jumpNotIndexablePointers type: #'AbstractInstruction *'>
jumpImmediate := self genJumpImmediate: ReceiverResultReg.
jumpBadIndex := self genJumpNotSmallInteger: Arg0Reg scratchReg: TempReg.
self genConvertSmallIntegerToIntegerInReg: Arg0Reg.
cogit SubCq: 1 R: Arg0Reg. "1-rel => 0-rel"
"formatReg := self formatOf: ReceiverResultReg"
+ self cppIf: IMMUTABILITY
+ ifTrue:
+ [ self genGetFormatOf: ReceiverResultReg
+ into: (formatReg := SendNumArgsReg)
+ leastSignificantHalfOfBaseHeaderIntoScratch: TempReg.
+ jumpImmutable := self genJumpBaseHeaderImmutable: TempReg ]
+ ifFalse:
+ [ self genGetFormatOf: ReceiverResultReg
+ into: (formatReg := SendNumArgsReg)
+ leastSignificantHalfOfBaseHeaderIntoScratch: NoReg ].
- self genGetFormatOf: ReceiverResultReg
- into: (formatReg := SendNumArgsReg)
- leastSignificantHalfOfBaseHeaderIntoScratch: NoReg.
self genGetNumSlotsOf: ReceiverResultReg into: ClassReg.
"dispatch on format in a combination of highest dynamic frequency order first and convenience.
0 = 0 sized objects (UndefinedObject True False et al)
1 = non-indexable objects with inst vars (Point et al)
2 = indexable objects with no inst vars (Array et al)
3 = indexable objects with inst vars (MethodContext AdditionalMethodState et al)
4 = weak indexable objects with inst vars (WeakArray et al)
5 = weak non-indexable objects with inst vars (ephemerons) (Ephemeron)
6 unused, reserved for exotic pointer objects?
7 Forwarded Object, 1st field is pointer, rest of fields are ignored
8 unused, reserved for exotic non-pointer objects?
9 (?) 64-bit indexable
10 - 11 32-bit indexable
12 - 15 16-bit indexable
16 - 23 byte indexable
24 - 31 compiled method"
cogit CmpCq: objectMemory weakArrayFormat R: formatReg.
jumpNotPointers := cogit JumpAbove: 0.
"optimistic store check; assume index in range (almost always is)."
self genStoreCheckReceiverReg: ReceiverResultReg
valueReg: Arg1Reg
scratchReg: TempReg
inFrame: false.
cogit CmpCq: objectMemory arrayFormat R: formatReg.
jumpNotIndexablePointers := cogit JumpBelow: 0.
jumpHasFixedFields := cogit JumpNonZero: 0.
cogit CmpR: Arg0Reg R: ClassReg.
jumpArrayOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit AddCq: objectMemory baseHeaderSize >> objectMemory shiftForWord R: Arg0Reg.
cogit MoveR: Arg1Reg Xwr: Arg0Reg R: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
cogit RetN: retNoffset.
jumpHasFixedFields jmpTarget: cogit Label.
self genGetClassIndexOfNonImm: ReceiverResultReg into: formatReg.
cogit CmpCq: ClassMethodContextCompactIndex R: formatReg.
jumpIsContext := cogit JumpZero: 0.
"get # fixed fields in formatReg"
cogit PushR: ClassReg.
self genGetClassObjectOfClassIndex: formatReg into: ClassReg scratchReg: TempReg.
self genLoadSlot: InstanceSpecificationIndex sourceReg: ClassReg destReg: formatReg.
cogit PopR: ClassReg.
self genConvertSmallIntegerToIntegerInReg: formatReg.
cogit AndCq: objectMemory fixedFieldsOfClassFormatMask R: formatReg.
cogit SubR: formatReg R: ClassReg.
cogit AddCq: objectMemory baseHeaderSize >> objectMemory shiftForWord R: formatReg.
cogit CmpR: Arg0Reg R: ClassReg.
jumpFixedFieldsOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit AddR: formatReg R: Arg0Reg.
cogit MoveR: Arg1Reg Xwr: Arg0Reg R: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
cogit RetN: retNoffset.
jumpNotPointers jmpTarget:
(cogit CmpCq: objectMemory firstCompiledMethodFormat R: formatReg).
jumpIsCompiledMethod := cogit JumpAboveOrEqual: 0.
jumpNonSmallIntegerValue := self genJumpNotSmallInteger: Arg1Reg scratchReg: TempReg.
cogit CmpCq: objectMemory firstByteFormat R: formatReg.
jumpIsBytes := cogit JumpAboveOrEqual: 0.
cogit CmpCq: objectMemory firstShortFormat R: formatReg.
jumpShortsUnsupported := cogit JumpAboveOrEqual: 0.
cogit CmpCq: objectMemory firstLongFormat R: formatReg.
"For now ignore 64-bit indexability."
jumpNotIndexableBits := cogit JumpBelow: 0.
cogit CmpR: Arg0Reg R: ClassReg.
jumpWordsOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit MoveR: Arg1Reg R: TempReg.
self genConvertSmallIntegerToIntegerInReg: TempReg.
(cogit lastOpcode setsConditionCodesFor: JumpNegative) ifFalse:
[self CmpCq: 0 R: ClassReg]. "N.B. FLAGS := ClassReg - 0"
jumpNegative := cogit JumpNegative: 0.
cogit AddCq: objectMemory baseHeaderSize >> objectMemory shiftForWord R: Arg0Reg.
cogit MoveR: TempReg Xwr: Arg0Reg R: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
cogit RetN: retNoffset.
jumpIsBytes jmpTarget:
(cogit CmpCq: (objectMemory integerObjectOf: 255) R: Arg1Reg).
jumpBytesOutOfRange := cogit JumpAbove: 0.
cogit LogicalShiftLeftCq: objectMemory shiftForWord R: ClassReg.
cogit AndCq: objectMemory wordSize - 1 R: formatReg.
cogit SubR: formatReg R: ClassReg;
CmpR: Arg0Reg R: ClassReg.
jumpBytesOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit MoveR: Arg1Reg R: TempReg.
self genConvertSmallIntegerToIntegerInReg: TempReg.
cogit AddCq: objectMemory baseHeaderSize R: Arg0Reg.
cogit MoveR: TempReg Xbr: Arg0Reg R: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
cogit RetN: retNoffset.
"there are no shorts as yet. so this is dead code:
jumpIsShorts jmpTarget:
(cogit CmpCq: (objectMemory integerObjectOf: 65535) R: Arg1Reg).
jumpShortsOutOfRange := cogit JumpAbove: 0.
cogit LogicalShiftLeftCq: objectMemory shiftForWord - 1 R: ClassReg.
cogit AndCq: 1 R: formatReg.
cogit SubR: formatReg R: ClassReg;
CmpR: Arg0Reg R: ClassReg.
jumpShortsOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit MoveR: Arg1Reg R: TempReg.
cogit genConvertSmallIntegerToIntegerInReg: TempReg.
cogit AddR: Arg0Reg R: ReceiverResultReg.
cogit MoveR: TempReg M16: objectMemory baseHeaderSize r: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
jumpShortsDone := cogit Jump: 0."
jumpIsContext jmpTarget:
(jumpNegative jmpTarget:
(jumpNotIndexableBits jmpTarget:
(jumpBytesOutOfRange jmpTarget:
(jumpIsCompiledMethod jmpTarget:
(jumpArrayOutOfBounds jmpTarget:
(jumpBytesOutOfBounds jmpTarget:
(jumpShortsUnsupported jmpTarget:
(jumpWordsOutOfBounds jmpTarget:
(jumpNotIndexablePointers jmpTarget:
(jumpNonSmallIntegerValue jmpTarget:
(jumpFixedFieldsOutOfBounds jmpTarget: cogit Label))))))))))).
+
+ self cppIf: IMMUTABILITY ifTrue: [ jumpImmutable jmpTarget: cogit Label ].
cogit AddCq: 1 R: Arg0Reg. "0-rel => 1-rel"
self genConvertIntegerToSmallIntegerInReg: Arg0Reg.
jumpBadIndex jmpTarget: (jumpImmediate jmpTarget: cogit Label).
^0!
Item was changed:
----- Method: CogObjectRepresentationFor32BitSpur>>genInnerPrimitiveStringAtPut: (in category 'primitive generators') -----
genInnerPrimitiveStringAtPut: retNoffset
"Implement the guts of primitiveStringAtPut"
| formatReg jumpBadIndex jumpBadArg jumpWordsDone jumpBytesOutOfRange
+ jumpIsBytes jumpNotString jumpIsCompiledMethod jumpImmutable
- jumpIsBytes jumpNotString jumpIsCompiledMethod
jumpBytesOutOfBounds jumpWordsOutOfBounds jumpShortsUnsupported |
<inline: true>
"c.f. StackInterpreter>>stSizeOf: SpurMemoryManager>>lengthOf:format: fixedFieldsOf:format:length:"
<var: #jumpBadArg type: #'AbstractInstruction *'>
<var: #jumpIsBytes type: #'AbstractInstruction *'>
<var: #jumpBadIndex type: #'AbstractInstruction *'>
<var: #jumpWordsDone type: #'AbstractInstruction *'>
<var: #jumpBytesOutOfBounds type: #'AbstractInstruction *'>
<var: #jumpShortsUnsupported type: #'AbstractInstruction *'>
<var: #jumpWordsOutOfBounds type: #'AbstractInstruction *'>
jumpBadIndex := self genJumpNotSmallInteger: Arg0Reg.
cogit MoveR: Arg1Reg R: TempReg.
jumpBadArg := self genJumpNotCharacterInScratchReg: TempReg.
self genConvertSmallIntegerToIntegerInReg: Arg0Reg.
cogit SubCq: 1 R: Arg0Reg. "1-rel => 0-rel"
"formatReg := self formatOf: ReceiverResultReg"
+ self cppIf: IMMUTABILITY
+ ifTrue:
+ [ self genGetFormatOf: ReceiverResultReg
+ into: (formatReg := SendNumArgsReg)
+ leastSignificantHalfOfBaseHeaderIntoScratch: TempReg.
+ jumpImmutable := self genJumpBaseHeaderImmutable: TempReg ]
+ ifFalse:
+ [ self genGetFormatOf: ReceiverResultReg
+ into: (formatReg := SendNumArgsReg)
+ leastSignificantHalfOfBaseHeaderIntoScratch: NoReg ].
- self genGetFormatOf: ReceiverResultReg
- into: (formatReg := SendNumArgsReg)
- leastSignificantHalfOfBaseHeaderIntoScratch: NoReg.
self genGetNumSlotsOf: ReceiverResultReg into: ClassReg.
"dispatch on format; words and/or bytes.
0 to 8 = pointer objects, forwarders, reserved.
9 (?) 64-bit indexable
10 - 11 32-bit indexable
12 - 15 16-bit indexable (but unused)
16 - 23 byte indexable
24 - 31 compiled method"
cogit CmpCq: objectMemory firstLongFormat R: formatReg.
jumpNotString := cogit JumpBelowOrEqual: 0.
cogit CmpCq: objectMemory firstCompiledMethodFormat R: formatReg.
jumpIsCompiledMethod := cogit JumpAboveOrEqual: 0.
cogit CmpCq: objectMemory firstByteFormat R: formatReg.
jumpIsBytes := cogit JumpGreaterOrEqual: 0.
cogit CmpCq: objectMemory firstShortFormat R: formatReg.
jumpShortsUnsupported := cogit JumpGreaterOrEqual: 0.
cogit CmpR: Arg0Reg R: ClassReg.
jumpWordsOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit MoveR: Arg1Reg R: TempReg.
self genConvertSmallIntegerToIntegerInReg: TempReg.
cogit AddCq: objectMemory baseHeaderSize >> objectMemory shiftForWord R: Arg0Reg.
cogit MoveR: TempReg Xwr: Arg0Reg R: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
jumpWordsDone := cogit Jump: 0.
"there are no shorts as yet. so this is dead code:
jumpIsShorts jmpTarget:
(cogit CmpCq: (objectMemory integerObjectOf: 65535) R: Arg1Reg).
jumpShortsOutOfRange := cogit JumpAbove: 0.
cogit LogicalShiftLeftCq: objectMemory shiftForWord - 1 R: ClassReg.
cogit AndCq: 1 R: formatReg.
cogit SubR: formatReg R: ClassReg;
CmpR: Arg0Reg R: ClassReg.
jumpShortsOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit MoveR: Arg1Reg R: TempReg.
cogit genConvertSmallIntegerToIntegerInReg: TempReg.
cogit AddR: Arg0Reg R: ReceiverResultReg.
cogit MoveR: TempReg M16: objectMemory baseHeaderSize r: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
jumpShortsDone := cogit Jump: 0."
jumpIsBytes jmpTarget:
(cogit CmpCq: (objectMemory characterObjectOf: 255) R: Arg1Reg).
jumpBytesOutOfRange := cogit JumpAbove: 0.
cogit LogicalShiftLeftCq: objectMemory shiftForWord R: ClassReg.
cogit AndCq: objectMemory wordSize - 1 R: formatReg.
cogit SubR: formatReg R: ClassReg;
CmpR: Arg0Reg R: ClassReg.
jumpBytesOutOfBounds := cogit JumpBelowOrEqual: 0.
cogit MoveR: Arg1Reg R: TempReg.
self genConvertCharacterToCodeInReg: TempReg.
cogit AddCq: objectMemory baseHeaderSize R: Arg0Reg.
cogit MoveR: TempReg Xbr: Arg0Reg R: ReceiverResultReg.
cogit MoveR: Arg1Reg R: ReceiverResultReg.
jumpWordsDone jmpTarget:
(cogit RetN: retNoffset).
jumpBadArg jmpTarget:
(jumpNotString jmpTarget:
(jumpBytesOutOfRange jmpTarget:
(jumpIsCompiledMethod jmpTarget:
(jumpBytesOutOfBounds jmpTarget:
(jumpShortsUnsupported jmpTarget:
(jumpWordsOutOfBounds jmpTarget: cogit Label)))))).
+ self cppIf: IMMUTABILITY ifTrue: [ jumpImmutable jmpTarget: cogit Label ].
+
cogit AddCq: 1 R: Arg0Reg. "0-rel => 1-rel"
self genConvertIntegerToSmallIntegerInReg: Arg0Reg.
jumpBadIndex jmpTarget: cogit Label.
^0!
Item was changed:
CogObjectRepresentation subclass: #CogObjectRepresentationForSpur
+ instanceVariableNames: 'ceScheduleScavengeTrampoline ceSmallActiveContextInMethodTrampoline ceSmallActiveContextInBlockTrampoline ceLargeActiveContextInMethodTrampoline ceLargeActiveContextInBlockTrampoline ceStoreCheckContextReceiverTrampoline ceCannotAssignToWithIndexTrampoline'
- instanceVariableNames: 'ceScheduleScavengeTrampoline ceSmallActiveContextInMethodTrampoline ceSmallActiveContextInBlockTrampoline ceLargeActiveContextInMethodTrampoline ceLargeActiveContextInBlockTrampoline ceStoreCheckContextReceiverTrampoline'
classVariableNames: ''
poolDictionaries: 'VMBytecodeConstants VMSqueakClassIndices'
category: 'VMMaker-JIT'!
Item was changed:
----- Method: CogObjectRepresentationForSpur class>>numTrampolines (in category 'accessing') -----
numTrampolines
+ (initializationOptions at: #IMMUTABILITY ifAbsent: [false])
+ ifTrue: [ ^ super numTrampolines + 7 ]
+ ifFalse: [ ^ super numTrampolines + 6 ]!
- ^super numTrampolines + 6!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genImmutableCheck:slotIndex:sourceReg:scratchReg:popBoolean:needRestoreRcvr: (in category 'compile abstract instructions') -----
+ genImmutableCheck: regHoldingObjectMutated slotIndex: index sourceReg: regHoldingValueToStore scratchReg: scratchReg popBoolean: popBoolean needRestoreRcvr: needRestoreRcvr
+ | mutableJump fail |
+ <var: #mutableJump type: #'AbstractInstruction *'>
+ <var: #fail type: #'AbstractInstruction *'>
+ <inline: true>
+ <option: #IMMUTABILITY>
+ "Trampoline convention:
+ - objectMutated passed in RcvrResultReg
+ - index (unboxed) passed in TempReg
+ - valueToStore passed in Arg1Reg.
+ Simulated stack is flushed until simulatedStackPointer - 1, which implies full flush
+ if popBoolean is true, else top value may not be flushed.
+ We spill the top value (the value to store) for the trampoline if needed."
+ self assert: regHoldingObjectMutated == ReceiverResultReg.
+ self assert: scratchReg == TempReg.
+ self assert: regHoldingValueToStore == ClassReg.
+ mutableJump := self genJumpMutable: ClassReg scratchReg: TempReg.
+
+ "We reach this code if the object mutated is immutable."
+ "simulatedStack state altered for the trampoline, spill top value if needed"
+ (popBoolean or: [ cogit ssTop spilled ]) ifFalse:
+ [ self assert: (cogit ssTop type = SSRegister and: [cogit ssTop register = ClassReg]).
+ cogit PushR: ClassReg ].
+ "pass the unboxed index using TempReg"
+ cogit MoveCq: index R: TempReg.
+ "trampoline call and mcpc to bcpc annotation."
+ cogit CallRT: ceCannotAssignToWithIndexTrampoline.
+ cogit annotateBytecode: cogit Label.
+ "Top of stack is consumed by the trampoline. In case of store with non spilled value,
+ restore ClassReg to match simulated stack state"
+ (popBoolean or: [ cogit ssTop spilled ]) ifFalse:
+ [cogit popR: ClassReg].
+ "restore ReceiverResultReg state if needed"
+ needRestoreRcvr ifTrue: [ self putSelfInReceiverResultReg ].
+ fail := cogit Jump: 0.
+
+ "We reach this code is the object mutated is mutable"
+ mutableJump jmpTarget: cogit Label.
+
+ ^ fail!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genJumpBaseHeaderImmutable: (in category 'compile abstract instructions') -----
+ genJumpBaseHeaderImmutable: baseHeaderReg
+ "baseHeader holds at least the least significant 32 bits of the object"
+ <returnTypeC: #'AbstractInstruction *'>
+ <option: #IMMUTABILITY>
+ cogit TstCq: objectMemory immutableBitMask R: baseHeaderReg.
+ ^ cogit JumpNonZero: 0!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genJumpBaseHeaderMutable: (in category 'compile abstract instructions') -----
+ genJumpBaseHeaderMutable: baseHeaderReg
+ "baseHeader holds at least the least significant 32 bits of the object"
+ <returnTypeC: #'AbstractInstruction *'>
+ <option: #IMMUTABILITY>
+ cogit TstCq: objectMemory immutableBitMask R: baseHeaderReg.
+ ^ cogit JumpZero: 0!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genJumpImmutable:scratchReg: (in category 'compile abstract instructions') -----
+ genJumpImmutable: sourceReg scratchReg: scratchReg
+ <returnTypeC: #'AbstractInstruction *'>
+ <option: #IMMUTABILITY>
+ cogit MoveMw: 0 r: sourceReg R: scratchReg.
+ ^ self genJumpBaseHeaderImmutable: scratchReg!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genJumpMutable:scratchReg: (in category 'compile abstract instructions') -----
+ genJumpMutable: sourceReg scratchReg: scratchReg
+ <returnTypeC: #'AbstractInstruction *'>
+ <option: #IMMUTABILITY>
+ cogit MoveMw: 0 r: sourceReg R: scratchReg.
+ ^ self genJumpBaseHeaderMutable: scratchReg!
Item was changed:
----- Method: CogObjectRepresentationForSpur>>genStoreCheckReceiverReg:valueReg:scratchReg:inFrame: (in category 'compile abstract instructions') -----
genStoreCheckReceiverReg: destReg valueReg: valueReg scratchReg: scratchReg inFrame: inFrame
"Generate the code for a store check of valueReg into destReg."
| jmpImmediate jmpDestYoung jmpSourceOld jmpAlreadyRemembered mask rememberedBitByteOffset |
<var: #jmpImmediate type: #'AbstractInstruction *'>
<var: #jmpDestYoung type: #'AbstractInstruction *'>
<var: #jmpSourceOld type: #'AbstractInstruction *'>
<var: #jmpAlreadyRemembered type: #'AbstractInstruction *'>
"Is value stored an integer? If so we're done"
cogit MoveR: valueReg R: scratchReg.
cogit AndCq: objectMemory tagMask R: scratchReg.
jmpImmediate := cogit JumpNonZero: 0.
"Get the old/new boundary in scratchReg"
cogit MoveCw: objectMemory storeCheckBoundary R: scratchReg.
"Is target young? If so we're done"
cogit CmpR: scratchReg R: destReg. "N.B. FLAGS := destReg - scratchReg"
jmpDestYoung := cogit JumpBelow: 0.
"Is value stored old? If so we're done."
cogit CmpR: scratchReg R: valueReg. "N.B. FLAGS := valueReg - scratchReg"
jmpSourceOld := cogit JumpAboveOrEqual: 0.
"value is young and target is old.
Need to remember this only if the remembered bit is not already set.
Test the remembered bit. Only need to fetch the byte containing it,
which reduces the size of the mask constant."
rememberedBitByteOffset := jmpSourceOld isBigEndian
ifTrue: [objectMemory baseHeaderSize - 1 - (objectMemory rememberedBitShift // 8)]
ifFalse:[objectMemory rememberedBitShift // 8].
mask := 1 << (objectMemory rememberedBitShift \\ 8).
cogit MoveMb: rememberedBitByteOffset r: destReg R: scratchReg.
cogit AndCq: mask R: scratchReg.
jmpAlreadyRemembered := cogit JumpNonZero: 0.
"Remembered bit is not set. Call store check to insert dest into remembered table."
self assert: destReg == ReceiverResultReg.
+ cogit
+ evaluateTrampolineCallBlock:
- inFrame
- ifTrue:
[cogit
CallRT: ceStoreCheckTrampoline
registersToBeSavedMask: (((cogit registerMaskFor: valueReg)
bitOr: cogit callerSavedRegMask)
bitClear: (cogit registerMaskFor: ReceiverResultReg))]
+ protectLinkRegIfNot: inFrame.
- ifFalse:
- [cogit backEnd saveAndRestoreLinkRegAround:
- [cogit
- CallRT: ceStoreCheckTrampoline
- registersToBeSavedMask: (((cogit registerMaskFor: valueReg)
- bitOr: cogit callerSavedRegMask)
- bitClear: (cogit registerMaskFor: ReceiverResultReg))]].
jmpImmediate jmpTarget:
(jmpDestYoung jmpTarget:
(jmpSourceOld jmpTarget:
(jmpAlreadyRemembered jmpTarget:
cogit Label))).
^0!
Item was removed:
- ----- Method: CogObjectRepresentationForSpur>>genStoreImmediateInSourceReg:slotIndex:destReg: (in category 'compile abstract instructions') -----
- genStoreImmediateInSourceReg: sourceReg slotIndex: index destReg: destReg
- cogit MoveR: sourceReg
- Mw: index * objectMemory wordSize + objectMemory baseHeaderSize
- r: destReg.
- ^0!
Item was removed:
- ----- Method: CogObjectRepresentationForSpur>>genStoreSourceReg:slotIndex:destReg:scratchReg: (in category 'compile abstract instructions') -----
- genStoreSourceReg: sourceReg slotIndex: index destReg: destReg scratchReg: scratchReg
- "do the store"
- cogit MoveR: sourceReg
- Mw: index * objectMemory wordSize + objectMemory baseHeaderSize
- r: destReg.
- "now the check"
- ^self genStoreCheckReceiverReg: destReg valueReg: sourceReg scratchReg: scratchReg inFrame: true!
Item was removed:
- ----- Method: CogObjectRepresentationForSpur>>genStoreSourceReg:slotIndex:destReg:scratchReg:inFrame: (in category 'compile abstract instructions') -----
- genStoreSourceReg: sourceReg slotIndex: index destReg: destReg scratchReg: scratchReg inFrame: inFrame
- "do the store"
- cogit MoveR: sourceReg
- Mw: index * objectMemory wordSize + objectMemory baseHeaderSize
- r: destReg.
- "now the check"
- ^self genStoreCheckReceiverReg: destReg valueReg: sourceReg scratchReg: scratchReg inFrame: inFrame!
Item was added:
+ ----- Method: CogObjectRepresentationForSpur>>genStoreSourceReg:slotIndex:destReg:scratchReg:inFrame:needsStoreCheck: (in category 'compile abstract instructions') -----
+ genStoreSourceReg: sourceReg slotIndex: index destReg: destReg scratchReg: scratchReg inFrame: inFrame needsStoreCheck: needsStoreCheck
+ "do the store"
+ cogit MoveR: sourceReg
+ Mw: index * objectMemory wordSize + objectMemory baseHeaderSize
+ r: destReg.
+ "now the check. needStoreCheck is false if the JIT has figured out that the value stored does not need the check (immediate, nil, true, false)"
+ needsStoreCheck ifTrue:
+ [ ^ self
+ genStoreCheckReceiverReg: destReg
+ valueReg: sourceReg
+ scratchReg: scratchReg
+ inFrame: inFrame ].
+ ^ 0!
Item was changed:
----- Method: CogObjectRepresentationForSpur>>genStoreSourceReg:slotIndex:intoNewObjectInDestReg: (in category 'compile abstract instructions') -----
genStoreSourceReg: sourceReg slotIndex: index intoNewObjectInDestReg: destReg
+ "This method is used for unchecked stores in objects after their creation (typically, inlined creation of Array, closures and some temp vectors).
+ Currently there is no need to do the immutability check here"
cogit MoveR: sourceReg
Mw: index * objectMemory wordSize + objectMemory baseHeaderSize
r: destReg.
^0!
Item was changed:
----- Method: CogObjectRepresentationForSpur>>generateObjectRepresentationTrampolines (in category 'initialization') -----
generateObjectRepresentationTrampolines
"Do the store check. Answer the argument for the benefit of the code generator;
ReceiverResultReg may be caller-saved and hence smashed by this call. Answering
it allows the code generator to reload ReceiverResultReg cheaply.
In Spur the only thing we leave to the run-time is adding the receiver to the
remembered set and setting its isRemembered bit."
+ self
+ cppIf: IMMUTABILITY
+ ifTrue:
+ [ "Arg1Reg is used as resultReg because cogit needs to restore the valueToStore
+ in the reg expected. The reg for the valueToStore is dynamically allocated, but
+ in most case, in the non-sista VM, it ends up being Arg1Reg."
+ ceCannotAssignToWithIndexTrampoline := cogit
+ genTrampolineFor: #ceCannotAssignTo:withIndex:valueToAssign:
+ called: 'ceCannotAssignToWithIndexTrampoline'
+ arg: ReceiverResultReg
+ arg: TempReg
+ arg: ClassReg ].
ceStoreCheckTrampoline := cogit
genTrampolineFor: #remember:
called: 'ceStoreCheckTrampoline'
arg: ReceiverResultReg
result: cogit returnRegForStoreCheck.
ceStoreCheckContextReceiverTrampoline := self genStoreCheckContextReceiverTrampoline.
ceScheduleScavengeTrampoline := cogit
genSafeTrampolineFor: #ceScheduleScavenge
called: 'ceScheduleScavengeTrampoline'.
ceSmallActiveContextInMethodTrampoline := self genActiveContextTrampolineLarge: false inBlock: false called: 'ceSmallMethodContext'.
ceSmallActiveContextInBlockTrampoline := self genActiveContextTrampolineLarge: false inBlock: true called: 'ceSmallBlockContext'.
ceLargeActiveContextInMethodTrampoline := self genActiveContextTrampolineLarge: true inBlock: false called: 'ceLargeMethodContext'.
ceLargeActiveContextInBlockTrampoline := self genActiveContextTrampolineLarge: true inBlock: true called: 'ceLargeBlockContext'!
Item was removed:
- ----- Method: CogObjectRepresentationForSqueakV3>>genStoreImmediateInSourceReg:slotIndex:destReg: (in category 'compile abstract instructions') -----
- genStoreImmediateInSourceReg: sourceReg slotIndex: index destReg: destReg
- cogit MoveR: sourceReg Mw: index * objectMemory wordSize + objectMemory baseHeaderSize r: destReg.
- ^0!
Item was removed:
- ----- Method: CogObjectRepresentationForSqueakV3>>genStoreSourceReg:slotIndex:destReg:scratchReg:inFrame: (in category 'compile abstract instructions') -----
- genStoreSourceReg: sourceReg slotIndex: index destReg: destReg scratchReg: scratchReg inFrame: inFrame
- | jmpImmediate jmpDestYoung jmpSourceOld jmpAlreadyRoot mask rootBitByteOffset |
- <var: #jmpImmediate type: #'AbstractInstruction *'>
- <var: #jmpDestYoung type: #'AbstractInstruction *'>
- <var: #jmpSourceOld type: #'AbstractInstruction *'>
- <var: #jmpAlreadyRoot type: #'AbstractInstruction *'>
- "do the store"
- cogit MoveR: sourceReg Mw: index * objectMemory wordSize + objectMemory baseHeaderSize r: destReg.
- "now the check. Is value stored an integer? If so we're done"
- cogit MoveR: sourceReg R: scratchReg.
- cogit AndCq: 1 R: scratchReg.
- jmpImmediate := cogit JumpNonZero: 0.
- "Get the old/new boundary in scratchReg"
- cogit MoveAw: objectMemory youngStartAddress R: scratchReg.
- "Is target young? If so we're done"
- cogit CmpR: scratchReg R: destReg. "N.B. FLAGS := destReg - scratchReg"
- jmpDestYoung := cogit JumpAboveOrEqual: 0.
- "Is value stored old? If so we're done."
- cogit CmpR: scratchReg R: sourceReg. "N.B. FLAGS := sourceReg - scratchReg"
- jmpSourceOld := cogit JumpBelow: 0.
- "value is young and target is old.
- Need to make this a root if the root bit is not already set.
- Test the root bit. Only need to fetch the byte containing it,
- which reduces the size of the mask constant."
- rootBitByteOffset := jmpSourceOld isBigEndian
- ifTrue: [objectMemory wordSize - RootBitDigitLength]
- ifFalse:[RootBitDigitLength - 1].
- mask := RootBitDigitLength > 1
- ifTrue: [RootBit >> (RootBitDigitLength - 1 * 8)]
- ifFalse: [RootBit].
- cogit MoveMb: rootBitByteOffset r: destReg R: scratchReg.
- cogit AndCq: mask R: scratchReg.
- jmpAlreadyRoot := cogit JumpNonZero: 0.
- "Root bit is not set. Call store check to insert dest into root table."
- self assert: destReg == ReceiverResultReg.
- inFrame
- ifTrue:
- [cogit
- CallRT: ceStoreCheckTrampoline
- registersToBeSavedMask: (((cogit registerMaskFor: sourceReg)
- bitOr: cogit callerSavedRegMask)
- bitClear: (cogit registerMaskFor: ReceiverResultReg))]
- ifFalse:
- [cogit backEnd saveAndRestoreLinkRegAround:
- [cogit
- CallRT: ceStoreCheckTrampoline
- registersToBeSavedMask: (((cogit registerMaskFor: sourceReg)
- bitOr: cogit callerSavedRegMask)
- bitClear: (cogit registerMaskFor: ReceiverResultReg))]].
- jmpImmediate jmpTarget:
- (jmpDestYoung jmpTarget:
- (jmpSourceOld jmpTarget:
- (jmpAlreadyRoot jmpTarget:
- cogit Label))).
- ^0!
Item was added:
+ ----- Method: CogObjectRepresentationForSqueakV3>>genStoreSourceReg:slotIndex:destReg:scratchReg:inFrame:needsStoreCheck: (in category 'compile abstract instructions') -----
+ genStoreSourceReg: sourceReg slotIndex: index destReg: destReg scratchReg: scratchReg inFrame: inFrame needsStoreCheck: needsStoreCheck
+ | jmpImmediate jmpDestYoung jmpSourceOld jmpAlreadyRoot mask rootBitByteOffset |
+ <var: #jmpImmediate type: #'AbstractInstruction *'>
+ <var: #jmpDestYoung type: #'AbstractInstruction *'>
+ <var: #jmpSourceOld type: #'AbstractInstruction *'>
+ <var: #jmpAlreadyRoot type: #'AbstractInstruction *'>
+ "do the store"
+ cogit MoveR: sourceReg Mw: index * objectMemory wordSize + objectMemory baseHeaderSize r: destReg.
+ "if no need for the store check then returns"
+ needsStoreCheck ifFalse: [ ^ 0 ].
+ "now the check. Is value stored an integer? If so we're done"
+ cogit MoveR: sourceReg R: scratchReg.
+ cogit AndCq: 1 R: scratchReg.
+ jmpImmediate := cogit JumpNonZero: 0.
+ "Get the old/new boundary in scratchReg"
+ cogit MoveAw: objectMemory youngStartAddress R: scratchReg.
+ "Is target young? If so we're done"
+ cogit CmpR: scratchReg R: destReg. "N.B. FLAGS := destReg - scratchReg"
+ jmpDestYoung := cogit JumpAboveOrEqual: 0.
+ "Is value stored old? If so we're done."
+ cogit CmpR: scratchReg R: sourceReg. "N.B. FLAGS := sourceReg - scratchReg"
+ jmpSourceOld := cogit JumpBelow: 0.
+ "value is young and target is old.
+ Need to make this a root if the root bit is not already set.
+ Test the root bit. Only need to fetch the byte containing it,
+ which reduces the size of the mask constant."
+ rootBitByteOffset := jmpSourceOld isBigEndian
+ ifTrue: [objectMemory wordSize - RootBitDigitLength]
+ ifFalse:[RootBitDigitLength - 1].
+ mask := RootBitDigitLength > 1
+ ifTrue: [RootBit >> (RootBitDigitLength - 1 * 8)]
+ ifFalse: [RootBit].
+ cogit MoveMb: rootBitByteOffset r: destReg R: scratchReg.
+ cogit AndCq: mask R: scratchReg.
+ jmpAlreadyRoot := cogit JumpNonZero: 0.
+ "Root bit is not set. Call store check to insert dest into root table."
+ self assert: destReg == ReceiverResultReg.
+ cogit
+ evaluateTrampolineCallBlock:
+ [cogit
+ CallRT: ceStoreCheckTrampoline
+ registersToBeSavedMask: (((cogit registerMaskFor: sourceReg)
+ bitOr: cogit callerSavedRegMask)
+ bitClear: (cogit registerMaskFor: ReceiverResultReg))]
+ protectLinkRegIfNot: inFrame.
+ jmpImmediate jmpTarget:
+ (jmpDestYoung jmpTarget:
+ (jmpSourceOld jmpTarget:
+ (jmpAlreadyRoot jmpTarget:
+ cogit Label))).
+ ^0!
Item was changed:
----- Method: CogVMSimulator>>maybeCheckStackDepth:sp:pc: (in category 'debug support') -----
maybeCheckStackDepth: delta sp: sp pc: mcpc
| asp bcpc startbcpc cogHomeMethod cogBlockMethod csp debugStackPointers |
debugStackDepthDictionary ifNil: [^self].
(self isMachineCodeFrame: framePointer) ifFalse: [^self].
cogBlockMethod := self mframeCogMethod: framePointer.
cogHomeMethod := self asCogHomeMethod: cogBlockMethod.
debugStackPointers := debugStackDepthDictionary
at: cogHomeMethod methodObject
ifAbsentPut: [self debugStackPointersFor: cogHomeMethod methodObject].
startbcpc := cogHomeMethod = cogBlockMethod
ifTrue: [self startPCOfMethod: cogHomeMethod methodObject]
ifFalse: [self startPCOfClosure: (self pushedReceiverOrClosureOfFrame: framePointer)].
bcpc := cogit bytecodePCFor: mcpc startBcpc: startbcpc in: cogBlockMethod.
self assert: bcpc ~= 0.
cogBlockMethod ~= cogHomeMethod ifTrue:
[| lastbcpc |
lastbcpc := cogit lastBytecodePCForBlockAt: startbcpc in: cogHomeMethod methodObject.
bcpc > lastbcpc ifTrue:
[bcpc := lastbcpc]].
asp := self stackPointerIndexForFrame: framePointer WithSP: sp + objectMemory wordSize.
csp := debugStackPointers at: bcpc.
"Compensate lazily for absent receiver sends."
(NewspeakVM
and: [asp - delta = csp
and: [cogit isAbsentReceiverSendAt: mcpc in: cogHomeMethod]]) ifTrue:
[csp := debugStackPointers at: bcpc put: csp + 1].
self assert: asp - delta + 1 = csp!
Item was added:
+ ----- Method: CurrentImageCoInterpreterFacadeForSpurObjectRepresentation>>immutableBitMask (in category 'accessing') -----
+ immutableBitMask
+ ^objectMemory immutableBitMask!
Item was added:
+ ----- Method: InterpreterPrimitives>>canBeImmutable: (in category 'object access primitives') -----
+ canBeImmutable: oop
+ <option: #IMMUTABILITY>
+ | scheduler processLists |
+
+ self assert: (objectMemory isNonImmediate: oop).
+
+ "For now we fail the primitive for contexts to we ensure there are no immutable contexts.
+ Later we can consider having immutable contexts and send cannotReturn callback
+ when returning to an immutable context. That would mean that setting a context
+ to immutable would require a divorce and returns to immutable context are
+ necessarily across stack pages"
+ (objectMemory isContext: oop) ifTrue: [ ^ false ].
+
+ "I don't get it for semaphores so they can't be immutable"
+ (objectMemory isSemaphoreObj: oop) ifTrue: [^ false].
+
+ "simple version of process management: we forbid Process and LinkedList instances to be immutable
+ as well as the Processor and the array of activeProcess"
+ scheduler := self fetchPointer: ValueIndex ofObject: (self splObj: SchedulerAssociation).
+ processLists := objectMemory fetchPointer: ProcessListsIndex ofObject: scheduler.
+ oop = scheduler ifTrue: [ ^ false ].
+ oop = processLists ifTrue: [ ^ false ].
+ "Is it a linkedList ?"
+ (objectMemory classIndexOf: (processLists at: 1)) = (objectMemory classIndexOf: oop) ifTrue: [ ^ false ].
+ "is it a Process ?"
+ (objectMemory classIndexOf: (objectMemory fetchPointer: ActiveProcessIndex ofObject: scheduler)) = (objectMemory classIndexOf: oop) ifTrue: [ ^ false ].
+
+ "The rest of the code is relative to process management: the Processor (the active
+ process scheduler) can't be immutable, as well as all the objects relative to Process management "
+ "scheduler := self fetchPointer: ValueIndex ofObject: (self splObj: SchedulerAssociation).
+ processLists := objectMemory fetchPointer: ProcessListsIndex ofObject: scheduler.
+ ((objectMemory formatOf: oop) = objectMemory nonIndexablePointerFormat)
+ ifFalse:
+ [ (objectMemory isArrayNonImm: oop) ifFalse: [ ^ true ].
+ ^ (oop = processLists) not ].
+ (objectMemory numSlotsOf: oop) >= 2 ifFalse: [ ^ true ].
+ ""is the oop the scheduler itself ?""
+ oop = scheduler ifTrue: [ ^ false ].
+ 1 to: (objectMemory numSlotsOf: processLists) do: [ :i |
+ ""is the oop one of the linked lists ?""
+ (list := processLists at: i) = oop ifTrue: [^ false].
+ ""is the oop one of the runnable process ?""
+ first := objectMemory fetchPointer: FirstLinkIndex ofObject: list.
+ first = objectMemory nilObject ifFalse:
+ [ last := objectMemory fetchPointer: LastLinkIndex ofObject: list.
+ link := first.
+ [ link = last ] whileFalse:
+ [ link = oop ifTrue: [ ^ false ].
+ link := objectMemory fetchPointer: NextLinkIndex ofObject: link. ] ] ]."
+ ^ true!
Item was changed:
----- Method: InterpreterPrimitives>>primitiveFloatAtPut (in category 'indexing primitives') -----
primitiveFloatAtPut
"Provide platform-independent access to 32-bit words comprising
a Float. Map index 1 onto the most significant word and index 2
onto the least significant word."
| rcvr index oopToStore valueToStore |
<var: #valueToStore type: #usqInt>
oopToStore := self stackTop.
valueToStore := self positive32BitValueOf: oopToStore.
self successful ifFalse:
[^self primitiveFailFor: PrimErrBadArgument].
rcvr := self stackValue: 2.
index := self stackValue: 1.
(objectMemory isImmediateFloat: rcvr) ifTrue:
[^self primitiveFailFor: PrimErrBadReceiver].
+ self cppIf: IMMUTABILITY
+ ifTrue: [ (objectMemory isImmutable: rcvr) ifTrue: [^self primitiveFailFor: PrimErrBadReceiver] ].
index = ConstOne ifTrue:
[objectMemory storeLong32: (VMBIGENDIAN ifTrue: [0] ifFalse: [1])
ofObject: rcvr
withValue: valueToStore.
^self pop: 3 thenPush: oopToStore].
index = ConstTwo ifTrue:
[objectMemory storeLong32: (VMBIGENDIAN ifTrue: [1] ifFalse: [0])
ofObject: rcvr
withValue: valueToStore.
^self pop: 3 thenPush: oopToStore].
self primitiveFailFor: ((objectMemory isIntegerObject: index)
ifTrue: [PrimErrBadIndex]
ifFalse: [PrimErrBadArgument])!
Item was added:
+ ----- Method: InterpreterPrimitives>>primitiveGetImmutability (in category 'object access primitives') -----
+ primitiveGetImmutability
+ <option: #IMMUTABILITY>
+ | rcvr bool |
+ rcvr := self stackValue: 0.
+ bool := (objectMemory isOopImmutable: rcvr)
+ ifTrue: [ TrueObject ]
+ ifFalse: [ FalseObject ].
+ self pop: argumentCount thenPush: (self splObj: bool)!
Item was changed:
----- Method: InterpreterPrimitives>>primitiveIntegerAtPut (in category 'sound primitives') -----
primitiveIntegerAtPut
"Return the 32bit signed integer contents of a words receiver"
| index rcvr sz addr value valueOop |
<var: 'value' type: 'int'>
valueOop := self stackValue: 0.
index := self stackIntegerValue: 1.
value := self signed32BitValueOf: valueOop.
self successful ifFalse:
[^self primitiveFailFor: PrimErrBadArgument].
rcvr := self stackValue: 2.
(objectMemory isWords: rcvr) ifFalse:
[^self primitiveFailFor: PrimErrInappropriate].
+ self cppIf: IMMUTABILITY "isWords: ensure non immediate"
+ ifTrue: [ (objectMemory isImmutable: rcvr) ifTrue: [ ^self primitiveFailFor: PrimErrInappropriate ] ].
sz := objectMemory lengthOf: rcvr. "number of fields"
(index >= 1 and: [index <= sz]) ifFalse:
[^self primitiveFailFor: PrimErrBadIndex].
"4 = 32 bits / 8"
addr := rcvr + objectMemory baseHeaderSize + (index - 1 * 4). "for zero indexing"
value := objectMemory intAt: addr put: value.
self pop: 3 thenPush: valueOop "pop all; return value"
!
Item was changed:
----- Method: InterpreterPrimitives>>primitiveObjectAtPut (in category 'object access primitives') -----
primitiveObjectAtPut
"Store a literal into a CompiledMethod at the given index. Defined for CompiledMethods only."
| thisReceiver index newValue |
newValue := self stackValue: 0.
index := self stackValue: 1.
((objectMemory isNonIntegerObject: index)
or: [index = ConstOne and: [(objectMemory isNonIntegerObject: newValue)]]) ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
index := objectMemory integerValueOf: index.
thisReceiver := self stackValue: 2.
+ self cppIf: IMMUTABILITY
+ ifTrue: [ (objectMemory isImmutable: thisReceiver) ifTrue: [ ^self primitiveFailFor: PrimErrInappropriate ] ].
(index > 0 and: [index <= ((objectMemory literalCountOf: thisReceiver) + LiteralStart)]) ifFalse:
[^self primitiveFailFor: PrimErrBadIndex].
objectMemory storePointer: index - 1 ofObject: thisReceiver withValue: newValue.
self pop: 3 thenPush: newValue!
Item was added:
+ ----- Method: InterpreterPrimitives>>primitiveSetImmutability (in category 'object access primitives') -----
+ primitiveSetImmutability
+ <option: #IMMUTABILITY>
+ | rcvr boolean wasImmutable |
+ rcvr := self stackValue: 1.
+ (objectMemory isImmediate: rcvr) ifTrue: [ ^ self primitiveFailFor: PrimErrInappropriate ].
+ boolean := self booleanValueOf: self stackTop.
+ self successful ifFalse:
+ [^self primitiveFailFor: PrimErrBadArgument].
+ boolean ifTrue:
+ [ (self canBeImmutable: rcvr) ifFalse: [ ^ self primitiveFailFor: PrimErrInappropriate ] ].
+ wasImmutable := (objectMemory isOopImmutable: rcvr)
+ ifTrue: [ TrueObject ]
+ ifFalse: [ FalseObject ].
+ objectMemory setIsImmutableOf: rcvr to: boolean.
+ self pop: argumentCount thenPush: (self splObj: wasImmutable)!
Item was changed:
----- Method: InterpreterPrimitives>>primitiveShortAtPut (in category 'sound primitives') -----
primitiveShortAtPut
"Treat the receiver, which can be indexible by either bytes or words, as an array
of signed 16-bit values. Set the contents of the given index to the given value.
Note that the index specifies the i-th 16-bit entry, not the i-th byte or word."
| index rcvr value |
value := self stackTop.
index := self stackValue: 1.
((objectMemory isIntegerObject: value)
and: [(objectMemory isIntegerObject: index)
and: [value := objectMemory integerValueOf: value.
(value >= -32768) and: [value <= 32767]]]) ifFalse:
[^self primitiveFailFor: PrimErrBadArgument].
rcvr := self stackValue: 2.
(objectMemory isWordsOrBytes: rcvr) ifFalse:
[^self primitiveFailFor: PrimErrInappropriate].
+ self cppIf: IMMUTABILITY "isWordsOrBytes ensure non immediate"
+ ifTrue: [ (objectMemory isImmutable: rcvr) ifTrue: [ ^self primitiveFailFor: PrimErrInappropriate ] ].
index := objectMemory integerValueOf: index.
(index >= 1 and: [index <= (objectMemory num16BitUnitsOf: rcvr)]) ifFalse:
[^self primitiveFailFor: PrimErrBadIndex].
objectMemory storeShort16: index - 1 ofObject: rcvr withValue: value.
self pop: 3 thenPush: (objectMemory integerObjectOf: value)!
Item was added:
+ ----- Method: ObjectMemory>>storePointerImmutabilityCheck:ofObject:withValue: (in category 'object access') -----
+ storePointerImmutabilityCheck: index ofObject: rcvr withValue: top
+ <inline: true>
+ ^ self storePointer: index ofObject: rcvr withValue: top!
Item was changed:
----- Method: SpurMemoryManager>>clone: (in category 'allocation') -----
clone: objOop
| numSlots fmt newObj |
numSlots := self numSlotsOf: objOop.
fmt := self formatOf: objOop.
numSlots > self maxSlotsForNewSpaceAlloc
ifTrue:
[newObj := self allocateSlotsInOldSpace: numSlots
format: fmt
classIndex: (self classIndexOf: objOop)]
ifFalse:
[newObj := self allocateSlots: numSlots
format: fmt
classIndex: (self classIndexOf: objOop)].
newObj ifNil:
[^0].
(self isPointersFormat: fmt)
ifTrue:
[| hasYoung |
hasYoung := false.
0 to: numSlots - 1 do:
[:i| | oop |
oop := self fetchPointer: i ofObject: objOop.
(self isNonImmediate: oop) ifTrue:
[(self isForwarded: oop) ifTrue:
[oop := self followForwarded: oop].
((self isNonImmediate: oop)
and: [self isYoungObject: oop]) ifTrue:
[hasYoung := true]].
self storePointerUnchecked: i
ofObject: newObj
withValue: oop].
(hasYoung
and: [(self isYoungObject: newObj) not]) ifTrue:
[scavenger remember: newObj]]
ifFalse:
[0 to: numSlots - 1 do:
[:i|
self storePointerUnchecked: i
ofObject: newObj
withValue: (self fetchPointer: i ofObject: objOop)].
fmt >= self firstCompiledMethodFormat ifTrue:
[coInterpreter maybeFixClonedCompiledMethod: newObj.
((self isOldObject: newObj)
and: [(self isYoungObject: objOop) or: [self isRemembered: objOop]]) ifTrue:
[scavenger remember: newObj]]].
^newObj!
Item was changed:
----- Method: SpurMemoryManager>>containsOnlyValidBecomeObjects: (in category 'become implementation') -----
containsOnlyValidBecomeObjects: array
"Answer 0 if the array contains only unpinned non-immediates.
Otherwise answer an informative error code.
Can't become: immediates!! Shouldn't become pinned objects."
+ | fieldOffset effectsFlags oop errCode |
- | fieldOffset effectsFlags oop |
fieldOffset := self lastPointerOfArray: array.
effectsFlags := 0.
"same size as array2"
[fieldOffset >= self baseHeaderSize] whileTrue:
[oop := self longAt: array + fieldOffset.
(self isOopForwarded: oop) ifTrue:
[oop := self followForwarded: oop.
self longAt: array + fieldOffset put: oop].
+ (errCode := self isOopValidBecome: oop) = 0 ifFalse: [^ errCode].
- (self isImmediate: oop) ifTrue: [^PrimErrInappropriate].
- (self isPinned: oop) ifTrue: [^PrimErrObjectIsPinned].
effectsFlags := effectsFlags bitOr: (self becomeEffectFlagsFor: oop).
fieldOffset := fieldOffset - self bytesPerOop].
"only set flags after checking all args."
becomeEffectsFlags := effectsFlags.
^0!
Item was changed:
----- Method: SpurMemoryManager>>forward:to: (in category 'become implementation') -----
forward: obj1 to: obj2
self set: obj1 classIndexTo: self isForwardedObjectClassIndexPun formatTo: self forwardedFormat.
+ self cppIf: IMMUTABILITY ifTrue: [ self setIsImmutableOf: obj1 to: false ].
self storePointer: 0 ofForwarder: obj1 withValue: obj2.
"For safety make sure the forwarder has a slot count that includes its contents."
(self rawNumSlotsOf: obj1) = 0 ifTrue:
[self rawNumSlotsOf: obj1 put: 1]!
Item was added:
+ ----- Method: SpurMemoryManager>>immutableBitMask (in category 'header format') -----
+ immutableBitMask
+ "mask the immutable bit in the base header word"
+ <option: #IMMUTABILITY>
+ ^ 1 << self immutableBitShift!
Item was added:
+ ----- Method: SpurMemoryManager>>isOopValidBecome: (in category 'become implementation') -----
+ isOopValidBecome: oop
+ "Answers 0 if the oop can be become.
+ Answers an error code in the other case"
+ (self isImmediate: oop) ifTrue: [^PrimErrInappropriate].
+ (self isPinned: oop) ifTrue: [^PrimErrObjectIsPinned].
+ self
+ cppIf: IMMUTABILITY
+ ifTrue: [ (self isImmutable: oop) ifTrue: [^PrimErrInappropriate] ].
+ ^ 0!
Item was added:
+ ----- Method: SpurMemoryManager>>storePointerImmutabilityCheck:ofObject:withValue: (in category 'object access') -----
+ storePointerImmutabilityCheck: fieldIndex ofObject: objOop withValue: valuePointer
+ "Note must check here for stores of young objects into old ones."
+ <inline: true> "normal send in cannotAssign"
+
+ self cppIf: IMMUTABILITY ifTrue:
+ [ self assert: (self isImmediate: objOop) not.
+ (self isImmutable: objOop) ifTrue:
+ [ ^ coInterpreter cannotAssign: valuePointer to: objOop withIndex: fieldIndex ] ].
+
+ ^ self storePointer: fieldIndex ofObject: objOop withValue: valuePointer!
Item was changed:
----- Method: StackInterpreter class>>initializePrimitiveTable (in category 'initialization') -----
(excessive size, no diff calculated)
Item was changed:
----- Method: StackInterpreter>>bytecodePrimAtPut (in category 'common selector sends') -----
bytecodePrimAtPut
"BytecodePrimAtPut will only succeed if the receiver is in the atCache.
Otherwise it will fail so that the more general primitiveAtPut will put it in the
cache after validating that message lookup results in a primitive response.
Override to insert in the atCache here. This is necessary since once there
is a compiled at:[put:] primitive method (which doesn't use the at: cache) the
only way something can get installed in the atCache is here."
+ | index rcvr atIx value correctRcvr |
- | index rcvr atIx value |
value := self internalStackTop.
index := self internalStackValue: 1.
rcvr := self internalStackValue: 2.
+ self cppIf: IMMUTABILITY
+ ifTrue: [ correctRcvr := objectMemory isOopMutable: rcvr ]
+ ifFalse: [ correctRcvr := objectMemory isNonImmediate: rcvr ].
+ (correctRcvr
- ((objectMemory isNonImmediate: rcvr)
and: [objectMemory isIntegerObject: index]) ifTrue:
[atIx := (rcvr bitAnd: AtCacheMask) + AtPutBase. "Index into atPutCache"
(atCache at: atIx+AtCacheOop) ~= rcvr ifTrue:
[lkupClassTag := objectMemory fetchClassTagOfNonImm: rcvr.
messageSelector := self specialSelector: 17.
(self lookupInMethodCacheSel: messageSelector classTag: lkupClassTag) ifFalse:
[argumentCount := 2.
^self commonSendOrdinary].
primitiveFunctionPointer == #primitiveAtPut
ifTrue: [self install: rcvr inAtCache: atCache at: atIx string: false]
ifFalse:
[primitiveFunctionPointer == #primitiveStringAtPut
ifTrue: [self install: rcvr inAtCache: atCache at: atIx string: true]
ifFalse:
[argumentCount := 2.
^self commonSendOrdinary]]].
self successful ifTrue:
[self commonVariable: rcvr at: (objectMemory integerValueOf: index) put: value cacheIndex: atIx].
self successful ifTrue:
[self fetchNextBytecode.
^self internalPop: 3 thenPush: value].
self initPrimCall].
messageSelector := self specialSelector: 17.
argumentCount := 2.
self normalSend!
Item was added:
+ ----- Method: StackInterpreter>>cannotAssign:to:withIndex: (in category 'stack bytecodes') -----
+ cannotAssign: resultObj to: targetObj withIndex: index
+ <option: #IMMUTABILITY>
+ <inline: true> "because of use of normalSend..."
+ self internalPush: targetObj.
+ self internalPush: resultObj.
+ self internalPush: (self integerObjectOf: index + 1).
+ messageSelector := self splObj: SelectorAttemptToAssign.
+ argumentCount := 2.
+ ^ self normalSend!
Item was changed:
----- Method: StackInterpreter>>commonAtPut: (in category 'indexing primitive support') -----
commonAtPut: stringy
"This code is called if the receiver responds primitively to at:Put:.
N.B. this does *not* use the at cache, instead inlining stObject:at:put:.
Using the at cache here would require that callers set messageSelector
and lkupClass and that is onerous and error-prone, and in any case,
inlining produces much better performance than using the at cache here."
+ | value index rcvr badRcvr |
- | value index rcvr |
<inline: true> "to get it inlined in primitiveAtPut and primitiveStringAtPut"
self initPrimCall.
rcvr := self stackValue: 2.
index := self stackValue: 1.
value := self stackTop.
+ self cppIf: IMMUTABILITY
+ ifTrue: [ badRcvr := objectMemory isOopImmutable: rcvr ]
+ ifFalse: [ badRcvr := objectMemory isImmediate: rcvr ].
+ badRcvr ifTrue:
- (objectMemory isImmediate: rcvr) ifTrue:
[^self primitiveFailFor: PrimErrInappropriate].
"No need to test for large positive integers here. No object has 1g elements"
((objectMemory isNonIntegerObject: index)
or: [argumentCount > 2 "e.g. object:basicAt:put:"
and: [objectMemory isForwarded: rcvr]]) ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
index := objectMemory integerValueOf: index.
stringy
ifTrue: [self stObject: rcvr at: index put: (self asciiOfCharacter: value)]
ifFalse: [self stObject: rcvr at: index put: value].
self successful ifTrue:
[self pop: argumentCount+1 thenPush: value]!
Item was changed:
----- Method: StackInterpreter>>extStoreAndPopLiteralVariableBytecode (in category 'stack bytecodes') -----
extStoreAndPopLiteralVariableBytecode
"236 11101100 i i i i i i i i Pop and Store Literal Variable #iiiiiiii (+ Extend A * 256)"
+ | variableIndex value |
+ variableIndex := self fetchByte + (extA << 8).
+ self fetchNextBytecode.
+ value := self internalStackTop.
+ self internalPop: 1.
+ extA := 0.
+ self storeLiteralVariable: variableIndex withValue: value!
- self extStoreLiteralVariableBytecode.
- self internalPop: 1!
Item was changed:
----- Method: StackInterpreter>>extStoreAndPopReceiverVariableBytecode (in category 'stack bytecodes') -----
extStoreAndPopReceiverVariableBytecode
"235 11101011 i i i i i i i i Pop and Store Receiver Variable #iiiiiii (+ Extend A * 256)"
+ | variableIndex value |
+ variableIndex := self fetchByte + (extA << 8).
+ self fetchNextBytecode.
+ extA := 0.
+ value := self internalStackTop.
+ self internalPop: 1.
+ self storeMaybeContextReceiverVariable: variableIndex withValue: value!
- self extStoreReceiverVariableBytecode.
- self internalPop: 1!
Item was changed:
----- Method: StackInterpreter>>extendedStoreAndPopBytecode (in category 'stack bytecodes') -----
extendedStoreAndPopBytecode
+ <inline: true>
+ self extendedStoreBytecodePop: true
-
- self extendedStoreBytecode.
- self internalPop: 1.
!
Item was changed:
----- Method: StackInterpreter>>extendedStoreBytecode (in category 'stack bytecodes') -----
extendedStoreBytecode
- | descriptor variableType variableIndex |
<inline: true>
+ self extendedStoreBytecodePop: false!
- descriptor := self fetchByte.
- self fetchNextBytecode.
- variableType := descriptor >> 6 bitAnd: 3.
- variableIndex := descriptor bitAnd: 63.
- variableType = 0 ifTrue:
- [^objectMemory storePointer: variableIndex ofObject: self receiver withValue: self internalStackTop].
- variableType = 1 ifTrue:
- [^self temporary: variableIndex in: localFP put: self internalStackTop].
- variableType = 3 ifTrue:
- [^self storeLiteralVariable: variableIndex withValue: self internalStackTop].
- self error: 'illegal store'!
Item was added:
+ ----- Method: StackInterpreter>>extendedStoreBytecodePop: (in category 'stack bytecodes') -----
+ extendedStoreBytecodePop: popBoolean
+ | descriptor variableType variableIndex value |
+ <inline: true>
+ descriptor := self fetchByte.
+ self fetchNextBytecode.
+ variableType := descriptor >> 6 bitAnd: 3.
+ variableIndex := descriptor bitAnd: 63.
+ value := self internalStackTop.
+ popBoolean ifTrue: [ self internalPop: 1 ].
+ variableType = 0 ifTrue:
+ [^objectMemory storePointerImmutabilityCheck: variableIndex ofObject: self receiver withValue: value].
+ variableType = 1 ifTrue:
+ [^self temporary: variableIndex in: localFP put: value].
+ variableType = 3 ifTrue:
+ [^self storeLiteralVariable: variableIndex withValue: value].
+ self error: 'illegal store'
+ !
Item was changed:
----- Method: StackInterpreter>>storeAndPopReceiverVariableBytecode (in category 'stack bytecodes') -----
storeAndPopReceiverVariableBytecode
"Note: This code uses
storePointerUnchecked:ofObject:withValue: and does the
store check explicitely in order to help the translator
produce better code."
| rcvr top |
rcvr := self receiver.
top := self internalStackTop.
+ self internalPop: 1.
- objectMemory storePointer: (currentBytecode bitAnd: 7) ofObject: rcvr withValue: top.
self fetchNextBytecode.
+ objectMemory storePointerImmutabilityCheck: (currentBytecode bitAnd: 7) ofObject: rcvr withValue: top.!
- self internalPop: 1!
Item was changed:
----- Method: StackInterpreter>>storeLiteralVariable:withValue: (in category 'stack bytecodes') -----
storeLiteralVariable: literalIndex withValue: anObject
| litVar |
litVar := self literal: literalIndex.
"push/store/popLiteralVariable all fetch a literal, and either read or write the literal's value field.
The fetch of the literal needs an explicit check (otherwise we would have to scan all literals in
all methods in the stack zone, and the entire method on return, and global variables are relatively
rare; in my work image 8.7% of literals are globals)."
(objectMemory isForwarded: litVar) ifTrue:
[litVar := objectMemory followForwarded: litVar].
+ ^objectMemory storePointerImmutabilityCheck: ValueIndex ofObject: litVar withValue: anObject!
- ^objectMemory storePointer: ValueIndex ofObject: litVar withValue: anObject!
Item was changed:
----- Method: StackInterpreter>>storeMaybeContextReceiverVariable:withValue: (in category 'stack bytecodes') -----
storeMaybeContextReceiverVariable: fieldIndex withValue: anObject
"Must trap accesses to married and widowed contexts.
But don't want to check on all inst var accesses. This
method is only used by the long-form bytecodes, evading the cost."
| rcvr |
rcvr := self receiver.
((self isWriteMediatedContextInstVarIndex: fieldIndex)
and: [(objectMemory isContextNonImm: rcvr)
and: [self isMarriedOrWidowedContext: rcvr]])
ifTrue:
[self instVar: fieldIndex ofContext: rcvr put: anObject]
ifFalse:
+ [objectMemory storePointerImmutabilityCheck: fieldIndex ofObject: rcvr withValue: anObject]
- [objectMemory storePointer: fieldIndex ofObject: rcvr withValue: anObject]
!
Item was changed:
----- Method: StackInterpreter>>trinaryInlinePrimitive: (in category 'miscellaneous bytecodes') -----
trinaryInlinePrimitive: primIndex
"SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution."
<option: #SistaVM>
| result |
primIndex caseOf: {
"3000 unchecked Pointer Object>>at:put:. The receiver is guaranteed to be a pointer object. The 0-relative (1-relative?) index is an in-range SmallInteger"
[0] -> [result := self internalStackTop.
objectMemory
storePointer: (objectMemory integerValueOf: (self internalStackValue: 1)) - 1
ofObject: (self internalStackValue: 2)
withValue: result.
self internalPop: 2; internalStackTopPut: result].
"3001 unchecked Byte Object>>at:put:. The receiver is guaranteed to be a non-pointer object. The 0-relative (1-relative?) index is an in-range SmallInteger. The argument is a SmallInteger. The primitive stores the least significant 8 bits."
[1] -> [result := self internalStackTop.
objectMemory
storeByte: (objectMemory integerValueOf: (self internalStackValue: 1)) - 1
ofObject: (self internalStackValue: 2)
withValue: (objectMemory integerValueOf: result).
self internalPop: 2; internalStackTopPut: result].
"3002 unchecked Word Object>>at:put:. The receiver is guaranteed to be a non-pointer object. The 0-relative (1-relative?) index is an in-range SmallInteger. The argument is a SmallInteger. The primitive stores the least significant 16 bits."
[2] -> [result := self internalStackTop.
objectMemory
storeShort16: (objectMemory integerValueOf: (self internalStackValue: 1)) - 1
ofObject: (self internalStackValue: 2)
withValue: (objectMemory integerValueOf: result).
self internalPop: 2; internalStackTopPut: result].
"3003 unchecked DoubleWord Object>>at:put:. The receiver is guaranteed to be a non-pointer object. The 0-relative (1-relative?) index is an in-range SmallInteger. The argument is a SmallInteger. The primitive stores the least significant 32 bits."
[3] -> [result := self internalStackTop.
objectMemory
storeLong32: (objectMemory integerValueOf: (self internalStackValue: 1)) - 1
ofObject: (self internalStackValue: 2)
withValue: (objectMemory integerValueOf: result).
self internalPop: 2; internalStackTopPut: result].
"3004 unchecked QuadWord Object>>at:put:. The receiver is guaranteed to be a non-pointer object. The 0-relative (1-relative?) index is an in-range SmallInteger. The argument is a SmallInteger. The primitive stores the least significant 64 bits."
[4] -> [result := self internalStackTop.
objectMemory
storeLong64: (objectMemory integerValueOf: (self internalStackValue: 1)) - 1
ofObject: (self internalStackValue: 2)
withValue: (objectMemory integerValueOf: result).
self internalPop: 2; internalStackTopPut: result] }
otherwise:
[localIP := localIP - 3.
self respondToUnknownBytecode]!
Item was changed:
----- Method: StackInterpreterPrimitives>>primitiveInstVarAt (in category 'object access primitives') -----
primitiveInstVarAt
| index rcvr hdr fmt totalLength fixedFields value |
index := self stackTop.
rcvr := self stackValue: 1.
((objectMemory isNonIntegerObject: index)
or: [argumentCount > 1 "e.g. object:instVarAt:"
and: [objectMemory isOopForwarded: rcvr]]) ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
+ (objectMemory isImmediate: rcvr) ifTrue: [^self primitiveFailFor: PrimErrInappropriate].
index := objectMemory integerValueOf: index.
hdr := objectMemory baseHeader: rcvr.
fmt := objectMemory formatOfHeader: hdr.
totalLength := objectMemory lengthOf: rcvr baseHeader: hdr format: fmt.
fixedFields := objectMemory fixedFieldsOf: rcvr format: fmt length: totalLength.
(index >= 1 and: [index <= fixedFields]) ifFalse:
[^self primitiveFailFor: PrimErrBadIndex].
(fmt = objectMemory indexablePointersFormat
and: [objectMemory isContextHeader: hdr])
ifTrue: [value := self externalInstVar: index - 1 ofContext: rcvr]
ifFalse: [value := self subscript: rcvr with: index format: fmt].
self pop: argumentCount + 1 thenPush: value!
Item was changed:
----- Method: StackInterpreterPrimitives>>primitiveInstVarAtPut (in category 'object access primitives') -----
primitiveInstVarAtPut
| newValue index rcvr hdr fmt totalLength fixedFields |
newValue := self stackTop.
index := self stackValue: 1.
rcvr := self stackValue: 2.
((objectMemory isNonIntegerObject: index)
or: [argumentCount > 2 "e.g. object:instVarAt:put:"
and: [objectMemory isOopForwarded: rcvr]]) ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
+ self cppIf: IMMUTABILITY
+ ifTrue: [ (objectMemory isOopImmutable: rcvr) ifTrue: [^self primitiveFailFor: PrimErrInappropriate] ]
+ ifFalse: [ (objectMemory isImmediate: rcvr) ifTrue: [^self primitiveFailFor: PrimErrInappropriate] ].
index := objectMemory integerValueOf: index.
hdr := objectMemory baseHeader: rcvr.
fmt := objectMemory formatOfHeader: hdr.
totalLength := objectMemory lengthOf: rcvr baseHeader: hdr format: fmt.
fixedFields := objectMemory fixedFieldsOf: rcvr format: fmt length: totalLength.
(index >= 1 and: [index <= fixedFields]) ifFalse:
[^self primitiveFailFor: PrimErrBadIndex].
(fmt = objectMemory indexablePointersFormat
and: [objectMemory isContextHeader: hdr])
ifTrue: [self externalInstVar: index - 1 ofContext: rcvr put: newValue]
ifFalse: [self subscript: rcvr with: index storing: newValue format: fmt].
self pop: argumentCount + 1 thenPush: newValue!
Item was changed:
----- Method: StackInterpreterPrimitives>>primitiveSlotAtPut (in category 'object access primitives') -----
primitiveSlotAtPut
"Assign a slot in an object. This numbers all slots from 1, ignoring the distinction between
named and indexed inst vars. In objects with both named and indexed inst vars, the named
inst vars precede the indexed ones. In non-object indexed objects (objects that contain
bits, not object references) this primitive assigns a raw integral value at each slot."
+ | newValue index rcvr fmt numSlots value badRcvr |
- | newValue index rcvr fmt numSlots value |
newValue := self stackTop.
index := self stackValue: 1.
rcvr := self stackValue: 2.
(objectMemory isIntegerObject: index) ifFalse:
[^self primitiveFailFor: PrimErrBadArgument].
+ self cppIf: IMMUTABILITY
+ ifTrue: [ badRcvr := objectMemory isOopImmutable: rcvr ]
+ ifFalse: [ badRcvr := objectMemory isImmediate: rcvr ].
+ badRcvr ifTrue:
- (objectMemory isImmediate: rcvr) ifTrue:
[^self primitiveFailFor: PrimErrBadReceiver].
fmt := objectMemory formatOf: rcvr.
index := (objectMemory integerValueOf: index) - 1.
fmt <= objectMemory lastPointerFormat ifTrue:
[numSlots := objectMemory numSlotsOf: rcvr.
(self asUnsigned: index) < numSlots ifTrue:
[(objectMemory isContextNonImm: rcvr)
ifTrue: [self externalInstVar: index ofContext: rcvr put: newValue]
ifFalse: [objectMemory storePointer: index ofObject: rcvr withValue: newValue].
self pop: argumentCount + 1 thenPush: newValue.
^0].
^self primitiveFailFor: PrimErrBadIndex].
value := self positiveMachineIntegerValueOf: newValue.
self failed ifTrue:
[primFailCode := PrimErrBadArgument.
^0].
fmt >= objectMemory firstByteFormat ifTrue:
[fmt >= objectMemory firstCompiledMethodFormat ifTrue:
[^self primitiveFailFor: PrimErrUnsupported].
(self asUnsigned: value) > 16rFF ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
numSlots := objectMemory numBytesOfBytes: rcvr.
(self asUnsigned: index) < numSlots ifTrue:
[objectMemory storeByte: index ofObject: rcvr withValue: value.
self pop: argumentCount + 1 thenPush: newValue.
^0].
^self primitiveFailFor: PrimErrBadIndex].
(objectMemory hasSpurMemoryManagerAPI
and: [fmt >= objectMemory firstShortFormat]) ifTrue:
[(self asUnsigned: value) > 16rFFFF ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
numSlots := objectMemory num16BitUnitsOf: rcvr.
(self asUnsigned: index) < numSlots ifTrue:
[objectMemory storeShort16: index ofObject: rcvr withValue: value.
self pop: argumentCount + 1 thenPush: newValue.
^0].
^self primitiveFailFor: PrimErrBadIndex].
(objectMemory bytesPerOop = 8
and: [fmt = objectMemory sixtyFourBitIndexableFormat]) ifTrue:
[numSlots := objectMemory num64BitUnitsOf: rcvr.
(self asUnsigned: index) < numSlots ifTrue:
[objectMemory storeLong64: index ofObject: rcvr withValue: value.
self pop: argumentCount + 1 thenPush: newValue.
^0].
^self primitiveFailFor: PrimErrBadIndex].
fmt >= objectMemory firstLongFormat ifTrue:
[(objectMemory wordSize > 4
and: [(self asUnsigned: value) > 16rFFFFFFFF]) ifTrue:
[^self primitiveFailFor: PrimErrBadArgument].
numSlots := objectMemory num32BitUnitsOf: rcvr.
(self asUnsigned: index) < numSlots ifTrue:
[objectMemory storeLong32: index ofObject: rcvr withValue: value.
self pop: argumentCount + 1 thenPush: newValue.
^0].
^self primitiveFailFor: PrimErrBadIndex].
^self primitiveFailFor: PrimErrBadReceiver!
Item was changed:
----- Method: StackToRegisterMappingCogit class>>initializeBytecodeTableForNewspeakV4 (in category 'class initialization') -----
initializeBytecodeTableForNewspeakV4
"StackToRegisterMappingCogit initializeBytecodeTableForNewspeakV4"
numPushNilsFunction := #v4:Num:Push:Nils:.
pushNilSizeFunction := #v4PushNilSize:numInitialNils:.
NSSendIsPCAnnotated := true. "IsNSSendCall used by SendAbsentImplicit"
FirstSpecialSelector := 80.
NumSpecialSelectors := 32.
self flag:
'Special selector send class must be inlined to agree with the interpreter, which
inlines class. If class is sent to e.g. a general instance of ProtoObject then unless
class is inlined there will be an MNU. It must be that the Cointerpreter and Cogit
have identical semantics. We get away with not hardwiring the other special
selectors either because in the Cointerpreter they are not inlined or because they
are inlined only to instances of classes for which there will always be a method.'.
self generatorTableFrom: #(
"1 byte bytecodes"
(1 0 15 genPushReceiverVariableBytecode isInstVarRef needsFrameNever: 1)
(1 16 31 genPushLiteralVariable16CasesBytecode needsFrameNever: 1)
(1 32 63 genPushLiteralConstantBytecode needsFrameNever: 1)
(1 64 75 genPushTemporaryVariableBytecode needsFrameIfMod16GENumArgs: 1)
(1 76 76 genPushReceiverBytecode needsFrameNever: 1)
(1 77 77 genExtPushPseudoVariableOrOuterBytecode needsFrameIfExtBGT2: 1)
(1 78 78 genPushConstantZeroBytecode needsFrameNever: 1)
(1 79 79 genPushConstantOneBytecode needsFrameNever: 1)
(1 80 80 genSpecialSelectorArithmetic isMapped AddRR)
(1 81 81 genSpecialSelectorArithmetic isMapped SubRR)
(1 82 82 genSpecialSelectorComparison isMapped JumpLess)
(1 83 83 genSpecialSelectorComparison isMapped JumpGreater)
(1 84 84 genSpecialSelectorComparison isMapped JumpLessOrEqual)
(1 85 85 genSpecialSelectorComparison isMapped JumpGreaterOrEqual)
(1 86 86 genSpecialSelectorComparison isMapped JumpZero)
(1 87 87 genSpecialSelectorComparison isMapped JumpNonZero)
(1 88 93 genSpecialSelectorSend isMapped) " #* #/ #\\ #@ #bitShift: //"
(1 94 94 genSpecialSelectorArithmetic isMapped AndRR)
(1 95 95 genSpecialSelectorArithmetic isMapped OrRR)
(1 96 101 genSpecialSelectorSend isMapped) "#at: #at:put: #size #next #nextPut: #atEnd"
(1 102 102 genSpecialSelectorEqualsEquals needsFrameNever: notMapped -1) "not mapped because it is directly inlined (for now)"
(1 103 103 genSpecialSelectorClass needsFrameIfStackGreaterThanOne: notMapped 0) "not mapped because it is directly inlined (for now)"
(1 104 111 genSpecialSelectorSend isMapped) "#blockCopy: #value #value: #do: #new #new: #x #y"
(1 112 127 genSendLiteralSelector0ArgsBytecode isMapped)
(1 128 143 genSendLiteralSelector1ArgBytecode isMapped)
(1 144 159 genSendLiteralSelector2ArgsBytecode isMapped)
+ (1 160 175 genSendAbsentImplicit0ArgsBytecode isMapped hasIRC)),
+
+ "N.B. not frameless if immutability"
+ ((initializationOptions at: #IMMUTABILITY ifAbsent: [false])
+ ifTrue: [#((1 176 183 genStoreAndPopReceiverVariableBytecode isMapped isInstVarRef -1))]
+ ifFalse: [#((1 176 183 genStoreAndPopReceiverVariableBytecode isInstVarRef needsFrameNever: -1)) ]),
+
+ #((1 184 191 genStoreAndPopTemporaryVariableBytecode)
- (1 160 175 genSendAbsentImplicit0ArgsBytecode isMapped hasIRC)
- (1 176 183 genStoreAndPopReceiverVariableBytecode isInstVarRef needsFrameNever: -1) "N.B. not frameless if immutability"
- (1 184 191 genStoreAndPopTemporaryVariableBytecode)
-
(1 192 199 genShortUnconditionalJump branch v3:ShortForward:Branch:Distance:)
(1 200 207 genShortJumpIfTrue branch isBranchTrue isMapped "because of mustBeBoolean"
v3:ShortForward:Branch:Distance:)
(1 208 215 genShortJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean"
v3:ShortForward:Branch:Distance:)
(1 216 216 genReturnReceiver return needsFrameIfInBlock: isMappedInBlock 0)
(1 217 217 genReturnTopFromMethod return needsFrameIfInBlock: isMappedInBlock -1)
(1 218 218 genExtReturnTopFromBlock return needsFrameNever: -1)
(1 219 219 duplicateTopBytecode needsFrameNever: 1)
(1 220 220 genPopStackBytecode needsFrameNever: -1)
(1 221 221 genExtNopBytecode needsFrameNever: 0)
(1 222 223 unknownBytecode)
"2 byte bytecodes"
(2 224 224 extABytecode extension needsFrameNever: 0)
(2 225 225 extBBytecode extension needsFrameNever: 0)
(2 226 226 genExtPushReceiverVariableBytecode isInstVarRef)
(2 227 227 genExtPushLiteralVariableBytecode needsFrameNever: 1)
(2 228 228 genExtPushLiteralBytecode needsFrameNever: 1)
(2 229 229 genExtPushIntegerBytecode needsFrameNever: 1)
(2 230 230 genLongPushTemporaryVariableBytecode)
(2 231 231 genPushNewArrayBytecode)
(2 232 232 genExtStoreReceiverVariableBytecode isInstVarRef)
(2 233 233 genExtStoreLiteralVariableBytecode)
(2 234 234 genLongStoreTemporaryVariableBytecode)
(2 235 235 genExtStoreAndPopReceiverVariableBytecode isInstVarRef)
(2 236 236 genExtStoreAndPopLiteralVariableBytecode)
(2 237 237 genLongStoreAndPopTemporaryVariableBytecode)
(2 238 238 genExtSendBytecode isMapped)
(2 239 239 genExtSendSuperBytecode isMapped)
(2 240 240 genExtSendAbsentImplicitBytecode isMapped hasIRC)
(2 241 241 genExtSendAbsentDynamicSuperBytecode isMapped hasIRC)
(2 242 242 genExtUnconditionalJump branch isMapped "because of interrupt check" v4:Long:Branch:Distance:)
(2 243 243 genExtJumpIfTrue branch isBranchTrue isMapped "because of mustBeBoolean" v4:Long:Branch:Distance:)
(2 244 244 genExtJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean" v4:Long:Branch:Distance:)
(2 245 245 genExtSendAbsentSelfBytecode isMapped hasIRC)
(2 246 248 unknownBytecode)
"3 byte bytecodes"
(3 249 249 genCallPrimitiveBytecode)
(3 250 250 genPushRemoteTempLongBytecode)
(3 251 251 genStoreRemoteTempLongBytecode)
(3 252 252 genStoreAndPopRemoteTempLongBytecode)
(3 253 253 genExtPushClosureBytecode block v4:Block:Code:Size:)
(3 254 254 genExtSendAbsentOuterBytecode isMapped hasIRC)
(3 255 255 unknownBytecode))!
Item was changed:
----- Method: StackToRegisterMappingCogit class>>initializeBytecodeTableForSistaV1 (in category 'class initialization') -----
initializeBytecodeTableForSistaV1
"StackToRegisterMappingCogit initializeBytecodeTableForSistaV1"
numPushNilsFunction := #sistaV1:Num:Push:Nils:.
pushNilSizeFunction := #sistaV1PushNilSize:numInitialNils:.
BytecodeSetHasDirectedSuperSend := true.
FirstSpecialSelector := 96.
NumSpecialSelectors := 32.
self flag:
'Special selector send class must be inlined to agree with the interpreter, which
inlines class. If class is sent to e.g. a general instance of ProtoObject then unless
class is inlined there will be an MNU. It must be that the Cointerpreter and Cogit
have identical semantics. We get away with not hardwiring the other special
selectors either because in the Cointerpreter they are not inlined or because they
are inlined only to instances of classes for which there will always be a method.'.
self generatorTableFrom: #(
"1 byte bytecodes"
"pushes"
(1 0 15 genPushReceiverVariableBytecode isInstVarRef needsFrameNever: 1)
(1 16 31 genPushLitVarDirSup16CasesBytecode needsFrameNever: 1)
(1 32 63 genPushLiteralConstantBytecode needsFrameNever: 1)
(1 64 75 genPushTemporaryVariableBytecode needsFrameIfMod16GENumArgs: 1)
(1 76 76 genPushReceiverBytecode needsFrameNever: 1)
(1 77 77 genPushConstantTrueBytecode needsFrameNever: 1)
(1 78 78 genPushConstantFalseBytecode needsFrameNever: 1)
(1 79 79 genPushConstantNilBytecode needsFrameNever: 1)
(1 80 80 genPushConstantZeroBytecode needsFrameNever: 1)
(1 81 81 genPushConstantOneBytecode needsFrameNever: 1)
(1 82 82 genExtPushPseudoVariable)
(1 83 83 duplicateTopBytecode needsFrameNever: 1)
(1 84 87 unknownBytecode)
"returns"
(1 88 88 genReturnReceiver return needsFrameIfInBlock: isMappedInBlock 0)
(1 89 89 genReturnTrue return needsFrameIfInBlock: isMappedInBlock 0)
(1 90 90 genReturnFalse return needsFrameIfInBlock: isMappedInBlock 0)
(1 91 91 genReturnNil return needsFrameIfInBlock: isMappedInBlock 0)
(1 92 92 genReturnTopFromMethod return needsFrameIfInBlock: isMappedInBlock -1)
(1 93 93 genReturnNilFromBlock return needsFrameNever: -1)
(1 94 94 genReturnTopFromBlock return needsFrameNever: -1)
(1 95 95 genExtNopBytecode needsFrameNever: 0)
"sends"
(1 96 96 genSpecialSelectorArithmetic isMapped AddRR)
(1 97 97 genSpecialSelectorArithmetic isMapped SubRR)
(1 98 98 genSpecialSelectorComparison isMapped JumpLess)
(1 99 99 genSpecialSelectorComparison isMapped JumpGreater)
(1 100 100 genSpecialSelectorComparison isMapped JumpLessOrEqual)
(1 101 101 genSpecialSelectorComparison isMapped JumpGreaterOrEqual)
(1 102 102 genSpecialSelectorComparison isMapped JumpZero)
(1 103 103 genSpecialSelectorComparison isMapped JumpNonZero)
(1 104 109 genSpecialSelectorSend isMapped) " #* #/ #\\ #@ #bitShift: //"
(1 110 110 genSpecialSelectorArithmetic isMapped AndRR)
(1 111 111 genSpecialSelectorArithmetic isMapped OrRR)
(1 112 117 genSpecialSelectorSend isMapped) "#at: #at:put: #size #next #nextPut: #atEnd"
(1 118 118 genSpecialSelectorEqualsEquals needsFrameNever: notMapped -1) "not mapped because it is directly inlined (for now)"
(1 119 119 genSpecialSelectorClass needsFrameIfStackGreaterThanOne: notMapped 0) "not mapped because it is directly inlined (for now)"
(1 120 127 genSpecialSelectorSend isMapped) "#blockCopy: #value #value: #do: #new #new: #x #y"
(1 128 143 genSendLiteralSelector0ArgsBytecode isMapped)
(1 144 159 genSendLiteralSelector1ArgBytecode isMapped)
(1 160 175 genSendLiteralSelector2ArgsBytecode isMapped)
"jumps"
(1 176 183 genShortUnconditionalJump branch v3:ShortForward:Branch:Distance:)
(1 184 191 genShortJumpIfTrue branch isBranchTrue isMapped "because of mustBeBoolean"
v3:ShortForward:Branch:Distance:)
(1 192 199 genShortJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean"
+ v3:ShortForward:Branch:Distance:)),
- v3:ShortForward:Branch:Distance:)
"stores"
+ ((initializationOptions at: #IMMUTABILITY ifAbsent: [false])
+ ifTrue: [#((1 200 207 genStoreAndPopReceiverVariableBytecode isInstVarRef isMapped -1))]
+ ifFalse: [#((1 200 207 genStoreAndPopReceiverVariableBytecode isInstVarRef needsFrameNever: -1)) ]),
+
+ #((1 208 215 genStoreAndPopTemporaryVariableBytecode)
- (1 200 207 genStoreAndPopReceiverVariableBytecode isInstVarRef needsFrameNever: -1) "N.B. not frameless if immutability"
- (1 208 215 genStoreAndPopTemporaryVariableBytecode)
(1 216 216 genPopStackBytecode needsFrameNever: -1)
(1 217 217 genUnconditionalTrapBytecode isMapped)
(1 218 223 unknownBytecode)
"2 byte bytecodes"
(2 224 224 extABytecode extension)
(2 225 225 extBBytecode extension)
"pushes"
(2 226 226 genExtPushReceiverVariableBytecode isInstVarRef) "Needs a frame for context inst var access"
(2 227 227 genExtPushLitVarDirSupBytecode needsFrameNever: 1)
(2 228 228 genExtPushLiteralBytecode needsFrameNever: 1)
(2 229 229 genLongPushTemporaryVariableBytecode)
(2 230 230 genPushClosureTempsBytecode)
(2 231 231 genPushNewArrayBytecode)
(2 232 232 genExtPushIntegerBytecode needsFrameNever: 1)
(2 233 233 genExtPushCharacterBytecode needsFrameNever: 1)
"returns"
"sends"
(2 234 234 genExtSendBytecode isMapped)
(2 235 235 genExtSendSuperBytecode isMapped)
"sista bytecodes"
(2 236 236 unknownBytecode)
"jumps"
(2 237 237 genExtUnconditionalJump branch isMapped "because of interrupt check" v4:Long:Branch:Distance:)
(2 238 238 genExtJumpIfTrue branch isBranchTrue isMapped "because of mustBeBoolean" v4:Long:Branch:Distance:)
(2 239 239 genExtJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean" v4:Long:Branch:Distance:)
"stores"
(2 240 240 genExtStoreAndPopReceiverVariableBytecode isInstVarRef)
(2 241 241 genExtStoreAndPopLiteralVariableBytecode)
(2 242 242 genLongStoreAndPopTemporaryVariableBytecode)
(2 243 243 genExtStoreReceiverVariableBytecode isInstVarRef)
(2 244 244 genExtStoreLiteralVariableBytecode)
(2 245 245 genLongStoreTemporaryVariableBytecode)
(2 246 247 unknownBytecode)
"3 byte bytecodes"
(3 248 248 genCallPrimitiveBytecode)
(3 249 249 unknownBytecode) "reserved for Push Float"
(3 250 250 genExtPushClosureBytecode block v4:Block:Code:Size:)
(3 251 251 genPushRemoteTempLongBytecode)
(3 252 252 genStoreRemoteTempLongBytecode)
(3 253 253 genStoreAndPopRemoteTempLongBytecode)
(3 254 254 genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode branch v4:Long:BranchIfNotInstanceOf:Distance:)
(3 255 255 unknownBytecode))!
Item was changed:
----- Method: StackToRegisterMappingCogit class>>initializeBytecodeTableForSqueakV3PlusClosures (in category 'class initialization') -----
initializeBytecodeTableForSqueakV3PlusClosures
"StackToRegisterMappingCogit initializeBytecodeTableForSqueakV3PlusClosures"
numPushNilsFunction := #v3:Num:Push:Nils:.
pushNilSizeFunction := #v3PushNilSize:numInitialNils:.
FirstSpecialSelector := 176.
NumSpecialSelectors := 32.
self flag:
'Special selector send class must be inlined to agree with the interpreter, which
inlines class. If class is sent to e.g. a general instance of ProtoObject then unless
class is inlined there will be an MNU. It must be that the Cointerpreter and Cogit
have identical semantics. We get away with not hardwiring the other special
selectors either because in the Cointerpreter they are not inlined or because they
are inlined only to instances of classes for which there will always be a method.'.
self generatorTableFrom: #(
(1 0 15 genPushReceiverVariableBytecode isInstVarRef needsFrameNever: 1)
(1 16 31 genPushTemporaryVariableBytecode needsFrameIfMod16GENumArgs: 1)
(1 32 63 genPushLiteralConstantBytecode needsFrameNever: 1)
+ (1 64 95 genPushLiteralVariableBytecode needsFrameNever: 1)) ,
+
+ "N.B. not frameless if immutability"
+ ((initializationOptions at: #IMMUTABILITY ifAbsent: [false])
+ ifTrue: [#((1 96 103 genStoreAndPopReceiverVariableBytecode isInstVarRef isMapped -1))]
+ ifFalse: [#((1 96 103 genStoreAndPopReceiverVariableBytecode isInstVarRef needsFrameNever: -1)) ]),
+
+ #((1 104 111 genStoreAndPopTemporaryVariableBytecode)
- (1 64 95 genPushLiteralVariableBytecode needsFrameNever: 1)
- (1 96 103 genStoreAndPopReceiverVariableBytecode isInstVarRef needsFrameNever: -1) "N.B. not frameless if immutability"
- (1 104 111 genStoreAndPopTemporaryVariableBytecode)
(1 112 112 genPushReceiverBytecode needsFrameNever: 1)
(1 113 113 genPushConstantTrueBytecode needsFrameNever: 1)
(1 114 114 genPushConstantFalseBytecode needsFrameNever: 1)
(1 115 115 genPushConstantNilBytecode needsFrameNever: 1)
(1 116 119 genPushQuickIntegerConstantBytecode needsFrameNever: 1)
"method returns in blocks need a frame because of nonlocalReturn:through:"
(1 120 120 genReturnReceiver return needsFrameIfInBlock: isMappedInBlock 0)
(1 121 121 genReturnTrue return needsFrameIfInBlock: isMappedInBlock 0)
(1 122 122 genReturnFalse return needsFrameIfInBlock: isMappedInBlock 0)
(1 123 123 genReturnNil return needsFrameIfInBlock: isMappedInBlock 0)
(1 124 124 genReturnTopFromMethod return needsFrameIfInBlock: isMappedInBlock -1)
(1 125 125 genReturnTopFromBlock return needsFrameNever: -1)
(1 126 127 unknownBytecode)
(2 128 128 extendedPushBytecode isInstVarRef) "well, maybe inst var ref"
(2 129 129 extendedStoreBytecode isInstVarRef) "well, maybe inst var ref"
(2 130 130 extendedStoreAndPopBytecode isInstVarRef) "well, maybe inst var ref"
(2 131 131 genExtendedSendBytecode isMapped)
(3 132 132 doubleExtendedDoAnythingBytecode isMapped) "well, maybe inst var ref"
(2 133 133 genExtendedSuperBytecode isInstVarRef isMapped)
(2 134 134 genSecondExtendedSendBytecode isMapped)
(1 135 135 genPopStackBytecode needsFrameNever: -1)
(1 136 136 duplicateTopBytecode needsFrameNever: 1)
(1 137 137 genPushActiveContextBytecode)
(2 138 138 genPushNewArrayBytecode)),
((initializationOptions at: #SpurObjectMemory ifAbsent: [false])
ifTrue: [#((3 139 139 genCallPrimitiveBytecode))]
ifFalse: [#((1 139 139 unknownBytecode))]),
#(
(3 140 140 genPushRemoteTempLongBytecode)
(3 141 141 genStoreRemoteTempLongBytecode)
(3 142 142 genStoreAndPopRemoteTempLongBytecode)
(4 143 143 genPushClosureCopyCopiedValuesBytecode block v3:Block:Code:Size:)
(1 144 151 genShortUnconditionalJump branch v3:ShortForward:Branch:Distance:)
(1 152 159 genShortJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean"
v3:ShortForward:Branch:Distance:)
(2 160 163 genLongUnconditionalBackwardJump branch isMapped "because of interrupt check"
v3:Long:Branch:Distance:)
(2 164 167 genLongUnconditionalForwardJump branch v3:Long:Branch:Distance:)
(2 168 171 genLongJumpIfTrue branch isBranchTrue isMapped "because of mustBeBoolean"
v3:LongForward:Branch:Distance:)
(2 172 175 genLongJumpIfFalse branch isBranchFalse isMapped "because of mustBeBoolean"
v3:LongForward:Branch:Distance:)
(1 176 176 genSpecialSelectorArithmetic isMapped AddRR)
(1 177 177 genSpecialSelectorArithmetic isMapped SubRR)
(1 178 178 genSpecialSelectorComparison isMapped JumpLess)
(1 179 179 genSpecialSelectorComparison isMapped JumpGreater)
(1 180 180 genSpecialSelectorComparison isMapped JumpLessOrEqual)
(1 181 181 genSpecialSelectorComparison isMapped JumpGreaterOrEqual)
(1 182 182 genSpecialSelectorComparison isMapped JumpZero)
(1 183 183 genSpecialSelectorComparison isMapped JumpNonZero)
(1 184 189 genSpecialSelectorSend isMapped) " #* #/ #\\ #@ #bitShift: //"
(1 190 190 genSpecialSelectorArithmetic isMapped AndRR)
(1 191 191 genSpecialSelectorArithmetic isMapped OrRR)
(1 192 197 genSpecialSelectorSend isMapped) "#at: #at:put: #size #next #nextPut: #atEnd"
(1 198 198 genSpecialSelectorEqualsEquals needsFrameNever: notMapped -1) "not mapped because it is directly inlined (for now)"
(1 199 199 genSpecialSelectorClass needsFrameIfStackGreaterThanOne: notMapped 0) "not mapped because it is directly inlined (for now)"
(1 200 207 genSpecialSelectorSend isMapped) "#blockCopy: #value #value: #do: #new #new: #x #y"
(1 208 223 genSendLiteralSelector0ArgsBytecode isMapped)
(1 224 239 genSendLiteralSelector1ArgBytecode isMapped)
(1 240 255 genSendLiteralSelector2ArgsBytecode isMapped))!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ensureReceiverResultRegContainsSelf (in category 'bytecode generator support') -----
ensureReceiverResultRegContainsSelf
needsFrame
ifTrue:
[optStatus isReceiverResultRegLive ifFalse:
[self ssAllocateRequiredReg: ReceiverResultReg.
+ self putSelfInReceiverResultReg ].
- (self addressOf: simSelf) storeToReg: ReceiverResultReg].
optStatus isReceiverResultRegLive: true]
ifFalse:
[self assert: (simSelf type = SSRegister
and: [simSelf register = ReceiverResultReg]).
self assert: (optStatus isReceiverResultRegLive
and: [optStatus ssEntry = (self addressOf: simSelf)])]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>evaluateTrampolineCallBlock:protectLinkRegIfNot: (in category 'trampoline support') -----
+ evaluateTrampolineCallBlock: block protectLinkRegIfNot: inFrame
+ <inline: true>
+ inFrame
+ ifFalse:
+ [ backEnd saveAndRestoreLinkRegAround: [ block value ] ]
+ ifTrue:
+ [ block value ].!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genReturnReceiver (in category 'bytecode generators') -----
genReturnReceiver
"In a frameless method ReceiverResultReg already contains self.
In a frameful method, ReceiverResultReg /may/ contain self."
needsFrame ifTrue:
[ optStatus isReceiverResultRegLive ifFalse:
+ [self putSelfInReceiverResultReg]].
- [ (self addressOf: simSelf) storeToReg: ReceiverResultReg]].
^self genUpArrowReturn!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genStorePop:LiteralVariable: (in category 'bytecode generator support') -----
genStorePop: popBoolean LiteralVariable: litVarIndex
<inline: false>
+ | topReg association needStoreCheck immutabilityFailure |
- | topReg assocReg association |
"The only reason we assert needsFrame here is that in a frameless method
ReceiverResultReg must and does contain only self, but the ceStoreCheck
trampoline expects the target of the store to be in ReceiverResultReg. So
in a frameless method we would have a conflict between the receiver and
the literal store, unless we we smart enough to realise that ReceiverResultReg
was unused after the literal variable store, unlikely given that methods
return self by default."
self assert: needsFrame.
+ self cppIf: IMMUTABILITY ifTrue: [ self ssFlushTo: simStackPtr - 1 ].
"N.B. No need to check the stack for references because we generate code for
literal variable loads that stores the result in a register, deferring only the register push."
+ needStoreCheck := (objectRepresentation isUnannotatableConstant: self ssTop) not.
association := self getLiteral: litVarIndex.
-
- "Avoid store check for immediate values"
- (objectRepresentation isUnannotatableConstant: self ssTop) ifTrue:
- [ assocReg := self allocateRegNotConflictingWith: 0.
- self genMoveConstant: association R: assocReg.
- objectRepresentation
- genEnsureObjInRegNotForwarded: assocReg
- scratchReg: TempReg.
- self ssStorePop: popBoolean toReg: TempReg.
- traceStores > 0 ifTrue:
- [ assocReg = ReceiverResultReg ifFalse:
- [ self ssAllocateRequiredReg: ReceiverResultReg.
- optStatus isReceiverResultRegLive: false.
- self MoveR: assocReg R: ReceiverResultReg ].
- self CallRT: ceTraceStoreTrampoline].
- ^objectRepresentation
- genStoreImmediateInSourceReg: TempReg
- slotIndex: ValueIndex
- destReg: assocReg ].
-
- topReg := self allocateRegForStackEntryAt: 0 notConflictingWith: (self registerMaskFor: ReceiverResultReg).
- self ssStorePop: popBoolean toReg: topReg.
optStatus isReceiverResultRegLive: false.
self ssAllocateRequiredReg: ReceiverResultReg. "for ceStoreCheck call in genStoreSourceReg: has to be ReceiverResultReg"
self genMoveConstant: association R: ReceiverResultReg.
objectRepresentation genEnsureObjInRegNotForwarded: ReceiverResultReg scratchReg: TempReg.
+ self
+ cppIf: IMMUTABILITY
+ ifTrue:
+ [ self ssAllocateRequiredReg: ClassReg.
+ topReg := ClassReg.
+ self ssStoreAndReplacePop: popBoolean toReg: ClassReg.
+ immutabilityFailure := objectRepresentation
+ genImmutableCheck: ReceiverResultReg
+ slotIndex: ValueIndex
+ sourceReg: ClassReg
+ scratchReg: TempReg
+ popBoolean: popBoolean
+ needRestoreRcvr: false ]
+ ifFalse:
+ [ topReg := self allocateRegForStackEntryAt: 0 notConflictingWith: (self registerMaskFor: ReceiverResultReg).
+ self ssStorePop: popBoolean toReg: topReg ].
traceStores > 0 ifTrue:
[self MoveR: topReg R: TempReg.
self CallRT: ceTraceStoreTrampoline].
+ objectRepresentation
- ^objectRepresentation
genStoreSourceReg: topReg
slotIndex: ValueIndex
destReg: ReceiverResultReg
scratchReg: TempReg
+ inFrame: needsFrame
+ needsStoreCheck: needStoreCheck.
+ self cppIf: IMMUTABILITY ifTrue: [ immutabilityFailure jmpTarget: self Label ].
+ ^ 0!
- inFrame: needsFrame!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genStorePop:MaybeContextReceiverVariable: (in category 'bytecode generator support') -----
genStorePop: popBoolean MaybeContextReceiverVariable: slotIndex
<inline: false>
+ | jmpSingle jmpDone needStoreCheck immutabilityFailure |
- | jmpSingle jmpDone valueReg |
<var: #jmpSingle type: #'AbstractInstruction *'>
<var: #jmpDone type: #'AbstractInstruction *'>
"The reason we need a frame here is that assigning to an inst var of a context may
involve wholesale reorganization of stack pages, and the only way to preserve the
execution state of an activation in that case is if it has a frame."
self assert: needsFrame.
+ self cppIf: IMMUTABILITY ifTrue: [ self ssFlushTo: simStackPtr - 1 ].
self ssFlushUpThroughReceiverVariable: slotIndex.
+ needStoreCheck := (objectRepresentation isUnannotatableConstant: self ssTop) not.
"Note that ReceiverResultReg remains live after both
ceStoreContextInstVarTrampoline and ceStoreCheckTrampoline."
self ensureReceiverResultRegContainsSelf.
self ssPop: 1.
self ssAllocateCallReg: ClassReg and: SendNumArgsReg. "for ceStoreContextInstVarTrampoline"
self ssPush: 1.
objectRepresentation
genLoadSlot: SenderIndex
sourceReg: ReceiverResultReg
destReg: TempReg.
+ self
+ cppIf: IMMUTABILITY
+ ifTrue: [ self ssStoreAndReplacePop: popBoolean toReg: ClassReg. ]
+ ifFalse: [ self ssStorePop: popBoolean toReg: ClassReg ].
- valueReg := self ssStorePop: popBoolean toPreferredReg: ClassReg.
- valueReg ~= ClassReg ifTrue:
- [self MoveR: valueReg R: ClassReg].
jmpSingle := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg.
self MoveCq: slotIndex R: SendNumArgsReg.
self CallRT: ceStoreContextInstVarTrampoline.
jmpDone := self Jump: 0.
jmpSingle jmpTarget: self Label.
traceStores > 0 ifTrue:
[self MoveR: ClassReg R: TempReg.
self CallRT: ceTraceStoreTrampoline].
+ self
+ cppIf: IMMUTABILITY
+ ifTrue:
+ [ immutabilityFailure := objectRepresentation
+ genImmutableCheck: ReceiverResultReg
+ slotIndex: ValueIndex
+ sourceReg: ClassReg
+ scratchReg: TempReg
+ popBoolean: popBoolean
+ needRestoreRcvr: true ].
objectRepresentation
genStoreSourceReg: ClassReg
slotIndex: slotIndex
destReg: ReceiverResultReg
scratchReg: TempReg
+ inFrame: true
+ needsStoreCheck: needStoreCheck.
- inFrame: true.
jmpDone jmpTarget: self Label.
+ self cppIf: IMMUTABILITY ifTrue: [ immutabilityFailure jmpTarget: self Label ].
^0!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genStorePop:ReceiverVariable: (in category 'bytecode generator support') -----
genStorePop: popBoolean ReceiverVariable: slotIndex
<inline: false>
+ | topReg needStoreCheck immutabilityFailure |
+ self cppIf: IMMUTABILITY ifTrue: [ self assert: needsFrame. self ssFlushTo: simStackPtr - 1 ].
+ self ssFlushUpThroughReceiverVariable: slotIndex.
+ needStoreCheck := (objectRepresentation isUnannotatableConstant: self ssTop) not.
+ "Note that ReceiverResultReg remains live after ceStoreCheckTrampoline."
+ self ensureReceiverResultRegContainsSelf.
+ self
+ cppIf: IMMUTABILITY
- ^ needsFrame
- ifFalse:
- [ self
- genStorePop: popBoolean
- ReceiverVariable: slotIndex
- traceBlock: [ backEnd saveAndRestoreLinkRegAround: [self CallRT: ceTraceStoreTrampoline] ]
- inFrame: needsFrame ]
ifTrue:
+ [ self ssAllocateRequiredReg: ClassReg.
+ topReg := ClassReg.
+ self ssStoreAndReplacePop: popBoolean toReg: topReg.
+ immutabilityFailure := objectRepresentation
+ genImmutableCheck: ReceiverResultReg
+ slotIndex: slotIndex
+ sourceReg: ClassReg
+ scratchReg: TempReg
+ popBoolean: popBoolean
+ needRestoreRcvr: true ]
+ ifFalse:
+ [ topReg := self allocateRegForStackEntryAt: 0 notConflictingWith: (self registerMaskFor: ReceiverResultReg).
+ self ssStorePop: popBoolean toReg: topReg ].
+ traceStores > 0 ifTrue:
+ [ self MoveR: topReg R: TempReg.
+ self evaluateTrampolineCallBlock: [ self CallRT: ceTraceStoreTrampoline ] protectLinkRegIfNot: needsFrame ].
+ objectRepresentation
+ genStoreSourceReg: topReg
+ slotIndex: slotIndex
+ destReg: ReceiverResultReg
+ scratchReg: TempReg
+ inFrame: needsFrame
+ needsStoreCheck: needStoreCheck.
+ self cppIf: IMMUTABILITY ifTrue: [ immutabilityFailure jmpTarget: self Label ].
+ ^ 0!
- [ self
- genStorePop: popBoolean
- ReceiverVariable: slotIndex
- traceBlock: [ self CallRT: ceTraceStoreTrampoline ]
- inFrame: needsFrame ]!
Item was removed:
- ----- Method: StackToRegisterMappingCogit>>genStorePop:ReceiverVariable:traceBlock:inFrame: (in category 'bytecode generator support') -----
- genStorePop: popBoolean ReceiverVariable: slotIndex traceBlock: block inFrame: inFrame
- <inline: true>
- | topReg |
- self ssFlushUpThroughReceiverVariable: slotIndex.
- "Avoid store check for immediate values"
- ^ (objectRepresentation isUnannotatableConstant: self ssTop)
- ifTrue:
- [self ensureReceiverResultRegContainsSelf.
- self ssStorePop: popBoolean toReg: TempReg.
- traceStores > 0 ifTrue: [block value].
- objectRepresentation
- genStoreImmediateInSourceReg: TempReg
- slotIndex: slotIndex
- destReg: ReceiverResultReg]
- ifFalse:
- [topReg := self allocateRegForStackEntryAt: 0 notConflictingWith: (self registerMaskFor: ReceiverResultReg).
- self ssStorePop: popBoolean toReg: topReg.
- "Note that ReceiverResultReg remains live after ceStoreCheckTrampoline."
- self ensureReceiverResultRegContainsSelf.
- traceStores > 0 ifTrue: [self MoveR: topReg R: TempReg. block value].
- objectRepresentation
- genStoreSourceReg: topReg
- slotIndex: slotIndex
- destReg: ReceiverResultReg
- scratchReg: TempReg
- inFrame: inFrame ]!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genStorePop:RemoteTemp:At: (in category 'bytecode generator support') -----
genStorePop: popBoolean RemoteTemp: slotIndex At: remoteTempIndex
<inline: false>
+ | topReg needStoreCheck |
- | topReg topSpilled tempVectReg |
"The only reason we assert needsFrame here is that in a frameless method
ReceiverResultReg must and does contain only self, but the ceStoreCheck
trampoline expects the target of the store to be in ReceiverResultReg. So
in a frameless method we would have a conflict between the receiver and
the temote temp store, unless we we smart enough to realise that
ReceiverResultReg was unused after the literal variable store, unlikely given
that methods return self by default."
self assert: needsFrame.
"N.B. No need to check the stack for references because we generate code for
remote temp loads that stores the result in a register, deferring only the register push."
+ needStoreCheck := (objectRepresentation isUnannotatableConstant: self ssTop) not.
- "Avoid store check for immediate values"
- (objectRepresentation isUnannotatableConstant: self ssTop) ifTrue:
- [ tempVectReg := self allocateRegNotConflictingWith: 0.
- self MoveMw: (self frameOffsetOfTemporary: remoteTempIndex) r: FPReg R: tempVectReg.
- self ssStorePop: popBoolean toReg: TempReg.
- traceStores > 0 ifTrue:
- [ tempVectReg = ReceiverResultReg ifFalse:
- [ self ssAllocateRequiredReg: ReceiverResultReg.
- optStatus isReceiverResultRegLive: false.
- self MoveR: tempVectReg R: ReceiverResultReg ].
- self CallRT: ceTraceStoreTrampoline].
- ^objectRepresentation
- genStoreImmediateInSourceReg: TempReg
- slotIndex: slotIndex
- destReg: tempVectReg].
topReg := self allocateRegForStackEntryAt: 0 notConflictingWith: (self registerMaskFor: ReceiverResultReg).
+ self ssAllocateRequiredReg: ReceiverResultReg.
- topSpilled := self ssTop spilled.
- self ssStorePop: (popBoolean or: [topSpilled]) toReg: topReg.
- popBoolean ifFalse:
- [topSpilled ifFalse: [self ssPop: 1].
- self ssPushRegister: topReg].
- self ssAllocateRequiredReg: ReceiverResultReg.
optStatus isReceiverResultRegLive: false.
+ self ssStoreAndReplacePop: popBoolean toReg: topReg.
self MoveMw: (self frameOffsetOfTemporary: remoteTempIndex) r: FPReg R: ReceiverResultReg.
traceStores > 0 ifTrue:
+ [ self MoveR: topReg R: TempReg.
+ self CallRT: ceTraceStoreTrampoline. ].
- [self MoveR: topReg R: TempReg.
- self CallRT: ceTraceStoreTrampoline].
^objectRepresentation
genStoreSourceReg: topReg
slotIndex: slotIndex
destReg: ReceiverResultReg
scratchReg: TempReg
+ inFrame: needsFrame
+ needsStoreCheck: needStoreCheck!
- inFrame: needsFrame!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>putSelfInReceiverResultReg (in category 'bytecode generator support') -----
+ putSelfInReceiverResultReg
+ <inline: true>
+ (self addressOf: simSelf) storeToReg: ReceiverResultReg
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssStoreAndReplacePop:toReg: (in category 'simulation stack') -----
+ ssStoreAndReplacePop: popBoolean toReg: reg
+ "In addition to ssStorePop:toReg:, if this is a store and not
+ a popInto and the top of the simulated stack is not spilled,
+ I change the simulated stack to use the register for the value"
+ | topSpilled |
+ topSpilled := self ssTop spilled.
+ self ssStorePop: (popBoolean or: [topSpilled]) toReg: reg.
+ popBoolean ifFalse:
+ [ topSpilled ifFalse: [self ssPop: 1].
+ self ssPushRegister: reg ].!
1
0
Hi Eliot,
I am looking for a way to obtain always the latest Cog vms (Spur &
non-Spur, Linux/Mac).
I don't really want to parse the version list at [1] and then
programmatically
determine and download the latest vms.
Can you think of a better way how to do this? Would it be possible to
provide a resource like:
http://www.mirandabanda.org/files/Cog/VM/*latest*/
which always contains the latest build?
Best,
Fabio
[1] http://www.mirandabanda.org/files/Cog/VM/
5
5
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1614.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1614
Author: eem
Time: 27 December 2015, 12:57:04.521 pm
UUID: 5ffe4d04-1144-4cc2-9b4d-4ab242e2217b
Ancestors: VMMaker.oscog-eem.1613
Cogit:
Eliminate some obsolete assignments to maxSize in computeFooSize methods.
Fix slips in genPrimitiveSmallFloatSquareRoot, generateInstructionsAt: & genJumpNotSmallFooInScratchReg:.
Slang:
Avoid computing variable and return typres prematurely i.e. don't derive types from as-yet-untyped methods.
=============== Diff against VMMaker.oscog-eem.1613 ===============
Item was added:
+ ----- Method: CCodeGenerator>>returnTypeOrNilForSend:in: (in category 'type inference') -----
+ returnTypeOrNilForSend: sendNode in: aTMethod
+ "Answer the return type for a send. Sends of known but as-yet-untyped methods answer nil."
+ | sel |
+ (self anyMethodNamed: (sel := sendNode selector)) ifNotNil:
+ [:m|
+ ^m returnType ifNotNil: [:type| ^self baseTypeForType: type]].
+ ^self returnTypeForSend: sendNode in: aTMethod!
Item was changed:
----- Method: CogIA32Compiler>>computeShiftRRSize (in category 'generate machine code') -----
computeShiftRRSize
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into ecx."
| shiftCountReg |
shiftCountReg := operands at: 0.
+ ^shiftCountReg = ECX
+ ifTrue: [2]
+ ifFalse:
+ [shiftCountReg = EAX
+ ifTrue: [1 "XCHG EAX,r2" + 2 "Sxx" + 1 "XCHG EAX,r2"]
+ ifFalse: [2 "XCHG r1,r2" + 2 "Sxx" + 2 "XCHG r1,r2"]]!
- shiftCountReg = ECX ifTrue:
- [^maxSize := 2].
- ^maxSize := shiftCountReg = EAX
- ifTrue: [1 "XCHG EAX,r2" + 2 "Sxx" + 1 "XCHG EAX,r2"]
- ifFalse: [2 "XCHG r1,r2" + 2 "Sxx" + 2 "XCHG r1,r2"]!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>genJumpNotSmallFloat:scratchReg: (in category 'compile abstract instructions') -----
genJumpNotSmallFloat: reg scratchReg: scratch
"Generate a compare and branch to test if aRegister contains other than a SmallFloat.
Answer the jump."
+ ^cogit
+ AndCq: objectMemory tagMask R: reg R: scratch;
+ CmpCq: objectMemory smallFloatTag R: scratch;
+ JumpNonZero: 0!
- cogit AndCq: objectMemory tagMask R: reg R: scratch.
- cogit CmpCq: objectMemory smallFloatTag R: scratch.
- ^cogit JumpNonZero: 0!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>genJumpNotSmallFloatInScratchReg: (in category 'compile abstract instructions') -----
genJumpNotSmallFloatInScratchReg: aRegister
+ <inline: true>
+ ^self genJumpNotSmallFloat: aRegister scratchReg: aRegister!
- ^self genJumpNotSmallFloat: aRegister scratchReg: TempReg!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>genJumpNotSmallIntegerInScratchReg: (in category 'compile abstract instructions') -----
genJumpNotSmallIntegerInScratchReg: aRegister
+ <inline: true>
+ ^self genJumpNotSmallInteger: aRegister scratchReg: aRegister!
- ^self genJumpNotSmallInteger: aRegister scratchReg: TempReg!
Item was changed:
----- Method: CogX64Compiler>>computeShiftRRSize (in category 'generate machine code') -----
computeShiftRRSize
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into ecx."
| shiftCountReg |
shiftCountReg := operands at: 0.
+ ^shiftCountReg = RCX
+ ifTrue: [3]
+ ifFalse:
+ [shiftCountReg = RAX
+ ifTrue: [2 "XCHG RAX,r2" + 3 "Sxx" + 2 "XCHG RAX,r2"]
+ ifFalse: [3 "XCHG r1,r2" + 3 "Sxx" + 3 "XCHG r1,r2"]]!
- shiftCountReg = RCX ifTrue:
- [^maxSize := 3].
- ^maxSize := shiftCountReg = RAX
- ifTrue: [2 "XCHG RAX,r2" + 3 "Sxx" + 2 "XCHG RAX,r2"]
- ifFalse: [3 "XCHG r1,r2" + 3 "Sxx" + 3 "XCHG r1,r2"]!
Item was changed:
----- Method: Cogit>>generateInstructionsAt: (in category 'generate machine code') -----
generateInstructionsAt: eventualAbsoluteAddress
"Size pc-dependent instructions and assign eventual addresses to all instructions.
Answer the size of the code.
Compute forward branches based on virtual address (abstract code starts at 0),
assuming that any branches branched over are long.
Compute backward branches based on actual address.
Reuse the fixups array to record the pc-dependent instructions that need to have
their code generation postponed until after the others."
| absoluteAddress pcDependentIndex abstractInstruction fixup |
<var: #abstractInstruction type: #'AbstractInstruction *'>
<var: #fixup type: #'BytecodeFixup *'>
absoluteAddress := eventualAbsoluteAddress.
pcDependentIndex := 0.
0 to: opcodeIndex - 1 do:
[:i|
+ self cCode: [] inSmalltalk: [self maybeBreakAt: absoluteAddress].
- self maybeBreakAt: absoluteAddress.
abstractInstruction := self abstractInstructionAt: i.
abstractInstruction isPCDependent
ifTrue:
[abstractInstruction sizePCDependentInstructionAt: absoluteAddress.
fixup := self fixupAt: pcDependentIndex.
pcDependentIndex := pcDependentIndex + 1.
fixup instructionIndex: i.
absoluteAddress := absoluteAddress + abstractInstruction machineCodeSize]
ifFalse:
[absoluteAddress := abstractInstruction concretizeAt: absoluteAddress]].
0 to: pcDependentIndex - 1 do:
[:j|
fixup := self fixupAt: j.
abstractInstruction := self abstractInstructionAt: fixup instructionIndex.
+ self cCode: [] inSmalltalk: [self maybeBreakAt: abstractInstruction address].
- self maybeBreakAt: abstractInstruction address.
abstractInstruction concretizeAt: abstractInstruction address].
^absoluteAddress - eventualAbsoluteAddress!
Item was changed:
----- Method: Cogit>>maybeBreakAt: (in category 'simulation only') -----
maybeBreakAt: address
+ <doNotGenerate>
((breakPC isBreakpointFor: address)
and: [breakBlock shouldStopIfAtPC: address]) ifTrue:
[coInterpreter changed: #byteCountText.
self halt: 'machine code breakpoint at ', address hex, ' in ', thisContext sender selector]!
Item was changed:
----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatSquareRoot (in category 'primitive generators') -----
genPrimitiveSmallFloatSquareRoot
<option: #Spur64BitMemoryManager>
"Stack looks like
receiver (also in ResultReceiverReg)
return address"
| jumpFailAlloc |
<var: #jumpFailAlloc type: #'AbstractInstruction *'>
+ objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg scratch: SendNumArgsReg into: DPFPReg0.
- objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg into: DPFPReg0.
self SqrtRd: DPFPReg0.
jumpFailAlloc := objectRepresentation
genAllocFloatValue: DPFPReg0
into: SendNumArgsReg
scratchReg: ClassReg
scratchReg: TempReg.
self MoveR: SendNumArgsReg R: ReceiverResultReg.
self RetN: (self primRetNOffsetFor: 0).
jumpFailAlloc jmpTarget: self Label.
^self compileFallbackToInterpreterPrimitive: 0!
Item was changed:
----- Method: TMethod>>addTypesFor:to:in: (in category 'type inference') -----
addTypesFor: node to: typeSet in: aCodeGen
+ "Add the value tupes for the node to typeSet.
+ Answer if any type was derived from an as-yet-untyped method, which allows us to abort
+ inferReturnTypeFromReturnsIn: if the return type depends on a yet-to-be-typed method."
| expr |
expr := node.
[expr isAssignment or: [expr isStmtList]] whileTrue:
[expr isAssignment ifTrue:
[expr := expr variable].
expr isStmtList ifTrue:
[expr := expr statements last]].
expr isSend ifTrue:
[(#(ifTrue: ifFalse: ifTrue:ifFalse: ifFalse:ifTrue:) includes: expr selector) ifTrue:
+ [^expr args
+ inject: false
+ into: [:asYetUntyped :block|
+ asYetUntyped := asYetUntyped | (self addTypesFor: block to: typeSet in: aCodeGen)]].
- [^expr args do:
- [:block|
- self addTypesFor: block to: typeSet in: aCodeGen]].
(#(= ~= == ~~ < > <= >= anyMask: noMask:) includes: expr selector) ifTrue:
+ [typeSet add: #sqInt. ^false].
- [^typeSet add: #sqInt].
(#(+ - * / // \\ mod: quo: bitAnd: bitClear: bitOr: bitXor: bitShift:) includes: expr selector) ifTrue:
[| types |
types := Set new.
self addTypesFor: expr receiver to: types in: aCodeGen.
(types size = 1 and: [types anyOne last = $*]) ifTrue: "pointer arithmetic"
+ [typeSet add: types anyOne. ^false].
- [^typeSet add: types anyOne].
self addTypesFor: expr args first to: types in: aCodeGen.
types := aCodeGen harmonizeReturnTypesIn: types.
types size = 2 ifTrue:
[(types includes: #double) ifTrue:
+ [typeSet add: #double. ^false].
- [^typeSet add: #double].
(types includes: #float) ifTrue:
+ [typeSet add: #float. ^false].
+ ^false]. "don't know; leave unspecified."
+ types notEmpty ifTrue:
+ [typeSet add: types anyOne].
+ ^false].
+ ^(aCodeGen returnTypeForSend: expr in: self)
+ ifNotNil: [:type| typeSet add: type. false]
+ ifNil: [(aCodeGen methodNamed: expr selector) notNil]]. "Abort only for untyped methods that will be typed"
- [^typeSet add: #float].
- ^self]. "don't know; leave unspecified."
- ^types notEmpty ifTrue:
- [typeSet add: types anyOne]].
- ^(aCodeGen returnTypeForSend: expr in: self) ifNotNil:
- [:type| typeSet add: type]].
expr isVariable ifTrue:
[(aCodeGen typeOfVariable: expr name)
ifNotNil: [:type| typeSet add: type]
ifNil: [typeSet add: (expr name = 'self'
ifTrue: [#void]
ifFalse: [#sqInt])]].
expr isConstant ifTrue:
[| val |
val := expr value.
val isInteger ifTrue:
[typeSet add: ((val >= 0 ifTrue: [val] ifFalse: [-1 - val]) highBit <= 32
ifTrue: [#sqInt]
ifFalse: [#sqLong])].
(#(nil true false) includes: val) ifTrue:
[typeSet add: #sqInt].
val isFloat ifTrue:
+ [typeSet add: #float]].
+ ^false!
- [typeSet add: #float]]!
Item was changed:
----- Method: TMethod>>inferReturnTypeFromReturnsIn: (in category 'type inference') -----
inferReturnTypeFromReturnsIn: aCodeGen
"Attempt to infer the return type of the receiver from returns in the parse tree."
"this for determining which returns have which return types:"
"aCodeGen
pushScope: declarations
while: [parseTree
nodesSelect: [:n| n isReturn]
thenCollect: [:n| | s |
s := Set new.
self addTypesFor: n expression to: s in: aCodeGen.
{n. s}]]"
aCodeGen maybeBreakForTestToInline: selector in: self.
+ returnType ifNotNil: [^self].
+ aCodeGen
+ pushScope: declarations
+ while:
+ [| hasReturn returnTypes |
+ hasReturn := false.
+ returnTypes := Set new.
+ "Debug:
+ (| rettypes |
+ rettypes := Dictionary new.
+ parseTree nodesDo:
+ [:node|
+ node isReturn ifTrue:
+ [| types |
+ self addTypesFor: node expression to: (types := Set new) in: aCodeGen.
+ rettypes at: node expression put: types]].
+ rettypes)"
+ parseTree nodesDo:
+ [:node|
+ node isReturn ifTrue:
+ [hasReturn := true.
+ "If we encounter a send of an as-yet-untyped method then abort,
+ retrying and computing the type when that method is fully typed."
+ (self addTypesFor: node expression to: returnTypes in: aCodeGen) ifTrue:
+ [^self]]].
+ returnTypes remove: #implicit ifAbsent: [].
+ returnTypes := aCodeGen harmonizeReturnTypesIn: returnTypes.
+ hasReturn
+ ifTrue:
+ [returnTypes size > 1 ifTrue:
+ [| message |
+ message := String streamContents:
+ [:s|
+ s nextPutAll: 'conflicting return types '.
+ returnTypes
+ do: [:t| s nextPutAll: t]
+ separatedBy: [s nextPutAll: ', '].
+ s nextPutAll: ' in '; nextPutAll: selector; cr].
+ Notification signal: message.
+ aCodeGen logger show: message].
+ returnTypes size = 1 ifTrue:
+ [self returnType: returnTypes anyOne]]
+ ifFalse:
+ [self returnType: (aCodeGen implicitReturnTypeFor: selector)]]!
- returnType ifNil: "the initial default"
- [aCodeGen
- pushScope: declarations
- while:
- [| hasReturn returnTypes |
- hasReturn := false.
- returnTypes := Set new.
- "Debug:
- (| rettypes |
- rettypes := Dictionary new.
- parseTree nodesDo:
- [:node|
- node isReturn ifTrue:
- [| types |
- self addTypesFor: node expression to: (types := Set new) in: aCodeGen.
- rettypes at: node expression put: types]].
- rettypes)"
- parseTree nodesDo:
- [:node|
- node isReturn ifTrue:
- [hasReturn := true.
- self addTypesFor: node expression to: returnTypes in: aCodeGen]].
- returnTypes remove: #implicit ifAbsent: [].
- returnTypes := aCodeGen harmonizeReturnTypesIn: returnTypes.
- hasReturn
- ifTrue:
- [returnTypes size > 1 ifTrue:
- [| message |
- message := String streamContents:
- [:s|
- s nextPutAll: 'conflicting return types '.
- returnTypes
- do: [:t| s nextPutAll: t]
- separatedBy: [s nextPutAll: ', '].
- s nextPutAll: ' in '; nextPutAll: selector; cr].
- Notification signal: message.
- aCodeGen logger show: message].
- returnTypes size = 1 ifTrue:
- [self returnType: returnTypes anyOne]]
- ifFalse:
- [self returnType: (aCodeGen implicitReturnTypeFor: selector)]]]!
Item was changed:
----- Method: TMethod>>inferTypesForImplicitlyTypedVariablesIn: (in category 'type inference') -----
inferTypesForImplicitlyTypedVariablesIn: aCodeGen
"infer types for untyped variables from assignments and arithmetic uses.
For debugging answer a Dictionary from var to the nodes that determined types
This for debugging:
(self copy inferTypesForImplicitlyTypedVariablesIn: aCodeGen)"
| alreadyExplicitlyTyped effectiveNodes |
aCodeGen maybeBreakForTestToInline: selector in: self.
alreadyExplicitlyTyped := declarations keys asSet.
effectiveNodes := Dictionary new. "this for debugging"
parseTree nodesDo:
[:node| | type var |
"If there is something of the form i >= 0, then i should be signed, not unsigned."
(node isSend
and: [(locals includes: (var := node receiver variableNameOrNil))
and: [(alreadyExplicitlyTyped includes: var) not "don't be fooled by inferred unsigned types"
and: [(#(<= < >= >) includes: node selector)
and: [node args first isConstant
and: [node args first value = 0
and: [(type := self typeFor: var in: aCodeGen) notNil
and: [type first == $u]]]]]]]) ifTrue:
[declarations at: var put: (aCodeGen signedTypeForIntegralType: type), ' ', var.
effectiveNodes at: var put: { declarations at: var. node }].
"if an assignment to an untyped local of a known type, set the local's type to that type.
Only observe known sends (methods in the current set) and typed local variables."
(node isAssignment
and: [(locals includes: (var := node variable name))
and: [(alreadyExplicitlyTyped includes: var) not "don't be fooled by previously inferred types"
and: [(type := node expression isSend
+ ifTrue: [aCodeGen returnTypeOrNilForSend: node expression in: self]
- ifTrue: [aCodeGen returnTypeForSend: node expression in: self]
ifFalse: [self typeFor: node expression in: aCodeGen]) notNil
and: [aCodeGen isSimpleType: type]]]]) ifTrue:
[aCodeGen mergeTypeOf: var in: declarations with: type method: self.
effectiveNodes at: var put: { declarations at: var. node }, (effectiveNodes at: var ifAbsent: [#()])]].
^effectiveNodes!
1
0
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1613.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1613
Author: eem
Time: 26 December 2015, 8:28:05.311 pm
UUID: c484a2ad-5f40-4de8-a9c2-3c4f4a4942aa
Ancestors: VMMaker.oscog-eem.1612
SpurMemoryManagers: Add Spur32BitMemoryManager or Spur64BitMemoryManager to the options so that Cogit can select small float prims properly.
Cogit:
Improve instruction printing so that floating point ops print with the right register names. Refactor computing the print format to allow special casing throughout the CogAbstractInstruction hierarchy.
Split out the abstract register names from CogRTLOpcodes to CogAbstractRegisters so that the mapping from opcode index to opcode name (and indeed the mapping from register index to register name) works straight-forwardly without hacks to prevent register index and opcode index confusion.
Make initializeAbstractRegisters initialize all abstract registers to #undefined before defining the used subset to the relevant concrete registers.
Nuke unused method.
=============== Diff against VMMaker.oscog-eem.1612 ===============
Item was changed:
TestCase subclass: #AbstractInstructionTests
instanceVariableNames: 'processor opcodes'
classVariableNames: ''
+ poolDictionaries: 'CogAbstractRegisters CogRTLOpcodes'
- poolDictionaries: 'CogRTLOpcodes'
category: 'VMMaker-Tests'!
Item was changed:
----- Method: CogARMCompiler class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"N.B. According to BSABI, R0-R3 are caller-save, R4-R12 are callee save.
Note that R9 might be a special register for the implementation. In some slides
it is refered to as sb. R10 can contain the stack limit (sl), R11 the fp. R12 is an
intra-procedure scratch instruction pointer for link purposes. It can also be used.
R10 is used as temporary inside a single abstract opcode implementation"
"R0-R3 are used when calling back to the interpreter. Using them would require
saving and restoring their values, so they are omitted so far. R12 is the only
scratch register at the moment.."
+ super initializeAbstractRegisters.
+
TempReg := R0.
ClassReg := R8.
ReceiverResultReg := R7.
SendNumArgsReg := R6.
SPReg := SP. "R13"
FPReg := R11.
Arg0Reg := R4.
Arg1Reg := R5.
VarBaseReg := ConcreteVarBaseReg. "Must be callee saved"
RISCTempReg := ConcreteIPReg. "a.k.a. IP"
Scratch0Reg := R12.
LinkReg := LR. "R14"
PCReg := PC. "R15"
DPFPReg0 := D0.
DPFPReg1 := D1.
DPFPReg2 := D2.
DPFPReg3 := D3.
DPFPReg4 := D4.
DPFPReg5 := D5.
DPFPReg6 := D6.
DPFPReg7 := D7
!
Item was added:
+ ----- Method: CogARMCompiler>>nameForFPRegister: (in category 'printing') -----
+ nameForFPRegister: reg "<Integer>"
+ <doNotGenerate>
+ (reg between: 0 and: 7) ifTrue:
+ [^#(D0 D1 D2 D3 D4 D5 D6 D7) at: reg + 1].
+ ^super nameForFPRegister: reg!
Item was changed:
VMStructType subclass: #CogAbstractInstruction
instanceVariableNames: 'opcode machineCodeSize maxSize annotation machineCode operands address dependent cogit objectMemory bcpc'
classVariableNames: 'NumOperands'
+ poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogRTLOpcodes'
- poolDictionaries: 'CogCompilationConstants CogRTLOpcodes'
category: 'VMMaker-JIT'!
!CogAbstractInstruction commentStamp: 'eem 4/21/2015 09:12' prior: 0!
I am an abstract instruction generated by the Cogit. I am subsequently concretized to machine code for the current processor. A sequence of concretized CogAbstractInstructions are concatenated to form the code for a CogMethod. I am an abstract class. My concrete subclasses concretize to the machine code of a specific processor.
Instance Variables
address: <Integer>
bcpc: <Integer>
cogit: <Cogit>
dependent: <AbstractInstruction|nil>
machineCode: <CArray on: (ByteArray|Array)>
machineCodeSize: <Integer>
maxSize: <Integer>
objectMemory: <NewCoObjectMemory|SpurCoMemoryManager etc>
opcode: <Integer>
operands: <CArray on: Array>
address
- the address at which the instruction will be generated
bcpc
- the bytecode pc for which the instruction was generated; simulation only
cogit
- the Cogit assembling the receiver; simulation only
dependent
- a reference to another instruction which depends on the receiver, if any; in C this is a pointer
machineCode
- the array of machine code the receiver generates when concretized
machineCodeSize
- the size of machineCode in bytes
maxSize
- the maximum size of machine code that the current instruction will generate, in bytes
objectMemory
- the memory manager for the system; simulation only
opcode
- the opcode for the receiver which defines which abstract opcode it represents; see CogRTLOpcodes class>>initialize and CogAbstractInstruction subclass initialize methods
operands
- the array containing any operands the instruction may have; the opcode defines implicitly how many operands are consdered!
Item was changed:
----- Method: CogAbstractInstruction class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
+ "Assign the abstract registers with the identities/indices of the relevant concrete registers.
+ First set all abstract registers to #undefined via CogAbstractRegisters initialize, and then,
+ each subclasses assigns the subset they choose with values of specific concrete registers."
+ CogAbstractRegisters initialize!
- "Assign the abstract registers with the identities/indices of the relevant concrete registers."
- self subclassResponsibility!
Item was added:
+ ----- Method: CogAbstractInstruction class>>printFormatForOpcodeName: (in category 'debug printing') -----
+ printFormatForOpcodeName: opcodeName
+ "Answer a sequence of $r, $f or nil for the operands in the opcode, used for printing, where
+ r => integer register, f => floating point register, and nil => numeric or address operand.
+ Subclasses can override to provide a format string for their own private opcodes."
+ ^#()!
Item was added:
+ ----- Method: CogAbstractInstruction>>nameForFPRegister: (in category 'printing') -----
+ nameForFPRegister: reg "<Integer>"
+ "subclasses with special purpose registers may need to override."
+ <doNotGenerate>
+ ^CogAbstractRegisters nameForFPRegister: reg!
Item was changed:
----- Method: CogAbstractInstruction>>nameForRegister: (in category 'printing') -----
nameForRegister: reg "<Integer>"
"subclasses with special purpose registers may need to override."
<doNotGenerate>
+ ^CogAbstractRegisters nameForRegister: reg!
- ^CogRTLOpcodes nameForRegister: reg!
Item was changed:
----- Method: CogAbstractInstruction>>printStateOn: (in category 'printing') -----
printStateOn: aStream
| opcodeName orneryOperands format |
<doNotGenerate> "Smalltalk-side only"
opcode ifNil:
[^self].
aStream space; nextPut: $(; nextPutAll: (opcodeName := self class nameForOpcode: opcode).
orneryOperands := operands isCObjectAccessor
ifTrue: [operands object]
ifFalse: [operands].
+ format := ((CogRTLOpcodes classPool includesKey: opcodeName)
+ ifTrue: [CogRTLOpcodes]
+ ifFalse: [self class]) printFormatForOpcodeName: opcodeName.
- format := [CogRTLOpcodes printFormatForOpcodeName: opcodeName]
- on: Error
- do: [:ex| ].
orneryOperands withIndexDo:
[:operand :index|
operand ifNotNil:
[aStream space.
index >= (orneryOperands identityIndexOf: nil ifAbsent: [orneryOperands size + 1]) ifTrue:
[aStream print: index - 1; nextPut: $:].
+ (format notNil and: ['rf' includes: (format at: index ifAbsent: $-)])
+ ifTrue: [aStream nextPutAll: ((format at: index) = $r
+ ifTrue: [self nameForRegister: operand]
+ ifFalse: [self nameForFPRegister: operand])]
- (format notNil and: [(format at: index ifAbsent: nil) = $r])
- ifTrue: [aStream nextPutAll: (self nameForRegister: operand)]
ifFalse:
[aStream print: operand.
(operand isInteger and: [operand > 16 and: [opcode ~= Label]]) ifTrue:
[(operand allMask: 16r80000000) ifTrue:
[aStream nextPut: $/; print: operand signedIntFromLong].
aStream nextPut: $/.
operand printOn: aStream base: 16]]]].
machineCodeSize ifNotNil:
[(machineCodeSize between: 1 and: machineCode size) ifTrue:
[0 to: machineCodeSize - 1 by: self codeGranularity do:
[:i|
aStream space.
(self machineCodeAt: i)
ifNil: [aStream nextPut: $.]
ifNotNil:
[:mc|
mc isInteger
ifTrue: [mc printOn: aStream base: 16]
ifFalse: [mc printOn: aStream]]]]].
address ifNotNil:
[aStream nextPut: $@.
address printOn: aStream base: 16].
aStream nextPut: $)!
Item was added:
+ SharedPool subclass: #CogAbstractRegisters
+ instanceVariableNames: ''
+ classVariableNames: 'Arg0Reg Arg1Reg ClassReg DPFPReg0 DPFPReg1 DPFPReg10 DPFPReg11 DPFPReg12 DPFPReg13 DPFPReg14 DPFPReg15 DPFPReg2 DPFPReg3 DPFPReg4 DPFPReg5 DPFPReg6 DPFPReg7 DPFPReg8 DPFPReg9 FPReg LinkReg NoReg PCReg RISCTempReg ReceiverResultReg SPReg Scratch0Reg Scratch1Reg Scratch2Reg Scratch3Reg Scratch4Reg Scratch5Reg Scratch6Reg Scratch7Reg SendNumArgsReg TempReg VarBaseReg'
+ poolDictionaries: ''
+ category: 'VMMaker-JIT'!
+
+ !CogAbstractRegisters commentStamp: 'eem 12/26/2015 14:06' prior: 0!
+ I am a pool for the abstract register set that the Cogit uses to define its model of Smalltalk compiled to machine code.!
Item was added:
+ ----- Method: CogAbstractRegisters class>>initialize (in category 'class initialization') -----
+ initialize
+ "Define a fixed set of abstract register names used in code generation for Smalltalk code.
+ These are given concrete values by the currently in-use back end, which is a subclass of
+ CogAbstractInstruction; see implementors of initializeAbstractRegisters.
+
+ We assume concrete registers defined by the back ends are in the range 0 to N, possibly
+ with integer registers and floating-point registers using overlapping ranges of indices.
+ Here we initialize all registers to #undefined, leaving it to initializeAbstractRegisters to
+ initialize the subset of the abstract registers that a platform actually uses."
+
+ "NoReg encodes no register, e.g. for parameters that supply an optional register.
+ Being negative it is distinct from abstract and concrete registers in the 0 to N range."
+ NoReg := -1.
+
+ "The core set of abstract registers that define the Cogit's model of Smalltalk code
+ provide for a register-based calling convention oriented towards inline cacheing and
+ executing a core set of machine code primitives in registers. The set is composed of
+ 8 registers, dictated by the available registers on IA32."
+ "Smalltalk machine code executes on stack pages in the stack zone, requiring frame and stack pointers."
+ FPReg := #undefined. "A frame pointer is used for Smalltalk frames."
+ SPReg := #undefined.
+ ReceiverResultReg := #undefined. "The receiver at point of send, and return value of a send"
+ ClassReg := #undefined. "The inline send cache class tag is in this register, loaded at the send site"
+ SendNumArgsReg := #undefined. "Sends > 2 args set the arg count in this reg"
+ Arg0Reg := #undefined. "In the StackToRegisterMappingCogit 1 & 2 arg sends marshall into these registers."
+ Arg1Reg := #undefined.
+ TempReg := #undefined.
+
+ "A small fixed set of abstract scratch registers for register-rich machines (ARM can use 1, x64 can use 6 or 7)."
+ Scratch0Reg := #undefined.
+ Scratch1Reg := #undefined.
+ Scratch2Reg := #undefined.
+ Scratch3Reg := #undefined.
+ Scratch4Reg := #undefined.
+ Scratch5Reg := #undefined.
+ Scratch6Reg := #undefined.
+ Scratch7Reg := #undefined.
+
+ "RISC-specific registers"
+ LinkReg := #undefined.
+ RISCTempReg := #undefined. "Used to synthesize CISC instructions from multiple RISC instructions."
+ PCReg := #undefined. "If the processor has an assignable pc, e.g. ARM"
+ VarBaseReg := #undefined. "If useful, points to base of interpreter variables."
+
+ "Up to 16 floating-point registers. e.g. IA32+SSE2 can use 8, x64 can use 16."
+ DPFPReg0 := #undefined.
+ DPFPReg1 := #undefined.
+ DPFPReg2 := #undefined.
+ DPFPReg3 := #undefined.
+ DPFPReg4 := #undefined.
+ DPFPReg5 := #undefined.
+ DPFPReg6 := #undefined.
+ DPFPReg7 := #undefined.
+ DPFPReg8 := #undefined.
+ DPFPReg9 := #undefined.
+ DPFPReg10 := #undefined.
+ DPFPReg11 := #undefined.
+ DPFPReg12 := #undefined.
+ DPFPReg13 := #undefined.
+ DPFPReg14 := #undefined.
+ DPFPReg15 := #undefined!
Item was added:
+ ----- Method: CogAbstractRegisters class>>nameForFPRegister: (in category 'debug printing') -----
+ nameForFPRegister: reg "<Integer>"
+ ^#(DPFPReg0 DPFPReg1 DPFPReg2 DPFPReg3 DPFPReg4 DPFPReg5 DPFPReg6 DPFPReg7
+ DPFPReg8 DPFPReg9 DPFPReg10 DPFPReg11 DPFPReg12 DPFPReg13 DPFPReg14 DPFPReg15)
+ detect: [:sym| (classPool at: sym) = reg]
+ ifNone: ['REG', reg printString, '?']!
Item was added:
+ ----- Method: CogAbstractRegisters class>>nameForRegister: (in category 'debug printing') -----
+ nameForRegister: reg "<Integer>"
+ ^#(Arg0Reg Arg1Reg ClassReg FPReg ReceiverResultReg SPReg SendNumArgsReg TempReg
+ LinkReg RISCTempReg VarBaseReg PCReg
+ Scratch0Reg Scratch1Reg Scratch2Reg Scratch3Reg Scratch4Reg Scratch5Reg)
+ detect: [:sym| (classPool at: sym) = reg]
+ ifNone: ['REG', reg printString, '?']!
Item was changed:
----- Method: CogIA32Compiler class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"N.B. EAX ECX & EDX are caller-save (scratch) registers. Hence we use ECX for class and EDX for
receiver/result since these are written in all normal sends. EBX ESI & EDI are callee-save."
+ super initializeAbstractRegisters.
+
TempReg := EAX.
ClassReg := ECX.
ReceiverResultReg := EDX.
SendNumArgsReg := EBX.
SPReg := ESP.
FPReg := EBP.
Arg0Reg := ESI.
Arg1Reg := EDI.
+ DPFPReg0 := XMM0L.
+ DPFPReg1 := XMM1L.
+ DPFPReg2 := XMM2L.
+ DPFPReg3 := XMM3L.
+ DPFPReg4 := XMM4L.
+ DPFPReg5 := XMM5L.
+ DPFPReg6 := XMM6L.
+ DPFPReg7 := XMM7L!
- DPFPReg0 := XMM0L / 2.
- DPFPReg1 := XMM1L / 2.
- DPFPReg2 := XMM2L / 2.
- DPFPReg3 := XMM3L / 2.
- DPFPReg4 := XMM4L / 2.
- DPFPReg5 := XMM5L / 2.
- DPFPReg6 := XMM6L / 2.
- DPFPReg7 := XMM7L / 2!
Item was changed:
----- Method: CogInLineLiteralsX64Compiler class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
- "[1] Figure 3.4 Register Usage in
- System V Application Binary Interface
- AMD64 Architecture Processor Supplement
+ super initializeAbstractRegisters.
+ RISCTempReg := R8!
- N.B. RAX RCX & RDX are caller-save (scratch) registers. Hence we use RCX for class and RDX for
- receiver/result since these are written in all normal sends."
-
- TempReg := RAX.
- ClassReg := RCX.
- ReceiverResultReg := RDX.
- SendNumArgsReg := R9.
- SPReg := RSP.
- FPReg := RBP.
- Arg0Reg := RDI. "So as to agree with C ABI arg 0"
- Arg1Reg := RSI. "So as to agree with C ABI arg 1"
- VarBaseReg := RBX. "Must be callee saved"
- RISCTempReg := R8.
- Scratch0Reg := R10.
- Scratch1Reg := R11.
- Scratch2Reg := R12.
- Scratch3Reg := R13.
- Scratch4Reg := R14.
- Scratch5Reg := R15.
-
- DPFPReg0 := XMM0L / 2.
- DPFPReg1 := XMM1L / 2.
- DPFPReg2 := XMM2L / 2.
- DPFPReg3 := XMM3L / 2.
- DPFPReg4 := XMM4L / 2.
- DPFPReg5 := XMM5L / 2.
- DPFPReg6 := XMM6L / 2.
- DPFPReg7 := XMM7L / 2!
Item was changed:
----- Method: CogMIPSELCompiler class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"See MIPSConstants>>initializeRegisters for a description of the C ABI."
"Note we can fit all of the abstract registers in C preserved registers, and
not need to save or restore them at runtime calls."
+ super initializeAbstractRegisters.
+
ReceiverResultReg := S0.
Arg0Reg := S1.
Arg1Reg := S2.
ClassReg := S3.
SendNumArgsReg := S4.
TempReg := S5.
VarBaseReg := S6. "Must be callee saved"
SPReg := SP.
FPReg := FP.
RISCTempReg := AT.
LinkReg := RA!
Item was added:
+ ----- Method: CogMIPSELCompiler class>>printFormatForOpcodeName: (in category 'debug printing') -----
+ printFormatForOpcodeName: opcodeName
+ "Answer a sequence of $r, $f or nil for the operands in the opcode, used for printing, where
+ r => integer register, f => floating point register, and nil => numeric or address operand.
+ Subclasses can override to provide a format string for their own private opcodes."
+ ^(opcodeName startsWith: 'Br') ifTrue: [' rr'] ifFalse: [#()]!
Item was changed:
CogClass subclass: #CogObjectRepresentation
instanceVariableNames: 'cogit methodZone objectMemory coInterpreter ceStoreCheckTrampoline'
classVariableNames: ''
+ poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogMethodConstants CogRTLOpcodes VMBasicConstants VMObjectIndices VMSqueakClassIndices VMStackFrameOffsets'
- poolDictionaries: 'CogCompilationConstants CogMethodConstants CogRTLOpcodes VMBasicConstants VMObjectIndices VMSqueakClassIndices VMStackFrameOffsets'
category: 'VMMaker-JIT'!
!CogObjectRepresentation commentStamp: '<historical>' prior: 0!
I am an abstract superclass for object representations whose job it is to generate abstract instructions for accessing objects. It is hoped that this level of indirection between the Cogit code generator and object access makes it easier to adapt the code generator to different garbage collectors, object representations and languages.!
Item was changed:
----- Method: CogOutOfLineLiteralsX64Compiler class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
- "[1] Figure 3.4 Register Usage in
- System V Application Binary Interface
- AMD64 Architecture Processor Supplement
+ super initializeAbstractRegisters.
+ Scratch6Reg := R8!
- N.B. RAX RCX & RDX are caller-save (scratch) registers. Hence we use RCX for class and RDX for
- receiver/result since these are written in all normal sends."
-
- TempReg := RAX.
- ClassReg := RCX.
- ReceiverResultReg := RDX.
- SendNumArgsReg := R9.
- SPReg := RSP.
- FPReg := RBP.
- Arg0Reg := RDI. "So as to agree with C ABI arg 0"
- Arg1Reg := RSI. "So as to agree with C ABI arg 1"
- VarBaseReg := RBX. "Must be callee saved"
- "No need for a RISCTempReg because out-of-line literal loads imply no need for a special MoveCwR"
- "RISCTempReg := R8."
- Scratch0Reg := R10.
- Scratch1Reg := R11.
- Scratch2Reg := R12.
- Scratch3Reg := R13.
- Scratch4Reg := R14.
- Scratch5Reg := R15.
- Scratch6Reg := R8.
-
- DPFPReg0 := XMM0L / 2.
- DPFPReg1 := XMM1L / 2.
- DPFPReg2 := XMM2L / 2.
- DPFPReg3 := XMM3L / 2.
- DPFPReg4 := XMM4L / 2.
- DPFPReg5 := XMM5L / 2.
- DPFPReg6 := XMM6L / 2.
- DPFPReg7 := XMM7L / 2!
Item was changed:
SharedPool subclass: #CogRTLOpcodes
instanceVariableNames: ''
+ classVariableNames: 'AddCqR AddCwR AddRR AddRdRd AlignmentNops AndCqR AndCqRR AndCwR AndRR ArithmeticShiftRightCqR ArithmeticShiftRightRR Call CallFull CmpC32R CmpCqR CmpCwR CmpRR CmpRdRd ConvertRRd DivRdRd Fill32 FirstJump FirstShortJump Jump JumpAbove JumpAboveOrEqual JumpBelow JumpBelowOrEqual JumpCarry JumpFPEqual JumpFPGreater JumpFPGreaterOrEqual JumpFPLess JumpFPLessOrEqual JumpFPNotEqual JumpFPOrdered JumpFPUnordered JumpFull JumpGreater JumpGreaterOrEqual JumpLess JumpLessOrEqual JumpLong JumpLongNonZero JumpLongZero JumpNegative JumpNoCarry JumpNoOverflow JumpNonNegative JumpNonZero JumpOverflow JumpR JumpZero Label LastJump LastRTLCode Literal LoadEffectiveAddressMwrR LoadEffectiveAddressXowrR LogicalShiftLeftCqR LogicalShiftLeftRR LogicalShiftRightCqR LogicalShiftRightRR MoveAbR MoveAwR MoveC32R MoveC64R MoveCqR MoveCwR MoveM16rR MoveM32rR MoveM64rRd MoveMbrR MoveMwrR MoveRAb MoveRAw MoveRM16r MoveRM32r MoveRMbr MoveRMwr MoveRR MoveRRd MoveRX16rR MoveRX32rR MoveRXbrR MoveRXowr MoveRXwrR MoveRdM64r MoveRdR MoveRdRd MoveX16rRR MoveX32rRR MoveXbrRR MoveXowrR MoveXwrRR MulRdRd NegateR Nop OrCqR OrCwR OrRR PopR PrefetchAw PushCq PushCw PushR RetN RotateLeftCqR RotateRightCqR SqrtRd Stop SubCqR SubCwR SubRR SubRdRd TstCqR XorCqR XorCwR XorRR'
- classVariableNames: 'AddCqR AddCwR AddRR AddRdRd AlignmentNops AndCqR AndCqRR AndCwR AndRR Arg0Reg Arg1Reg ArithmeticShiftRightCqR ArithmeticShiftRightRR Call CallFull ClassReg CmpC32R CmpCqR CmpCwR CmpRR CmpRdRd ConvertRRd DPFPReg0 DPFPReg1 DPFPReg2 DPFPReg3 DPFPReg4 DPFPReg5 DPFPReg6 DPFPReg7 DivRdRd FPReg Fill32 FirstJump FirstShortJump Jump JumpAbove JumpAboveOrEqual JumpBelow JumpBelowOrEqual JumpCarry JumpFPEqual JumpFPGreater JumpFPGreaterOrEqual JumpFPLess JumpFPLessOrEqual JumpFPNotEqual JumpFPOrdered JumpFPUnordered JumpFull JumpGreater JumpGreaterOrEqual JumpLess JumpLessOrEqual JumpLong JumpLongNonZero JumpLongZero JumpNegative JumpNoCarry JumpNoOverflow JumpNonNegative JumpNonZero JumpOverflow JumpR JumpZero Label LastJump LastRTLCode LinkReg Literal LoadEffectiveAddressMwrR LoadEffectiveAddressXowrR LogicalShiftLeftCqR LogicalShiftLeftRR LogicalShiftRightCqR LogicalShiftRightRR MoveAbR MoveAwR MoveC32R MoveC64R MoveCqR MoveCwR MoveM16rR MoveM32rR MoveM64rRd MoveMbrR MoveMwrR MoveRAb MoveRAw MoveRM16r MoveRM32r MoveRMbr MoveRMwr MoveRR MoveRRd MoveRX16rR MoveRX32rR MoveRXbrR MoveRXowr MoveRXwrR MoveRdM64r MoveRdR MoveRdRd MoveX16rRR MoveX32rRR MoveXbrRR MoveXowrR MoveXwrRR MulRdRd NegateR NoReg Nop OrCqR OrCwR OrRR PCReg PopR PrefetchAw PushCq PushCw PushR RISCTempReg ReceiverResultReg RetN RotateLeftCqR RotateRightCqR SPReg Scratch0Reg Scratch1Reg Scratch2Reg Scratch3Reg Scratch4Reg Scratch5Reg Scratch6Reg Scratch7Reg SendNumArgsReg SqrtRd Stop SubCqR SubCwR SubRR SubRdRd TempReg TstCqR VarBaseReg XorCqR XorCwR XorRR'
poolDictionaries: ''
category: 'VMMaker-JIT'!
+ !CogRTLOpcodes commentStamp: 'eem 12/26/2015 14:00' prior: 0!
+ I am a pool for the Register-Transfer-Language to which Cog compiles. I define unique integer values for all RTL opcodes. See CogAbstractInstruction for instances of instructions with the opcodes that I define.!
- !CogRTLOpcodes commentStamp: '<historical>' prior: 0!
- I am a pool for the Register-Transfer-Language to which Cog compiles. I define unique integer values for all RTL opcodes and abstract registers. See CogAbstractInstruction for instances of instructions with the opcodes that I define.!
Item was changed:
----- Method: CogRTLOpcodes class>>initialize (in category 'class initialization') -----
initialize
"Abstract opcodes are a compound of a one word operation specifier and zero or more operand type specifiers.
The assembler is in Cogit protocol abstract instructions and uses `at&t' syntax, assigning to the register on the
right. e.g. MoveRR is the Move opcode with two register operand specifiers and defines a move register to
register instruction from operand 0 to operand 1. The word and register size is assumed to be either 32-bits
on a 32-bit architecture or 64-bits on a 64-bit architecture. The abstract machine is mostly a 2 address machine
with the odd three address instruction added to better exploit RISCs.
(self initialize)
The operand specifiers are
R - general purpose register
Rd - double-precision floating-point register
Cq - a `quick' constant that can be encoded in the minimum space possible.
Cw - a constant with word size where word is the default operand size for the Smalltalk VM, 32-bits
for a 32-bit VM, 64-bits for a 64-bit VM. The generated constant must occupy the default number
of bits. This allows e.g. a garbage collector to update the value without invalidating the code.
C32 - a constant with 32 bit size. The generated constant must occupy 32 bits.
C64 - a constant with 64 bit size. The generated constant must occupy 64 bits.
Aw - memory word at an absolute address
Ab - memory byte at an absolute address
Mwr - memory word whose address is at a constant offset from an address in a register
Mbr - memory byte whose address is at a constant offset from an address in a register (zero-extended on read)
M16r - memory 16-bit halfword whose address is at a constant offset from an address in a register
M32r - memory 32-bit halfword whose address is at a constant offset from an address in a register
M64r - memory 64-bit doubleword whose address is at a constant offset from an address in a register
+ Xbr - memory word whose address is r * byte size away from an address in a register
+ X16r - memory word whose address is r * (2 bytes size) away from an address in a register
+ X32r - memory word whose address is r * (4 bytes size) away from an address in a register
+ Xwr - memory word whose address is r * word size away from an address in a register
+ Xowr - memory word whose address is o + (r * word size) away from an address in a register (scaled indexed)
- XbrR - memory word whose address is r * byte size away from an address in a register
- X16rR - memory word whose address is r * (2 bytes size) away from an address in a register
- X32rR - memory word whose address is r * (4 bytes size) away from an address in a register
- XwrR - memory word whose address is r * word size away from an address in a register
- XowrR - memory word whose address is (r * word size) + o away from an address in a register (scaled indexed)
An alternative would be to decouple opcodes from operands, e.g.
Move := 1. Add := 2. Sub := 3...
RegisterOperand := 1. ConstantQuickOperand := 2. ConstantWordOperand := 3...
But not all combinations make sense and even fewer are used so we stick with the simple compound approach.
The assumption is that comparison and arithmetic instructions set condition codes and that move instructions
leave the condition codes unaffected. In particular LoadEffectiveAddressMwrR does not set condition codes
although it can be used to do arithmetic. On processors such as MIPS this distinction is invalid; there are no
condition codes. So the backend is allowed to collapse operation, branch pairs to internal instruciton definitions
(see sender and implementors of noteFollowingConditionalBranch:).
Not all of the definitions in opcodeDefinitions below are implemented. In particular we do not implement the
XowrR scaled index addressing mode since it requires 4 operands.
Not all instructions make sense on all architectures. MoveRRd and MoveRdR aqre meaningful only on 64-bit machines.
Note that there are no generic division instructions defined, but a processor may define some.
Branch/Call ranges. Jump[Cond] can be generated as short as possible. Call/Jump[Cond]Long must be generated
in the same number of bytes irrespective of displacement since their targets may be updated, but they need only
span 16Mb, the maximum size of the code zone. This allows e.g. ARM to use single-word call and jump instructions
for most calls and jumps. CallFull/JumpFull must also be generated in the same number of bytes irrespective of
displacement for the same reason, but they must be able to span the full (32-bit or 64-bit) address space because
they are used to call code in the C runtime, which may be distant from the code zone. CallFull/JumpFull are allowed
to use the cResultRegister as a scratch if required (e.g. on x64 where there is no direct 64-bit call or jump).
Byte reads. If the concrete compiler class answers true to byteReadsZeroExtend then byte reads must zero-extend
the byte read into the destination register. If not, the other bits of the register should be left undisturbed and the
Cogit will add an instruction to zero the register as required. Under no circumstances should byte reads sign-extend.
16-bit (and on 64-bits, 32-bit) reads. These /are/ expected to always zero-extend."
| opcodeNames refs |
- "A small fixed set of abstract register names are defined and used in code
- generation for Smalltalk code, which executes on stack pages in the stack zone."
-
- "NoReg encodes no register."
- NoReg := -1.
-
- "The core set of abstract registers that define the Cogits model of Smalltalk code.
- These are given concrete values by the currently in-use back end; see implementors
- of initializeAbstractRegisters."
- FPReg := #undefined. "A frame pointer is used for Smalltalk frames."
- SPReg := #undefined.
- ReceiverResultReg := #undefined. "The receiver at point of send, and return value of a send"
- TempReg := #undefined.
- ClassReg := #undefined. "The inline send cache class tag is in this register, loaded at the send site"
- SendNumArgsReg := #undefined. "Sends > 2 args set the arg count in this reg"
- Arg0Reg := #undefined. "In the StackToRegisterMappingCogit 1 & 2 arg sends marshall into these registers."
- Arg1Reg := #undefined.
-
- "A small fixed set of abstract scratch registers for register-rich machines (ARM can use 1, x64 can use 6 or 7)."
- Scratch0Reg := #undefined.
- Scratch1Reg := #undefined.
- Scratch2Reg := #undefined.
- Scratch3Reg := #undefined.
- Scratch4Reg := #undefined.
- Scratch5Reg := #undefined.
- Scratch6Reg := #undefined.
- Scratch7Reg := #undefined.
-
- "RISC-specific registers"
- LinkReg := #undefined.
- RISCTempReg := #undefined. "Used to synthesize CISC instructions from multiple RISC instructions."
- PCReg := #undefined. "If the processor has an assignable pc, e.g. ARM"
- VarBaseReg := #undefined. "If useful, points to base of interpreter variables."
-
- "Floating-point registers"
- DPFPReg0 := #undefined.
- DPFPReg1 := #undefined.
- DPFPReg2 := #undefined.
- DPFPReg3 := #undefined.
- DPFPReg4 := #undefined.
- DPFPReg5 := #undefined.
- DPFPReg6 := #undefined.
- DPFPReg7 := #undefined.
-
opcodeNames := #("Noops & Pseudo Ops"
Label
Literal "a word-sized literal"
AlignmentNops
Fill32 "output four byte's worth of bytes with operand 0"
Nop
"Control"
Call "call within the code zone"
CallFull "call anywhere within the full address space"
RetN
JumpR "Not a regular jump, i.e. not pc dependent."
Stop "Halt the processor"
"N.B. Jumps are contiguous. Long and Full jumps are contigiuous within them. See FirstJump et al below"
JumpFull "Jump anywhere within the address space"
JumpLong "Jump anywhere within the 16mb code zone."
JumpLongZero "a.k.a. JumpLongEqual"
JumpLongNonZero "a.k.a. JumpLongNotEqual"
Jump "short jumps; can be encoded in as few bytes as possible; will not be disturbed by GC or relocation."
JumpZero "a.k.a. JumpEqual"
JumpNonZero "a.k.a. JumpNotEqual"
JumpNegative
JumpNonNegative
JumpOverflow
JumpNoOverflow
JumpCarry
JumpNoCarry
JumpLess "signed"
JumpGreaterOrEqual
JumpGreater
JumpLessOrEqual
JumpBelow "unsigned"
JumpAboveOrEqual
JumpAbove
JumpBelowOrEqual
JumpFPEqual
JumpFPNotEqual
JumpFPLess
JumpFPLessOrEqual
JumpFPGreater
JumpFPGreaterOrEqual
JumpFPOrdered
JumpFPUnordered
"Data Movement; destination is always last operand"
MoveRR
MoveAwR
MoveRAw
MoveAbR
MoveRAb
MoveMwrR MoveRMwr MoveXwrRR MoveRXwrR MoveXowrR MoveRXowr
MoveM16rR MoveRM16r MoveX16rRR MoveRX16rR
MoveM32rR MoveRM32r MoveX32rRR MoveRX32rR
MoveMbrR MoveRMbr MoveXbrRR MoveRXbrR
MoveCqR MoveCwR MoveC32R MoveC64R
MoveRRd MoveRdR MoveRdRd MoveM64rRd MoveRdM64r
PopR PushR PushCq PushCw
PrefetchAw
"Arithmetic; destination is always last operand except Cmp; CmpXR is SubRX with no update of result"
LoadEffectiveAddressMwrR LoadEffectiveAddressXowrR "Variants of add/multiply"
NegateR "2's complement negation"
ArithmeticShiftRightCqR ArithmeticShiftRightRR
LogicalShiftRightCqR LogicalShiftRightRR
LogicalShiftLeftCqR LogicalShiftLeftRR
RotateLeftCqR RotateRightCqR
CmpRR AddRR SubRR AndRR OrRR XorRR
CmpCqR AddCqR SubCqR AndCqR OrCqR TstCqR XorCqR
CmpCwR CmpC32R AddCwR SubCwR AndCwR OrCwR XorCwR
AndCqRR "Three address ops for RISCs; feel free to add and extend"
CmpRdRd AddRdRd SubRdRd MulRdRd DivRdRd SqrtRd
"Conversion"
ConvertRRd
LastRTLCode).
"Magic auto declaration. Add to the classPool any new variables and nuke any obsolete ones, and assign values"
"Find the variables directly referenced by this method"
refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
[:ea| ea key].
"Move to Undeclared any opcodes in classPool not in opcodes or this method."
(classPool keys reject: [:k| (opcodeNames includes: k) or: [refs includes: k]]) do:
[:k|
Undeclared declare: k from: classPool].
"Declare as class variables and number elements of opcodeArray above"
opcodeNames withIndexDo:
[:classVarName :value|
self classPool
declare: classVarName from: Undeclared;
at: classVarName put: value].
"For CogAbstractInstruction>>isJump etc..."
FirstJump := JumpFull.
LastJump := JumpFPUnordered.
FirstShortJump := Jump.
"And now initialize the backends; they add their own opcodes and hence these must be reinitialized."
(Smalltalk classNamed: #CogAbstractInstruction) ifNotNil:
[:cogAbstractInstruction| cogAbstractInstruction allSubclasses do: [:sc| sc initialize]]!
Item was changed:
----- Method: CogRTLOpcodes class>>nameForOpcode: (in category 'debug printing') -----
nameForOpcode: opcode "<Integer>"
+ opcode < LastRTLCode ifTrue:
+ [classPool associations do:
+ [:assoc| | opcodeName |
+ assoc value = opcode ifTrue:
+ [(((opcodeName := assoc key) beginsWith: 'First')
+ or: [(opcodeName beginsWith: 'Last')]) ifFalse:
+ [^opcodeName]]]].
+ ^nil!
- ^opcode < LastRTLCode ifTrue:
- [(classPool keyAtValue: opcode ifAbsent: []) ifNotNil:
- [:opcodeName|
- ((opcodeName beginsWith: 'First')
- or: [opcodeName beginsWith: 'Last'])
- ifTrue: [#(JumpFull JumpLong JumpBelowOrEqual Jump) detect: [:k| (classPool at: k) = opcode]]
- ifFalse: [opcodeName]]]!
Item was removed:
- ----- Method: CogRTLOpcodes class>>nameForRegister: (in category 'debug printing') -----
- nameForRegister: reg "<Integer>"
- ^#(Arg0Reg Arg1Reg ClassReg FPReg ReceiverResultReg SPReg SendNumArgsReg TempReg
- DPFPReg0 DPFPReg1 DPFPReg2 DPFPReg3 DPFPReg4 DPFPReg5 DPFPReg6 DPFPReg7
- LinkReg RISCTempReg VarBaseReg PCReg
- Scratch0Reg Scratch1Reg Scratch2Reg Scratch3Reg Scratch4Reg Scratch5Reg)
- detect: [:sym| (classPool at: sym) = reg]
- ifNone: ['REG', reg printString, '?']!
Item was changed:
----- Method: CogRTLOpcodes class>>printFormatForOpcodeName: (in category 'debug printing') -----
printFormatForOpcodeName: opcodeName
+ "Answer a sequence of $r, $f or nil for the operands in the opcode, used for printing, where
+ r => integer register, f => floating point register, and nil => numeric or address operand."
+ | printFormat operands |
+ printFormat := OrderedCollection new.
+ operands := opcodeName.
+ [(#( ('Ab' nil) ('Aw' nil)
+ ('Cw' nil) ('Cq' nil) ('C32' nil)
+ (Fill32 nil)
+ (Label nil) (Literal nil)
+ ('Mb' nil) ('Mw' nil) ('M16' nil) ('M32' nil) ('M64' nil)
+ ('Nops' nil)
+ ('R' $r) ('Rd' $f)
+ ('Xbr' $r) ('Xwr' $r) ('X16r' $r) ('X32r' $r) ('X64r' $r) ('X' $r) ('ow' nil)
+ ('Greater' exit) ('Xor' exit) ('r' $r))
+ detect: [:pair| operands endsWith: pair first]
+ ifNone: [])
+ ifNil: [false]
+ ifNotNil:
+ [:match|
+ match last ~~ #exit
+ and: [operands := operands allButLast: match first size.
+ printFormat addFirst: match last.
+ true]]]
+ whileTrue.
+ (printFormat isEmpty and: [(operands beginsWith: 'Jump') or: [operands beginsWith: 'Call']]) ifTrue:
+ [printFormat addFirst: nil].
+ ^printFormat
- "Answer a sequence of $r or nil for the operands in the opcode, used for printing."
- | format operands size |
- format := OrderedCollection new.
- size := (operands := opcodeName) size.
- (operands startsWith: 'Br') ifTrue: [^' rr'].
- [#('XwrR' 'X16rR' 'XbrR' 'RR' 'RdR' 'RRd' 'RdRd') do:
- [:regRegFmt|
- (operands endsWith: regRegFmt) ifTrue:
- [format addLast: $r; addLast: $r.
- operands := operands allButLast: regRegFmt size]].
- #('Mwr' 'M16r' 'Mbr' 'M64r') do:
- [:constRegFmt|
- (operands endsWith: constRegFmt) ifTrue:
- [format addLast: $r; addLast: nil.
- operands := operands allButLast: constRegFmt size]].
- #('Cq' 'Cw' 'C32' 'C64' 'Aw' 'Ab') do:
- [:constFmt|
- (operands endsWith: constFmt) ifTrue:
- [format addLast: nil.
- operands := operands allButLast: constFmt size]].
- #('R' 'Rd') do:
- [:regFmt|
- (operands endsWith: regFmt) ifTrue:
- [format addLast: $r.
- operands := operands allButLast: regFmt size]].
- operands size < size]
- whileTrue: [size := operands size].
- ^format reverse
+ "classPool keys sort collect: [:k| { k. (self printFormatForOpcodeName: k) asArray}]"!
- "classPool keys collect: [:k| { k. (self printFormatForOpcodeName: k) asArray}]"!
Item was changed:
VMStructType subclass: #CogSimStackEntry
instanceVariableNames: 'cogit objectRepresentation type spilled annotateUse register offset constant bcptr'
classVariableNames: ''
+ poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogRTLOpcodes'
- poolDictionaries: 'CogCompilationConstants CogRTLOpcodes'
category: 'VMMaker-JIT'!
Item was changed:
----- Method: CogX64Compiler class>>initializeAbstractRegisters (in category 'class initialization') -----
initializeAbstractRegisters
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
+ "[1] Figure 3.4 Register Usage in
+ System V Application Binary Interface
+ AMD64 Architecture Processor Supplement
+
+ N.B. RAX RCX & RDX are caller-save (scratch) registers. Hence we use RCX for class and RDX for
+ receiver/result since these are written in all normal sends."
+
+ super initializeAbstractRegisters.
+
+ TempReg := RAX.
+ ClassReg := RCX.
+ ReceiverResultReg := RDX.
+ SendNumArgsReg := R9.
+ SPReg := RSP.
+ FPReg := RBP.
+ Arg0Reg := RDI. "So as to agree with C ABI arg 0"
+ Arg1Reg := RSI. "So as to agree with C ABI arg 1"
+ VarBaseReg := RBX. "Must be callee saved"
+ "R8 is either RISCTempReg or Scratch6Reg depending on subclass."
+ Scratch0Reg := R10.
+ Scratch1Reg := R11.
+ Scratch2Reg := R12.
+ Scratch3Reg := R13.
+ Scratch4Reg := R14.
+ Scratch5Reg := R15.
+
+ DPFPReg0 := XMM0L.
+ DPFPReg1 := XMM1L.
+ DPFPReg2 := XMM2L.
+ DPFPReg3 := XMM3L.
+ DPFPReg4 := XMM4L.
+ DPFPReg5 := XMM5L.
+ DPFPReg6 := XMM6L.
+ DPFPReg7 := XMM7L.
+ DPFPReg8 := XMM8L.
+ DPFPReg9 := XMM9L.
+ DPFPReg10 := XMM10L.
+ DPFPReg11 := XMM11L.
+ DPFPReg12 := XMM12L.
+ DPFPReg13 := XMM13L.
+ DPFPReg14 := XMM14L.
+ DPFPReg15 := XMM15L!
- self ~~ CogX64Compiler ifTrue:
- [self subclassResponsibility]!
Item was added:
+ ----- Method: CogX64Compiler>>nameForFPRegister: (in category 'printing') -----
+ nameForFPRegister: reg "<Integer>"
+ <doNotGenerate>
+ (reg between: 0 and: 15) ifTrue:
+ [^#(XMM0L XMM1L XMM2L XMM3L XMM4L XMM5L XMM6L XMM7L XMM8L XMM9L XMM10L XMM11L XMM12L XMM13L XMM14L XMM15L) at: reg + 1].
+ ^super nameForFPRegister: reg!
Item was changed:
CogClass subclass: #Cogit
instanceVariableNames: 'coInterpreter objectMemory objectRepresentation processor threadManager methodZone methodZoneBase codeBase minValidCallAddress lastNInstructions simulatedAddresses simulatedTrampolines simulatedVariableGetters simulatedVariableSetters printRegisters printInstructions compilationTrace clickConfirm breakPC breakBlock singleStep guardPageSize traceFlags traceStores breakMethod methodObj enumeratingCogMethod methodHeader initialPC endPC methodOrBlockNumArgs inBlock needsFrame hasYoungReferent primitiveIndex backEnd literalsManager callerSavedRegMask postCompileHook methodLabel stackCheckLabel blockEntryLabel blockEntryNoContextSwitch blockNoContextSwitchOffset stackOverflowCall sendMiss missOffset entryPointMask checkedEntryAlignment uncheckedEntryAlignment cmEntryOffset entry cmNoCheckEntryOffset noCheckEntry picMNUAbort picInterpretAbort endCPICCase0 endCPICCase1 firstCPICCaseOffset cPICCaseSize cPICEndSize closedPICSize openPICSize fixups abstractOpcodes generatorTable primitiveGeneratorTable byte0 byte1 byte2 byte3 bytecodePC bytecodeSetOffset opcodeIndex numAbstractOpcodes blockStarts blockCount labelCounter cStackAlignment expectedSPAlignment expectedFPAlignment codeModified maxLitIndex ceMethodAbortTrampoline cePICAbortTrampoline ceCheckForInterruptTrampoline ceCPICMissTrampoline ceReturnToInterpreterTrampoline ceBaseFrameReturnTrampoline ceSendMustBeBooleanAddTrueTrampoline ceSendMustBeBooleanAddFalseTrampoline ceCannotResumeTrampoline ceEnterCogCodePopReceiverReg ceCallCogCodePopReceiverReg ceCallCogCodePopReceiverAndClassRegs cePrimReturnEnterCogCode cePrimReturnEnterCogCodeProfiling ceNonLocalReturnTrampoline ceFetchContextInstVarTrampoline ceStoreContextInstVarTrampoline ceEnclosingObjectTrampoline ceCaptureCStackPointers ceFlushICache ceCheckFeaturesFunction ceTraceLinkedSendTrampoline ceTraceBlockActivationTrampoline ceTraceStoreTrampoline ceGetSP ordinarySendTrampolines superSendTrampolines directedSuperSendTrampolines dynamicSuperSendTrampolines outerSendTrampolines selfSendTrampolines firstSend lastSend realCEEnterCogCodePopReceiverReg realCECallCogCodePopReceiverReg realCECallCogCodePopReceiverAndClassRegs trampolineTableIndex trampolineAddresses objectReferencesInRuntime runtimeObjectRefIndex cFramePointerInUse debugPrimCallStackOffset ceTryLockVMOwner ceUnlockVMOwner extA extB tempOop numIRCs indexOfIRC theIRCs implicitReceiverSendTrampolines cogMethodSurrogateClass cogBlockMethodSurrogateClass nsSendCacheSurrogateClass CStackPointer CFramePointer cPICPrototype cPICEndOfCodeOffset cPICEndOfCodeLabel maxCPICCases debugOpcodeIndices disassemblingMethod'
classVariableNames: 'AltBlockCreationBytecodeSize AltFirstSpecialSelector AltNSSendIsPCAnnotated AltNumSpecialSelectors AnnotationConstantNames AnnotationShift AnnotationsWithBytecodePCs BlockCreationBytecodeSize Debug DisplacementMask DisplacementX2N EagerInstructionDecoration FirstAnnotation FirstSpecialSelector HasBytecodePC IsAbsPCReference IsAnnotationExtension IsDirectedSuperSend IsDisplacementX2N IsNSDynamicSuperSend IsNSImplicitReceiverSend IsNSSelfSend IsNSSendCall IsObjectReference IsRelativeCall IsSendCall IsSuperSend MapEnd MaxCompiledPrimitiveIndex MaxStackAllocSize MaxX2NDisplacement NSCClassTagIndex NSCEnclosingObjectIndex NSCNumArgsIndex NSCSelectorIndex NSCTargetIndex NSSendIsPCAnnotated NumObjRefsInRuntime NumOopsPerNSC NumSpecialSelectors NumTrampolines ProcessorClass'
+ poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogMethodConstants CogRTLOpcodes VMBasicConstants VMBytecodeConstants VMObjectIndices VMStackFrameOffsets'
- poolDictionaries: 'CogCompilationConstants CogMethodConstants CogRTLOpcodes VMBasicConstants VMBytecodeConstants VMObjectIndices VMStackFrameOffsets'
category: 'VMMaker-JIT'!
Cogit class
instanceVariableNames: 'generatorTable primitiveTable'!
!Cogit commentStamp: 'eem 4/6/2015 15:56' prior: 0!
I am the code generator for the Cog VM. My job is to produce machine code versions of methods for faster execution and to manage inline caches for faster send performance. I can be tested in the current image using my class-side in-image compilation facilities. e.g. try
StackToRegisterMappingCogit genAndDis: (Integer >> #benchFib)
I have concrete subclasses that implement different levels of optimization:
SimpleStackBasedCogit is the simplest code generator.
StackToRegisterMappingCogit is the current production code generator It defers pushing operands
to the stack until necessary and implements a register-based calling convention for low-arity sends.
StackToRegisterMappingCogit is an experimental code generator with support for counting
conditional branches, intended to support adaptive optimization.
coInterpreter <CoInterpreterSimulator>
the VM's interpreter with which I cooperate
methodZoneManager <CogMethodZoneManager>
the manager of the machine code zone
objectRepresentation <CogObjectRepresentation>
the object used to generate object accesses
processor <BochsIA32Alien|?>
the simulator that executes the IA32/x86 machine code I generate when simulating execution in Smalltalk
simulatedTrampolines <Dictionary of Integer -> MessageSend>
the dictionary mapping trap jump addresses to run-time routines used to warp from simulated machine code in to the Smalltalk run-time.
simulatedVariableGetters <Dictionary of Integer -> MessageSend>
the dictionary mapping trap read addresses to variables in run-time objects used to allow simulated machine code to read variables in the Smalltalk run-time.
simulatedVariableSetters <Dictionary of Integer -> MessageSend>
the dictionary mapping trap write addresses to variables in run-time objects used to allow simulated machine code to write variables in the Smalltalk run-time.
printRegisters printInstructions clickConfirm <Boolean>
flags controlling debug printing and code simulation
breakPC <Integer>
machine code pc breakpoint
cFramePointer cStackPointer <Integer>
the variables representing the C stack & frame pointers, which must change on FFI callback and return
selectorOop <sqInt>
the oop of the methodObj being compiled
methodObj <sqInt>
the bytecode method being compiled
initialPC endPC <Integer>
the start and end pcs of the methodObj being compiled
methodOrBlockNumArgs <Integer>
argument count of current method or block being compiled
needsFrame <Boolean>
whether methodObj or block needs a frame to execute
primitiveIndex <Integer>
primitive index of current method being compiled
methodLabel <CogAbstractOpcode>
label for the method header
blockEntryLabel <CogAbstractOpcode>
label for the start of the block dispatch code
stackOverflowCall <CogAbstractOpcode>
label for the call of ceStackOverflow in the method prolog
sendMissCall <CogAbstractOpcode>
label for the call of ceSICMiss in the method prolog
entryOffset <Integer>
offset of method entry code from start (header) of method
entry <CogAbstractOpcode>
label for the first instruction of the method entry code
noCheckEntryOffset <Integer>
offset of the start of a method proper (after the method entry code) from start (header) of method
noCheckEntry <CogAbstractOpcode>
label for the first instruction of start of a method proper
fixups <Array of <AbstractOpcode Label | nil>>
the labels for forward jumps that will be fixed up when reaching the relevant bytecode. fixup shas one element per byte in methodObj's bytecode
abstractOpcodes <Array of <AbstractOpcode>>
the code generated when compiling methodObj
byte0 byte1 byte2 byte3 <Integer>
individual bytes of current bytecode being compiled in methodObj
bytecodePointer <Integer>
bytecode pc (same as Smalltalk) of the current bytecode being compiled
opcodeIndex <Integer>
the index of the next free entry in abstractOpcodes (this code is translated into C where OrderedCollection et al do not exist)
numAbstractOpcodes <Integer>
the number of elements in abstractOpcocdes
blockStarts <Array of <BlockStart>>
the starts of blocks in the current method
blockCount
the index into blockStarts as they are being noted, and hence eventually the total number of blocks in the current method
labelCounter <Integer>
a nicety for numbering labels not needed in the production system but probably not expensive enough to worry about
ceStackOverflowTrampoline <Integer>
ceSend0ArgsTrampoline <Integer>
ceSend1ArgsTrampoline <Integer>
ceSend2ArgsTrampoline <Integer>
ceSendNArgsTrampoline <Integer>
ceSendSuper0ArgsTrampoline <Integer>
ceSendSuper1ArgsTrampoline <Integer>
ceSendSuper2ArgsTrampoline <Integer>
ceSendSuperNArgsTrampoline <Integer>
ceSICMissTrampoline <Integer>
ceCPICMissTrampoline <Integer>
ceStoreCheckTrampoline <Integer>
ceReturnToInterpreterTrampoline <Integer>
ceBaseFrameReturnTrampoline <Integer>
ceSendMustBeBooleanTrampoline <Integer>
ceClosureCopyTrampoline <Integer>
the various trampolines (system-call-like jumps from machine code to the run-time).
See Cogit>>generateTrampolines for the mapping from trampoline to run-time
routine and then read the run-time routine for a funcitonal description.
ceEnterCogCodePopReceiverReg <Integer>
the enilopmart (jump from run-time to machine-code)
methodZoneBase <Integer>
!
Cogit class
instanceVariableNames: 'generatorTable primitiveTable'!
Item was changed:
----- Method: Cogit class>>cog:selector:options: (in category 'in-image compilation') -----
cog: aCompiledMethod selector: aSelector options: optionsDictionaryOrArray
"StackToRegisterMappingCogit cog: (Integer >> #benchFib) selector: #benchFib options: #(COGMTVM false)"
+ | initOptions coInterpreter cogit |
+ initOptions := self asOptionsDictionary: optionsDictionaryOrArray.
+ CoInterpreter initializeWithOptions: initOptions.
+ CoInterpreter objectMemoryClass initializeWithOptions: initOptions.
+ self initializeWithOptions: initOptions.
- | coInterpreter cogit |
- self initializeWithOptions: (self asOptionsDictionary: optionsDictionaryOrArray).
- CoInterpreter initializeWithOptions: initializationOptions.
- CoInterpreter objectMemoryClass initializeWithOptions: initializationOptions.
coInterpreter := CurrentImageCoInterpreterFacade forCogit: (cogit := self new).
[cogit
setInterpreter: coInterpreter;
singleStep: true;
initializeCodeZoneFrom: 1024 upTo: coInterpreter memory size / 2. "leave space for rump C stack"
cogit methodZone freeStart: (cogit methodZone freeStart roundUpTo: 1024)]
on: Notification
do: [:ex|
(ex messageText beginsWith: 'cannot find receiver for') ifTrue:
[ex resume: coInterpreter].
ex pass].
^{ coInterpreter.
cogit.
cogit cog: (coInterpreter oopForObject: aCompiledMethod) selector: (coInterpreter oopForObject: aSelector) }!
Item was changed:
VMClass subclass: #OutOfLineLiteralsManager
instanceVariableNames: 'cogit objectMemory objectRepresentation firstOpcodeIndex nextLiteralIndex lastDumpedLiteralIndex literals literalsSize savedFirstOpcodeIndex savedNextLiteralIndex savedLastDumpedLiteralIndex'
classVariableNames: ''
+ poolDictionaries: 'CogAbstractRegisters CogCompilationConstants CogRTLOpcodes'
- poolDictionaries: 'CogCompilationConstants CogRTLOpcodes'
category: 'VMMaker-JIT'!
!OutOfLineLiteralsManager commentStamp: 'eem 6/7/2015 12:10' prior: 0!
An OutOfLineLiteralsManager manages the dumping of literals for backends that wat to keep literals out-of-line, accessed by pc-relative addressing.
Instance Variables
cogit: <Cogit>!
Item was removed:
- ----- Method: SimpleStackBasedCogit>>compileFallbackToInterpreterPrimitive (in category 'primitive generators') -----
- compileFallbackToInterpreterPrimitive
- <inline: false>
- ^self compileInterpreterPrimitive: (coInterpreter
- functionPointerForCompiledMethod: methodObj
- primitiveIndex: primitiveIndex)!
Item was added:
+ ----- Method: Spur32BitCoMemoryManager class>>initializeWithOptions: (in category 'class initialization') -----
+ initializeWithOptions: optionsDictionary
+ "SpurMemoryManager initializeWithOptions: Dictionary new"
+
+ optionsDictionary at: #Spur32BitMemoryManager put: true.
+ super initializeWithOptions: optionsDictionary!
Item was added:
+ ----- Method: Spur64BitCoMemoryManager class>>initializeWithOptions: (in category 'class initialization') -----
+ initializeWithOptions: optionsDictionary
+ "SpurMemoryManager initializeWithOptions: Dictionary new"
+
+ optionsDictionary at: #Spur64BitMemoryManager put: true.
+ super initializeWithOptions: optionsDictionary!
Item was changed:
----- Method: VMClass class>>shouldIncludeMethodForSelector: (in category 'translation') -----
shouldIncludeMethodForSelector: selector
"Answer whether a primitive method shoud be translated. Emit a warning to the transcript if the method doesn't exist."
^(self whichClassIncludesSelector: selector)
ifNotNil:
[:c|
(c >> selector pragmaAt: #option:)
ifNotNil:
[:pragma|
+ initializationOptions at: pragma arguments first ifAbsent: [false]]
- initializationOptions at: (pragma arguments first) ifAbsent: [false]]
ifNil: [true]]
ifNil:
[Transcript nextPutAll: 'Cannot find implementation of '; nextPutAll: selector; nextPutAll: ' in hierarchy of '; print: self; cr; flush.
false]!
1
0
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1612.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1612
Author: eem
Time: 25 December 2015, 7:36:01.334 pm
UUID: be393e64-c959-4132-b754-cd2bda5bcf0d
Ancestors: VMMaker.oscog-eem.1611
Complete the "abstract registers simply name concrete registers" coup. Eliminate all uses of concreteRegister: concreteDPFPRegister: abstractRegisterForConcreteRegister:.
Make the abstract instruction tests initializeAbstractRegisters before running (CogRTLOpcodes still needs to be initialized separately).
Slang: fix default in shouldIncludeMethodForSelector:. Missing options need to default to false.
=============== Diff against VMMaker.oscog-eem.1611 ===============
Item was changed:
----- Method: AbstractInstructionTests>>runAddCwR: (in category 'running') -----
runAddCwR: assertPrintBar
"self defaultTester runAddCwR: false"
self concreteCompilerClass dataRegistersWithAccessorsDo:
[:reg :rgetter :rsetter|
self pairs: (-2 to: 2) do:
[:a :b| | inst len bogus memory |
inst := self gen: AddCwR operand: a operand: reg.
len := inst concretizeAt: 0.
memory := self memoryAsBytes: inst machineCode.
self processor
reset;
perform: rsetter with: (self processor convertIntegerToInternal: b).
[[processor pc < len] whileTrue:
[self processor singleStepIn: memory]]
on: Error
do: [:ex| ].
"self processor printRegistersOn: Transcript.
Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr"
assertPrintBar
ifTrue: [self assert: processor pc = inst machineCodeSize.
self assertCheckLongArithOpCodeSize: inst machineCodeSize]
ifFalse: [bogus := processor pc ~= inst machineCodeSize].
self concreteCompilerClass dataRegistersWithAccessorsDo:
[:ireg :getter :setter| | expected |
+ (self concreteCompilerClass isRISCTempRegister: ireg) ifFalse:
- (self concreteCompilerClass isConcreteRISCTempRegister: ireg) ifFalse:
[expected := getter == rgetter ifTrue: [b + a] ifFalse: [0].
assertPrintBar
ifTrue: [self assert: (self processor convertInternalToInteger: (self processor perform: getter)) equals: expected]
ifFalse:
[(self processor convertInternalToInteger: (self processor perform: getter)) ~= expected ifTrue:
[bogus := true]]].
assertPrintBar ifFalse:
[Transcript
nextPutAll: rgetter; nextPut: $(; print: b; nextPutAll: ') + '; print: a; nextPutAll: ' = ';
print: (self processor convertInternalToInteger: (self processor perform: rgetter)); cr; flush.
bogus ifTrue:
[self processor printRegistersOn: Transcript.
Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr]]]]]!
Item was changed:
----- Method: AbstractInstructionTests>>runSubCwR: (in category 'running') -----
runSubCwR: assertPrintBar
"self defaultTester runSubCwR: false"
self concreteCompilerClass dataRegistersWithAccessorsDo:
[:reg :rgetter :rsetter|
self pairs: (-2 to: 2) do:
[:a :b| | inst len bogus memory |
inst := self gen: SubCwR operand: a operand: reg.
len := inst concretizeAt: 0.
memory := self memoryAsBytes: inst machineCode.
self processor
reset;
perform: rsetter with: (self processor convertIntegerToInternal: b).
[[processor pc < len] whileTrue:
[self processor singleStepIn: memory]]
on: Error
do: [:ex| ].
"self processor printRegistersOn: Transcript.
Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr"
assertPrintBar
ifTrue: [self assert: processor pc = inst machineCodeSize.
self assertCheckLongArithOpCodeSize: inst machineCodeSize]
ifFalse: [bogus := processor pc ~= inst machineCodeSize].
self concreteCompilerClass dataRegistersWithAccessorsDo:
[:ireg :getter :setter| | expected |
+ (self concreteCompilerClass isRISCTempRegister: ireg) ifFalse:
- (self concreteCompilerClass isConcreteRISCTempRegister: ireg) ifFalse:
[expected := getter == rgetter ifTrue: [b - a] ifFalse: [0].
assertPrintBar
ifTrue: [self assert: (self processor convertInternalToInteger: (self processor perform: getter)) equals: expected]
ifFalse:
[(self processor convertInternalToInteger: (self processor perform: getter)) ~= expected ifTrue:
[bogus := true]]].
assertPrintBar ifFalse:
[Transcript
nextPutAll: rgetter; nextPut: $(; print: b; nextPutAll: ') - '; print: a; nextPutAll: ' = ';
print: (self processor convertInternalToInteger: (self processor perform: rgetter)); cr; flush.
bogus ifTrue:
[self processor printRegistersOn: Transcript.
Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr]]]]]!
Item was added:
+ ----- Method: AbstractInstructionTests>>setUp (in category 'running') -----
+ setUp
+ self concreteCompilerClass initializeAbstractRegisters!
Item was removed:
- ----- Method: CogARMCompiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
- isConcreteRISCTempRegister: concreteRegister
- "For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
- ^concreteRegister = ConcreteIPReg!
Item was added:
+ ----- Method: CogARMCompiler class>>isRISCTempRegister: (in category 'testing') -----
+ isRISCTempRegister: reg
+ "For tests to filter-out bogus values left in the RISCTempRegister, if any."
+ ^reg = ConcreteIPReg!
Item was changed:
----- Method: CogARMCompiler>>cResultRegister (in category 'abi') -----
cResultRegister
+ "Answer the register through which C funcitons return integral results."
+ <inline: true>
- "Answer the abstract register for the C result register.
- Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
^R0!
Item was changed:
----- Method: CogARMCompiler>>callerSavedRegisterMask (in category 'accessing') -----
callerSavedRegisterMask
"According to IHI0042E ARM Architecture Procedure Calling Standard, in section 5.1.1:
A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP (and r9 in PCS variants that designate r9 as v6).
SP = r13, so the callee-saved regs are r4-r8 & r10-r12.
The caller-saved registers are those that are not callee-saved and not reserved for hardware/abi uses,
i..e r0-r3, r9 & r12. We can't name all the C argument registers. So..."
^cogit
+ registerMaskFor: 0
+ "and: 1"
+ "and: 2"
+ "and: 3"
+ "and: 9"
+ and: 12!
- registerMaskFor: (self abstractRegisterForConcreteRegister: 0)
- "and: (self abstractRegisterForConcreteRegister: 1)"
- "and: (self abstractRegisterForConcreteRegister: 2)"
- "and: (self abstractRegisterForConcreteRegister: 3)"
- "and: (self abstractRegisterForConcreteRegister: 9)"
- and: (self abstractRegisterForConcreteRegister: 12)!
Item was changed:
----- Method: CogARMCompiler>>concretizeAddRdRd (in category 'generate machine code - concretize') -----
concretizeAddRdRd
"Will get inlined into concretizeAt: switch."
<inline: true>
"Add FP regRHS to FP regLHS and stick result in FP regLHS"
| regLHS regRHS |
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode at: 0 put:(self faddd: regLHS with: regRHS).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeAndCqRR (in category 'generate machine code - concretize') -----
concretizeAndCqRR
"Will get inlined into concretizeAt: switch."
"AND is very important since it's used to mask all sorts of flags in the jit. We take special care to try to find compact ways to make the masks"
<inline: true>
| val srcReg dstReg |
val := operands at: 0.
+ srcReg := operands at: 1.
+ dstReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- dstReg := self concreteRegister: (operands at: 2).
self rotateable8bitBitwiseImmediate: val
ifTrue:
[:rot :immediate :invert|
self machineCodeAt: 0 put: (invert
ifTrue: [self bics: dstReg rn: srcReg imm: immediate ror: rot]
ifFalse: [self ands: dstReg rn: srcReg imm: immediate ror: rot]).
^machineCodeSize := 4]
ifFalse: "let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
[| hb |
hb := (operands at: 0) highBit.
1 << hb = (val +1)
ifTrue: "MVN temp reg, 0, making 0xffffffff"
[self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0).
"Then AND reg, temp reg, lsr #(32-hb)"
self machineCodeAt: 4 put: (self dataOpType: AndOpcode rd: dstReg rn: srcReg rm: ConcreteIPReg lsr: 32 - hb).
^machineCodeSize := 8]
ifFalse:
[^self concretizeDataOperationCwR: AndOpcode]].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeArithmeticShiftRightCqR (in category 'generate machine code - concretize') -----
concretizeArithmeticShiftRightCqR
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, ASR #distance"
<inline: true>
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
"cond 000 1101 0 0000 dest dist -100 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: reg
shifterOperand: (distance << 7 bitOr: (64 "flag for arithmetic" bitOr: reg))).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeArithmeticShiftRightRR (in category 'generate machine code - concretize') -----
concretizeArithmeticShiftRightRR
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, ASR distReg"
<inline: true>
| destReg distReg |
+ distReg := operands at: 0.
+ destReg := operands at: 1.
- distReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
"cond 000 1101 0 0000 destR distR 0101 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: destReg
shifterOperand: (distReg << 8 bitOr: (80 bitOr: destReg))).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeCMPSMULL (in category 'generate machine code - concretize') -----
concretizeCMPSMULL
"Generate a CMP a, b, ASR #31 instruction, specifically for comparing the resutls of SMULLs in genMulR:R:"
| hiReg loReg |
+ hiReg := operands at: 0.
+ loReg := operands at: 1.
- hiReg := self concreteRegister: (operands at: 0).
- loReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0
put: (self type: 0 op: CmpOpcode set: 1 rn: hiReg rd: 0)
+ (31<<7) "the shift amount"
+ (2<<5) "the shift type - ASR"
+ loReg.
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeCmpRdRd (in category 'generate machine code - concretize') -----
concretizeCmpRdRd
"Will get inlined into concretizeAt: switch."
<inline: true>
"Compare FP regB with FP regA and leave the FP status reg ready to be transferred back to ARM with next instruction"
| regB regA |
+ regA := operands at:0.
+ regB := operands at: 1.
- regA := self concreteDPFPRegister: (operands at:0).
- regB := self concreteDPFPRegister: (operands at: 1).
machineCode at: 0 put:(self fcmpFrom: regB to: regA).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeConvertRRd (in category 'generate machine code - concretize') -----
concretizeConvertRRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg destReg |
+ srcReg := operands at:0.
+ destReg := operands at: 1.
- srcReg := self concreteRegister: (operands at:0).
- destReg := self concreteDPFPRegister: (operands at: 1).
machineCode at: 0 put:(self fmsrFrom: srcReg to: 9).
machineCode at: 1 put: (self fsitodFrom: 9 to: destReg). "probably not quite right"
^machineCodeSize := 8
!
Item was changed:
----- Method: CogARMCompiler>>concretizeDataOperationCqR: (in category 'generate machine code - concretize') -----
concretizeDataOperationCqR: armOpcode
"Will get inlined into concretizeAt: switch."
"4 == Add, 2 == Sub, Xor == 1, And == 0, Or == 12, Bic == 14"
<inline: true>
|val rd rn |
val := operands at: 0.
+ rn := operands at: 1.
- rn := self concreteRegister: (operands at: 1).
rd := opcode = CmpOpcode ifTrue: [0] ifFalse:[rn]. "Extra note - if ever a version of this code wants to NOT set the Set flag - Cmp must always have it set or it will pretend to be a SMALALBT and Very Bad Things might happen"
self rotateable8bitImmediate: val
ifTrue: [:rot :immediate |
self machineCodeAt: 0 put: (self type: 1 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: ((rot>>1)"in this usage we have to halve the rot value" << 8 bitOr: immediate)).
^machineCodeSize := 4]
ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
val > 0 ifTrue: [
|hb |
hb := val highBit.
1 << hb = (val +1)
ifTrue: [ "MVN temp, #0, making 0xffffffff"
self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0).
"Then armOpcode reg, temp reg, lsr #(32-hb)"
self machineCodeAt: 4 put:(self dataOpType: armOpcode rd: rd rn: rn rm: ConcreteIPReg lsr: (32-hb)).
^machineCodeSize :=8]].
^self concretizeDataOperationCwR: armOpcode].
^0 "to keep Slang happy"
!
Item was changed:
----- Method: CogARMCompiler>>concretizeDataOperationCwR: (in category 'generate machine code - concretize') -----
concretizeDataOperationCwR: armOpcode
"Will get inlined into concretizeAt: switch."
"Load the word into the RISCTempReg, then cmp R, RISCTempReg"
<inline: true>
| constant rn rd instrOffset|
constant := operands at: 0.
+ rn := operands at: 1.
- rn := (self concreteRegister: (operands at: 1)).
rd := armOpcode = CmpOpcode ifTrue: [0] ifFalse:[rn].
instrOffset := self moveCw: constant intoR: ConcreteIPReg.
self machineCodeAt: instrOffset
put: (self type: 0 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: ConcreteIPReg).
^machineCodeSize := instrOffset + 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeDataOperationRR: (in category 'generate machine code - concretize') -----
concretizeDataOperationRR: armOpcode
"Will get inlined into concretizeAt: switch."
"Load the word into the RISCTempReg, then op R, RISCTempReg"
<inline: true>
| rn rd srcReg |
+ srcReg := operands at: 0.
+ rn := operands at: 1.
- srcReg := self concreteRegister: (operands at: 0).
- rn := (self concreteRegister: (operands at: 1)).
rd := armOpcode = CmpOpcode ifTrue: [0] ifFalse: [rn].
self machineCodeAt: 0
put: (self type: 0 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: srcReg).
^machineCodeSize := 4.!
Item was changed:
----- Method: CogARMCompiler>>concretizeDivRdRd (in category 'generate machine code - concretize') -----
concretizeDivRdRd
"Will get inlined into concretizeAt: switch."
<inline: true>
"FP divide regLHS by regRHS and stick result in regLHS"
| regLHS regRHS |
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode at: 0 put:(self fdivd: regLHS by: regRHS).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeInvertibleDataOperationCqR: (in category 'generate machine code - concretize') -----
concretizeInvertibleDataOperationCqR: armOpcode
"Will get inlined into concretizeAt: switch."
"Xor == 1, And == 0, Or == 12, Bic == 14"
<inline: true>
| val rn |
val := operands at: 0.
+ rn := operands at: 1.
- rn := self concreteRegister: (operands at: 1).
self deny: opcode = CmpOpcode.
self rotateable8bitBitwiseImmediate: val
ifTrue:
[:rot :immediate : invert|
self machineCodeAt: 0
put: (self
type: 1
op: (invert ifTrue: [self inverseOpcodeFor: armOpcode] ifFalse: [armOpcode])
set: 1
rn: rn
rd: rn
shifterOperand: (rot >> 1"in this usage we have to halve the rot value" << 8 bitOr: immediate)).
^machineCodeSize := 4]
ifFalse: "let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
[val > 0 ifTrue:
[| hb |
hb := val highBit.
1 << hb = (val +1) ifTrue: "MVN temp, #0, making 0xffffffff"
[self machineCodeAt: 0 put: (self mvn: ConcreteIPReg imm: 0 ror: 0).
"Then armOpcode reg, temp reg, lsr #(32-hb)"
self machineCodeAt: 4 put: (self dataOpType: armOpcode rd: rn rn: rn rm: ConcreteIPReg lsr: 32 - hb).
^machineCodeSize := 8]].
^self concretizeDataOperationCqR: armOpcode].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeJumpR (in category 'generate machine code - concretize') -----
concretizeJumpR
"Will get inlined into concretizeAt: switch."
"Sizing/generating jumps.
Jump targets can be to absolute addresses or other abstract instructions.
Generating initial trampolines instructions may have no maxSize and be to absolute addresses.
Otherwise instructions must have a machineCodeSize which must be kept to."
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
"bx reg"
self machineCodeAt: 0 put: (self bx: reg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeLoadEffectiveAddressMwrR (in category 'generate machine code - concretize') -----
concretizeLoadEffectiveAddressMwrR
"Will get inlined into concretizeAt: switch."
"destReg = srcReg (which contains an address) + offset"
<inline: true>
| srcReg offset destReg instrOffset |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self rotateable8bitImmediate: offset
ifTrue:
[ :rot :immediate |
self machineCodeAt: 0
"add destReg, srcReg, #immediate ROR rot"
put: (self add: destReg rn: srcReg imm: immediate ror: rot<<1).
machineCodeSize := 4]
ifFalse:
[instrOffset := self moveCw: offset intoR: ConcreteIPReg.
"add destReg, srcReg, ConcreteIPReg"
self machineCodeAt: 16 put: (self add: destReg rn: srcReg rm: ConcreteIPReg).
machineCodeSize := instrOffset + 4].
^machineCodeSize "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeLogicalShiftLeftCqR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftLeftCqR
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, LSL #distance"
<inline: true>
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
"cond 000 1101 0 0000 dest dista 000 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: reg shifterOperand: (distance << 7 bitOr: reg)).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeLogicalShiftLeftRR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftLeftRR
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, LSL distReg"
<inline: true>
| destReg distReg |
+ distReg := operands at: 0.
+ destReg := operands at: 1.
- distReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
"cond 000 1101 0 0000 dest dist 0001 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: destReg
shifterOperand: (distReg << 8 bitOr: (16 bitOr: destReg))).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeLogicalShiftRightCqR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftRightCqR
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, LSR #distance"
<inline: true>
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
"cond 000 1101 0 0000 dest dist -010 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: reg
shifterOperand: (distance << 7 bitOr: (32 bitOr: reg))).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeLogicalShiftRightRR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftRightRR
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, LSR distReg"
<inline: true>
| destReg distReg |
+ distReg := operands at: 0.
+ destReg := operands at: 1.
- distReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
"cond 000 1101 0 0000 dest dist 0011 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: destReg
shifterOperand: (distReg << 8 bitOr: (48 bitOr: destReg))).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMSR (in category 'generate machine code - concretize') -----
concretizeMSR
"Generate an MSR CPSR_f, #flags instruction.
Note that we only have business with the NZCV flags so we use
N -> 8
Z -> 4
C -> 2
V -> 1.
You don't want to mess with this too much."
| flags |
+ flags := operands at: 0.
- flags := self concreteRegister: (operands at: 0).
self machineCodeAt: 0 put: (self msr: flags).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveAbR (in category 'generate machine code - concretize') -----
concretizeMoveAbR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcAddr destReg instrOffset|
srcAddr := operands at: 0.
+ destReg := operands at: 1.
- destReg := self concreteRegister: (operands at: 1).
(self isAddressRelativeToVarBase: srcAddr) ifTrue:
[self machineCodeAt: 0 put: (self ldrb: destReg rn: ConcreteVarBaseReg plus: 1 imm: srcAddr - cogit varBaseAddress).
^machineCodeSize := 4].
"load the address into ConcreteIPReg"
instrOffset := self moveCw: srcAddr intoR: ConcreteIPReg.
"We *could* overwrite the last instruction above with a LDR a, b, last-byte-of-srcAddr BUT that would break if we change to loading literals instead of forming long constants"
self machineCodeAt: instrOffset put: (self ldrb: destReg rn: ConcreteIPReg plus: 1 imm: 0).
^machineCodeSize := instrOffset + 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveAwR (in category 'generate machine code - concretize') -----
concretizeMoveAwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcAddr destReg instrOffset|
srcAddr := operands at: 0.
+ destReg := operands at: 1.
- destReg := self concreteRegister: (operands at: 1).
(self isAddressRelativeToVarBase: srcAddr) ifTrue:
[self machineCodeAt: 0 put: (self ldr: destReg rn: ConcreteVarBaseReg plusImm: srcAddr - cogit varBaseAddress).
^machineCodeSize := 4].
"load the address into ConcreteIPReg"
instrOffset := self moveCw: srcAddr intoR: ConcreteIPReg.
"We *could* overwrite the last instruction above with a LDR a, b, last-byte-of-srcAddr BUT that would break if we change to loading literals instead of forming long constants"
self machineCodeAt: instrOffset put: (self ldr: destReg rn: ConcreteIPReg plusImm: 0).
^machineCodeSize := instrOffset + 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveCqR (in category 'generate machine code - concretize') -----
concretizeMoveCqR
"Will get inlined into concretizeAt: switch."
"If the quick constant is in fact a shiftable 8bit, generate the apropriate MOV, otherwise do what is necessary for a whole word."
<var: #word type: #sqInt>
<inline: true>
|word reg|
word := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self
rotateable8bitImmediate: word
ifTrue: [:rot :immediate |
self machineCodeAt: 0 put: (self mov: reg imm: immediate ror: rot).
^machineCodeSize := 4]
ifFalse: [|invVal|
word <0
ifTrue:[invVal := -1 - word]
ifFalse:[invVal := word bitInvert32].
self rotateable8bitImmediate: invVal
ifTrue: [ :rot :immediate |
self machineCodeAt: 0 put: (self mvn: reg imm: immediate ror: rot).
^machineCodeSize := 4]
ifFalse: [^self concretizeMoveCwR]].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveCwR (in category 'generate machine code - concretize') -----
concretizeMoveCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
+ ^machineCodeSize := self loadCwInto: (operands at: 1)!
- ^machineCodeSize := self loadCwInto: (self concreteRegister: (operands at: 1))!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveM16rR (in category 'generate machine code - concretize') -----
concretizeMoveM16rR
"Will get inlined into concretizeAt: switch."
"ldrh destReg, [srcReg, #immediate],
or
move offset to ConcreteIPReg
ldrh destReg, [srcReg, ConcreteIPReg]"
<var: #offset type: #sqInt>
<inline: true>
| srcReg offset destReg instrOffset|
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self is8BitValue: offset
ifTrue:
[ :u :immediate |
self machineCodeAt: 0 "ldrh destReg, [srcReg, #immediate]"
put: (self ldrh: destReg rn: srcReg plus: u imm: immediate).
^machineCodeSize := 4]
ifFalse:
[instrOffset := self moveCw: offset intoR: ConcreteIPReg.
"ldrh destReg, [srcReg, ConcreteIPReg]"
self machineCodeAt: instrOffset put: (self ldrh: destReg rn: srcReg rm: ConcreteIPReg).
^machineCodeSize := instrOffset + 4 ].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveM64rRd (in category 'generate machine code - concretize') -----
concretizeMoveM64rRd
"Will get inlined into concretizeAt: switch."
<inline: true>
"Load a float from srcReg+offset into FP destReg"
| srcReg offset destReg u|
offset := operands at: 0.
u := offset >0 ifTrue:[1] ifFalse:[0].
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteDPFPRegister: (operands at: 2).
machineCode at: 0 put: (self fldd: destReg rn: srcReg plus: u imm: offset>>2).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveMbrR (in category 'generate machine code - concretize') -----
concretizeMoveMbrR
"Will get inlined into concretizeAt: switch."
"ldrb destReg, [srcReg, #immediate] or ldrb destReg, [srcReg, ConcreteIPReg]"
<var: #offset type: #sqInt>
<inline: true>
| srcReg offset destReg instrOffset|
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self is12BitValue: offset
ifTrue:
[ :u :immediate |
self machineCodeAt: 0 "ldrb destReg, [srcReg, #immediate]"
put: (self ldrb: destReg rn: srcReg plus: u imm: immediate).
^machineCodeSize := 4]
ifFalse:
[(self isAddressRelativeToVarBase: offset)
ifTrue:
[self machineCodeAt: 0 put: (self adds: ConcreteIPReg rn: ConcreteVarBaseReg imm: offset - cogit varBaseAddress ror: 0).
instrOffset := 4]
ifFalse:
[instrOffset := self moveCw: offset intoR: ConcreteIPReg].
"ldrb destReg, [srcReg, ConcreteIPReg]"
self machineCodeAt: instrOffset put: (self ldrb: destReg rn: srcReg rm: ConcreteIPReg).
^machineCodeSize := instrOffset + 4].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveMwrR (in category 'generate machine code - concretize') -----
concretizeMoveMwrR
"Will get inlined into concretizeAt: switch."
<var: #offset type: #sqInt>
<inline: true>
| srcReg offset destReg instrOffset|
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self is12BitValue: offset
ifTrue:
[ :u :immediate |
self machineCodeAt: 0 "ldr destReg, [srcReg, #immediate]"
put: (self ldr: destReg rn: srcReg plus: u imm: immediate).
^machineCodeSize := 4]
ifFalse:
[instrOffset := self moveCw: offset intoR: ConcreteIPReg.
"ldr destReg, [srcReg, ConcreteIPReg]"
self machineCodeAt: instrOffset put: (self ldr: destReg rn: srcReg rm: ConcreteIPReg).
^machineCodeSize := instrOffset + 4].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRAb (in category 'generate machine code - concretize') -----
concretizeMoveRAb
"Will get inlined into concretizeAt: switch."
"LEA ConcreteIPReg
strb srcReg, [ConcreteIPReg]"
<inline: true>
| srcReg destAddr instrOffset|
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
destAddr := operands at: 1.
(self isAddressRelativeToVarBase: destAddr) ifTrue:
[self machineCodeAt: 0 put: (self strb: srcReg rn: ConcreteVarBaseReg plus: 1 imm: destAddr - cogit varBaseAddress).
^machineCodeSize := 4].
"load the address into ConcreteIPReg"
instrOffset := self moveCw: destAddr intoR: ConcreteIPReg.
"We *could* overwrite the last instruction above with a LDR a, b, last-byte-of-srcAddr BUT that would break if we change to loading literals instead of forming long constants"
self machineCodeAt: instrOffset put: (self strb: srcReg rn: ConcreteIPReg plus: 1 imm: 0).
^machineCodeSize := instrOffset + 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRAw (in category 'generate machine code - concretize') -----
concretizeMoveRAw
"Will get inlined into concretizeAt: switch."
"LEA ConcreteIPReg
str srcReg, [ConcreteIPReg]"
<inline: true>
| srcReg destAddr instrOffset|
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
destAddr := operands at: 1.
(self isAddressRelativeToVarBase: destAddr) ifTrue:
[self machineCodeAt: 0 put: (self str: srcReg rn: ConcreteVarBaseReg plusImm: destAddr - cogit varBaseAddress).
^machineCodeSize := 4].
"load the address into ConcreteIPReg"
instrOffset := self moveCw: destAddr intoR: ConcreteIPReg.
"We *could* overwrite the last instruction above with a LDR a, b, last-byte-of-srcAddr BUT that would break if we change to loading literals instead of forming long constants"
self machineCodeAt: instrOffset put: (self str: srcReg rn: ConcreteIPReg plusImm: 0).
^machineCodeSize := instrOffset + 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRMbr (in category 'generate machine code - concretize') -----
concretizeMoveRMbr
"Will get inlined into concretizeAt: switch."
<var: #offset type: #sqInt>
<inline: true>
| srcReg offset baseReg instrOffset|
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
offset := operands at: 1.
+ baseReg := operands at: 2.
- baseReg := self concreteRegister: (operands at: 2).
self is12BitValue: offset
ifTrue:
[ :u :immediate |
self machineCodeAt: 0 "strb srcReg, [baseReg, #immediate]"
put: (self strb: srcReg rn: baseReg plus: u imm: immediate).
^machineCodeSize := 4]
ifFalse:
[(self isAddressRelativeToVarBase: offset)
ifTrue:
[self machineCodeAt: 0 put: (self adds: ConcreteIPReg rn: ConcreteVarBaseReg imm: offset - cogit varBaseAddress ror: 0).
instrOffset := 4]
ifFalse:
[instrOffset := self moveCw: offset intoR: ConcreteIPReg].
"strb srcReg, [baseReg, ConcreteIPReg]"
self machineCodeAt: instrOffset put: (self strb: srcReg rn: baseReg rm: ConcreteIPReg).
^machineCodeSize := instrOffset + 4 ].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRMwr (in category 'generate machine code - concretize') -----
concretizeMoveRMwr
"Will get inlined into concretizeAt: switch."
<var: #offset type: #sqInt>
<inline: true>
| srcReg offset baseReg instrOffset|
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
offset := operands at: 1.
+ baseReg := operands at: 2.
- baseReg := self concreteRegister: (operands at: 2).
self is12BitValue: offset
ifTrue:
[ :u :immediate |
self machineCodeAt: 0 "str srcReg, [baseReg, #immediate]"
put: (self str: srcReg rn: baseReg plus: u imm: immediate).
^machineCodeSize := 4]
ifFalse:
[instrOffset := self moveCw: offset intoR: ConcreteIPReg.
"str srcReg, [baseReg, ConcreteIPReg]"
self machineCodeAt: instrOffset put: (self str: srcReg rn: baseReg rm: ConcreteIPReg).
^machineCodeSize := instrOffset + 4].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRR (in category 'generate machine code - concretize') -----
concretizeMoveRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
- srcReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
"cond 000 1101 0 0000 dest 0000 0000 srcR"
self machineCodeAt: 0 put: (self mov: destReg rn: srcReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRXbrR (in category 'generate machine code - concretize') -----
concretizeMoveRXbrR
"Will get inlined into concretizeAt: switch."
"Write the word in R(src) into memory at address (base+1*index)"
<inline: true>
| index base src |
+ src := operands at: 0.
+ index := operands at: 1.
+ base := operands at: 2.
- src := self concreteRegister: (operands at: 0).
- index := self concreteRegister: (operands at: 1).
- base := self concreteRegister: (operands at: 2).
"str b src, [base, +index, LSL #0]"
"cond 011 1100 0 base srcR 00000 00 0 index"
self machineCodeAt: 0 put: (self strb: src rn: base rm: index).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRXwrR (in category 'generate machine code - concretize') -----
concretizeMoveRXwrR
"Will get inlined into concretizeAt: switch."
"Write the word in R(src) into memory at address (base+4*index)"
<inline: true>
| index base src |
+ src := operands at: 0.
+ index := operands at: 1. "index is number of *words* = 4* bytes"
+ base := operands at: 2.
- src := self concreteRegister: (operands at: 0).
- index := self concreteRegister: (operands at: 1). "index is number of *words* = 4* bytes"
- base := self concreteRegister: (operands at: 2).
"str src, [base, +index, LSL #2]"
"cond 011 1100 0 base srcR 00010 00 0 inde"
self machineCodeAt: 0 put: (self memMxr: AL reg: src base: base p: 1 u: 1 b: 0 w: 0 l: 0 rmLsl2: index).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveRdM64r (in category 'generate machine code - concretize') -----
concretizeMoveRdM64r
"Will get inlined into concretizeAt: switch."
<inline: true>
"Store FP fpReg to dstReg+offset"
| dstReg offset fpReg u|
offset := operands at: 1.
u := offset >0 ifTrue:[1] ifFalse:[0].
+ dstReg := operands at: 2.
+ fpReg := operands at: 0.
- dstReg := self concreteRegister: (operands at: 2).
- fpReg := self concreteDPFPRegister: (operands at: 0).
machineCode at: 0 put: (self fstd: fpReg rn: dstReg plus: u imm: offset>>2).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveXbrRR (in category 'generate machine code - concretize') -----
concretizeMoveXbrRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base dest |
+ index := operands at: 0. "index is number of *bytes*"
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0). "index is number of *bytes*"
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
"LDRB dest, [base, +index, LSL #0]"
"cond 011 1100 1 base dest 00000 00 0 inde"
self machineCodeAt: 0 put: (self ldrb: dest rn: base rm: index).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveXwrRR (in category 'generate machine code - concretize') -----
concretizeMoveXwrRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base dest |
+ index := operands at: 0.
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0).
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
"LDR dest, [base, +index, LSL #2]"
"cond 011 1100 1 base dest 00010 00 0 inde bulit by lowest level generator so we can do the lsl #2 on the index register"
self machineCodeAt: 0 put: (self memMxr: AL reg: dest base: base p: 1 u: 1 b: 0 w: 0 l: 1 rmLsl2: index).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeMulRdRd (in category 'generate machine code - concretize') -----
concretizeMulRdRd
"Will get inlined into concretizeAt: switch."
<inline: true>
"FP multiply regLHS by regRHS and stick result in regLHS"
| regLHS regRHS |
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode at: 0 put:(self fmuld: regLHS with: regRHS).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeNegateR (in category 'generate machine code - concretize') -----
concretizeNegateR
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
"RSB destReg, srcReg, #0"
self machineCodeAt: 0 put: (self type: 1 op: RsbOpcode set: 0 rn: reg rd: reg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeNegateableDataOperationCqR: (in category 'generate machine code - concretize') -----
concretizeNegateableDataOperationCqR: armOpcode
"Will get inlined into concretizeAt: switch."
"4 == Add, 2 == Sub, 10 = Cmp"
<inline: true>
| val rd rn |
val := operands at: 0.
+ rn := operands at: 1.
- rn := self concreteRegister: (operands at: 1).
"Extra note - if ever a version of this code wants to NOT set the Set flag
- Cmp must always have it set or it will pretend to be a SMALALBT and Very Bad Things might happen."
rd := opcode = CmpOpcode ifTrue: [0] ifFalse: [rn].
self rotateable8bitSignedImmediate: val
ifTrue:
[:rot :immediate : negate|
self machineCodeAt: 0
put: (self
type: 1
op: (negate ifTrue: [self inverseOpcodeFor: armOpcode] ifFalse: [armOpcode])
set: 1
rn: rn
rd: rd
shifterOperand: (rot >> 1"in this usage we have to halve the rot value" << 8 bitOr: immediate)).
^machineCodeSize := 4]
ifFalse: "let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
[val > 0 ifTrue:
[| hb |
hb := val highBit.
1 << hb = (val +1) ifTrue: "MVN temp, #0, making 0xffffffff"
[self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0).
"Then armOpcode reg, temp reg, lsr #(32-hb)"
self machineCodeAt: 4 put:(self dataOpType: armOpcode rd: rd rn: rn rm: ConcreteIPReg lsr: 32 - hb).
^machineCodeSize := 8]].
^self concretizeDataOperationCwR: armOpcode].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizePopR (in category 'generate machine code - concretize') -----
concretizePopR
"Will get inlined into concretizeAt: switch."
<inline: true>
| destReg |
+ destReg := operands at: 0.
- destReg := self concreteRegister: (operands at: 0).
"LDR destReg, [SP], #4"
self machineCodeAt: 0 put: (self popR: destReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizePushR (in category 'generate machine code - concretize') -----
concretizePushR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
"cond | 010 | 1001 | 0 | -Rn- | -Rd- | 0000 0000 0100" "STR srcReg, [sp, #-4]"
self machineCodeAt: 0 put: (self pushR: srcReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeSMULL (in category 'generate machine code - concretize') -----
concretizeSMULL
| srcA srcB hiResultReg loResultReg |
"Generate an SMULL loResultReg, hiResultReg, srcA, srcB instruction"
+ srcA := operands at: 0.
- srcA := self concreteRegister: (operands at: 0).
"NOTE: srcB contains the other mutiplicand at this point. It is OK to use it as the destination for the low part of the result and in fact this saves us moving it later"
+ loResultReg := srcB := operands at: 1.
+ hiResultReg := RISCTempReg.
- loResultReg := srcB := self concreteRegister: (operands at: 1).
- hiResultReg := self concreteRegister: RISCTempReg.
self machineCodeAt: 0
put: (self type: 0 op: 6 set: 0 rn: hiResultReg rd: loResultReg)
+ (srcA << 8)
+ (9 << 4)
+ srcB.
^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>concretizeSqrtRd (in category 'generate machine code - concretize') -----
concretizeSqrtRd
"Will get inlined into concretizeAt: switch."
<inline: true>
"Square root of FP regLHS into regLHS"
| regLHS |
+ regLHS := operands at: 1.
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode at: 0 put:(self fsqrtd: regLHS).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeSubCqR (in category 'generate machine code - concretize') -----
concretizeSubCqR
"Will get inlined into concretizeAt: switch."
"Try whether the quick constant is a small negative number. If it is, optimize."
<var: #word type: #sqInt>
<inline: true>
| word |
word := operands at: 0.
self rotateable8bitImmediate: word
ifTrue: [ :rot :immediate | | reg |
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self subs: reg rn: reg imm: immediate ror: rot).
^machineCodeSize := 4]
ifFalse: [
"before building a full load of a big constant, see if we can do an add of the constant negated"
self rotateable8bitImmediate: word negated
ifTrue: [ :rot :immediate | | reg |
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self adds: reg rn: reg imm: immediate ror: rot).
^machineCodeSize := 4]
ifFalse: [^self concretizeDataOperationCwR: SubOpcode]].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>concretizeSubRdRd (in category 'generate machine code - concretize') -----
concretizeSubRdRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| regLHS regRHS |
"Subtract FP regRHS from FP regLHS and leave the result in FP regLHS"
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode at: 0 put:(self fsubd: regLHS with: regRHS).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogARMCompiler>>concretizeTstCqR (in category 'generate machine code - concretize') -----
concretizeTstCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
self rotateable8bitImmediate: (operands at: 0)
ifTrue: [ :rot :immediate | | reg |
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self tst: reg rn: reg imm: immediate ror: rot).
^machineCodeSize := 4]
ifFalse: [^self concretizeDataOperationCwR: TstOpcode].
^0 "to keep Slang happy"!
Item was changed:
----- Method: CogARMCompiler>>genDivR:R:Quo:Rem: (in category 'abstract instructions') -----
genDivR: abstractRegDivisor R: abstractRegDividend Quo: abstractRegQuotient Rem: abstractRegRemainder
"Currently no instruction level support for divide on ARM. See also #canDivQuoRem"
| rDividend rDivisor rQuotient rRemainder divRemFunctionAddr |
<var: #divRemFunctionAddr type: #usqInt>
self assert: abstractRegDividend ~= abstractRegDivisor.
self assert: abstractRegQuotient ~= abstractRegRemainder.
+ rDividend := abstractRegDividend.
+ rDivisor := abstractRegDivisor.
- rDividend := self concreteRegister: abstractRegDividend.
- rDivisor := self concreteRegister: abstractRegDivisor.
rDividend = CArg0Reg ifFalse:[
"we need to move the value in rDividend to CArg0Reg. Best to double check if rDivisor is already using it first"
rDivisor = CArg0Reg ifTrue:[ "oh dear; we also need to move rDivisor's value out of the way first.. I'll move it to CArg1Reg and if some nitwit has managed to put rDividend there they deserve the crash"
rDividend = CArg1Reg ifTrue:[self error: 'register choices in genDivR:R:Quo:Rem: made life impossible'].
cogit MoveR: rDivisor R: CArg1Reg.
"and update rDivisor or we get buggerd by the next clause"
rDivisor := CArg1Reg].
cogit MoveR: rDividend R: CArg0Reg.
].
rDivisor = CArg1Reg ifFalse:[
cogit MoveR: rDivisor R: CArg1Reg].
divRemFunctionAddr := self aeabiDivModFunctionAddr.
cogit backEnd saveAndRestoreLinkRegAround:
[cogit CallFullRT: (self cCode: [divRemFunctionAddr asUnsignedInteger]
inSmalltalk: [cogit simulatedTrampolineFor: divRemFunctionAddr])].
"Now we need to move the r0/1 results back to rQuotient & rRemainder"
+ rQuotient := abstractRegQuotient.
+ rRemainder := abstractRegRemainder.
- rQuotient := self concreteRegister: abstractRegQuotient.
- rRemainder := self concreteRegister: abstractRegRemainder.
rQuotient = CArg0Reg ifFalse:["oh good grief, not again"
cogit MoveR: CArg0Reg R: rQuotient.
rQuotient = CArg1Reg ifTrue:[self error: 'register choices in genDivR:R:Quo:Rem: made life impossible'] ].
rRemainder = CArg1Reg ifFalse:[
cogit MoveR: CArg1Reg R: rRemainder].
!
Item was removed:
- ----- Method: CogAbstractInstruction class>>isConcreteRISCTempRegister: (in category 'testing') -----
- isConcreteRISCTempRegister: concreteRegister
- "For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
- ^self subclassResponsibility!
Item was added:
+ ----- Method: CogAbstractInstruction class>>isRISCTempRegister: (in category 'testing') -----
+ isRISCTempRegister: reg
+ "For tests to filter-out bogus values left in the RISCTempRegister, if any."
+ ^self subclassResponsibility!
Item was removed:
- ----- Method: CogAbstractInstruction>>abstractRegisterForConcreteRegister: (in category 'private') -----
- abstractRegisterForConcreteRegister: reg
- <inline: true>
- self cCode: [] inSmalltalk: [self assert: reg isInteger].
- ^reg!
Item was changed:
----- Method: CogAbstractInstruction>>cResultRegister (in category 'accessing') -----
cResultRegister
+ "Answer the register through which C funcitons return integral results."
+ <inline: true>
- "Answer the abstract register for the C result register.
- Only partially implemented (there is as yet no CResultReg abstract reg).
- Works on x86 since TempReg = EAX = C result reg."
self subclassResponsibility!
Item was removed:
- ----- Method: CogAbstractInstruction>>concreteDPFPRegister: (in category 'encoding') -----
- concreteDPFPRegister: reg
- <inline: true>
- self cCode: [] inSmalltalk: [self assert: reg isInteger].
- ^reg!
Item was removed:
- ----- Method: CogAbstractInstruction>>concreteRegister: (in category 'private') -----
- concreteRegister: reg
- <inline: true>
- self cCode: [] inSmalltalk: [self assert: reg isInteger].
- ^reg!
Item was changed:
CogAbstractInstruction subclass: #CogIA32Compiler
instanceVariableNames: ''
+ classVariableNames: 'CDQ CMPXCHGAwR CMPXCHGMwrR CPUID EAX EBP EBX ECX EDI EDX ESI ESP IDIVR IMULRR LFENCE LOCK MFENCE ModReg ModRegInd ModRegIndDisp32 ModRegIndSIB ModRegRegDisp32 ModRegRegDisp8 SFENCE SIB1 SIB2 SIB4 SIB8 XCHGAwR XCHGMwrR XCHGRR XMM0L XMM1L XMM2L XMM3L XMM4L XMM5L XMM6L XMM7L'
- classVariableNames: 'CDQ CMPXCHGAwR CMPXCHGMwrR CPUID EAX EBP EBX ECX EDI EDX ESI ESP IDIVR IMULRR LFENCE LOCK MFENCE ModReg ModRegInd ModRegIndDisp32 ModRegIndSIB ModRegRegDisp32 ModRegRegDisp8 SFENCE SIB1 SIB2 SIB4 SIB8 XCHGAwR XCHGMwrR XCHGRR XMM0H XMM0L XMM1H XMM1L XMM2H XMM2L XMM3H XMM3L XMM4H XMM4L XMM5H XMM5L XMM6H XMM6L XMM7H XMM7L'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogIA32Compiler commentStamp: 'eem 9/14/2015 17:13' prior: 0!
I generate IA32 (x86) instructions from CogAbstractInstructions. For reference see
1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
http://www.intel.com/products/processor/manuals/
(® is supposed to be the Unicode "registered sign".
This class does not take any special action to flush the instruction cache on instruction-modification, trusting that Intel and AMD processors correctly invalidate the instruction cache via snooping. According to the manuals, this will work on systems where code and data have the same virtual address. The CogICacheFlushingIA32Compiler subclass exists to use the CPUID instruction to serialize instruction-modification for systems with code and data at different virtual addresses.!
Item was changed:
----- Method: CogIA32Compiler class>>initialize (in category 'class initialization') -----
initialize
"Initialize various IA32/x86 instruction-related constants.
[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M"
"CogIA32Compiler initialize"
self ~~ CogIA32Compiler ifTrue: [^self].
"N.B. EAX ECX and EDX are caller-save (scratch) registers.
EBX ESI and EDI are callee-save; see concreteRegisterFor:"
EAX := 0.
ECX := 1. "Were they completely mad or simply sadistic?"
EDX := 2.
EBX := 3.
ESP := 4.
EBP := 5.
ESI := 6.
EDI := 7.
XMM0L := 0.
+ XMM1L := 1.
+ XMM2L := 2.
+ XMM3L := 3.
+ XMM4L := 4.
+ XMM5L := 5.
+ XMM6L := 6.
+ XMM7L := 7.
- XMM1L := 2.
- XMM2L := 4.
- XMM3L := 6.
- XMM4L := 8.
- XMM5L := 10.
- XMM6L := 12.
- XMM7L := 14.
- XMM0H := 1.
- XMM1H := 3.
- XMM2H := 5.
- XMM3H := 7.
- XMM4H := 9.
- XMM5H := 11.
- XMM6H := 13.
- XMM7H := 15.
-
"Mod R/M Mod fields. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-2"
ModRegInd := 0.
ModRegIndSIB := 4.
ModRegIndDisp32 := 5.
ModRegRegDisp8 := 1.
ModRegRegDisp32 := 2.
ModReg := 3.
"SIB Scaled Index modes. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-3"
SIB1 := 0.
SIB2 := 1.
SIB4 := 2.
SIB8 := 3.
"Specific instructions"
self
initializeSpecificOpcodes: #(CDQ IDIVR IMULRR CPUID LFENCE MFENCE SFENCE LOCK CMPXCHGAwR CMPXCHGMwrR XCHGAwR XCHGMwrR XCHGRR)
in: thisContext method!
Item was removed:
- ----- Method: CogIA32Compiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
- isConcreteRISCTempRegister: concreteRegister
- "For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
- ^false!
Item was added:
+ ----- Method: CogIA32Compiler class>>isRISCTempRegister: (in category 'testing') -----
+ isRISCTempRegister: reg
+ "For tests to filter-out bogus values left in the RISCTempRegister, if any."
+ ^false!
Item was changed:
----- Method: CogIA32Compiler>>cResultRegister (in category 'accessing') -----
cResultRegister
+ "Answer the register through which C funcitons return integral results."
+ <inline: true>
+ ^EAX!
- "Answer the abstract register for the C result register.
- Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
- ^self abstractRegisterForConcreteRegister: EAX!
Item was changed:
----- Method: CogIA32Compiler>>callerSavedRegisterMask (in category 'accessing') -----
callerSavedRegisterMask
+ ^cogit registerMaskFor: EAX and: ECX and: EDX!
- ^cogit
- registerMaskFor: (self abstractRegisterForConcreteRegister: EAX)
- and: (self abstractRegisterForConcreteRegister: ECX)
- and: (self abstractRegisterForConcreteRegister: EDX)!
Item was changed:
----- Method: CogIA32Compiler>>computeMaximumSize (in category 'generate machine code') -----
computeMaximumSize
"Compute the maximum size for each opcode. This allows jump offsets to
be determined, provided that all backward branches are long branches."
"N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^0].
[AlignmentNops] -> [^(operands at: 0) - 1].
[Fill32] -> [^4].
[Nop] -> [^1].
"Specific Control/Data Movement"
[CDQ] -> [^1].
[IDIVR] -> [^2].
[IMULRR] -> [^3].
[CPUID] -> [^2].
[CMPXCHGAwR] -> [^7].
+ [CMPXCHGMwrR] -> [^(operands at: 1) = ESP
- [CMPXCHGMwrR] -> [^(self concreteRegister: (operands at: 1)) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[LFENCE] -> [^3].
[MFENCE] -> [^3].
[SFENCE] -> [^3].
[LOCK] -> [^1].
[XCHGAwR] -> [^6].
+ [XCHGMwrR] -> [^(operands at: 1) = ESP
- [XCHGMwrR] -> [^(self concreteRegister: (operands at: 1)) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [6]]].
+ [XCHGRR] -> [^((operands at: 0) = EAX
+ or: [(operands at: 1) = EAX])
- [XCHGRR] -> [^((self concreteRegister: (operands at: 0)) = EAX
- or: [(self concreteRegister: (operands at: 1)) = EAX])
ifTrue: [1]
ifFalse: [2]].
"Control"
[CallFull] -> [^5].
[Call] -> [^5].
[JumpR] -> [^2].
[JumpFull] -> [self resolveJumpTarget. ^5].
[JumpLong] -> [self resolveJumpTarget. ^5].
[Jump] -> [self resolveJumpTarget. ^5].
[JumpZero] -> [self resolveJumpTarget. ^6].
[JumpNonZero] -> [self resolveJumpTarget. ^6].
[JumpNegative] -> [self resolveJumpTarget. ^6].
[JumpNonNegative] -> [self resolveJumpTarget. ^6].
[JumpOverflow] -> [self resolveJumpTarget. ^6].
[JumpNoOverflow] -> [self resolveJumpTarget. ^6].
[JumpCarry] -> [self resolveJumpTarget. ^6].
[JumpNoCarry] -> [self resolveJumpTarget. ^6].
[JumpLess] -> [self resolveJumpTarget. ^6].
[JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpGreater] -> [self resolveJumpTarget. ^6].
[JumpLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpBelow] -> [self resolveJumpTarget. ^6].
[JumpAboveOrEqual] -> [self resolveJumpTarget. ^6].
[JumpAbove] -> [self resolveJumpTarget. ^6].
[JumpBelowOrEqual] -> [self resolveJumpTarget. ^6].
[JumpLongZero] -> [self resolveJumpTarget. ^6].
[JumpLongNonZero] -> [self resolveJumpTarget. ^6].
[JumpFPEqual] -> [self resolveJumpTarget. ^6].
[JumpFPNotEqual] -> [self resolveJumpTarget. ^6].
[JumpFPLess] -> [self resolveJumpTarget. ^6].
[JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPGreater] -> [self resolveJumpTarget. ^6].
[JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPOrdered] -> [self resolveJumpTarget. ^6].
[JumpFPUnordered] -> [self resolveJumpTarget. ^6].
[RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]].
[Stop] -> [^1].
"Arithmetic"
[AddCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
+ ifFalse: [(operands at: 1) = EAX
- ifFalse: [(self concreteRegister: (operands at: 1)) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AndCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
+ ifFalse: [(operands at: 1) = EAX
- ifFalse: [(self concreteRegister: (operands at: 1)) = EAX
ifTrue: [5]
ifFalse: [6]]].
[CmpCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
+ ifFalse: [(operands at: 1) = EAX
- ifFalse: [(self concreteRegister: (operands at: 1)) = EAX
ifTrue: [5]
ifFalse: [6]]].
[OrCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
+ ifFalse: [(operands at: 1) = EAX
- ifFalse: [(self concreteRegister: (operands at: 1)) = EAX
ifTrue: [5]
ifFalse: [6]]].
[SubCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
+ ifFalse: [(operands at: 1) = EAX
- ifFalse: [(self concreteRegister: (operands at: 1)) = EAX
ifTrue: [5]
ifFalse: [6]]].
+ [TstCqR] -> [^((self isQuick: (operands at: 0)) and: [(operands at: 1) < 4])
- [TstCqR] -> [^((self isQuick: (operands at: 0)) and: [(self concreteRegister: (operands at: 1)) < 4])
ifTrue: [3]
+ ifFalse: [(operands at: 1) = EAX
- ifFalse: [(self concreteRegister: (operands at: 1)) = EAX
ifTrue: [5]
ifFalse: [6]]].
+ [AddCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
+ [AndCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
+ [CmpCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
+ [OrCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
+ [SubCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
+ [XorCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
- [AddCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].
- [AndCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].
- [CmpCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].
- [OrCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].
- [SubCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].
- [XorCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].
[AddRR] -> [^2].
[AndRR] -> [^2].
[CmpRR] -> [^2].
[OrRR] -> [^2].
[XorRR] -> [^2].
[SubRR] -> [^2].
[NegateR] -> [^2].
[LoadEffectiveAddressMwrR]
-> [^((self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [6])
+ + ((operands at: 1) = ESP
- + ((self concreteRegister: (operands at: 1)) = ESP
ifTrue: [1]
ifFalse: [0])].
[LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftLeftRR] -> [^self computeShiftRRSize].
[LogicalShiftRightRR] -> [^self computeShiftRRSize].
[ArithmeticShiftRightRR] -> [^self computeShiftRRSize].
[AddRdRd] -> [^4].
[CmpRdRd] -> [^4].
[SubRdRd] -> [^4].
[MulRdRd] -> [^4].
[DivRdRd] -> [^4].
[SqrtRd] -> [^4].
"Data Movement"
[MoveCqR] -> [^(operands at: 0) = 0 ifTrue: [2] ifFalse: [5]].
[MoveCwR] -> [^5].
[MoveRR] -> [^2].
[MoveRdRd] -> [^4].
+ [MoveAwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
+ [MoveRAw] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
- [MoveAwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].
- [MoveRAw] -> [^(self concreteRegister: (operands at: 0)) = EAX ifTrue: [5] ifFalse: [6]].
[MoveAbR] -> [^7].
+ [MoveRAb] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
- [MoveRAb] -> [^(self concreteRegister: (operands at: 0)) = EAX ifTrue: [5] ifFalse: [6]].
[MoveRMwr] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
+ and: [(operands at: 2) ~= EBP])
- and: [(self concreteRegister: (operands at: 2)) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ + ((operands at: 2) = ESP
- + ((self concreteRegister: (operands at: 2)) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRdM64r] -> [^((self isQuick: (operands at: 1))
ifTrue: [5]
ifFalse: [8])
+ + ((operands at: 2) = ESP
- + ((self concreteRegister: (operands at: 2)) = ESP
ifTrue: [1]
ifFalse: [0])].
+ [MoveMbrR] -> [^(operands at: 1) = ESP
- [MoveMbrR] -> [^(self concreteRegister: (operands at: 1)) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
+ [MoveRMbr] -> [^(operands at: 2) = ESP
- [MoveRMbr] -> [^(self concreteRegister: (operands at: 2)) = ESP
ifTrue: [7]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].
+ [MoveM16rR] -> [^(operands at: 1) = ESP
- [MoveM16rR] -> [^(self concreteRegister: (operands at: 1)) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveM64rRd] -> [^((self isQuick: (operands at: 0))
ifTrue: [5]
ifFalse: [8])
+ + ((operands at: 1) = ESP
- + ((self concreteRegister: (operands at: 1)) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveMwrR] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
+ and: [(operands at: 1) ~= EBP])
- and: [(self concreteRegister: (operands at: 1)) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ + ((operands at: 1) = ESP
- + ((self concreteRegister: (operands at: 1)) = ESP
ifTrue: [1]
ifFalse: [0])].
+ [MoveXbrRR] -> [self assert: (operands at: 0) ~= ESP.
+ ^(operands at: 1) = EBP
- [MoveXbrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= ESP.
- ^(self concreteRegister: (operands at: 1)) = EBP
ifTrue: [5]
ifFalse: [4]].
+ [MoveRXbrR] -> [self assert: (operands at: 1) ~= ESP.
+ ^((operands at: 2) = EBP
- [MoveRXbrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= ESP.
- ^((self concreteRegister: (operands at: 2)) = EBP
ifTrue: [4]
ifFalse: [3])
+ + ((operands at: 0) >= 4
- + ((self concreteRegister: (operands at: 0)) >= 4
ifTrue: [2]
ifFalse: [0])].
+ [MoveXwrRR] -> [self assert: (operands at: 0) ~= ESP.
+ ^(operands at: 1) = EBP
- [MoveXwrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= ESP.
- ^(self concreteRegister: (operands at: 1)) = EBP
ifTrue: [4]
ifFalse: [3]].
+ [MoveRXwrR] -> [self assert: (operands at: 1) ~= ESP.
+ ^(operands at: 2) = EBP
- [MoveRXwrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= ESP.
- ^(self concreteRegister: (operands at: 2)) = EBP
ifTrue: [4]
ifFalse: [3]].
[PopR] -> [^1].
[PushR] -> [^1].
[PushCq] -> [^(self isQuick: (operands at: 0)) ifTrue: [2] ifFalse: [5]].
[PushCw] -> [^5].
[PrefetchAw] -> [^self hasSSEInstructions ifTrue: [7] ifFalse: [0]].
"Conversion"
[ConvertRRd] -> [^4] }.
^0 "to keep C compiler quiet"!
Item was changed:
----- Method: CogIA32Compiler>>computeShiftRRSize (in category 'generate machine code') -----
computeShiftRRSize
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into ecx."
| shiftCountReg |
+ shiftCountReg := operands at: 0.
- shiftCountReg := self concreteRegister: (operands at: 0).
shiftCountReg = ECX ifTrue:
[^maxSize := 2].
^maxSize := shiftCountReg = EAX
ifTrue: [1 "XCHG EAX,r2" + 2 "Sxx" + 1 "XCHG EAX,r2"]
ifFalse: [2 "XCHG r1,r2" + 2 "Sxx" + 2 "XCHG r1,r2"]!
Item was changed:
----- Method: CogIA32Compiler>>concretizeAddCqR (in category 'generate machine code') -----
concretizeAddCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r05;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeAddCwR (in category 'generate machine code') -----
concretizeAddCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r05;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeAndCqR (in category 'generate machine code') -----
concretizeAndCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| mask reg |
mask := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
(self isQuick: mask) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (mask bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r25;
at: 1 put: (mask bitAnd: 16rFF);
at: 2 put: (mask >> 8 bitAnd: 16rFF);
at: 3 put: (mask >> 16 bitAnd: 16rFF);
at: 4 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (mask bitAnd: 16rFF);
at: 3 put: (mask >> 8 bitAnd: 16rFF);
at: 4 put: (mask >> 16 bitAnd: 16rFF);
at: 5 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeAndCwR (in category 'generate machine code') -----
concretizeAndCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r25;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeArithmeticShiftRightCqR (in category 'generate machine code') -----
concretizeArithmeticShiftRightCqR
<inline: true>
| shiftCount reg |
shiftCount := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
shiftCount = 1 ifTrue:
[machineCode
at: 0 put: 16rD1;
at: 1 put: (self mod: ModReg RM: reg RO: 7).
^machineCodeSize := 2].
machineCode
at: 0 put: 16rC1;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: shiftCount.
^machineCodeSize := 3!
Item was changed:
----- Method: CogIA32Compiler>>concretizeArithmeticShiftRightRR (in category 'generate machine code') -----
concretizeArithmeticShiftRightRR
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into %ecx."
<inline: true>
| shiftCountReg destReg regToShift |
+ shiftCountReg := operands at: 0.
+ destReg := operands at: 1.
- shiftCountReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
shiftCountReg = ECX ifTrue:
[machineCode
at: 0 put: 16rD3;
at: 1 put: (self mod: ModReg RM: destReg RO: 7).
^machineCodeSize := 2].
regToShift := destReg == shiftCountReg
ifTrue: [ECX]
ifFalse: [destReg = ECX
ifTrue: [shiftCountReg]
ifFalse: [destReg]].
shiftCountReg = EAX ifTrue:
[machineCode
at: 0 put: 16r90 + ECX; "XCHG EAX,ECX"
at: 1 put: 16rD3; "SAR ECX,EAX"
at: 2 put: (self mod: ModReg RM: regToShift RO: 7);
at: 3 put: 16r90 + ECX. "XCHG EAX,ECX"
^machineCodeSize := 4].
machineCode
at: 0 put: 16r87; "XCHG E?X,ECX"
at: 1 put: (self mod: ModReg RM: ECX RO: shiftCountReg);
at: 2 put: 16rD3; "SAR ECX,E!!X"
at: 3 put: (self mod: ModReg RM: regToShift RO: 7);
at: 4 put: 16r87; "XCHG E?X,ECX"
at: 5 put: (self mod: ModReg RM: ECX RO: shiftCountReg).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeCMPXCHGAwR (in category 'generate machine code') -----
concretizeCMPXCHGAwR
<inline: true>
| addressOperand reg |
addressOperand := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 3 put: (addressOperand bitAnd: 16rFF);
at: 4 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 6 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogIA32Compiler>>concretizeCMPXCHGMwrR (in category 'generate machine code') -----
concretizeCMPXCHGMwrR
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogIA32Compiler>>concretizeCmpCqR (in category 'generate machine code') -----
concretizeCmpCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r3D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeCmpCwR (in category 'generate machine code') -----
concretizeCmpCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r3D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeCmpRdRd (in category 'generate machine code') -----
concretizeCmpRdRd
"Will get inlined into concretizeAt: switch.
We use UCOMISD (see p 4-260 [2])"
<inline: true>
| regLHS regRHS |
"CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode
at: 0 put: 16r66;
at: 1 put: 16r0F;
at: 2 put: 16r2E;
at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
^machineCodeSize := 4!
Item was changed:
----- Method: CogIA32Compiler>>concretizeConvertRRd (in category 'generate machine code') -----
concretizeConvertRRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg destReg |
+ srcReg := operands at:0.
+ destReg := operands at: 1.
- srcReg := self concreteRegister: (operands at:0).
- destReg := self concreteDPFPRegister: (operands at: 1).
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r2A;
at: 3 put: (self mod: ModReg RM: srcReg RO: destReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogIA32Compiler>>concretizeIDIVR (in category 'generate machine code') -----
concretizeIDIVR
"Will get inlined into concretizeAt: switch."
<inline: true>
| regDivisor |
+ regDivisor := operands at: 0.
- regDivisor := self concreteRegister: (operands at: 0).
machineCode
at: 0 put: 16rF7;
at: 1 put: (self mod: ModReg RM: regDivisor RO: 7).
^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>concretizeJumpR (in category 'generate machine code') -----
concretizeJumpR
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
machineCode
at: 0 put: 16rFF;
at: 1 put: (self mod: ModReg RM: reg RO: 4).
^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>concretizeLoadEffectiveAddressMwrR (in category 'generate machine code') -----
concretizeLoadEffectiveAddressMwrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r8D;
at: 1 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 2 put: (offset bitAnd: 16rFF).
^machineCodeSize := 3].
machineCode
at: 0 put: 16r8D;
at: 1 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 2 put: (offset bitAnd: 16rFF);
at: 3 put: (offset >> 8 bitAnd: 16rFF);
at: 4 put: (offset >> 16 bitAnd: 16rFF);
at: 5 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r8D;
at: 1 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 2 put: (self s: SIB1 i: 4 b: srcReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r8D;
at: 1 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 2 put: (self s: SIB1 i: 4 b: srcReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogIA32Compiler>>concretizeLogicalShiftLeftCqR (in category 'generate machine code') -----
concretizeLogicalShiftLeftCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
distance = 1 ifTrue:
[machineCode
at: 0 put: 16rD1;
at: 1 put: (self mod: ModReg RM: reg RO: 4).
^machineCodeSize := 2].
machineCode
at: 0 put: 16rC1;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: distance.
^machineCodeSize := 3!
Item was changed:
----- Method: CogIA32Compiler>>concretizeLogicalShiftLeftRR (in category 'generate machine code') -----
concretizeLogicalShiftLeftRR
<inline: true>
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into %ecx."
| shiftCountReg destReg regToShift |
+ shiftCountReg := operands at: 0.
+ destReg := operands at: 1.
- shiftCountReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
shiftCountReg = ECX ifTrue:
[machineCode
at: 0 put: 16rD3;
at: 1 put: (self mod: ModReg RM: destReg RO: 4).
^machineCodeSize := 2].
regToShift := destReg == shiftCountReg
ifTrue: [ECX]
ifFalse: [destReg = ECX
ifTrue: [shiftCountReg]
ifFalse: [destReg]].
shiftCountReg = EAX ifTrue:
[machineCode
at: 0 put: 16r90 + ECX; "XCHG EAX,ECX"
at: 1 put: 16rD3; "SAR ECX,EAX"
at: 2 put: (self mod: ModReg RM: regToShift RO: 4);
at: 3 put: 16r90 + ECX. "XCHG EAX,ECX"
^machineCodeSize := 4].
machineCode
at: 0 put: 16r87; "XCHG E?X,ECX"
at: 1 put: (self mod: ModReg RM: ECX RO: shiftCountReg);
at: 2 put: 16rD3; "SAR ECX,E!!X"
at: 3 put: (self mod: ModReg RM: regToShift RO: 4);
at: 4 put: 16r87; "XCHG E?X,ECX"
at: 5 put: (self mod: ModReg RM: ECX RO: shiftCountReg).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeLogicalShiftRightCqR (in category 'generate machine code') -----
concretizeLogicalShiftRightCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
distance = 1 ifTrue:
[machineCode
at: 0 put: 16rD1;
at: 1 put: (self mod: ModReg RM: reg RO: 5).
^machineCodeSize := 2].
machineCode
at: 0 put: 16rC1;
at: 1 put: (self mod: ModReg RM: reg RO: 5);
at: 2 put: distance.
^machineCodeSize := 3!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveAbR (in category 'generate machine code') -----
concretizeMoveAbR
"N.B. we zero-extend because we state byteReadsZeroExtend."
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg |
addressOperand := operands at: 0.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB6;
at: 2 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 3 put: (addressOperand bitAnd: 16rFF);
at: 4 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 6 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveAwR (in category 'generate machine code') -----
concretizeMoveAwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg |
addressOperand := operands at: 0.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = EAX ifTrue:
[machineCode
at: 0 put: 16rA1;
at: 1 put: (addressOperand bitAnd: 16rFF);
at: 2 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 3 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 4 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 2 put: (addressOperand bitAnd: 16rFF);
at: 3 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveCqR (in category 'generate machine code') -----
concretizeMoveCqR
"Will get inlined into concretizeAt: switch.
Note that for quick constants, xor reg,reg, movq r8 may be shorter. But
we don't consider it worthwhile and so just provide concretizeMoveCwR."
<inline: true>
| reg |
(operands at: 0) ~= 0 ifTrue:
[^self concretizeMoveCwR].
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: 16r31;
at: 1 put: (self mod: ModReg RM: reg RO: reg).
^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveCwR (in category 'generate machine code') -----
concretizeMoveCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value |
value := operands at: 0.
machineCode
+ at: 0 put: 16rB8 + (operands at: 1);
- at: 0 put: 16rB8 + (self concreteRegister: (operands at: 1));
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveM16rR (in category 'generate machine code') -----
concretizeMoveM16rR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB7;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB7;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB7;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB7;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveM64rRd (in category 'generate machine code') -----
concretizeMoveM64rRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteDPFPRegister: (operands at: 2).
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r10;
at: 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r10;
at: 3 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r10;
at: 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 4 put: (self s: SIB1 i: 4 b: srcReg);
at: 5 put: (offset bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r10;
at: 3 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 4 put: (self s: SIB1 i: 4 b: srcReg);
at: 5 put: (offset bitAnd: 16rFF);
at: 6 put: (offset >> 8 bitAnd: 16rFF);
at: 7 put: (offset >> 16 bitAnd: 16rFF);
at: 8 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 9!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveMbrR (in category 'generate machine code') -----
concretizeMoveMbrR
"N.B. we zero-extend because we state byteReadsZeroExtend."
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0f;
at: 1 put: 16rb6;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r0f;
at: 1 put: 16rb6;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0f;
at: 1 put: 16rb6;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r0f;
at: 1 put: 16rb6;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveMwrR (in category 'generate machine code') -----
concretizeMoveMwrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
srcReg ~= ESP ifTrue:
[(offset = 0 and: [srcReg ~= EBP]) ifTrue:
[machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegInd RM: srcReg RO: destReg).
^machineCodeSize := 2].
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 2 put: (offset bitAnd: 16rFF).
^machineCodeSize := 3].
machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 2 put: (offset bitAnd: 16rFF);
at: 3 put: (offset >> 8 bitAnd: 16rFF);
at: 4 put: (offset >> 16 bitAnd: 16rFF);
at: 5 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
"ESP:"
offset = 0 ifTrue:
[machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegInd RM: srcReg RO: destReg);
at: 2 put: (self s: SIB1 i: 4 b: srcReg).
^machineCodeSize := 3].
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 2 put: (self s: SIB1 i: 4 b: srcReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 2 put: (self s: SIB1 i: 4 b: srcReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveRAb (in category 'generate machine code') -----
concretizeMoveRAb
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
addressOperand := operands at: 1.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16rA2;
at: 1 put: (addressOperand bitAnd: 16rFF);
at: 2 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 3 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 4 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r88;
at: 1 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 2 put: (addressOperand bitAnd: 16rFF);
at: 3 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveRAw (in category 'generate machine code') -----
concretizeMoveRAw
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
addressOperand := operands at: 1.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16rA3;
at: 1 put: (addressOperand bitAnd: 16rFF);
at: 2 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 3 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 4 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 2 put: (addressOperand bitAnd: 16rFF);
at: 3 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveRMbr (in category 'generate machine code') -----
concretizeMoveRMbr
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 1.
+ srcReg := operands at: 0.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 2).
srcReg >= 4 ifTrue: [self error: 'invalid register'].
destReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r88;
at: 1 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 2 put: (offset bitAnd: 16rFF).
^machineCodeSize := 3].
machineCode
at: 0 put: 16r88;
at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 2 put: (offset bitAnd: 16rFF);
at: 3 put: (offset >> 8 bitAnd: 16rFF);
at: 4 put: (offset >> 16 bitAnd: 16rFF);
at: 5 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 0 put: 16r88;
at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 2 put: (self s: SIB1 i: 4 b: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveRMwr (in category 'generate machine code') -----
concretizeMoveRMwr
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
offset := operands at: 1.
+ destReg := operands at: 2.
- destReg := self concreteRegister: (operands at: 2).
destReg ~= ESP ifTrue:
[(offset = 0 and: [destReg ~= EBP]) ifTrue:
[machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegInd RM: destReg RO: srcReg).
^machineCodeSize := 2].
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 2 put: (offset bitAnd: 16rFF).
^machineCodeSize := 3].
machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 2 put: (offset bitAnd: 16rFF);
at: 3 put: (offset >> 8 bitAnd: 16rFF);
at: 4 put: (offset >> 16 bitAnd: 16rFF);
at: 5 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
"ESP:"
offset = 0 ifTrue:
[machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegInd RM: destReg RO: srcReg);
at: 2 put: (self s: SIB1 i: 4 b: destReg).
^machineCodeSize := 3].
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 2 put: (self s: SIB1 i: 4 b: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 2 put: (self s: SIB1 i: 4 b: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveRXbrR (in category 'generate machine code') -----
concretizeMoveRXbrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| src index base swapreg mcIdx |
+ src := operands at: 0.
+ index := operands at: 1.
+ base := operands at: 2.
- src := self concreteRegister: (operands at: 0).
- index := self concreteRegister: (operands at: 1).
- base := self concreteRegister: (operands at: 2).
mcIdx := 0.
swapreg := NoReg.
src >= 4 ifTrue: "x86 allows movb %rl, mem only with %al, %bl, %cl, %dl, so swap with the first one that isn't used."
[swapreg := src.
index = EAX ifTrue: [index := swapreg].
base = EAX ifTrue: [base := swapreg].
src := EAX.
mcIdx := 1.
machineCode at: 0 put: 16r90 + swapreg].
base ~= EBP ifTrue:
[machineCode
at: mcIdx + 0 put: 16r88;
at: mcIdx + 1 put: (self mod: ModRegInd RM: 4 RO: src);
at: mcIdx + 2 put: (self s: SIB1 i: index b: base).
swapreg ~= NoReg ifTrue:
[machineCode at: mcIdx + 3 put: 16r90 + swapreg].
^machineCodeSize := 3 + (2 * mcIdx)].
machineCode
at: mcIdx + 0 put: 16r88;
at: mcIdx + 1 put: (self mod: ModRegRegDisp8 RM: 4 RO: src);
at: mcIdx + 2 put: (self s: SIB1 i: index b: base);
at: mcIdx + 3 put: 0.
swapreg ~= NoReg ifTrue:
[machineCode at: mcIdx + 4 put: 16r90 + swapreg].
^machineCodeSize := 4 + (2 * mcIdx)!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveRXwrR (in category 'generate machine code') -----
concretizeMoveRXwrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base src |
+ src := operands at: 0.
+ index := operands at: 1.
+ base := operands at: 2.
- src := self concreteRegister: (operands at: 0).
- index := self concreteRegister: (operands at: 1).
- base := self concreteRegister: (operands at: 2).
base ~= EBP ifTrue:
[machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegInd RM: 4 RO: src);
at: 2 put: (self s: SIB4 i: index b: base).
^machineCodeSize := 3].
machineCode
at: 0 put: 16r89;
at: 1 put: (self mod: ModRegRegDisp8 RM: 4 RO: src);
at: 2 put: (self s: SIB4 i: index b: base);
at: 3 put: 0.
^machineCodeSize := 4!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveRdM64r (in category 'generate machine code') -----
concretizeMoveRdM64r
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
+ srcReg := operands at: 0.
- srcReg := self concreteDPFPRegister: (operands at: 0).
offset := operands at: 1.
+ destReg := operands at: 2.
- destReg := self concreteRegister: (operands at: 2).
destReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r11;
at: 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r11;
at: 3 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r11;
at: 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 4 put: (self s: SIB1 i: 4 b: destReg);
at: 5 put: (offset bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r11;
at: 3 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 4 put: (self s: SIB1 i: 4 b: destReg);
at: 5 put: (offset bitAnd: 16rFF);
at: 6 put: (offset >> 8 bitAnd: 16rFF);
at: 7 put: (offset >> 16 bitAnd: 16rFF);
at: 8 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 9!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveXbrRR (in category 'generate machine code') -----
concretizeMoveXbrRR
"N.B. we zero-extend because we state byteReadsZeroExtend."
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base dest |
+ index := operands at: 0.
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0).
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
base ~= EBP ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB6;
at: 2 put: (self mod: ModRegInd RM: 4 RO: dest);
at: 3 put: (self s: SIB1 i: index b: base).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB6;
at: 2 put: (self mod: ModRegRegDisp8 RM: 4 RO: dest);
at: 3 put: (self s: SIB1 i: index b: base);
at: 4 put: 0.
^machineCodeSize := 5!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMoveXwrRR (in category 'generate machine code') -----
concretizeMoveXwrRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base dest |
+ index := operands at: 0.
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0).
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
base ~= EBP ifTrue:
[machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegInd RM: 4 RO: dest);
at: 2 put: (self s: SIB4 i: index b: base).
^machineCodeSize := 3].
machineCode
at: 0 put: 16r8B;
at: 1 put: (self mod: ModRegRegDisp8 RM: 4 RO: dest);
at: 2 put: (self s: SIB4 i: index b: base);
at: 3 put: 0.
^machineCodeSize := 4!
Item was changed:
----- Method: CogIA32Compiler>>concretizeMulRR (in category 'generate machine code') -----
concretizeMulRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg1 reg2 |
+ reg1 := operands at: 0.
+ reg2 := operands at: 1.
- reg1 := self concreteRegister: (operands at: 0).
- reg2 := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rAF;
at: 2 put: (self mod: ModReg RM: reg1 RO: reg2).
^machineCodeSize := 3!
Item was changed:
----- Method: CogIA32Compiler>>concretizeNegateR (in category 'generate machine code') -----
concretizeNegateR
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
machineCode
at: 0 put: 16rF7;
at: 1 put: (self mod: ModReg RM: reg RO: 3).
^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>concretizeOpRR: (in category 'generate machine code') -----
concretizeOpRR: x86opcode
| regLHS regRHS |
+ regLHS := operands at: 0.
+ regRHS := operands at: 1.
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: x86opcode;
at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>concretizeOrCqR (in category 'generate machine code') -----
concretizeOrCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| mask reg |
mask := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
(self isQuick: mask) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 1);
at: 2 put: (mask bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r0D;
at: 1 put: (mask bitAnd: 16rFF);
at: 2 put: (mask >> 8 bitAnd: 16rFF);
at: 3 put: (mask >> 16 bitAnd: 16rFF);
at: 4 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 1);
at: 2 put: (mask bitAnd: 16rFF);
at: 3 put: (mask >> 8 bitAnd: 16rFF);
at: 4 put: (mask >> 16 bitAnd: 16rFF);
at: 5 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeOrCwR (in category 'generate machine code') -----
concretizeOrCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r0D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 1);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizePopR (in category 'generate machine code') -----
concretizePopR
<inline: true>
+ machineCode at: 0 put: 16r58 + (operands at: 0).
- machineCode at: 0 put: 16r58 + (self concreteRegister: (operands at: 0)).
^machineCodeSize := 1!
Item was changed:
----- Method: CogIA32Compiler>>concretizePushR (in category 'generate machine code') -----
concretizePushR
<inline: true>
+ machineCode at: 0 put: 16r50 + (operands at: 0).
- machineCode at: 0 put: 16r50 + (self concreteRegister: (operands at: 0)).
^machineCodeSize := 1!
Item was changed:
----- Method: CogIA32Compiler>>concretizeReverseOpRR: (in category 'generate machine code') -----
concretizeReverseOpRR: x86opcode
| regLHS regRHS |
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteRegister: (operands at: 0).
- regLHS := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: x86opcode;
at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>concretizeSEE2OpRdRd: (in category 'generate machine code') -----
concretizeSEE2OpRdRd: opCode
"Will get inlined into concretizeAt: switch."
<inline: true>
| regLHS regRHS |
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: opCode;
at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
^machineCodeSize := 4!
Item was changed:
----- Method: CogIA32Compiler>>concretizeSqrtRd (in category 'generate machine code') -----
concretizeSqrtRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteDPFPRegister: (operands at: 0).
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r51;
at: 3 put: (self mod: ModReg RM: reg RO: reg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogIA32Compiler>>concretizeSubCqR (in category 'generate machine code') -----
concretizeSubCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 5);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r2D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 5);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeSubCwR (in category 'generate machine code') -----
concretizeSubCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r2D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 5);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeTstCqR (in category 'generate machine code') -----
concretizeTstCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| mask reg |
mask := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
((self isQuick: mask) and: [reg < 4]) ifTrue:
[machineCode
at: 0 put: 16rF6;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (mask bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16rA9;
at: 1 put: (mask bitAnd: 16rFF);
at: 2 put: (mask >> 8 bitAnd: 16rFF);
at: 3 put: (mask >> 16 bitAnd: 16rFF);
at: 4 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16rF7;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (mask bitAnd: 16rFF);
at: 3 put: (mask >> 8 bitAnd: 16rFF);
at: 4 put: (mask >> 16 bitAnd: 16rFF);
at: 5 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeXCHGAwR (in category 'generate machine code') -----
concretizeXCHGAwR
<inline: true>
| addressOperand reg |
addressOperand := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: 16r87;
at: 1 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 2 put: (addressOperand bitAnd: 16rFF);
at: 3 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>concretizeXCHGMwrR (in category 'generate machine code') -----
concretizeXCHGMwrR
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r87;
at: 1 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 2 put: (offset bitAnd: 16rFF).
^machineCodeSize := 3].
machineCode
at: 0 put: 16r87;
at: 1 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 2 put: (offset bitAnd: 16rFF);
at: 3 put: (offset >> 8 bitAnd: 16rFF);
at: 4 put: (offset >> 16 bitAnd: 16rFF);
at: 5 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r87;
at: 1 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 2 put: (self s: SIB1 i: 4 b: srcReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r87;
at: 1 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 2 put: (self s: SIB1 i: 4 b: srcReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogIA32Compiler>>concretizeXCHGRR (in category 'generate machine code') -----
concretizeXCHGRR
<inline: true>
| reg1 reg2 |
+ reg1 := operands at: 0.
+ reg2 := operands at: 1.
- reg1 := self concreteRegister: (operands at: 0).
- reg2 := self concreteRegister: (operands at: 1).
reg2 = EAX ifTrue:
[reg2 := reg1.
reg1 := EAX].
reg1 = EAX ifTrue:
[machineCode at: 0 put: 16r90 + reg2.
^machineCodeSize := 1].
machineCode
at: 0 put: 16r87;
at: 1 put: (self mod: ModReg RM: reg1 RO: reg2).
^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>concretizeXorCwR (in category 'generate machine code') -----
concretizeXorCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r35;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 6);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6!
Item was changed:
----- Method: CogIA32Compiler>>genDivR:R:Quo:Rem: (in category 'abstract instructions') -----
genDivR: abstractRegDivisor R: abstractRegDividend Quo: abstractRegQuotient Rem: abstractRegRemainder
| rDividend rDivisor rQuotient rRemainder saveRestoreEAX saveRestoreEDX saveRestoreExchanged |
self assert: abstractRegDividend ~= abstractRegDivisor.
self assert: abstractRegQuotient ~= abstractRegRemainder.
+ rDividend := abstractRegDividend.
+ rDivisor := abstractRegDivisor.
+ rQuotient := abstractRegQuotient.
+ rRemainder := abstractRegRemainder.
- rDividend := self concreteRegister: abstractRegDividend.
- rDivisor := self concreteRegister: abstractRegDivisor.
- rQuotient := self concreteRegister: abstractRegQuotient.
- rRemainder := self concreteRegister: abstractRegRemainder.
"IDIV r does a signed divide of EDX:EAX by r, EAX := Quotient, EDX := Remainder.
Since we must sign extend the dividend into EDX we must substitute another register if EDX is an input"
(rDividend = EDX or: [rDivisor = EDX]) ifTrue:
[| rUnused |
"Slang, sigh..."
rUnused := EAX.
[rUnused <= EDI] whileTrue:
[(rUnused ~= ESP and: [rUnused ~= EBP and: [rUnused ~= EDX
and: [rUnused ~= rDividend and: [rUnused ~= rDivisor
and: [rUnused ~= rQuotient and: [rUnused ~= rRemainder]]]]]]) ifTrue:
[cogit PushR: rUnused.
cogit MoveR: EDX R: rUnused.
rDividend = EDX
ifTrue: [self genDivR: rDivisor R: rUnused Quo: rQuotient Rem: rRemainder]
ifFalse: [self genDivR: rUnused R: rDividend Quo: rQuotient Rem: rRemainder].
cogit PopR: rUnused.
^self].
rUnused := rUnused + 1].
self error: 'couldn''t find unused register in genDivR:R:Quo:Rem:'].
"If either output does not include EAX or EDX we must save and restore EAX and/or EDX."
(saveRestoreEAX := rQuotient ~= EAX and: [rRemainder ~= EAX]) ifTrue:
[cogit PushR: EAX].
(saveRestoreEDX := rQuotient ~= EDX and: [rRemainder ~= EDX]) ifTrue:
[cogit PushR: EDX].
saveRestoreExchanged := -1.
rDividend ~= EAX ifTrue:
[rDivisor = EAX
ifTrue: [((rDividend ~= rQuotient and: [rDividend ~= rRemainder])
and: [rDividend ~= EDX or: [saveRestoreEDX not]]) ifTrue:
[cogit PushR: (saveRestoreExchanged := rDividend)].
cogit gen: XCHGRR operand: rDivisor operand: rDividend]
ifFalse: [cogit MoveR: rDividend R: EAX]].
"CDQ sign-extends EAX into EDX as required for IDIV"
cogit gen: CDQ.
cogit gen: IDIVR operand: (rDivisor = EAX ifTrue: [rDividend] ifFalse: [rDivisor]).
"Must not overwrite result while juggling"
(rQuotient = EDX and: [rRemainder = EAX])
ifTrue: [cogit gen: XCHGRR operand: rQuotient operand: rRemainder]
ifFalse:
[rQuotient = EDX
ifTrue:
[rRemainder ~= EDX ifTrue:
[cogit MoveR: EDX R: rRemainder].
rQuotient ~= EAX ifTrue:
[cogit MoveR: EAX R: rQuotient]]
ifFalse:
[rQuotient ~= EAX ifTrue:
[cogit MoveR: EAX R: rQuotient].
rRemainder ~= EDX ifTrue:
[cogit MoveR: EDX R: rRemainder]]].
saveRestoreExchanged >= 0 ifTrue:
[cogit PopR: saveRestoreExchanged].
saveRestoreEDX ifTrue:
[cogit PopR: EDX].
saveRestoreEAX ifTrue:
[cogit PopR: EAX]!
Item was changed:
----- Method: CogIA32Compiler>>genRestoreRegsExcept: (in category 'abi') -----
+ genRestoreRegsExcept: preservedReg
- genRestoreRegsExcept: abstractReg
- | realReg |
- realReg := self concreteRegister: abstractReg.
self assert: (EDI > EAX and: [EDI - EAX + 1 = 6]).
EAX to: EDI do:
[:reg|
(reg between: ESP and: EBP) ifFalse:
+ [preservedReg = reg
- [realReg = reg
ifTrue: [cogit AddCq: 4 R: ESP]
ifFalse: [cogit PopR: reg]]].
^0!
Item was changed:
CogX64Compiler subclass: #CogInLineLiteralsX64Compiler
instanceVariableNames: ''
+ classVariableNames: ''
- classVariableNames: 'ConcreteRISCTempReg'
poolDictionaries: ''
category: 'VMMaker-JIT'!
Item was removed:
- ----- Method: CogInLineLiteralsX64Compiler class>>initialize (in category 'class initialization') -----
- initialize
- ConcreteRISCTempReg := self basicNew concreteRegister: RISCTempReg!
Item was removed:
- ----- Method: CogInLineLiteralsX64Compiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
- isConcreteRISCTempRegister: concreteRegister
- "For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
- ^concreteRegister = ConcreteRISCTempReg!
Item was added:
+ ----- Method: CogInLineLiteralsX64Compiler class>>isRISCTempRegister: (in category 'testing') -----
+ isRISCTempRegister: reg
+ "For tests to filter-out bogus values left in the RISCTempRegister, if any."
+ ^reg = RISCTempReg!
Item was changed:
----- Method: CogInLineLiteralsX64Compiler>>computeSizeOfArithCqR (in category 'generate machine code') -----
computeSizeOfArithCqR
"With CqR we assume constants are 32-bits or less."
<inline: true>
(self isQuick: (operands at: 0)) ifTrue:
[^4].
(self isSignExtendedFourByteValue: (operands at: 0)) ifTrue:
+ [^(operands at: 1) = RAX ifTrue: [6] ifFalse: [7]].
- [^(self concreteRegister: (operands at: 1)) = RAX
- ifTrue: [6]
- ifFalse: [7]].
^10 "movabsq" + 3 "r op r"!
Item was changed:
----- Method: CogInLineLiteralsX64Compiler>>concretizeArithCwR: (in category 'generate machine code') -----
concretizeArithCwR: x64opcode
| value reg reverse |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reverse := x64opcode = 16r85 or: [x64opcode = 16r39]. "Tst & Cmp; backwards"
machineCode
+ at: 0 put: (self rexR: RISCTempReg x: 0 b: RISCTempReg);
+ at: 1 put: 16rB8 + (RISCTempReg bitAnd: 7);
- at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg);
- at: 1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF);
at: 6 put: (value >> 32 bitAnd: 16rFF);
at: 7 put: (value >> 40 bitAnd: 16rFF);
at: 8 put: (value >> 48 bitAnd: 16rFF);
at: 9 put: (value >> 56 bitAnd: 16rFF);
at: 10 put: (reverse
+ ifTrue: [self rexR: RISCTempReg x: 0 b: reg]
+ ifFalse: [self rexR: reg x: 0 b: RISCTempReg]);
- ifTrue: [self rexR: ConcreteRISCTempReg x: 0 b: reg]
- ifFalse: [self rexR: reg x: 0 b: ConcreteRISCTempReg]);
at: 11 put: x64opcode;
at: 12 put: (reverse
+ ifTrue: [self mod: ModReg RM: reg RO: RISCTempReg]
+ ifFalse: [self mod: ModReg RM: RISCTempReg RO: reg]).
- ifTrue: [self mod: ModReg RM: reg RO: ConcreteRISCTempReg]
- ifFalse: [self mod: ModReg RM: ConcreteRISCTempReg RO: reg]).
^machineCodeSize := 13!
Item was changed:
----- Method: CogInLineLiteralsX64Compiler>>concretizeMoveCwR (in category 'generate machine code') -----
concretizeMoveCwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg offset |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
(self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue:
[value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address].
(cogit addressIsInCurrentCompilation: value) ifTrue:
[offset := value - (address + 7).
machineCode
at: 0 put: (self rexR: reg x: 0 b: 0);
at: 1 put: 16r8D; "LoadEffectiveAddress"
at: 2 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16rB8 + (reg bitAnd: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF);
at: 6 put: (value >> 32 bitAnd: 16rFF);
at: 7 put: (value >> 40 bitAnd: 16rFF);
at: 8 put: (value >> 48 bitAnd: 16rFF);
at: 9 put: (value >> 56 bitAnd: 16rFF).
opcode = MoveCqR ifTrue:
[^machineCodeSize := 10].
"Add a nop to disambiguate between MoveCwR/PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"
machineCode at: 10 put: 16r90.
self assert: (self mod: ModReg RM: 0 RO: 0) > 16r90.
^machineCodeSize := 11!
Item was changed:
----- Method: CogInLineLiteralsX64Compiler>>concretizePushCw (in category 'generate machine code') -----
concretizePushCw
"Will get inlined into concretizeAt: switch."
<inline: true>
| value offset |
value := operands at: 0.
(self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue:
[value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address].
(cogit addressIsInCurrentCompilation: value) ifTrue:
[offset := value - (address + 7).
machineCode
+ at: 0 put: (self rexR: RISCTempReg x: 0 b: 0);
- at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: 0);
at: 1 put: 16r8D; "LoadEffectiveAddress"
+ at: 2 put: (self mod: ModRegInd RM: 5 RO: RISCTempReg);
- at: 2 put: (self mod: ModRegInd RM: 5 RO: ConcreteRISCTempReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF);
at: 7 put: 16r41;
+ at: 8 put: 16r48 + RISCTempReg.
- at: 8 put: 16r48 + ConcreteRISCTempReg.
^machineCodeSize := 9].
machineCode
+ at: 0 put: (self rexR: RISCTempReg x: 0 b: RISCTempReg);
+ at: 1 put: 16rB8 + (RISCTempReg bitAnd: 7);
- at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg);
- at: 1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF);
at: 6 put: (value >> 32 bitAnd: 16rFF);
at: 7 put: (value >> 40 bitAnd: 16rFF);
at: 8 put: (value >> 48 bitAnd: 16rFF);
at: 9 put: (value >> 56 bitAnd: 16rFF);
at: 10 put: 16r41;
+ at: 11 put: 16r48 + RISCTempReg. "The 48 will disambiguate between MoveCwR, PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"
+ self assert: RISCTempReg >= 8.
- at: 11 put: 16r48 + ConcreteRISCTempReg. "The 48 will disambiguate between MoveCwR, PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"
- self assert: ConcreteRISCTempReg >= 8.
self assert: (self mod: ModReg RM: 0 RO: 0) > 16r57.
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>cResultRegister (in category 'generate machine code') -----
cResultRegister
+ "Answer the register through which C funcitons return integral results."
+ <inline: true>
- "Answer the abstract register for the C result register."
^V0!
Item was changed:
----- Method: CogMIPSELCompiler>>callerSavedRegisterMask (in category 'accessing') -----
callerSavedRegisterMask
"See MIPSConstants initializeRegisters."
- | mask |
self flag: #OABI.
+ ^cogit
+ registerMaskFor: S0
+ and: S1
+ and: S2
+ and: S3
+ and: S4
+ and: S5
+ and: S6
+ and: S7!
- mask := 0.
- mask := mask bitOr: 1 << S0.
- mask := mask bitOr: 1 << S1.
- mask := mask bitOr: 1 << S2.
- mask := mask bitOr: 1 << S3.
- mask := mask bitOr: 1 << S4.
- mask := mask bitOr: 1 << S5.
- mask := mask bitOr: 1 << S6.
- mask := mask bitOr: 1 << S7.
- ^mask!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAddCheckOverflowCqR (in category 'generate machine code - concretize') -----
concretizeAddCheckOverflowCqR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
"Save original LHS"
self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
"The actual addition"
self machineCodeAt: 12 put: (self adduR: destReg R: leftReg R: AT).
"Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: destReg R: AT).
"Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
"Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
self machineCodeAt: 24 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
^machineCodeSize := 28!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAddCheckOverflowRR (in category 'generate machine code - concretize') -----
concretizeAddCheckOverflowRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
"Save original LHS"
self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
"The actual addition"
self machineCodeAt: 4 put: (self adduR: destReg R: leftReg R: rightReg).
"Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: destReg R: rightReg).
"Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
"Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
self machineCodeAt: 16 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
^machineCodeSize := 20!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAddCqR (in category 'generate machine code - concretize') -----
concretizeAddCqR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
(rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAddCwR].
self machineCodeAt: 0 put: (self addiuR: destReg R: leftReg C: rightImm).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAddCwR (in category 'generate machine code - concretize') -----
concretizeAddCwR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self adduR: destReg R: leftReg R: AT).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAddRR (in category 'generate machine code - concretize') -----
concretizeAddRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self adduR: destReg R: leftReg R: rightReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAndCqR (in category 'generate machine code - concretize') -----
concretizeAndCqR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
(rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAndCwR].
self machineCodeAt: 0 put: (self andiR: destReg R: leftReg C: rightImm).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAndCqRR (in category 'generate machine code - concretize') -----
concretizeAndCqRR
| value srcReg dstReg |
value := operands at: 0.
+ srcReg := operands at: 1.
+ dstReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- dstReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)).
self machineCodeAt: 8 put: (self andR: dstReg R: srcReg R: AT).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAndCwR (in category 'generate machine code - concretize') -----
concretizeAndCwR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self andR: destReg R: leftReg R: AT).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeAndRR (in category 'generate machine code - concretize') -----
concretizeAndRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self andR: destReg R: leftReg R: rightReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeArithmeticShiftRightCqR (in category 'generate machine code - concretize') -----
concretizeArithmeticShiftRightCqR
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self sraR: reg R: reg C: distance).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeArithmeticShiftRightRR (in category 'generate machine code - concretize') -----
concretizeArithmeticShiftRightRR
| destReg distReg |
+ distReg := operands at: 0.
+ destReg := operands at: 1.
- distReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self sravR: destReg R: destReg R: distReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrEqualRR (in category 'generate machine code - concretize') -----
concretizeBrEqualRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 4.
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self beqR: leftReg R: rightReg offset: offset).
self machineCodeAt: 4 put: (self nop). "Delay slot"
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrLongEqualRR (in category 'generate machine code - concretize') -----
concretizeBrLongEqualRR
| jumpTargetInstruction jumpTargetAddr leftReg rightReg |
<var: #jumpTargetInstruction type: #'AbstractInstruction *'>
jumpTargetInstruction := self longJumpTargetAddress.
self flag: #todo. "Check not crossing 256MB block."
jumpTargetAddr := jumpTargetInstruction asUnsignedInteger bitAnd: 16rFFFFFFF.
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self bneR: leftReg R: rightReg offset: 12).
self machineCodeAt: 4 put: (self nop). "Delay slot"
self machineCodeAt: 8 put: (self jA: jumpTargetAddr).
self machineCodeAt: 12 put: self nop. "Delay slot"
^machineCodeSize := 16!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrLongNotEqualRR (in category 'generate machine code - concretize') -----
concretizeBrLongNotEqualRR
| jumpTargetInstruction jumpTargetAddr leftReg rightReg |
<var: #jumpTargetInstruction type: #'AbstractInstruction *'>
jumpTargetInstruction := self longJumpTargetAddress.
self flag: #todo. "Check not crossing 256MB block."
jumpTargetAddr := jumpTargetInstruction asUnsignedInteger bitAnd: 16rFFFFFFF.
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self beqR: leftReg R: rightReg offset: 12).
self machineCodeAt: 4 put: (self nop). "Delay slot"
self machineCodeAt: 8 put: (self jA: jumpTargetAddr).
self machineCodeAt: 12 put: self nop. "Delay slot"
^machineCodeSize := 16!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrNotEqualRR (in category 'generate machine code - concretize') -----
concretizeBrNotEqualRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 4.
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self bneR: leftReg R: rightReg offset: offset).
self machineCodeAt: 4 put: (self nop). "Delay slot"
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrSignedGreaterEqualRR (in category 'generate machine code - concretize') -----
concretizeBrSignedGreaterEqualRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrSignedGreaterRR (in category 'generate machine code - concretize') -----
concretizeBrSignedGreaterRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrSignedLessEqualRR (in category 'generate machine code - concretize') -----
concretizeBrSignedLessEqualRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrSignedLessRR (in category 'generate machine code - concretize') -----
concretizeBrSignedLessRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrUnsignedGreaterEqualRR (in category 'generate machine code - concretize') -----
concretizeBrUnsignedGreaterEqualRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrUnsignedGreaterRR (in category 'generate machine code - concretize') -----
concretizeBrUnsignedGreaterRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrUnsignedLessEqualRR (in category 'generate machine code - concretize') -----
concretizeBrUnsignedLessEqualRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeBrUnsignedLessRR (in category 'generate machine code - concretize') -----
concretizeBrUnsignedLessRR
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
+ leftReg := operands at: 1.
+ rightReg := operands at: 2.
- leftReg := self concreteRegister: (operands at: 1).
- rightReg := self concreteRegister: (operands at: 2).
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeDivRR (in category 'generate machine code - concretize') -----
concretizeDivRR
| dividendReg divisorReg |
+ dividendReg := operands at: 0.
+ divisorReg := operands at: 1.
- dividendReg := self concreteRegister: (operands at: 0).
- divisorReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self divR: dividendReg R: divisorReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeJumpR (in category 'generate machine code - concretize') -----
concretizeJumpR
| reg |
self flag: #OABI. "Does this ever target C code? If so we should move the target into TargetReg first."
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
self machineCodeAt: 0 put: (self jR: reg).
self machineCodeAt: 4 put: self nop. "Delay slot"
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeLoadEffectiveAddressMwrR (in category 'generate machine code - concretize') -----
concretizeLoadEffectiveAddressMwrR
<var: #offset type: #sqInt>
| baseReg offset destReg |
offset := operands at: 0.
+ baseReg := operands at: 1.
+ destReg := operands at: 2.
- baseReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
(self isShortOffset: offset) ifTrue:
[self machineCodeAt: 0 put: (self addiuR: destReg R: baseReg C: offset).
^machineCodeSize := 4].
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: offset)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: offset)).
self machineCodeAt: 8 put: (self adduR: destReg R: baseReg R: AT).
^machineCodeSize := 12.
!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeLogicalShiftLeftCqR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftLeftCqR
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self sllR: reg R: reg C: distance).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeLogicalShiftLeftRR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftLeftRR
| destReg distReg |
+ distReg := operands at: 0.
+ destReg := operands at: 1.
- distReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self sllvR: destReg R: destReg R: distReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeLogicalShiftRightCqR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftRightCqR
| distance reg |
distance := (operands at: 0) min: 31.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self srlR: reg R: reg C: distance).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeLogicalShiftRightRR (in category 'generate machine code - concretize') -----
concretizeLogicalShiftRightRR
| destReg distReg |
+ distReg := operands at: 0.
+ destReg := operands at: 1.
- distReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self srlvR: destReg R: destReg R: distReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveAbR (in category 'generate machine code - concretize') -----
concretizeMoveAbR
| srcAddr destReg |
srcAddr := operands at: 0.
+ destReg := operands at: 1.
- destReg := self concreteRegister: (operands at: 1).
(self isAddressRelativeToVarBase: srcAddr) ifTrue:
[self machineCodeAt: 0 put: (self lwR: destReg base: ConcreteVarBaseReg offset: srcAddr - cogit varBaseAddress).
^machineCodeSize := 4].
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: srcAddr)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: srcAddr)).
self machineCodeAt: 8 put: (self lbuR: destReg base: AT offset: 0).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveAwR (in category 'generate machine code - concretize') -----
concretizeMoveAwR
| srcAddr destReg |
srcAddr := operands at: 0.
+ destReg := operands at: 1.
- destReg := self concreteRegister: (operands at: 1).
(self isAddressRelativeToVarBase: srcAddr) ifTrue:
[self machineCodeAt: 0 put: (self lwR: destReg base: ConcreteVarBaseReg offset: srcAddr - cogit varBaseAddress).
^machineCodeSize := 4].
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: srcAddr)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: srcAddr)).
self machineCodeAt: 8 put: (self lwR: destReg base: AT offset: 0).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveCqR (in category 'generate machine code - concretize') -----
concretizeMoveCqR
<var: #word type: #sqInt>
| word reg |
word := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
(word between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeMoveCwR].
"Could also load up to 16rFFFF with ori or 16rXXXX0000 with lui"
self machineCodeAt: 0 put: (self addiuR: reg R: ZR C: word).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveCwR (in category 'generate machine code - concretize') -----
concretizeMoveCwR
<var: #word type: #sqInt>
| word reg |
word := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: reg C: (self high16BitsOf: word)).
self machineCodeAt: 4 put: (self oriR: reg R: reg C: (self low16BitsOf: word)).
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveHighR (in category 'generate machine code - concretize') -----
concretizeMoveHighR
| destReg |
+ destReg := operands at: 0.
- destReg := self concreteRegister: (operands at: 0).
self machineCodeAt: 0 put: (self mfhiR: destReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveLowR (in category 'generate machine code - concretize') -----
concretizeMoveLowR
| destReg |
+ destReg := operands at: 0.
- destReg := self concreteRegister: (operands at: 0).
self machineCodeAt: 0 put: (self mfloR: destReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveM16rR (in category 'generate machine code - concretize') -----
concretizeMoveM16rR
<var: #offset type: #sqInt>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self lhuR: destReg base: srcReg offset: offset).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveMbrR (in category 'generate machine code - concretize') -----
concretizeMoveMbrR
<var: #offset type: #sqInt>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self lbuR: destReg base: srcReg offset: offset).
^machineCodeSize := 4
!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveMwrR (in category 'generate machine code - concretize') -----
concretizeMoveMwrR
<var: #offset type: #sqInt>
| baseReg offset destReg |
offset := operands at: 0.
+ baseReg := operands at: 1.
+ destReg := operands at: 2.
- baseReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
(self isShortOffset: offset) ifTrue:
[self machineCodeAt: 0 put: (self lwR: destReg base: baseReg offset: offset).
^machineCodeSize := 4].
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: offset)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: offset)).
self machineCodeAt: 8 put: (self adduR: AT R: baseReg R: AT).
self machineCodeAt: 12 put: (self lwR: destReg base: AT offset: 0).
^machineCodeSize := 16.
!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveRAb (in category 'generate machine code - concretize') -----
concretizeMoveRAb
| srcReg destAddr |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
destAddr := operands at: 1.
(self isAddressRelativeToVarBase: destAddr) ifTrue:
[self machineCodeAt: 0 put: (self swR: srcReg base: ConcreteVarBaseReg offset: destAddr - cogit varBaseAddress).
^machineCodeSize := 4].
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: destAddr)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: destAddr)).
self machineCodeAt: 8 put: (self sbR: srcReg base: AT offset: 0).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveRAw (in category 'generate machine code - concretize') -----
concretizeMoveRAw
| srcReg destAddr |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
destAddr := operands at: 1.
(self isAddressRelativeToVarBase: destAddr) ifTrue:
[self machineCodeAt: 0 put: (self swR: srcReg base: ConcreteVarBaseReg offset: destAddr - cogit varBaseAddress).
^machineCodeSize := 4].
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: destAddr)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: destAddr)).
self machineCodeAt: 8 put: (self swR: srcReg base: AT offset: 0).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveRMwr (in category 'generate machine code - concretize') -----
concretizeMoveRMwr
<var: #offset type: #sqInt>
| srcReg offset baseReg |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
offset := operands at: 1.
+ baseReg := operands at: 2.
- baseReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self swR: srcReg base: baseReg offset: offset).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveRR (in category 'generate machine code - concretize') -----
concretizeMoveRR
| srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
- srcReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self adduR: destReg R: srcReg R: ZR).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveRXbrR (in category 'generate machine code - concretize') -----
concretizeMoveRXbrR
| srcReg indexReg baseReg |
+ srcReg := operands at: 0.
+ indexReg := operands at: 1.
+ baseReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 0).
- indexReg := self concreteRegister: (operands at: 1).
- baseReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self adduR: AT R: baseReg R: indexReg).
self machineCodeAt: 4 put: (self sbR: srcReg base: AT offset: 0).
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveRXwrR (in category 'generate machine code - concretize') -----
concretizeMoveRXwrR
| srcReg indexReg baseReg |
+ srcReg := operands at: 0.
+ indexReg := operands at: 1.
+ baseReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 0).
- indexReg := self concreteRegister: (operands at: 1).
- baseReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self sllR: AT R: indexReg C: 2). "index is number of words"
self machineCodeAt: 4 put: (self adduR: AT R: baseReg R: AT).
self machineCodeAt: 8 put: (self swR: srcReg base: AT offset: 0).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveXbrRR (in category 'generate machine code - concretize') -----
concretizeMoveXbrRR
| indexReg baseReg destReg |
+ indexReg := operands at: 0. "index is number of *bytes*"
+ baseReg := operands at: 1.
+ destReg := operands at: 2.
- indexReg := self concreteRegister: (operands at: 0). "index is number of *bytes*"
- baseReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self adduR: AT R: baseReg R: indexReg).
self machineCodeAt: 4 put: (self lbuR: destReg base: AT offset: 0).
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMoveXwrRR (in category 'generate machine code - concretize') -----
concretizeMoveXwrRR
| indexReg baseReg destReg |
+ indexReg := operands at: 0.
+ baseReg := operands at: 1.
+ destReg := operands at: 2.
- indexReg := self concreteRegister: (operands at: 0).
- baseReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
self machineCodeAt: 0 put: (self sllR: AT R: indexReg C: 2). "index is in words"
self machineCodeAt: 4 put: (self adduR: AT R: baseReg R: AT).
self machineCodeAt: 8 put: (self lwR: destReg base: AT offset: 0).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeMulCheckOverflowRR (in category 'generate machine code - concretize') -----
concretizeMulCheckOverflowRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
"Overflow occured if the sign bit of the low part is different from the high part."
self machineCodeAt: 0 put: (self multR: leftReg R: rightReg).
self machineCodeAt: 4 put: (self mfloR: destReg).
self machineCodeAt: 8 put: (self sraR: OverflowTemp1 R: destReg C: 31).
self machineCodeAt: 12 put: (self mfhiR: OverflowTemp2).
^machineCodeSize := 16!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeNegateR (in category 'generate machine code - concretize') -----
concretizeNegateR
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
self machineCodeAt: 0 put: (self subuR: reg R: ZR R: reg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeOrCqR (in category 'generate machine code - concretize') -----
concretizeOrCqR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
(rightImm between: 0 and: 16rFFFF) ifFalse: [^self concretizeOrCwR].
self machineCodeAt: 0 put: (self oriR: destReg R: leftReg C: rightImm).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeOrCwR (in category 'generate machine code - concretize') -----
concretizeOrCwR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self orR: destReg R: leftReg R: AT).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeOrRR (in category 'generate machine code - concretize') -----
concretizeOrRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self orR: destReg R: leftReg R: rightReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizePopR (in category 'generate machine code - concretize') -----
concretizePopR
| destReg |
+ destReg := operands at: 0.
- destReg := self concreteRegister: (operands at: 0).
self machineCodeAt: 0 put: (self lwR: destReg base: SP offset: 0).
self machineCodeAt: 4 put: (self addiuR: SP R: SP C: 4).
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizePushR (in category 'generate machine code - concretize') -----
concretizePushR
| srcReg |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
self machineCodeAt: 0 put: (self addiuR: SP R: SP C: -4).
self machineCodeAt: 4 put: (self swR: srcReg base: SP offset: 0).
^machineCodeSize := 8!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeSubCheckOverflowCqR (in category 'generate machine code - concretize') -----
concretizeSubCheckOverflowCqR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
"Save original LHS"
self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
"The actual subtraction"
self machineCodeAt: 12 put: (self subuR: destReg R: leftReg R: AT).
"Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: destReg R: AT).
"Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
"Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
self machineCodeAt: 24 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
^machineCodeSize := 28!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeSubCheckOverflowRR (in category 'generate machine code - concretize') -----
concretizeSubCheckOverflowRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
"Save original LHS"
self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
"The actual subtraction"
self machineCodeAt: 4 put: (self subuR: destReg R: leftReg R: rightReg).
"Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: destReg R: rightReg).
"Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
"Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
self machineCodeAt: 16 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
^machineCodeSize := 20!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeSubCqR (in category 'generate machine code - concretize') -----
concretizeSubCqR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
(rightImm negated between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeSubCwR].
self machineCodeAt: 0 put: (self addiuR: destReg R: leftReg C: rightImm negated).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeSubCwR (in category 'generate machine code - concretize') -----
concretizeSubCwR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self subuR: destReg R: leftReg R: AT).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeSubRR (in category 'generate machine code - concretize') -----
concretizeSubRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self subuR: destReg R: leftReg R: rightReg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeTstCqR (in category 'generate machine code - concretize') -----
concretizeTstCqR
| leftReg rightImm |
rightImm := operands at: 0.
+ leftReg := operands at: 1.
- leftReg := self concreteRegister: (operands at: 1).
(rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeTstCwR].
self machineCodeAt: 0 put: (self andiR: Cmp R: leftReg C: rightImm).
^machineCodeSize := 4!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeTstCwR (in category 'generate machine code - concretize') -----
concretizeTstCwR
| leftReg rightImm |
rightImm := operands at: 0.
+ leftReg := operands at: 1.
- leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self andR: Cmp R: leftReg R: AT).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeXorCwR (in category 'generate machine code - concretize') -----
concretizeXorCwR
| destReg leftReg rightImm |
rightImm := operands at: 0.
+ destReg := leftReg := operands at: 1.
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self xorR: destReg R: leftReg R: AT).
^machineCodeSize := 12!
Item was changed:
----- Method: CogMIPSELCompiler>>concretizeXorRR (in category 'generate machine code - concretize') -----
concretizeXorRR
| destReg leftReg rightReg |
+ rightReg := operands at: 0.
+ destReg := leftReg := operands at: 1.
- rightReg := self concreteRegister: (operands at: 0).
- destReg := leftReg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self xorR: destReg R: leftReg R: rightReg).
^machineCodeSize := 4!
Item was removed:
- ----- Method: CogMIPSELCompilerForTests class>>isConcreteRISCTempRegister: (in category 'as yet unclassified') -----
- isConcreteRISCTempRegister: concreteRegister
- "For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
- ^concreteRegister = AT
- or: [concreteRegister = Cmp
- or: [concreteRegister = Overflow
- or: [concreteRegister = BranchTemp]]]!
Item was added:
+ ----- Method: CogMIPSELCompilerForTests class>>isRISCTempRegister: (in category 'as yet unclassified') -----
+ isRISCTempRegister: reg
+ "For tests to filter-out bogus values left in the RISCTempRegister, if any."
+ ^reg = AT
+ or: [reg = Cmp
+ or: [reg = Overflow
+ or: [reg = BranchTemp]]]!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>genInnerPrimitiveNewWithArg: (in category 'primitive generators') -----
genInnerPrimitiveNewWithArg: retNoffset
"Implement primitiveNewWithArg for convenient cases:
- the receiver has a hash
- the receiver is variable and not compiled method
- single word header/num slots < numSlotsMask
- the result fits in eden
See superclass method for dynamic frequencies of formats.
For the moment we implement only arrayFormat, firstByteFormat & firstLongFormat"
| headerReg fillReg instSpecReg byteSizeReg maxSlots
jumpArrayTooBig jumpByteTooBig jumpLongTooBig
jumpArrayFormat jumpByteFormat jumpBytePrepDone jumpLongPrepDone
jumpUnhashed jumpNElementsNonInt jumpFailCuzFixed jumpNoSpace jumpHasSlots fillLoop skip |
<var: 'skip' type: #'AbstractInstruction *'>
<var: 'fillLoop' type: #'AbstractInstruction *'>
<var: 'jumpHasSlots' type: #'AbstractInstruction *'>
<var: 'jumpNoSpace' type: #'AbstractInstruction *'>
<var: 'jumpUnhashed' type: #'AbstractInstruction *'>
<var: 'jumpByteFormat' type: #'AbstractInstruction *'>
<var: 'jumpByteTooBig' type: #'AbstractInstruction *'>
<var: 'jumpLongTooBig' type: #'AbstractInstruction *'>
<var: 'jumpArrayFormat' type: #'AbstractInstruction *'>
<var: 'jumpArrayTooBig' type: #'AbstractInstruction *'>
<var: 'jumpFailCuzFixed' type: #'AbstractInstruction *'>
<var: 'jumpBytePrepDone' type: #'AbstractInstruction *'>
<var: 'jumpLongPrepDone' type: #'AbstractInstruction *'>
<var: 'jumpNElementsNonInt' type: #'AbstractInstruction *'>
"header will contain classIndex/class's hash & format & numSlots/fixed size"
headerReg := SendNumArgsReg.
+ "Assume there's an available scratch register on 64-bit machines. This holds the saved numFixedFields and then the value to fill with"
- "Assume there's an available scratch register on 64-bit machines. This holds the saved numFixedFileds and then the value to fill with"
fillReg := Scratch0Reg.
+ self assert: fillReg > 0.
- self assert: (cogit backEnd concreteRegister: fillReg) > 0.
"inst spec will hold class's instance specification and then byte size"
instSpecReg := byteSizeReg := ClassReg.
"The max slots we'll allocate here are those for a single header"
maxSlots := objectMemory numSlotsMask - 1.
"get freeStart as early as possible so as not to wait later..."
cogit MoveAw: objectMemory freeStartAddress R: Arg1Reg.
"get class's hash & fail if 0"
self genGetHashFieldNonImmOf: ReceiverResultReg into: headerReg.
jumpUnhashed := cogit JumpZero: 0.
"get index and fail if not a +ve integer"
jumpNElementsNonInt := self genJumpNotSmallInteger: Arg0Reg scratchReg: TempReg.
"get class's format inst var for inst spec (format field)"
self genLoadSlot: InstanceSpecificationIndex sourceReg: ReceiverResultReg destReg: instSpecReg.
cogit LogicalShiftRightCq: objectMemory fixedFieldsFieldWidth + self numSmallIntegerTagBits R: instSpecReg.
cogit AndCq: objectMemory formatMask R: instSpecReg.
"Add format to classIndex/format header now"
cogit MoveR: instSpecReg R: TempReg.
cogit LogicalShiftLeftCq: objectMemory formatShift R: TempReg.
cogit AddR: TempReg R: headerReg.
"get integer value of num fields in fillReg now"
cogit MoveR: Arg0Reg R: fillReg.
self genConvertSmallIntegerToIntegerInReg: fillReg.
"dispatch on format, failing if not variable or if compiled method"
cogit CmpCq: objectMemory arrayFormat R: instSpecReg.
jumpArrayFormat := cogit JumpZero: 0.
cogit CmpCq: objectMemory firstByteFormat R: instSpecReg.
jumpByteFormat := cogit JumpZero: 0.
cogit CmpCq: objectMemory firstLongFormat R: instSpecReg.
jumpFailCuzFixed := cogit JumpNonZero: 0.
cogit CmpCq: (objectMemory integerObjectOf: maxSlots * 2) R: Arg0Reg.
jumpLongTooBig := cogit JumpAbove: 0.
"save num elements/slot size to instSpecReg"
cogit MoveR: fillReg R: instSpecReg.
"compute odd bits and add into headerReg; oddBits := 2 - nElements bitAnd: 1"
cogit MoveCq: objectMemory wordSize / 4 R: TempReg.
cogit SubR: instSpecReg R: TempReg.
cogit AndCq: objectMemory wordSize / 4 - 1 R: TempReg.
cogit LogicalShiftLeftCq: objectMemory formatShift R: TempReg.
cogit AddR: TempReg R: headerReg.
"round up num elements to numSlots in instSpecReg"
cogit AddCq: objectMemory wordSize / 4 - 1 R: instSpecReg.
cogit LogicalShiftRightCq: objectMemory shiftForWord - 2 R: instSpecReg.
cogit MoveCq: 0 R: fillReg.
jumpLongPrepDone := cogit Jump: 0. "go allocate"
jumpByteFormat jmpTarget:
(cogit CmpCq: (objectMemory integerObjectOf: maxSlots * objectMemory wordSize) R: Arg0Reg).
jumpByteTooBig := cogit JumpAbove: 0.
"save num elements to instSpecReg"
cogit MoveR: fillReg R: instSpecReg.
"compute odd bits and add into headerReg; oddBits := 4 - nElements bitAnd: 3"
cogit MoveCq: objectMemory wordSize R: TempReg.
cogit SubR: instSpecReg R: TempReg.
cogit AndCq: objectMemory wordSize - 1 R: TempReg.
cogit LogicalShiftLeftCq: objectMemory formatShift R: TempReg.
cogit AddR: TempReg R: headerReg.
"round up num elements to numSlots in instSpecReg"
cogit AddCq: objectMemory wordSize - 1 R: instSpecReg.
cogit LogicalShiftRightCq: objectMemory shiftForWord R: instSpecReg.
cogit MoveCq: 0 R: fillReg.
jumpBytePrepDone := cogit Jump: 0. "go allocate"
jumpArrayFormat jmpTarget:
(cogit CmpCq: (objectMemory integerObjectOf: maxSlots) R: Arg0Reg).
jumpArrayTooBig := cogit JumpAbove: 0.
"save num elements/slot size to instSpecReg"
cogit MoveR: fillReg R: instSpecReg.
cogit MoveCq: objectMemory nilObject R: fillReg.
"fall through to allocate"
jumpBytePrepDone jmpTarget:
(jumpLongPrepDone jmpTarget: cogit Label).
"store numSlots to headerReg"
cogit MoveR: instSpecReg R: TempReg.
cogit LogicalShiftLeftCq: objectMemory numSlotsFullShift R: TempReg.
cogit AddR: TempReg R: headerReg.
"compute byte size; remember 0-sized objects still need 1 slot."
cogit CmpCq: 0 R: byteSizeReg. "a.k.a. instSpecReg"
jumpHasSlots := cogit JumpNonZero: 0.
cogit MoveCq: objectMemory baseHeaderSize * 2 R: byteSizeReg.
skip := cogit Jump: 0.
jumpHasSlots jmpTarget:
(cogit AddCq: objectMemory baseHeaderSize / objectMemory wordSize R: byteSizeReg).
cogit LogicalShiftLeftCq: objectMemory shiftForWord R: byteSizeReg.
skip jmpTarget:
"check if allocation fits"
(cogit AddR: Arg1Reg R: byteSizeReg).
cogit CmpCq: objectMemory getScavengeThreshold R: byteSizeReg.
jumpNoSpace := cogit JumpAboveOrEqual: 0.
"get result, increment freeStart and write it back. Arg1Reg holds new freeStart, the limit of the object"
cogit MoveR: Arg1Reg R: ReceiverResultReg.
cogit MoveR: byteSizeReg Aw: objectMemory freeStartAddress.
"write other half of header (numSlots/0 identityHash)"
cogit MoveR: headerReg Mw: 0 r: ReceiverResultReg.
"now fill"
cogit LoadEffectiveAddressMw: objectMemory baseHeaderSize r: ReceiverResultReg R: Arg1Reg.
fillLoop :=
cogit MoveR: fillReg Mw: 0 r: Arg1Reg.
cogit AddCq: 8 R: Arg1Reg.
cogit CmpR: Arg1Reg R: byteSizeReg.
cogit JumpAbove: fillLoop.
cogit RetN: retNoffset.
jumpNoSpace jmpTarget:
(jumpUnhashed jmpTarget:
(jumpFailCuzFixed jmpTarget:
(jumpArrayTooBig jmpTarget:
(jumpByteTooBig jmpTarget:
(jumpLongTooBig jmpTarget:
(jumpNElementsNonInt jmpTarget: cogit Label)))))).
^0!
Item was removed:
- ----- Method: CogOutOfLineLiteralsX64Compiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
- isConcreteRISCTempRegister: concreteRegister
- "For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
- ^false!
Item was added:
+ ----- Method: CogOutOfLineLiteralsX64Compiler class>>isRISCTempRegister: (in category 'testing') -----
+ isRISCTempRegister: reg
+ "For tests to filter-out bogus values left in the RISCTempRegister, if any."
+ ^false!
Item was changed:
CogAbstractInstruction subclass: #CogX64Compiler
instanceVariableNames: ''
+ classVariableNames: 'ABI CDQ CMPXCHGAwR CMPXCHGMwrR CPUID IDIVR IMULRR LFENCE LOCK MFENCE ModReg ModRegInd ModRegIndDisp32 ModRegIndSIB ModRegRegDisp32 ModRegRegDisp8 R10 R11 R12 R13 R14 R15 R8 R9 RAX RBP RBX RCX RDI RDX RSI RSP SFENCE SIB1 SIB2 SIB4 SIB8 XCHGAwR XCHGMwrR XCHGRR XMM0L XMM10L XMM11L XMM12L XMM13L XMM14L XMM15L XMM1L XMM2L XMM3L XMM4L XMM5L XMM6L XMM7L XMM8L XMM9L'
- classVariableNames: 'ABI CDQ CMPXCHGAwR CMPXCHGMwrR CPUID IDIVR IMULRR LFENCE LOCK MFENCE ModReg ModRegInd ModRegIndDisp32 ModRegIndSIB ModRegRegDisp32 ModRegRegDisp8 R10 R11 R12 R13 R14 R15 R8 R9 RAX RBP RBX RCX RDI RDX RSI RSP SFENCE SIB1 SIB2 SIB4 SIB8 XCHGAwR XCHGMwrR XCHGRR XMM0H XMM0L XMM10H XMM10L XMM11H XMM11L XMM12H XMM12L XMM13H XMM13L XMM14H XMM14L XMM15H XMM15L XMM1H XMM1L XMM2H XMM2L XMM3H XMM3L XMM4H XMM4L XMM5H XMM5L XMM6H XMM6L XMM7H XMM7L XMM8H XMM8L XMM9H XMM9L'
poolDictionaries: ''
category: 'VMMaker-JIT'!
!CogX64Compiler commentStamp: 'eem 9/14/2015 17:12' prior: 0!
I generate x64 (x86-64) instructions from CogAbstractInstructions. For reference see
1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
http://www.intel.com/products/processor/manuals/
or
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions
AMD64 Architecture Programmer's Manual Volume 4: 128-bit Media Instructions
AMD64 Architecture Programmer's Manual Volume 5: 64-bit Media and x87 Floating Point Instructions
http://developer.amd.com/resources/documentation-articles/developer-guides-…
(® is supposed to be the Unicode "registered sign").!
Item was changed:
----- Method: CogX64Compiler class>>initialize (in category 'class initialization') -----
initialize
"Initialize various x64 instruction-related constants.
[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M"
"CogX64Compiler initialize"
self ~~ CogX64Compiler ifTrue: [^self].
ABI ifNil:
[ABI := #SysV]. "Default ABI; other choice is #MSVC"
RAX := 0.
RCX := 1. "Were they completely mad or simply sadistic?"
RDX := 2.
RBX := 3.
RSP := 4.
RBP := 5.
RSI := 6.
RDI := 7.
R8 := 8.
R9 := 9.
R10 := 10.
R11 := 11.
R12 := 12.
R13 := 13.
R14 := 14.
R15 := 15.
XMM0L := 0.
+ XMM1L := 1.
+ XMM2L := 2.
+ XMM3L := 3.
+ XMM4L := 4.
+ XMM5L := 5.
+ XMM6L := 6.
+ XMM7L := 7.
+ XMM8L := 8.
+ XMM9L := 9.
+ XMM10L := 10.
+ XMM11L := 11.
+ XMM12L := 12.
+ XMM13L := 13.
+ XMM14L := 14.
+ XMM15L := 15.
- XMM1L := 2.
- XMM2L := 4.
- XMM3L := 6.
- XMM4L := 8.
- XMM5L := 10.
- XMM6L := 12.
- XMM7L := 14.
- XMM8L := 16.
- XMM9L := 18.
- XMM10L := 20.
- XMM11L := 22.
- XMM12L := 24.
- XMM13L := 26.
- XMM14L := 28.
- XMM15L := 30.
- XMM0H := 1.
- XMM1H := 3.
- XMM2H := 5.
- XMM3H := 7.
- XMM4H := 9.
- XMM5H := 11.
- XMM6H := 13.
- XMM7H := 15.
- XMM8H := 17.
- XMM9H := 19.
- XMM10H := 21.
- XMM11H := 23.
- XMM12H := 25.
- XMM13H := 27.
- XMM14H := 29.
- XMM15H := 31.
-
"Mod R/M Mod fields. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-2"
ModRegInd := 0.
ModRegIndSIB := 4.
ModRegIndDisp32 := 5.
ModRegRegDisp8 := 1.
ModRegRegDisp32 := 2.
ModReg := 3.
"SIB Scaled Index modes. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-3"
SIB1 := 0.
SIB2 := 1.
SIB4 := 2.
SIB8 := 3.
"Specific instructions"
self
initializeSpecificOpcodes: #(CDQ IDIVR IMULRR CPUID LFENCE MFENCE SFENCE LOCK CMPXCHGAwR CMPXCHGMwrR XCHGAwR XCHGMwrR XCHGRR)
in: thisContext method!
Item was changed:
----- Method: CogX64Compiler>>cResultRegister (in category 'accessing') -----
cResultRegister
+ "Answer the register through which C funcitons return integral results."
+ <inline: true>
+ ^RAX!
- "Answer the abstract register for the C result register.
- Only partially implemented. Works on x64 since TempReg = RAX = C result reg."
- ^self abstractRegisterForConcreteRegister: RAX!
Item was changed:
----- Method: CogX64Compiler>>callerSavedRegisterMask (in category 'accessing') -----
callerSavedRegisterMask
"See e.g. Figure 3.4 Register Usage in
System V Application Binary Interface
AMD64 Architecture Processor Supplement
N.B. We are playing fast and loose here being processor-specific.
Soon enough this needs to be OS-specific."
^cogit
+ registerMaskFor: RAX
+ and: RCX
+ and: RDX
+ and: RSI
+ and: RDI
+ and: R8
+ and: R9
+ and: R10
+ and: R11!
- registerMaskFor: (self abstractRegisterForConcreteRegister: RAX)
- and: (self abstractRegisterForConcreteRegister: RCX)
- and: (self abstractRegisterForConcreteRegister: RDX)
- and: (self abstractRegisterForConcreteRegister: RSI)
- and: (self abstractRegisterForConcreteRegister: RDI)
- and: (self abstractRegisterForConcreteRegister: R8)
- and: (self abstractRegisterForConcreteRegister: R9)
- and: (self abstractRegisterForConcreteRegister: R10)
- and: (self abstractRegisterForConcreteRegister: R11)!
Item was changed:
----- Method: CogX64Compiler>>computeMaximumSize (in category 'generate machine code') -----
(excessive size, no diff calculated)
Item was changed:
----- Method: CogX64Compiler>>computeShiftRRSize (in category 'generate machine code') -----
computeShiftRRSize
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into ecx."
| shiftCountReg |
+ shiftCountReg := operands at: 0.
- shiftCountReg := self concreteRegister: (operands at: 0).
shiftCountReg = RCX ifTrue:
[^maxSize := 3].
^maxSize := shiftCountReg = RAX
ifTrue: [2 "XCHG RAX,r2" + 3 "Sxx" + 2 "XCHG RAX,r2"]
ifFalse: [3 "XCHG r1,r2" + 3 "Sxx" + 3 "XCHG r1,r2"]!
Item was changed:
----- Method: CogX64Compiler>>concretizeArithCqRWithRO:raxOpcode: (in category 'generate machine code') -----
concretizeArithCqRWithRO: regOpcode raxOpcode: raxOpcode
"Will get inlined into concretizeAt: switch."
<inline: false>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg).
(self isQuick: value) ifTrue:
[machineCode
at: 1 put: 16r83;
at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
at: 3 put: (value bitAnd: 16rFF).
^machineCodeSize := 4].
(self isSignExtendedFourByteValue: value) ifTrue:
[reg = RAX ifTrue:
[machineCode
at: 1 put: raxOpcode;
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 1 put: 16r81;
at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
at: 3 put: (value bitAnd: 16rFF);
at: 4 put: (value >> 8 bitAnd: 16rFF);
at: 5 put: (value >> 16 bitAnd: 16rFF);
at: 6 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
^self concretizeArithCwR: (raxOpcode = 16r3D "Cmp" ifTrue: [16r39] ifFalse: [raxOpcode - 2])!
Item was changed:
----- Method: CogX64Compiler>>concretizeCmpC32R (in category 'generate machine code') -----
concretizeCmpC32R
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = RAX ifTrue:
[machineCode
at: 0 put: 16r48;
at: 1 put: 16r3D;
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 0 put: 16r49;
at: 1 put: 16r81;
at: 2 put: (self mod: ModReg RM: reg RO: 7);
at: 3 put: (value bitAnd: 16rFF);
at: 4 put: (value >> 8 bitAnd: 16rFF);
at: 5 put: (value >> 16 bitAnd: 16rFF);
at: 6 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogX64Compiler>>concretizeCmpRdRd (in category 'generate machine code') -----
concretizeCmpRdRd
"Will get inlined into concretizeAt: switch.
We use UCOMISD (see p 4-260 [2])"
<inline: true>
| regLHS regRHS |
"CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode
at: 0 put: 16r66;
at: 1 put: 16r0F;
at: 2 put: 16r2E;
at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
^machineCodeSize := 4!
Item was changed:
----- Method: CogX64Compiler>>concretizeConvertRRd (in category 'generate machine code') -----
concretizeConvertRRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg destReg |
+ srcReg := operands at:0.
+ destReg := operands at: 1.
- srcReg := self concreteRegister: (operands at:0).
- destReg := self concreteDPFPRegister: (operands at: 1).
machineCode
at: 0 put: 16rF2;
at: 1 put: (self rexR: destReg x: 0 b: srcReg);
at: 2 put: 16r0F;
at: 3 put: 16r2A;
at: 4 put: (self mod: ModReg RM: srcReg RO: destReg).
^machineCodeSize := 5!
Item was changed:
----- Method: CogX64Compiler>>concretizeIDIVR (in category 'generate machine code') -----
concretizeIDIVR
"Will get inlined into concretizeAt: switch."
<inline: true>
| regDivisor |
+ regDivisor := operands at: 0.
- regDivisor := self concreteRegister: (operands at: 0).
machineCode
at: 0 put: (self rexR: 0 x: 0 b: regDivisor);
at: 1 put: 16rF7;
at: 2 put: (self mod: ModReg RM: regDivisor RO: 7).
^machineCodeSize := 3!
Item was changed:
----- Method: CogX64Compiler>>concretizeJumpR (in category 'generate machine code') -----
concretizeJumpR
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
machineCode
at: 0 put: 16rFF;
at: 1 put: (self mod: ModReg RM: reg RO: 4).
^machineCodeSize := 2!
Item was changed:
----- Method: CogX64Compiler>>concretizeLoadEffectiveAddressMwrR (in category 'generate machine code') -----
concretizeLoadEffectiveAddressMwrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: destReg x: 0 b: srcReg);
at: 1 put: 16r8D.
(srcReg ~= RSP and: [srcReg ~= R12]) ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"ESP/R12:"
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveAbR (in category 'generate machine code') -----
concretizeMoveAbR
"N.B. The Cogit makes no assumption about the upper bits being set to zero because we
deny byteReadsZeroExtend. The cogit will clear the register before hand if necessary."
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg offset save0 save1 |
addressOperand := operands at: 0.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
(self isAddressRelativeToVarBase: addressOperand) ifTrue:
[save0 := operands at: 0.
save1 := operands at: 1.
operands
at: 0 put: addressOperand - cogit varBaseAddress;
at: 1 put: RBX;
at: 2 put: save1.
self concretizeMoveMbrR.
operands
at: 0 put: save0;
at: 1 put: save1;
at: 2 put: 0.
^machineCodeSize].
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = RAX
ifTrue: [offset := 0]
ifFalse:
[machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16r90 + (reg \\ 8).
offset := 2].
machineCode
at: 0 + offset put: 16r48;
at: 1 + offset put: 16rA0;
at: 2 + offset put: (addressOperand bitAnd: 16rFF);
at: 3 + offset put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 + offset put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 + offset put: (addressOperand >> 24 bitAnd: 16rFF);
at: 6 + offset put: (addressOperand >> 32 bitAnd: 16rFF);
at: 7 + offset put: (addressOperand >> 40 bitAnd: 16rFF);
at: 8 + offset put: (addressOperand >> 48 bitAnd: 16rFF);
at: 9 + offset put: (addressOperand >> 56 bitAnd: 16rFF).
reg = RAX ifTrue:
[^machineCodeSize := 10].
machineCode
at: 12 put: (machineCode at: 0);
at: 13 put: (machineCode at: 1).
^machineCodeSize := 14!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveAwR (in category 'generate machine code') -----
concretizeMoveAwR
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg offset save0 save1 |
addressOperand := operands at: 0.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
(self isAddressRelativeToVarBase: addressOperand) ifTrue:
[save0 := operands at: 0.
save1 := operands at: 1.
operands
at: 0 put: addressOperand - cogit varBaseAddress;
at: 1 put: RBX;
at: 2 put: save1.
self concretizeMoveMwrR.
operands
at: 0 put: save0;
at: 1 put: save1;
at: 2 put: 0.
^machineCodeSize].
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
reg = RAX
ifTrue: [offset := 0]
ifFalse:
[machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16r90 + (reg \\ 8).
offset := 2].
machineCode
at: 0 + offset put: 16r48;
at: 1 + offset put: 16rA1;
at: 2 + offset put: (addressOperand bitAnd: 16rFF);
at: 3 + offset put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 + offset put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 + offset put: (addressOperand >> 24 bitAnd: 16rFF);
at: 6 + offset put: (addressOperand >> 32 bitAnd: 16rFF);
at: 7 + offset put: (addressOperand >> 40 bitAnd: 16rFF);
at: 8 + offset put: (addressOperand >> 48 bitAnd: 16rFF);
at: 9 + offset put: (addressOperand >> 56 bitAnd: 16rFF).
reg = RAX ifTrue:
[^machineCodeSize := 10].
machineCode
at: 12 put: (machineCode at: 0);
at: 13 put: (machineCode at: 1).
^machineCodeSize := 14!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveC32R (in category 'generate machine code') -----
concretizeMoveC32R
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16rC7;
at: 2 put: (self mod: ModReg RM: reg RO: 0);
at: 3 put: (value bitAnd: 16rFF);
at: 4 put: (value >> 8 bitAnd: 16rFF);
at: 5 put: (value >> 16 bitAnd: 16rFF);
at: 6 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveCqR (in category 'generate machine code') -----
concretizeMoveCqR
"Will get inlined into concretizeAt: switch.
On x64 we can short-cut mov 0, reg using xor, and use 32-bit displacement, signed or unsigned, if possible."
<inline: true>
| value reg |
value := operands at: 0.
(self is32BitSignedImmediate: value) ifFalse:
[^self concretizeMoveCwR].
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
value = 0 ifTrue:
[machineCode
at: 0 put: (self rexR: reg x: 0 b: reg);
at: 1 put: 16r31;
at: 2 put: (self mod: ModReg RM: reg RO: reg).
^machineCodeSize := 3].
machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16rC7;
at: 2 put: (self mod: ModReg RM: reg RO: 0);
at: 3 put: (value bitAnd: 16rFF);
at: 4 put: (value >> 8 bitAnd: 16rFF);
at: 5 put: (value >> 16 bitAnd: 16rFF);
at: 6 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 7!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveM16rR (in category 'generate machine code') -----
concretizeMoveM16rR
"N.B. The Cogit compiler makes no assumption about the upper bits being set to zero.
It will clear the register before hand if necessary."
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: destReg x: 0 b: srcReg);
at: 1 put: 16r0f;
at: 2 put: 16rb7.
(srcReg ~= RSP and: [srcReg ~= R12]) ifTrue:
[(offset = 0 and: [destReg ~= RBP and: [destReg ~= R13]]) ifTrue:
[machineCode
at: 3 put: (self mod: ModRegInd RM: srcReg RO: destReg).
^machineCodeSize := 4].
(self isQuick: offset) ifTrue:
[machineCode
at: 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 3 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8].
"RSP & R12:"
(offset = 0 and: [destReg ~= RBP and: [destReg ~= R13]]) ifTrue:
[machineCode
at: 3 put: (self mod: ModRegInd RM: srcReg RO: destReg);
at: 4 put: (self s: SIB1 i: 4 b: srcReg).
^machineCodeSize := 5].
(self isQuick: offset) ifTrue:
[machineCode
at: 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 4 put: (self s: SIB1 i: 4 b: srcReg);
at: 5 put: (offset bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 3 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 4 put: (self s: SIB1 i: 4 b: srcReg);
at: 5 put: (offset bitAnd: 16rFF);
at: 6 put: (offset >> 8 bitAnd: 16rFF);
at: 7 put: (offset >> 16 bitAnd: 16rFF);
at: 8 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 9!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveM64rRd (in category 'generate machine code') -----
concretizeMoveM64rRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| offset srcReg destReg skip |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteDPFPRegister: (operands at: 2).
machineCode at: 0 put: 16rF3.
(srcReg <= 7 and: [destReg <= 7])
ifTrue: [skip := 0]
ifFalse: [machineCode at: (skip := 1) put: (self rexw: false r: destReg x: 0 b: srcReg)].
machineCode
at: skip + 1 put: 16r0f;
at: skip + 2 put: 16r7e.
offset = 0 ifTrue:
[(srcReg bitAnd: 6) ~= RSP ifTrue:
[machineCode at: skip + 3 put: (self mod: ModRegInd RM: srcReg RO: destReg).
^machineCodeSize := skip + 4].
(srcReg bitAnd: 7) = RSP ifTrue: "RBP & R13 fall through"
[machineCode
at: skip + 3 put: (self mod: ModRegInd RM: srcReg RO: destReg);
at: skip + 4 put: (self s: SIB1 i: 4 b: srcReg).
^machineCodeSize := skip + 5]].
(self isQuick: offset) ifTrue:
[(srcReg bitAnd: 7) ~= RSP ifTrue:
[machineCode
at: skip + 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: skip + 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := skip + 5].
machineCode
at: skip + 3 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: skip + 4 put: (self s: SIB1 i: 4 b: srcReg);
at: skip + 5 put: (offset bitAnd: 16rFF).
^machineCodeSize := skip + 6].
machineCode at: skip + 3 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg).
(srcReg bitAnd: 7) = RSP ifTrue:
[machineCode at: skip + 4 put: (self s: SIB1 i: 4 b: srcReg).
skip := skip + 1].
machineCode
at: skip + 4 put: (offset bitAnd: 16rFF);
at: skip + 5 put: (offset >> 8 bitAnd: 16rFF);
at: skip + 6 put: (offset >> 16 bitAnd: 16rFF);
at: skip + 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := skip + 8!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveMbrR (in category 'generate machine code') -----
concretizeMoveMbrR
"N.B. The Cogit makes no assumption about the upper bits being set to zero because we
deny byteReadsZeroExtend. The cogit will clear the register before hand if necessary."
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: destReg x: 0 b: srcReg);
at: 1 put: 16r8A.
(srcReg ~= RSP and: [srcReg ~= R12]) ifTrue:
[(offset = 0 and: [srcReg ~= RBP and: [srcReg ~= R13]]) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: srcReg RO: destReg).
^machineCodeSize := 3].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"RSP:"
offset = 0 ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg).
^machineCodeSize := 4].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveMwrR (in category 'generate machine code') -----
concretizeMoveMwrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
+ srcReg := operands at: 1.
+ destReg := operands at: 2.
- srcReg := self concreteRegister: (operands at: 1).
- destReg := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: destReg x: 0 b: srcReg);
at: 1 put: 16r8B.
(srcReg ~= RSP and: [srcReg ~= R12]) ifTrue:
[(offset = 0 and: [srcReg ~= RBP and: [srcReg ~= R13]]) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: srcReg RO: destReg).
^machineCodeSize := 3].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"RSP:"
offset = 0 ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg).
^machineCodeSize := 4].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRAb (in category 'generate machine code') -----
concretizeMoveRAb
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg offset save1 |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
addressOperand := operands at: 1.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
(self isAddressRelativeToVarBase: addressOperand) ifTrue:
[save1 := operands at: 1.
operands
at: 1 put: addressOperand - cogit varBaseAddress;
at: 2 put: RBX.
self concretizeMoveRMbr.
operands
at: 1 put: save1;
at: 2 put: 0.
^machineCodeSize].
reg = RAX
ifTrue: [offset := 0]
ifFalse:
[machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16r90 + (reg \\ 8).
offset := 2].
machineCode
at: 0 + offset put: 16r48;
at: 1 + offset put: 16rA2;
at: 2 + offset put: (addressOperand bitAnd: 16rFF);
at: 3 + offset put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 + offset put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 + offset put: (addressOperand >> 24 bitAnd: 16rFF);
at: 6 + offset put: (addressOperand >> 32 bitAnd: 16rFF);
at: 7 + offset put: (addressOperand >> 40 bitAnd: 16rFF);
at: 8 + offset put: (addressOperand >> 48 bitAnd: 16rFF);
at: 9 + offset put: (addressOperand >> 56 bitAnd: 16rFF).
reg = RAX ifTrue:
[^machineCodeSize := 10].
machineCode
at: 12 put: (machineCode at: 0);
at: 13 put: (machineCode at: 1).
^machineCodeSize := 14!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRAw (in category 'generate machine code') -----
concretizeMoveRAw
"Will get inlined into concretizeAt: switch."
<inline: true>
| addressOperand reg offset save1 |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
addressOperand := operands at: 1.
(self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:
[addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].
(self isAddressRelativeToVarBase: addressOperand) ifTrue:
[save1 := operands at: 1.
operands
at: 1 put: addressOperand - cogit varBaseAddress;
at: 2 put: RBX.
self concretizeMoveRMwr.
operands
at: 1 put: save1;
at: 2 put: 0.
^machineCodeSize].
reg = RAX
ifTrue: [offset := 0]
ifFalse:
[machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16r90 + (reg \\ 8).
offset := 2].
machineCode
at: 0 + offset put: 16r48;
at: 1 + offset put: 16rA3;
at: 2 + offset put: (addressOperand bitAnd: 16rFF);
at: 3 + offset put: (addressOperand >> 8 bitAnd: 16rFF);
at: 4 + offset put: (addressOperand >> 16 bitAnd: 16rFF);
at: 5 + offset put: (addressOperand >> 24 bitAnd: 16rFF);
at: 6 + offset put: (addressOperand >> 32 bitAnd: 16rFF);
at: 7 + offset put: (addressOperand >> 40 bitAnd: 16rFF);
at: 8 + offset put: (addressOperand >> 48 bitAnd: 16rFF);
at: 9 + offset put: (addressOperand >> 56 bitAnd: 16rFF).
reg = RAX ifTrue:
[^machineCodeSize := 10].
machineCode
at: 12 put: (machineCode at: 0);
at: 13 put: (machineCode at: 1).
^machineCodeSize := 14!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRMbr (in category 'generate machine code') -----
concretizeMoveRMbr
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
offset := operands at: 1.
+ destReg := operands at: 2.
- destReg := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: srcReg x: 0 b: destReg);
at: 1 put: 16r88.
(destReg ~= RSP and: [destReg ~= R12]) ifTrue:
[(offset = 0 and: [destReg ~= RBP and: [destReg ~= R13]]) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: destReg RO: srcReg).
^machineCodeSize := 3].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"RSP:"
offset = 0 ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: destReg RO: srcReg);
at: 3 put: (self s: SIB1 i: 4 b: destReg).
^machineCodeSize := 4].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 3 put: (self s: SIB1 i: 4 b: destReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 3 put: (self s: SIB1 i: 4 b: destReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRMwr (in category 'generate machine code') -----
concretizeMoveRMwr
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg offset destReg |
+ srcReg := operands at: 0.
- srcReg := self concreteRegister: (operands at: 0).
offset := operands at: 1.
+ destReg := operands at: 2.
- destReg := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: srcReg x: 0 b: destReg);
at: 1 put: 16r89.
(destReg ~= RSP and: [destReg ~= R12]) ifTrue:
[(offset = 0 and: [destReg ~= RBP and: [destReg ~= R13]]) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: destReg RO: srcReg).
^machineCodeSize := 3].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"RSP:"
offset = 0 ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: destReg RO: srcReg);
at: 3 put: (self s: SIB1 i: 4 b: destReg).
^machineCodeSize := 4].
(self isQuick: offset) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: 3 put: (self s: SIB1 i: 4 b: destReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 2 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg);
at: 3 put: (self s: SIB1 i: 4 b: destReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRRd (in category 'generate machine code') -----
concretizeMoveRRd
<inline: true>
| srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
- srcReg := self concreteRegister: (operands at: 0).
- destReg := self concreteDPFPRegister: (operands at: 1).
machineCode
at: 0 put: 16r66;
at: 1 put: (self rexR: destReg x: 0 b: srcReg);
at: 2 put: 16r0f;
at: 3 put: 16r6e;
at: 4 put: (self mod: ModReg RM: srcReg RO: destReg).
^machineCodeSize := 5!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRXbrR (in category 'generate machine code') -----
concretizeMoveRXbrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base dest offset |
+ index := operands at: 0.
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0).
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
offset := 0.
(dest >= 8 or: [base >= 8 or: [index >= 8]]) ifTrue:
[machineCode at: 0 put: (self rexR: dest x: index b: base).
offset := 1].
machineCode
at: 0 + offset put: 16r88.
(base ~= RBP and: [base ~= R13]) ifTrue:
[machineCode
at: 1 + offset put: (self mod: ModRegInd RM: 4 RO: dest);
at: 2 + offset put: (self s: SIB1 i: index b: base).
^machineCodeSize := 3 + offset].
machineCode
at: 1 + offset put: (self mod: ModRegRegDisp8 RM: 4 RO: dest);
at: 2 + offset put: (self s: SIB1 i: index b: base);
at: 3 + offset put: 0.
^machineCodeSize := 4 + offset!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRXwrR (in category 'generate machine code') -----
concretizeMoveRXwrR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base src |
+ src := operands at: 0.
+ index := operands at: 1.
+ base := operands at: 2.
- src := self concreteRegister: (operands at: 0).
- index := self concreteRegister: (operands at: 1).
- base := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: src x: index b: base).
(base ~= RBP and: [base ~= R13]) ifTrue:
[machineCode
at: 1 put: 16r89;
at: 2 put: (self mod: ModRegInd RM: 4 RO: src);
at: 3 put: (self s: SIB8 i: index b: base).
^machineCodeSize := 4].
machineCode
at: 1 put: 16r89;
at: 2 put: (self mod: ModRegRegDisp8 RM: 4 RO: src);
at: 3 put: (self s: SIB8 i: index b: base);
at: 4 put: 0.
^machineCodeSize := 5!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRdM64r (in category 'generate machine code') -----
concretizeMoveRdM64r
<inline: true>
| offset srcReg destReg skip |
+ srcReg := operands at: 0.
- srcReg := self concreteDPFPRegister: (operands at: 0).
offset := operands at: 1.
+ destReg := operands at: 2.
- destReg := self concreteRegister: (operands at: 2).
machineCode at: 0 put: 16r66.
(srcReg <= 7 and: [destReg <= 7])
ifTrue: [skip := 0]
ifFalse: [machineCode at: (skip := 1) put: (self rexw: false r: srcReg x: 0 b: destReg)].
machineCode
at: skip + 1 put: 16r0f;
at: skip + 2 put: 16rd6.
offset = 0 ifTrue:
[(destReg bitAnd: 6) ~= RSP ifTrue:
[machineCode at: skip + 3 put: (self mod: ModRegInd RM: destReg RO: srcReg).
^machineCodeSize := skip + 4].
(destReg bitAnd: 7) = RSP ifTrue: "RBP & R13 fall through"
[machineCode
at: skip + 3 put: (self mod: ModRegInd RM: destReg RO: srcReg);
at: skip + 4 put: (self s: SIB1 i: 4 b: destReg).
^machineCodeSize := skip + 5]].
(self isQuick: offset) ifTrue:
[(destReg bitAnd: 7) ~= RSP ifTrue:
[machineCode
at: skip + 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: skip + 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := skip + 5].
machineCode
at: skip + 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
at: skip + 4 put: (self s: SIB1 i: 4 b: destReg);
at: skip + 5 put: (offset bitAnd: 16rFF).
^machineCodeSize := skip + 6].
machineCode at: skip + 3 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg).
(destReg bitAnd: 7) = RSP ifTrue:
[machineCode at: skip + 4 put: (self s: SIB1 i: 4 b: destReg).
skip := skip + 1].
machineCode
at: skip + 4 put: (offset bitAnd: 16rFF);
at: skip + 5 put: (offset >> 8 bitAnd: 16rFF);
at: skip + 6 put: (offset >> 16 bitAnd: 16rFF);
at: skip + 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := skip + 8!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveRdR (in category 'generate machine code') -----
concretizeMoveRdR
<inline: true>
| srcReg destReg |
+ srcReg := operands at: 0.
+ destReg := operands at: 1.
- srcReg := self concreteDPFPRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: 16r66;
at: 1 put: (self rexR: srcReg x: 0 b: destReg);
at: 2 put: 16r0f;
at: 3 put: 16r7e;
at: 4 put: (self mod: ModReg RM: destReg RO: srcReg).
^machineCodeSize := 5!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveX32rRR (in category 'generate machine code') -----
concretizeMoveX32rRR
"MoveX32rRR is expected to zero-extend, so explicitly zero the destination."
| index base dest offset |
+ index := operands at: 0.
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0).
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: dest x: 0 b: dest);
at: 1 put: 16r31;
at: 2 put: (self mod: ModReg RM: dest RO: dest).
(index > 7 or: [base > 7 or: [dest > 7]])
ifTrue:
[machineCode at: 3 put: (self rexw: false r: dest x: index b: base).
offset := 1]
ifFalse:
[offset := 0].
(base bitAnd: 7) ~= RBP ifTrue:
[machineCode
at: offset + 3 put: 16r8B;
at: offset + 4 put: (self mod: ModRegInd RM: 4 RO: dest);
at: offset + 5 put: (self s: SIB4 i: index b: base).
^machineCodeSize := offset + 6].
machineCode
at: offset + 3 put: 16r8B;
at: offset + 4 put: (self mod: ModRegRegDisp8 RM: 4 RO: dest);
at: offset + 5 put: (self s: SIB4 i: index b: base);
at: offset + 6 put: 0.
^machineCodeSize := offset + 7!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveXbrRR (in category 'generate machine code') -----
concretizeMoveXbrRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base dest |
+ index := operands at: 0.
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0).
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: dest x: index b: base);
at: 1 put: 16r8A.
(base ~= RBP and: [base ~= R13]) ifTrue:
[machineCode
at: 2 put: (self mod: ModRegInd RM: 4 RO: dest);
at: 3 put: (self s: SIB1 i: index b: base).
^machineCodeSize := 4].
machineCode
at: 2 put: (self mod: ModRegRegDisp8 RM: 4 RO: dest);
at: 3 put: (self s: SIB1 i: index b: base);
at: 4 put: 0.
^machineCodeSize := 5!
Item was changed:
----- Method: CogX64Compiler>>concretizeMoveXwrRR (in category 'generate machine code') -----
concretizeMoveXwrRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| index base dest |
+ index := operands at: 0.
+ base := operands at: 1.
+ dest := operands at: 2.
- index := self concreteRegister: (operands at: 0).
- base := self concreteRegister: (operands at: 1).
- dest := self concreteRegister: (operands at: 2).
machineCode
at: 0 put: (self rexR: dest x: index b: base).
(base ~= RBP and: [base ~= R13]) ifTrue:
[machineCode
at: 1 put: 16r8B;
at: 2 put: (self mod: ModRegInd RM: 4 RO: dest);
at: 3 put: (self s: SIB8 i: index b: base).
^machineCodeSize := 4].
machineCode
at: 1 put: 16r8B;
at: 2 put: (self mod: ModRegRegDisp8 RM: 4 RO: dest);
at: 3 put: (self s: SIB8 i: index b: base);
at: 4 put: 0.
^machineCodeSize := 5!
Item was changed:
----- Method: CogX64Compiler>>concretizeMulRR (in category 'generate machine code') -----
concretizeMulRR
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg1 reg2 |
+ reg1 := operands at: 0.
+ reg2 := operands at: 1.
- reg1 := self concreteRegister: (operands at: 0).
- reg2 := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: (self rexR: reg2 x: 0 b: reg1);
at: 1 put: 16r0F;
at: 2 put: 16rAF;
at: 3 put: (self mod: ModReg RM: reg1 RO: reg2).
^machineCodeSize := 4!
Item was changed:
----- Method: CogX64Compiler>>concretizeNegateR (in category 'generate machine code') -----
concretizeNegateR
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg);
at: 1 put: 16rF7;
at: 2 put: (self mod: ModReg RM: reg RO: 3).
^machineCodeSize := 3!
Item was changed:
----- Method: CogX64Compiler>>concretizeOpRR: (in category 'generate machine code') -----
concretizeOpRR: x64opcode
| regLHS regRHS |
+ regLHS := operands at: 0.
+ regRHS := operands at: 1.
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
at: 1 put: x64opcode;
at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
^machineCodeSize := 3!
Item was changed:
----- Method: CogX64Compiler>>concretizePopR (in category 'generate machine code') -----
concretizePopR
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
reg < 8 ifTrue:
[machineCode at: 0 put: 16r58 + reg.
^machineCodeSize := 1].
machineCode
at: 0 put: 16r41;
at: 1 put: 16r58 + (reg - 8).
^machineCodeSize := 2!
Item was changed:
----- Method: CogX64Compiler>>concretizePushR (in category 'generate machine code') -----
concretizePushR
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteRegister: (operands at: 0).
reg < 8 ifTrue:
[machineCode at: 0 put: 16r50 + reg.
^machineCodeSize := 1].
machineCode
at: 0 put: 16r41;
at: 1 put: 16r50 + (reg - 8).
^machineCodeSize := 2!
Item was changed:
----- Method: CogX64Compiler>>concretizeReverseOpRR: (in category 'generate machine code') -----
concretizeReverseOpRR: x64opcode
| regLHS regRHS |
"CmpRR/MoveRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteRegister: (operands at: 0).
- regLHS := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
at: 1 put: x64opcode;
at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
^machineCodeSize := 3!
Item was changed:
----- Method: CogX64Compiler>>concretizeSEE2OpRdRd: (in category 'generate machine code') -----
concretizeSEE2OpRdRd: x64opcode
"Will get inlined into concretizeAt: switch."
<inline: true>
| regLHS regRHS |
+ regRHS := operands at: 0.
+ regLHS := operands at: 1.
- regRHS := self concreteDPFPRegister: (operands at: 0).
- regLHS := self concreteDPFPRegister: (operands at: 1).
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: x64opcode;
at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
^machineCodeSize := 4!
Item was changed:
----- Method: CogX64Compiler>>concretizeShiftCqRegOpcode: (in category 'generate machine code') -----
concretizeShiftCqRegOpcode: regOpcode
"Will get inlined into concretizeAt: switch."
<inline: true>
| distance reg |
distance := operands at: 0.
self assert: (distance between: 1 and: 63).
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode at: 0 put: (self rexR: 0 x: 0 b: reg).
distance = 1 ifTrue:
[machineCode
at: 1 put: 16rD1;
at: 2 put: (self mod: ModReg RM: reg RO: regOpcode).
^machineCodeSize := 3].
machineCode
at: 1 put: 16rC1;
at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
at: 3 put: distance.
^machineCodeSize := 4!
Item was changed:
----- Method: CogX64Compiler>>concretizeShiftRegRegOpcode: (in category 'generate machine code') -----
concretizeShiftRegRegOpcode: regOpcode
"On the x64 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into %ecx."
<inline: true>
| shiftCountReg destReg regToShift |
+ shiftCountReg := operands at: 0.
+ destReg := operands at: 1.
- shiftCountReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
shiftCountReg = RCX ifTrue:
[machineCode
at: 0 put: (self rexR: 0 x: 0 b: destReg);
at: 1 put: 16rD3;
at: 2 put: (self mod: ModReg RM: destReg RO: regOpcode).
^machineCodeSize := 3].
regToShift := destReg = shiftCountReg
ifTrue: [RCX]
ifFalse: [destReg = RCX
ifTrue: [shiftCountReg]
ifFalse: [destReg]].
shiftCountReg = RAX ifTrue:
[machineCode
at: 0 put: 16r48;
at: 1 put: 16r90 + RCX; "XCHG RAX,RCX"
at: 2 put: (self rexR: 0 x: 0 b: regToShift);
at: 3 put: 16rD3; "SAR RCX,RAX"
at: 4 put: (self mod: ModReg RM: regToShift RO: regOpcode);
at: 5 put: 16r48;
at: 6 put: 16r90 + RCX. "XCHG RAX,RCX"
^machineCodeSize := 7].
machineCode
at: 0 put: (self rexR: shiftCountReg x: 0 b: RCX); "XCHG R?X,RCX"
at: 1 put: 16r87;
at: 2 put: (self mod: ModReg RM: RCX RO: shiftCountReg);
at: 3 put: (self rexR: 0 x: 0 b: regToShift); "SAR RCX,R!!X"
at: 4 put: 16rD3;
at: 5 put: (self mod: ModReg RM: regToShift RO: regOpcode);
at: 6 put: (self rexR: shiftCountReg x: 0 b: RCX); "XCHG R?X,RCX"
at: 7 put: 16r87;
at: 8 put: (self mod: ModReg RM: RCX RO: shiftCountReg).
^machineCodeSize := 9!
Item was changed:
----- Method: CogX64Compiler>>concretizeSqrtRd (in category 'generate machine code') -----
concretizeSqrtRd
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
+ reg := operands at: 0.
- reg := self concreteDPFPRegister: (operands at: 0).
machineCode
at: 0 put: 16rF2;
at: 1 put: 16r0F;
at: 2 put: 16r51;
at: 3 put: (self mod: ModReg RM: reg RO: reg).
^machineCodeSize := 4!
Item was changed:
----- Method: CogX64Compiler>>concretizeTstCqR (in category 'generate machine code') -----
concretizeTstCqR
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
+ reg := operands at: 1.
- reg := self concreteRegister: (operands at: 1).
machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg).
(self isQuick: value) ifTrue:
[machineCode
at: 1 put: 16rF6;
at: 2 put: (self mod: ModReg RM: reg RO: 0);
at: 3 put: (value bitAnd: 16rFF).
^machineCodeSize := 4].
(self isSignExtendedFourByteValue: value) ifTrue:
[reg = RAX ifTrue:
[machineCode
at: 1 put: 16rA9;
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 1 put: 16rF7;
at: 2 put: (self mod: ModReg RM: reg RO: 0);
at: 3 put: (value bitAnd: 16rFF);
at: 4 put: (value >> 8 bitAnd: 16rFF);
at: 5 put: (value >> 16 bitAnd: 16rFF);
at: 6 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
^self concretizeArithCwR: 16r85!
Item was changed:
----- Method: CogX64Compiler>>concretizeXCHGRR (in category 'generate machine code') -----
concretizeXCHGRR
| r1 r2 |
+ r1 := operands at: 0.
+ r2 := operands at: 1.
- r1 := self concreteRegister: (operands at: 0).
- r2 := self concreteRegister: (operands at: 1).
r2 = RAX ifTrue:
[r2 := r1. r1 := RAX].
r1 = RAX ifTrue:
[machineCode
at: 0 put: (self rexR: 0 x: 0 b: r2);
at: 1 put: 16r90 + (r2 \\ 8).
^machineCodeSize := 2].
machineCode
at: 0 put: (self rexR: r1 x: 0 b: r2);
at: 1 put: 87;
at: 2 put: (self mod: r2 RM: 0 RO: r1).
^machineCodeSize := 3!
Item was changed:
----- Method: CogX64Compiler>>genDivR:R:Quo:Rem: (in category 'abstract instructions') -----
genDivR: abstractRegDivisor R: abstractRegDividend Quo: abstractRegQuotient Rem: abstractRegRemainder
| rDividend rDivisor rQuotient rRemainder saveRestoreEAX saveRestoreEDX saveRestoreExchanged |
self assert: abstractRegDividend ~= abstractRegDivisor.
self assert: abstractRegQuotient ~= abstractRegRemainder.
+ rDividend := abstractRegDividend.
+ rDivisor := abstractRegDivisor.
+ rQuotient := abstractRegQuotient.
+ rRemainder := abstractRegRemainder.
- rDividend := self concreteRegister: abstractRegDividend.
- rDivisor := self concreteRegister: abstractRegDivisor.
- rQuotient := self concreteRegister: abstractRegQuotient.
- rRemainder := self concreteRegister: abstractRegRemainder.
"IDIV r does a signed divide of RDX:RAX by r, RAX := Quotient, RDX := Remainder.
Since we must sign extend the dividend into RDX we must substitute another register if RDX is an input."
(rDividend = RDX or: [rDivisor = RDX]) ifTrue:
[| rUnused |
"Slang, sigh..."
rUnused := RAX.
[rUnused <= RDI] whileTrue:
[(rUnused ~= RSP and: [rUnused ~= RBP and: [rUnused ~= RDX
and: [rUnused ~= rDividend and: [rUnused ~= rDivisor
and: [rUnused ~= rQuotient and: [rUnused ~= rRemainder]]]]]]) ifTrue:
[cogit PushR: rUnused.
cogit MoveR: RDX R: rUnused.
rDividend = RDX
ifTrue: [self genDivR: rDivisor R: rUnused Quo: rQuotient Rem: rRemainder]
ifFalse: [self genDivR: rUnused R: rDividend Quo: rQuotient Rem: rRemainder].
cogit PopR: rUnused.
^self].
rUnused := rUnused + 1].
self error: 'couldn''t find unused register in genDivR:R:Quo:Rem:'].
"If either output does not include RAX or RDX we must save and restore RAX and/or RDX."
(saveRestoreEAX := rQuotient ~= RAX and: [rRemainder ~= RAX]) ifTrue:
[cogit PushR: RAX].
(saveRestoreEDX := rQuotient ~= RDX and: [rRemainder ~= RDX]) ifTrue:
[cogit PushR: RDX].
saveRestoreExchanged := -1.
rDividend ~= RAX ifTrue:
[rDivisor = RAX
ifTrue: [((rDividend ~= rQuotient and: [rDividend ~= rRemainder])
and: [rDividend ~= RDX or: [saveRestoreEDX not]]) ifTrue:
[cogit PushR: (saveRestoreExchanged := rDividend)].
cogit gen: XCHGRR operand: rDivisor operand: rDividend]
ifFalse: [cogit MoveR: rDividend R: RAX]].
"CDQ sign-extends RAX into RDX as required for IDIV"
cogit gen: CDQ.
cogit gen: IDIVR operand: (rDivisor = RAX ifTrue: [rDividend] ifFalse: [rDivisor]).
"Must not overwrite result while juggling"
(rQuotient = RDX and: [rRemainder = RAX])
ifTrue: [cogit gen: XCHGRR operand: rQuotient operand: rRemainder]
ifFalse:
[rQuotient = RDX
ifTrue:
[rRemainder ~= RDX ifTrue:
[cogit MoveR: RDX R: rRemainder].
rQuotient ~= RAX ifTrue:
[cogit MoveR: RAX R: rQuotient]]
ifFalse:
[rQuotient ~= RAX ifTrue:
[cogit MoveR: RAX R: rQuotient].
rRemainder ~= RDX ifTrue:
[cogit MoveR: RDX R: rRemainder]]].
saveRestoreExchanged >= 0 ifTrue:
[cogit PopR: saveRestoreExchanged].
saveRestoreEDX ifTrue:
[cogit PopR: RDX].
saveRestoreEAX ifTrue:
[cogit PopR: RAX]!
Item was changed:
----- Method: CogX64Compiler>>genRestoreRegsExcept: (in category 'abi') -----
+ genRestoreRegsExcept: preservedReg
- genRestoreRegsExcept: abstractReg
- | realReg |
- realReg := self concreteRegister: abstractReg.
self assert: (R15 > RAX and: [R15 - RAX + 1 = 16]).
RAX to: R15 do:
[:reg|
(reg between: RSP and: RBP) ifFalse:
+ [preservedReg = reg
- [realReg = reg
ifTrue: [cogit AddCq: 8 R: RSP]
ifFalse: [cogit PopR: reg]]].
^0!
Item was changed:
----- Method: Cogit>>printRegisterMapOn: (in category 'disassembly') -----
printRegisterMapOn: aStream
<doNotGenerate>
| map n |
map := backEnd generalPurposeRegisterMap.
n := 0.
map keys sort
do: [:regName| | abstractName |
+ abstractName := CogRTLOpcodes nameForRegister: (map at: regName).
- abstractName := CogRTLOpcodes nameForRegister: (backEnd abstractRegisterForConcreteRegister: (map at: regName)).
aStream nextPutAll: abstractName; nextPutAll: ' => '; nextPutAll: regName]
separatedBy: [(n := n + 1) \\ 4 = 0 ifTrue: [aStream cr] ifFalse: [aStream tab]].
aStream cr; flush!
Item was changed:
----- Method: SimpleStackBasedCogit>>ceShortCutTraceLinkedSend: (in category 'simulation only') -----
ceShortCutTraceLinkedSend: aProcessorSimulationTrap
self shortcutTrampoline: aProcessorSimulationTrap
+ to: [coInterpreter ceTraceLinkedSend: (processor registerAt: ReceiverResultReg)]!
- to: [coInterpreter ceTraceLinkedSend: (processor registerAt: (backEnd concreteRegister: ReceiverResultReg))]!
Item was changed:
----- Method: SimpleStackBasedCogit>>ceShortCutTraceStore: (in category 'simulation only') -----
ceShortCutTraceStore: aProcessorSimulationTrap
<doNotGenerate>
self shortcutTrampoline: aProcessorSimulationTrap
to: [coInterpreter
+ ceTraceStoreOf: (processor registerAt: ClassReg)
+ into: (processor registerAt: ReceiverResultReg)]!
- ceTraceStoreOf: (processor registerAt: (backEnd concreteRegister: ClassReg))
- into: (processor registerAt: (backEnd concreteRegister: ReceiverResultReg))]!
Item was changed:
----- Method: StackToRegisterMappingCogit>>ceShortCutTraceStore: (in category 'simulation only') -----
ceShortCutTraceStore: aProcessorSimulationTrap
<doNotGenerate>
self shortcutTrampoline: aProcessorSimulationTrap
to: [coInterpreter
+ ceTraceStoreOf: (processor registerAt: TempReg)
+ into: (processor registerAt: ReceiverResultReg)]!
- ceTraceStoreOf: (processor registerAt: (backEnd concreteRegister: TempReg))
- into: (processor registerAt: (backEnd concreteRegister: ReceiverResultReg))]!
Item was changed:
----- Method: VMClass class>>shouldIncludeMethodForSelector: (in category 'translation') -----
shouldIncludeMethodForSelector: selector
"Answer whether a primitive method shoud be translated. Emit a warning to the transcript if the method doesn't exist."
^(self whichClassIncludesSelector: selector)
ifNotNil:
[:c|
(c >> selector pragmaAt: #option:)
ifNotNil:
[:pragma|
+ initializationOptions at: (pragma arguments first) ifAbsent: [false]]
- initializationOptions at: (pragma arguments first) ifAbsent: [true]]
ifNil: [true]]
ifNil:
[Transcript nextPutAll: 'Cannot find implementation of '; nextPutAll: selector; nextPutAll: ' in hierarchy of '; print: self; cr; flush.
false]!
1
0
Begin forwarded message:
Date: Fri, 25 Dec 2015 03:41:51 -0500
From: "Phil \(list\) via Cuis-dev" <cuis-dev(a)cuis-smalltalk.org>
To: Discussion of Cuis Smalltalk <cuis-dev(a)cuis-smalltalk.org>
Cc: "Phil \(list\)" <pbpublist(a)gmail.com>
Subject: [Cuis-dev] More robust package loading?
Happy holidays all! Here's my gift to the list... ;-)
It's been a couple of weeks since I attempted to rebuild completely
from a totally clean base image (2595) and of course it failed utterly
and completely. After some trial and error, I finally narrowed it down
to a problem installing the stock FFI.pck.st. I am running a rather
fluid version of Linux (Debian testing) and it's entirely likely that a
recent system update is causing the problem but I'm having a difficult
time getting more specific than that because when I attempt to load
FFI, all I get is this wonderful segfault:
C stack backtrace & registers:
eax 0xff887b24 ebx 0xff887a40 ecx 0xff887ad8 edx 0xff887a8c
edi 0xff887910 esi 0xff887910 ebp 0xff8879a8 esp 0xff8879f4
eip 0xff887c08
*[0xff887c08]
../lib/squeak/4.5-3427/squeak[0x805e8c0]
../lib/squeak/4.5-3427/squeak[0x805ebac]
linux-gate.so.1(__kernel_rt_sigreturn+0x0)[0xf77a4b50]
../lib/squeak/4.5-3427/squeak[0x80769bd]
../lib/squeak/4.5-3427/squeak(incrementalGC+0x237)[0x807c217]
../lib/squeak/4.5-3427/squeak[0x807cb66]
../lib/squeak/4.5-3427/squeak[0x807cf7f]
../lib/squeak/4.5-3427/squeak[0x807d0bd]
../lib/squeak/4.5-3427/squeak(ceStackOverflow+0x6d)[0x807f44d]
[0xb35832e6]
../lib/squeak/4.5-3427/squeak(interpret+0x7b6)[0x8087ef6]
../lib/squeak/4.5-3427/squeak(main+0x2af)[0x805f30f]
/lib/i386-linux-
gnu/i686/cmov/libc.so.6(__libc_start_main+0xde)[0xf753c70e]
../lib/squeak/4.5-3427/squeak[0x8131564]
Smalltalk stack dump:
0xff894cd0 M Array(SequenceableCollection)>at:ifAbsent: 0xb4c9705c:
a(n) Array
0xff894cf0 M Array(Scanner)>typeTableAt: 0xb4ca8ee0: a(n) Array
0xff894d0c M Array(Scanner)>scanToken 0xb4ca8ee0: a(n) Array
0xff894d28 M Array(Parser)>advance 0xb4ca8ee0: a(n) Array
0xff894d40 M Array(Parser)>init:notifying:failBlock: 0xb4ca8ee0: a(n)
Array
0xff894d68 M Array(Parser)>privateReadSelectorFrom: 0xb4ca8ee0: a(n)
Array
0xff894d84 M Parser class>selectorFrom: 0xb3753bd0: a(n) Parser class
0xff894da4 M INVALID RECEIVER>addMethodChange: 0xb4ca5d04: a(n) bad
class
0xff894dc0 M INVALID RECEIVER>methodChange: 0xb4ca5d04: a(n) bad class
0xff894ddc M CodePackageFile(CodeFile)>method: 0xb4c8f2ec: a(n)
CodePackageFile
Segmentation fault Fri Dec 25 03:05:08 2015
(and so on...)
Granted my main issue is largely the (lack of) information in the VM
output on the crash (i.e. I have no idea what class/method/line the is
the cause of the problem) but since this is unlikely to change in the
near term, some sort of verbose package loading mode would be most
helpful (i.e. 'loading method foo... completed loading method foo' type
messages to transcript when a package is being installed) While this
is just about a worst case package loading problem for me, I have had
other issues in the past loading packages (almost always with the code
being imported, not the package loader itself) and am thinking a more
robust package loading process (at least when running in some sort of
debug mode) would be most welcome... does this sound useful to anyone
else?
Thanks,
Phil
_______________________________________________
Cuis-dev mailing list
Cuis-dev(a)cuis-smalltalk.org
http://cuis-smalltalk.org/mailman/listinfo/cuis-dev_cuis-smalltalk.org
--
-KenD
1
0
On Thu, Dec 17, 2015 at 1:43 AM, Ben Coman <btc(a)openinworld.com> wrote:
> I'm having a go at getting this working with the Spur svn sources per...
> http://www.mirandabanda.org/cogblog/compiling-the-vm/
@Eliot,
I am currently stuck on Spur's requirement for mmap.
Could you describe this requirement and any ideas on path to proceed
to check compatibilty with these...
https://github.com/rumpkernel/wiki/wiki/Info:-FAQ
says "For simplicity reasons, the Rumprun unikernel does not support
virtual memory -- unnecessary in a unikernel -- nor does it support
signals the traditional way. That means that programs which absolutely
depend on things like fork(),execve(), mmap() and sigaction() may not
work correctly. In some cases we provide a small amount of cheap
emulation for common cases (e.g. mmap(MAP_ANON))"
http://rumpkernel.org/misc/usenix-login-2014/login_1410_03_kantee.pdf
says "The more or less only negative effect caused by the lack of
virtual memory support is that the mmap() system call cannot be fully
handled by a rump kernel. A number of workarounds are possible for
applications that absolutely need to use mmap(). For example, the
bozohttpd Web server uses mmap() to read the files it serves, so when
running bozohttpd on top of a rump kernel, we simply read the mmap’d
window into memory at the time the mapping is made instead of
gradually faulting pages in. A perfect emulation of mmap() is hard to
achieve, but one that works for most practical purposes is easy to
achieve"
cheers -ben
P.S. Here is the compilation error...
platforms/unix/vm/sqUnixSpurMemory.c:72:3: error: #error "Spur requires mmap"
# error "Spur requires mmap"
^
platforms/unix/vm/sqUnixSpurMemory.c: In function ‘sqAllocateMemory’:
platforms/unix/vm/sqUnixSpurMemory.c:108:47: warning: passing argument
3 of ‘sqAllocateMemorySegmentOfSizeAboveAllocatedSizeInto’ from
incompatible pointer type
(roundUpToPage(desiredHeapSize), address, &allocBytes);
^
In file included from platforms/unix/vm/sqUnixSpurMemory.c:33:0:
platforms/Cross/vm/sq.h:88:14: note: expected ‘sqInt *’ but argument
is of type ‘long unsigned int *’
extern void *sqAllocateMemorySegmentOfSizeAboveAllocatedSizeInto(sqInt
sz, void *minAddr, sqInt *asp);
^
Makefile:276: recipe for target 'sqUnixSpurMemory.o' failed
make[1]: *** [sqUnixSpurMemory.o] Error 1
Makefile:407: recipe for target 'vm/vm.a' failed
make: *** [vm/vm.a] Error 2
4
9
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1611.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1611
Author: eem
Time: 24 December 2015, 2:14:20.511 pm
UUID: 854947cd-58c3-4c34-a8cc-bf673b67983c
Ancestors: VMMaker.oscog-eem.1610
x64 Cogit:
Implement machine code SmallFloat primitives. Fix conversion bug in maybeGenConvertIfSmallFloatIn:... (fix refactored into genGetSmallFloatValueOf:scratch:into:).
Streamline genJumpNotSmallFloatValueBits:scratch:'s isolation of the exponent.
Slang:
Allow the Cogit's primitive table to reference optional primitives (since SmallFloat prims are <option: #Spur64BitMemoryManager>.
Simulator:
Reimplement the brakpoint machinery in an OO manner, allowing multiple breakpoints and deleting all breakpoints.
=============== Diff against VMMaker.oscog-eem.1610 ===============
Item was added:
+ ----- Method: Array>>addBreakpoint: (in category '*VMMaker-interpreter simulator') -----
+ addBreakpoint: address
+ ^self, {address}!
Item was added:
+ ----- Method: Array>>isActiveBreakpoint (in category '*VMMaker-interpreter simulator') -----
+ isActiveBreakpoint
+ ^self size > 0!
Item was added:
+ ----- Method: Array>>isBreakpointFor: (in category '*VMMaker-interpreter simulator') -----
+ isBreakpointFor: address
+ 1 to: self size do:
+ [:i| (self at: i) = address ifTrue: [^true]].
+ ^false!
Item was added:
+ ----- Method: Array>>menuPrompt (in category '*VMMaker-interpreter simulator') -----
+ menuPrompt
+ ^String streamContents:
+ [:s|
+ s space; nextPut: $(.
+ self do: [:address| s nextPutAll: address hex]
+ separatedBy: [s space].
+ s nextPut: $)]!
Item was added:
+ ----- Method: Array>>removeBreakpoint: (in category '*VMMaker-interpreter simulator') -----
+ removeBreakpoint: address
+ ^(self copyWithout: address) ifEmpty: nil!
Item was added:
+ ----- Method: Array>>singleStepRequiredToTriggerIn: (in category '*VMMaker-interpreter simulator') -----
+ singleStepRequiredToTriggerIn: aCogit
+ ^self anySatisfy: [:address| address between: aCogit cogCodeBase and: aCogit methodZone limitZony]!
Item was added:
+ ----- Method: BlockClosure>>shouldStopIfAtPC: (in category '*VMMaker-interpreter simulator') -----
+ shouldStopIfAtPC: address
+ <primitive: 202>
+ ^self value: address!
Item was added:
+ ----- Method: Boolean>>isBreakpointFor: (in category '*VMMaker-interpreter simulator') -----
+ isBreakpointFor: address
+ ^self!
Item was added:
+ ----- Method: Boolean>>menuPrompt (in category '*VMMaker-interpreter simulator') -----
+ menuPrompt
+ ^' (CLICK STEPPING!!!!)'!
Item was added:
+ ----- Method: Boolean>>shouldStopIfAtPC: (in category '*VMMaker-interpreter simulator') -----
+ shouldStopIfAtPC: address
+ ^self!
Item was added:
+ ----- Method: CogObjectRepresentation class>>wordSize (in category 'accessing') -----
+ wordSize
+ ^4!
Item was changed:
----- Method: CogObjectRepresentationFor32BitSpur>>branchIf:hasNotImmediateTag:target: (in category 'sista support') -----
branchIf: reg hasNotImmediateTag: classIndex target: targetFixUp
+ <var: #targetFixUp type: #'AbstractInstruction *'>
| jmpImmediate|
<inline: true>
- <var: #targetFixUp type: #'AbstractInstruction *'>
cogit MoveR: reg R: TempReg.
classIndex = objectMemory smallIntegerTag ifTrue:
[jmpImmediate := self genJumpNotSmallIntegerInScratchReg: TempReg].
classIndex = objectMemory characterTag ifTrue:
[jmpImmediate := self genJumpNotCharacterInScratchReg: TempReg].
jmpImmediate jmpTarget: targetFixUp!
Item was added:
+ ----- Method: CogObjectRepresentationFor64BitSpur class>>wordSize (in category 'accessing') -----
+ wordSize
+ ^8!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>branchIf:hasNotImmediateTag:target: (in category 'sista support') -----
branchIf: reg hasNotImmediateTag: classIndex target: targetFixUp
+ <var: #targetFixUp type: #'AbstractInstruction *'>
| jmpImmediate|
<inline: true>
cogit MoveR: reg R: TempReg.
classIndex = objectMemory smallIntegerTag ifTrue:
[jmpImmediate := self genJumpNotSmallIntegerInScratchReg: TempReg].
classIndex = objectMemory characterTag ifTrue:
[jmpImmediate := self genJumpNotCharacterInScratchReg: TempReg].
classIndex = objectMemory smallFloatTag ifTrue:
[jmpImmediate := self genJumpNotSmallFloatInScratchReg: TempReg].
jmpImmediate jmpTarget: targetFixUp!
Item was added:
+ ----- Method: CogObjectRepresentationFor64BitSpur>>genGetSmallFloatValueOf:scratch:into: (in category 'compile abstract instructions') -----
+ genGetSmallFloatValueOf: oopReg scratch: scratch into: dpReg
+ "Convert the SmallFloat oop in ooppReg into the corresponding float value in dpReg.
+ c.f. Spur64BitMemoryManager>>smallFloatBitsOf:"
+ | jumpSFZero |
+ <var: 'jumpSFZero' type: #'AbstractInstruction *'>
+ cogit
+ MoveR: oopReg R: scratch;
+ LogicalShiftRightCq: objectMemory numTagBits R: scratch;
+ CmpCq: 1 R: scratch.
+ jumpSFZero := cogit JumpLessOrEqual: 0.
+ cogit AddCq: objectMemory smallFloatExponentOffset << (objectMemory smallFloatMantissaBits + 1) R: scratch.
+ jumpSFZero jmpTarget: (cogit RotateRightCq: 1 R: scratch).
+ cogit MoveR: scratch Rd: dpReg.
+ ^0!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>genJumpNotSmallFloatValueBits:scratch: (in category 'compile abstract instructions') -----
genJumpNotSmallFloatValueBits: reg scratch: exponent
"Generate a test to check that the integer register contains a floating point value within the SmallFloat64 range,
and answer the jump. c.f. Spur64BitMemoryManager>>isSmallFloatValue:"
| jumpFail jumpTest jumpMinExponent jumpMaxExponent jumpZeroMantissa |
<var: #jumpFail type: #'AbstractInstruction *'>
<var: #jumpTest type: #'AbstractInstruction *'>
<var: #jumpMinExponent type: #'AbstractInstruction *'>
<var: #jumpMaxExponent type: #'AbstractInstruction *'>
<var: #jumpZeroMantissa type: #'AbstractInstruction *'>
+ self flag: 'if we combine the exponent range test with the conversion to tagged representation we test for a zero exponent only once. further, if we extract tags once into a scratch on the input side we test for immediates, SmallInteger and SmallFloat using the same intermediate result. so to do is to move fp arithmetic into the object representations'.
+ cogit MoveR: reg R: exponent.
+ true
+ ifTrue: [cogit
+ LogicalShiftLeftCq: 1 R: exponent; "drop sign"
+ LogicalShiftRightCq: objectMemory smallFloatMantissaBits + 1 R: exponent] "shift exponent down"
+ ifFalse: [cogit
+ LogicalShiftRightCq: objectMemory smallFloatMantissaBits R: exponent;
+ AndCq: 16r7FF R: exponent]. "ieee double precision mantissa is 11 bits"
+ cogit CmpCq: objectMemory smallFloatExponentOffset R: exponent.
- cogit MoveR: reg R: exponent;
- LogicalShiftRightCq: objectMemory smallFloatMantissaBits R: exponent;
- AndCq: 16r7FF R: exponent; "ieee double precision mantissa is 11 bits"
- CmpCq: objectMemory smallFloatExponentOffset R: exponent.
jumpMinExponent := cogit JumpLessOrEqual: 0.
cogit CmpCq: 255 + objectMemory smallFloatExponentOffset R: exponent. "SmallFloat exponent is 8 bits"
jumpMaxExponent := cogit JumpLessOrEqual: 0.
jumpFail :=
cogit Jump: 0.
jumpMinExponent jmpTarget:
(cogit TstCq: 1 << objectMemory smallFloatMantissaBits - 1 R: reg). "test mantissa bits"
jumpZeroMantissa := cogit JumpZero: 0.
cogit CmpCq: objectMemory smallFloatExponentOffset R: exponent.
jumpTest :=
cogit Jump: 0.
jumpZeroMantissa jmpTarget:
(cogit CmpCq: 0 R: exponent).
jumpTest jmpTarget:
(cogit JumpNonZero: jumpFail).
jumpMaxExponent jmpTarget: cogit Label.
^jumpFail!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>genJumpNotSmallInteger:scratchReg: (in category 'compile abstract instructions') -----
genJumpNotSmallInteger: reg scratchReg: scratch
"Generate a compare and branch to test if aRegister contains other than a SmallInteger.
Answer the jump. Override since scratch is needed."
- <returnTypeC: #'AbstractInstruction *'>
^cogit
AndCq: objectMemory tagMask R: reg R: scratch;
CmpCq: objectMemory smallIntegerTag R: scratch;
JumpNonZero: 0!
Item was changed:
----- Method: CogObjectRepresentationFor64BitSpur>>maybeGenConvertIfSmallFloatIn:scratchReg:into:andJumpTo: (in category 'primitive generators') -----
maybeGenConvertIfSmallFloatIn: oopReg scratchReg: scratch into: dpReg andJumpTo: targetInst
+ "Generate a test for a smallFloat in oopReg, converting it to the float value in dpReg
+ and jumping to targetInst. If oopReg does not contain a SmallFloat, fall through."
- "Generate a test for a smallFloat in oopReg, converting it to the float value in dpReg and jumping to targetInst.
- c.f. Spur64BitMemoryManager>>smallFloatBitsOf:"
<var: 'targetInst' type: #'AbstractInstruction *'>
+ | jumpNotSF |
- | jumpNotSF jumpSFZero |
<var: 'jumpNotSF' type: #'AbstractInstruction *'>
- <var: 'jumpSFZero' type: #'AbstractInstruction *'>
jumpNotSF := self genJumpNotSmallFloat: oopReg scratchReg: scratch.
+ self genGetSmallFloatValueOf: oopReg scratch: scratch into: dpReg.
+ cogit Jump: targetInst.
- cogit
- MoveR: oopReg R: scratch;
- LogicalShiftRightCq: objectMemory numTagBits R: scratch;
- CmpCq: 1 R: scratch.
- jumpSFZero := cogit JumpAbove: 0.
- cogit AddCq: objectMemory smallFloatExponentOffset << (objectMemory smallFloatMantissaBits + 1) R: scratch.
- jumpSFZero jmpTarget: (cogit RotateRightCq: 1 R: scratch).
- cogit
- MoveR: scratch Rd: dpReg;
- Jump: targetInst.
jumpNotSF jmpTarget: cogit Label.
^0!
Item was changed:
----- Method: CogVMSimulator>>utilitiesMenu: (in category 'UI') -----
utilitiesMenu: aMenuMorph
aMenuMorph
add: 'toggle transcript' action: #toggleTranscript;
add: 'clone VM' action: #cloneSimulationWindow;
addLine;
add: 'print ext head frame' action: #printExternalHeadFrame;
add: 'print int head frame' action: #printHeadFrame;
add: 'print mc/cog frame' action: [self printFrame: cogit processor fp WithSP: cogit processor sp];
add: 'short print ext frame & callers' action: [self shortPrintFrameAndCallers: framePointer];
add: 'short print int frame & callers' action: [self shortPrintFrameAndCallers: localFP];
add: 'short print mc/cog frame & callers' action: [self shortPrintFrameAndCallers: cogit processor fp];
add: 'long print ext frame & callers' action: [self printFrameAndCallers: framePointer SP: stackPointer];
add: 'long print int frame & callers' action: [self printFrameAndCallers: localFP SP: localSP];
add: 'long print mc/cog frame & callers' action: [self printFrameAndCallers: cogit processor fp SP: cogit processor sp];
add: 'print frame...' action: [(self promptHex: 'print frame') ifNotNil: [:fp| self printFrame: fp]];
add: 'print call stack' action: #printCallStack;
add: 'print stack call stack' action: #printStackCallStack;
add: 'print stack call stack of...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printStackCallStackOf: fp]];
add: 'print call stack of...' action: [(self promptHex: 'context or process oop') ifNotNil: [:obj| self printCallStackOf: obj]];
add: 'print call stack of frame...' action: [(self promptHex: 'frame') ifNotNil: [:fp| self printCallStackFP: fp]];
add: 'print all stacks' action: #printAllStacks;
add: 'write back local ptrs' action: [stackPointer := localSP. framePointer := localFP. instructionPointer := localIP.
self writeBackHeadFramePointers];
add: 'write back mc ptrs' action: [stackPointer := cogit processor sp. framePointer := cogit processor fp. instructionPointer := cogit processor eip.
self writeBackHeadFramePointers];
addLine;
add: 'print rump C stack' action: [objectMemory printMemoryFrom: cogit processor sp to: cogit getCStackPointer];
add: 'print registers' action: [cogit processor printRegistersOn: transcript];
add: 'print register map' action: [cogit printRegisterMapOn: transcript];
add: 'disassemble method/trampoline...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit disassembleCodeAt: pc]];
add: 'disassemble method/trampoline at pc' action:
[cogit disassembleCodeAt: (((cogit codeEntryFor: cogit processor pc) isNil
and: [(cogit methodZone methodFor: cogit processor pc) = 0])
ifTrue: [instructionPointer]
ifFalse: [cogit processor pc])];
add: 'disassemble ext head frame method' action: [cogit disassembleMethod: (self frameMethod: framePointer)];
add: 'print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self printOop: oop]];
add: 'long print oop...' action: [(self promptHex: 'print oop') ifNotNil: [:oop| self longPrintOop: oop]];
add: 'print context...' action: [(self promptHex: 'print context') ifNotNil: [:oop| self printContext: oop]];
addLine;
add: 'inspect object memory' target: objectMemory action: #inspect;
add: 'run leak checker' action: [Cursor execute showWhile: [self runLeakChecker]];
add: 'inspect cointerpreter' action: #inspect;
add: 'inspect cogit' target: cogit action: #inspect;
add: 'inspect method zone' target: cogit methodZone action: #inspect.
self isThreadedVM ifTrue:
[aMenuMorph add: 'inspect thread manager' target: self threadManager action: #inspect].
aMenuMorph
addLine;
add: 'print cog methods' target: cogMethodZone action: #printCogMethods;
add: 'print cog methods with prim...' action: [(self promptNum: 'prim index') ifNotNil: [:pix| cogMethodZone printCogMethodsWithPrimitive: pix]];
add: 'print cog methods with selector...' action:
[|s| s := UIManager default request: 'selector'.
s notEmpty ifTrue:
[s = 'nil' ifTrue: [s := nil].
cogMethodZone methodsDo:
[:m|
(s ifNil: [m selector = objectMemory nilObject]
ifNotNil: [(objectMemory numBytesOf: m selector) = s size
and: [(self str: s
n: (m selector + objectMemory baseHeaderSize)
cmp: (objectMemory numBytesOf: m selector)) = 0]]) ifTrue:
[cogit printCogMethod: m]]]];
add: 'print cog method for...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit printCogMethodFor: pc]];
add: 'print cog method header for...' action: [(self promptHex: 'pc') ifNotNil: [:pc| cogit printCogMethodHeaderFor: pc]];
add: 'print trampoline table' target: cogit action: #printTrampolineTable;
add: 'print prim trace log' action: #dumpPrimTraceLog;
add: 'report recent instructions' target: cogit action: #reportLastNInstructions;
+ add: 'set break pc', cogit breakPC menuPrompt, '...-ve to disable or remove' action: [cogit promptForBreakPC];
- add: 'set break pc (', (cogit breakPC isInteger ifTrue: [cogit breakPC hex] ifFalse: [cogit breakPC printString]), ')...-ve to disable' action: [(self promptHex: 'break pc') ifNotNil: [:bpc| cogit breakPC: (bpc >= 0 ifTrue: [bpc])]];
add: (cogit singleStep
ifTrue: ['no single step']
ifFalse: ['single step'])
action: [cogit singleStep: cogit singleStep not];
add: (cogit printRegisters
ifTrue: ['no print registers each instruction']
ifFalse: ['print registers each instruction'])
action: [cogit printRegisters: cogit printRegisters not];
add: (cogit printInstructions
ifTrue: ['no print instructions each instruction']
ifFalse: ['print instructions each instruction'])
action: [cogit printInstructions: cogit printInstructions not];
addLine;
add: 'click step' action: [cogit setClickStepBreakBlock];
add: 'set break count...' action: [|s| s := UIManager default request: 'break count (dec)'.
s notEmpty ifTrue: [breakCount := Integer readFrom: s readStream]];
add: 'set break selector...' action: [|s| s := UIManager default request: 'break selector'.
s notEmpty ifTrue: [self setBreakSelector: s]];
add: 'set break block...' action: [|s| s := UIManager default request: 'break block' initialAnswer: '[:theCogit| false]'.
s notEmpty ifTrue: [self setBreakBlockFromString: s]];
add: 'set cogit break method...' action: [(self promptHex: 'cogit breakMethod') ifNotNil: [:bm| cogit setBreakMethod: bm]];
add: (printBytecodeAtEachStep
ifTrue: ['no print bytecode each bytecode']
ifFalse: ['print bytecode each bytecode'])
action: [self ensureDebugAtEachStepBlock.
printBytecodeAtEachStep := printBytecodeAtEachStep not];
add: (printFrameAtEachStep
ifTrue: ['no print frame each bytecode']
ifFalse: ['print frame each bytecode'])
action: [self ensureDebugAtEachStepBlock.
printFrameAtEachStep := printFrameAtEachStep not].
^aMenuMorph!
Item was changed:
----- Method: CogX64Compiler>>hasDoublePrecisionFloatingPointSupport (in category 'testing') -----
hasDoublePrecisionFloatingPointSupport
+ <inline: true>
^true!
Item was changed:
----- Method: Cogit class>>table:from: (in category 'class initialization') -----
table: primArray from: specArray
"Fill in the specified entries in the primitive table."
specArray do:
+ [:spec |
+ (self shouldIncludeMethodForSelector: spec second) ifTrue:
+ [(primArray at: spec first put: CogPrimitiveDescriptor new)
+ primitiveGenerator: spec second;
+ primNumArgs: (spec at: 3 ifAbsent: -1);
+ enabled: (spec at: 4 ifAbsent: nil)]].
- [:spec | | descriptor |
- (primArray at: spec first put: CogPrimitiveDescriptor new)
- primitiveGenerator: spec second;
- primNumArgs: (spec at: 3 ifAbsent: -1);
- enabled: (spec at: 4 ifAbsent: nil)].
primArray object withIndexDo:
[:generator :i|
generator ifNil:
[(primArray object at: i put: CogPrimitiveDescriptor new)
primNumArgs: -1]]!
Item was added:
+ ----- Method: Cogit>>breakAt: (in category 'simulation only') -----
+ breakAt: address
+ ((breakPC isBreakpointFor: address)
+ and: [breakBlock shouldStopIfAtPC: address]) ifTrue:
+ [coInterpreter changed: #byteCountText.
+ self halt: 'machine code breakpoint at ', address]!
Item was changed:
----- Method: Cogit>>breakBlock: (in category 'simulation only') -----
breakBlock: aBlock
<doNotGenerate>
+ breakBlock := aBlock.
+ singleStep := singleStep or: [breakPC singleStepRequiredToTriggerIn: self]!
- breakBlock := aBlock!
Item was changed:
----- Method: Cogit>>breakPC: (in category 'simulation only') -----
+ breakPC: anAddressArrayOrNil
- breakPC: anAddress
<doNotGenerate>
+ breakPC := anAddressArrayOrNil.
+ singleStep := singleStep or: [anAddressArrayOrNil singleStepRequiredToTriggerIn: self]!
- breakPC := anAddress.
- (breakPC isInteger
- and: [anAddress between: codeBase and: coInterpreter heapBase]) ifTrue:
- [singleStep := true].
- "If there's a breakPC then it is anded with breakBlock's result, so the breakBlock must default to true.
- If there's no breakPC the break block is used on its own and so must befault to false."
- (breakBlock isNil
- or: [breakBlock method = thisContext method]) ifTrue:
- [breakBlock := breakPC isInteger
- ifTrue: [[:cogit| processor pc = breakPC]]
- ifFalse: [[:cogit| false]]]!
Item was changed:
----- Method: Cogit>>fillInCPICHeader:numArgs:numCases:hasMNUCase:selector: (in category 'generate machine code') -----
fillInCPICHeader: pic numArgs: numArgs numCases: numCases hasMNUCase: hasMNUCase selector: selector
<returnTypeC: #'CogMethod *'>
<var: #pic type: #'CogMethod *'>
<inline: true>
self assert: (objectMemory isYoung: selector) not.
pic cmType: CMClosedPIC.
pic objectHeader: 0.
pic blockSize: closedPICSize.
pic methodObject: 0.
pic methodHeader: 0.
pic selector: selector.
pic cmNumArgs: numArgs.
pic cmRefersToYoung: false.
pic cmUsageCount: self initialClosedPICUsageCount.
pic cpicHasMNUCase: hasMNUCase.
pic cPICNumCases: numCases.
pic blockEntryOffset: 0.
self assert: pic cmType = CMClosedPIC.
self assert: pic selector = selector.
self assert: pic cmNumArgs = numArgs.
self assert: pic cPICNumCases = numCases.
self assert: (backEnd callTargetFromReturnAddress: pic asInteger + missOffset) = (self picAbortTrampolineFor: numArgs).
self assert: closedPICSize = (methodZone roundUpLength: closedPICSize).
processor flushICacheFrom: pic asUnsignedInteger to: pic asUnsignedInteger + closedPICSize.
+ self maybeEnableSingleStep.
^pic!
Item was changed:
----- Method: Cogit>>fillInMethodHeader:size:selector: (in category 'generate machine code') -----
fillInMethodHeader: method size: size selector: selector
<returnTypeC: #'CogMethod *'>
<var: #method type: #'CogMethod *'>
| originalMethod rawHeader |
<var: #originalMethod type: #'CogMethod *'>
method cmType: CMMethod.
method objectHeader: objectMemory nullHeaderForMachineCodeMethod.
method blockSize: size.
method methodObject: methodObj.
rawHeader := coInterpreter rawHeaderOf: methodObj.
"If the method has already been cogged (e.g. Newspeak accessors) then
leave the original method attached to its cog method, but get the right header."
(coInterpreter isCogMethodReference: rawHeader)
ifTrue:
[originalMethod := self cCoerceSimple: rawHeader to: #'CogMethod *'.
self assert: originalMethod blockSize = size.
self assert: methodHeader = originalMethod methodHeader.
NewspeakVM ifTrue:
[methodZone addToUnpairedMethodList: method]]
ifFalse:
[coInterpreter rawHeaderOf: methodObj put: method asInteger.
NewspeakVM ifTrue:
[method nextMethodOrIRCs: theIRCs]].
method methodHeader: methodHeader.
method selector: selector.
method cmNumArgs: (coInterpreter argumentCountOfMethodHeader: methodHeader).
(method cmRefersToYoung: hasYoungReferent) ifTrue:
[methodZone addToYoungReferrers: method].
method cmUsageCount: self initialMethodUsageCount.
method cpicHasMNUCase: false.
method cmUsesPenultimateLit: maxLitIndex >= ((objectMemory literalCountOfMethodHeader: methodHeader) - 2).
method blockEntryOffset: (blockEntryLabel notNil
ifTrue: [blockEntryLabel address - method asInteger]
ifFalse: [0]).
"This can be an error check since a large stackCheckOffset is caused by compiling
a machine-code primitive, and hence depends on the Cogit, not the input method."
needsFrame ifTrue:
[stackCheckLabel address - method asInteger <= MaxStackCheckOffset ifFalse:
[self error: 'too much code for stack check offset']].
method stackCheckOffset: (needsFrame
ifTrue: [stackCheckLabel address - method asInteger]
ifFalse: [0]).
self assert: (backEnd callTargetFromReturnAddress: method asInteger + missOffset)
= (self methodAbortTrampolineFor: method cmNumArgs).
self assert: size = (methodZone roundUpLength: size).
processor flushICacheFrom: method asUnsignedInteger to: method asUnsignedInteger + size.
+ self maybeEnableSingleStep.
^method!
Item was changed:
----- Method: Cogit>>fillInOPICHeader:numArgs:selector: (in category 'generate machine code') -----
fillInOPICHeader: pic numArgs: numArgs selector: selector
<returnTypeC: #'CogMethod *'>
<var: #pic type: #'CogMethod *'>
<inline: true>
pic cmType: CMOpenPIC.
pic objectHeader: 0.
pic blockSize: openPICSize.
"pic methodObject: 0.""This is also the nextOpenPIC link so don't initialize it"
methodZone addToOpenPICList: pic.
pic methodHeader: 0.
pic selector: selector.
pic cmNumArgs: numArgs.
(pic cmRefersToYoung: (objectMemory isYoung: selector)) ifTrue:
[methodZone addToYoungReferrers: pic].
pic cmUsageCount: self initialOpenPICUsageCount.
pic cpicHasMNUCase: false.
pic cPICNumCases: 0.
pic blockEntryOffset: 0.
self assert: pic cmType = CMOpenPIC.
self assert: pic selector = selector.
self assert: pic cmNumArgs = numArgs.
self assert: (backEnd callTargetFromReturnAddress: pic asInteger + missOffset) = (self picAbortTrampolineFor: numArgs).
self assert: openPICSize = (methodZone roundUpLength: openPICSize).
processor flushICacheFrom: pic asUnsignedInteger to: pic asUnsignedInteger + openPICSize.
+ self maybeEnableSingleStep.
^pic!
Item was changed:
----- Method: Cogit>>generateInstructionsAt: (in category 'generate machine code') -----
generateInstructionsAt: eventualAbsoluteAddress
"Size pc-dependent instructions and assign eventual addresses to all instructions.
Answer the size of the code.
Compute forward branches based on virtual address (abstract code starts at 0),
assuming that any branches branched over are long.
Compute backward branches based on actual address.
Reuse the fixups array to record the pc-dependent instructions that need to have
their code generation postponed until after the others."
| absoluteAddress pcDependentIndex abstractInstruction fixup |
<var: #abstractInstruction type: #'AbstractInstruction *'>
<var: #fixup type: #'BytecodeFixup *'>
absoluteAddress := eventualAbsoluteAddress.
pcDependentIndex := 0.
0 to: opcodeIndex - 1 do:
[:i|
+ self maybeBreakAt: absoluteAddress.
- breakPC = absoluteAddress ifTrue:
- [self halt: 'breakPC reached in generateInstructionsAt:'].
abstractInstruction := self abstractInstructionAt: i.
abstractInstruction isPCDependent
ifTrue:
[abstractInstruction sizePCDependentInstructionAt: absoluteAddress.
fixup := self fixupAt: pcDependentIndex.
pcDependentIndex := pcDependentIndex + 1.
fixup instructionIndex: i.
absoluteAddress := absoluteAddress + abstractInstruction machineCodeSize]
ifFalse:
[absoluteAddress := abstractInstruction concretizeAt: absoluteAddress]].
0 to: pcDependentIndex - 1 do:
[:j|
fixup := self fixupAt: j.
abstractInstruction := self abstractInstructionAt: fixup instructionIndex.
+ self maybeBreakAt: abstractInstruction address.
- breakPC = absoluteAddress ifTrue:
- [self halt: 'breakPC reached in generateInstructionsAt:'].
abstractInstruction concretizeAt: abstractInstruction address].
- self cCode: ''
- inSmalltalk:
- [breakPC ifNotNil:
- [breakPC <= absoluteAddress ifTrue:
- [self singleStep: true]]].
^absoluteAddress - eventualAbsoluteAddress!
Item was added:
+ ----- Method: Cogit>>maybeBreakAt: (in category 'simulation only') -----
+ maybeBreakAt: address
+ ((breakPC isBreakpointFor: address)
+ and: [breakBlock shouldStopIfAtPC: address]) ifTrue:
+ [coInterpreter changed: #byteCountText.
+ self halt: 'machine code breakpoint at ', address hex, ' in ', thisContext sender selector]!
Item was added:
+ ----- Method: Cogit>>maybeEnableSingleStep (in category 'simulation only') -----
+ maybeEnableSingleStep
+ <inline: true>
+ self cCode: '' inSmalltalk:
+ [singleStep ifFalse: [singleStep := breakPC singleStepRequiredToTriggerIn: self]]!
Item was added:
+ ----- Method: Cogit>>promptForBreakPC (in category 'simulation only') -----
+ promptForBreakPC
+ <doNotGenerate>
+ | s first pc |
+ s := UIManager default request: 'Break pc (hex)'.
+ s := s withBlanksTrimmed.
+ s isEmpty ifTrue: [^self].
+ ('+-' includes: s first) ifTrue: [first := s first. s := s allButFirst].
+ (s isEmpty and: [first = $-]) ifTrue:
+ [^self breakPC: nil].
+ pc := (s includes: $r)
+ ifTrue:
+ [Number readFrom: s readStream]
+ ifFalse:
+ [(#('0x' '-0x') detect: [:prefix| s beginsWith: prefix] ifNone: []) ifNotNil:
+ [:prefix|
+ s := s allButFirst: prefix size.
+ prefix first = $- ifTrue: [s := '-', s]].
+ Integer readFrom: s readStream base: 16].
+ first = $+ ifTrue:
+ [^self breakPC: (breakPC addBreakpoint: pc)].
+ first = $- ifTrue:
+ [^self breakPC: (breakPC removeBreakpoint: pc)].
+ self breakPC: pc!
Item was changed:
----- Method: Cogit>>setClickStepBreakBlock (in category 'simulation only') -----
setClickStepBreakBlock
"Set the break block to present a confirmer, breaking if true, and restoring the previous break block.
If an open debugger on the receiver can be found, proceed it."
<doNotGenerate>
+ | previousBreakBlock previousBreakPC previousSingleStep |
+ (breakBlock isNil or: [breakBlock method ~~ thisContext method]) ifTrue:
+ [previousBreakBlock := breakBlock.
+ previousBreakPC := breakPC.
+ previousSingleStep := singleStep.
+ breakBlock := [:ign|
+ (processor pc ~= previousBreakPC
+ and: [UIManager confirm: 'step?'])
+ ifTrue: [false]
+ ifFalse: [breakBlock := previousBreakBlock.
+ breakPC := previousBreakPC.
+ singleStep := previousSingleStep.
+ true]].
+ singleStep := breakPC := true].
- | previousBreakBlock previousBreakPC |
- previousBreakBlock := breakBlock.
- previousBreakPC := breakPC.
- breakBlock := [:ign|
- (processor pc ~= previousBreakPC
- and: [UIManager confirm: 'step?'])
- ifTrue: [false]
- ifFalse: [breakBlock := previousBreakBlock.
- breakPC := previousBreakPC.
- true]].
- singleStep := true.
- breakPC := nil.
(World submorphs
detect:
[:m|
m model class == Debugger
and: [(m model interruptedProcess suspendedContext findContextSuchThat:
[:ctxt|
ctxt receiver == self
and: [ctxt selector == #simulateCogCodeAt:]]) notNil]]
ifNone: []) ifNotNil:
[:debuggerWindow|
WorldState addDeferredUIMessage:
[debuggerWindow model proceed]]!
Item was changed:
----- Method: Cogit>>setInterpreter: (in category 'initialization') -----
setInterpreter: aCoInterpreter
"Initialization of the code generator in the simulator.
These objects already exist in the generated C VM
or are used only in the simulation."
<doNotGenerate>
coInterpreter := aCoInterpreter.
objectMemory := aCoInterpreter objectMemory.
threadManager := aCoInterpreter threadManager. "N.B. may be nil"
methodZone := CogMethodZone new.
objectRepresentation := objectMemory objectRepresentationClass
forCogit: self methodZone: methodZone.
methodZone setInterpreter: aCoInterpreter
objectRepresentation: objectRepresentation
cogit: self.
generatorTable := self class generatorTable.
primitiveGeneratorTable := self class primitiveTable.
processor := ProcessorClass new.
simulatedAddresses := Dictionary new.
simulatedTrampolines := Dictionary new.
simulatedVariableGetters := Dictionary new.
simulatedVariableSetters := Dictionary new.
traceStores := 0.
traceFlags := (self class initializationOptions at: #recordPrimTrace ifAbsent: [true])
ifTrue: [8] "record prim trace on by default (see Cogit class>>decareCVarsIn:)"
ifFalse: [0].
debugPrimCallStackOffset := 0.
singleStep := printRegisters := printInstructions := clickConfirm := false.
- breakBlock ifNil: [self breakPC: breakPC].
backEnd := CogCompilerClass for: self.
methodLabel := CogCompilerClass for: self.
(literalsManager := backEnd class literalsManagerClass new) cogit: self.
ordinarySendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
superSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
BytecodeSetHasDirectedSuperSend ifTrue:
[directedSuperSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines)].
NewspeakVM ifTrue:
[selfSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
dynamicSuperSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
implicitReceiverSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines).
outerSendTrampolines := CArrayAccessor on: (Array new: NumSendTrampolines)].
"debug metadata"
objectReferencesInRuntime := CArrayAccessor on: (Array new: NumObjRefsInRuntime).
runtimeObjectRefIndex := 0.
"debug metadata"
trampolineAddresses := CArrayAccessor on: (Array new: NumTrampolines * 2).
trampolineTableIndex := 0.
extA := extB := 0.
compilationTrace ifNil: [compilationTrace := self class initializationOptions at: #compilationTrace ifAbsent: [0]].
debugOpcodeIndices := self class initializationOptions at: #debugOpcodeIndices ifAbsent: [Set new].!
Item was changed:
----- Method: Cogit>>simulateCogCodeAt: (in category 'simulation only') -----
simulateCogCodeAt: address "<Integer>"
<doNotGenerate>
| stackZoneBase |
stackZoneBase := coInterpreter stackZoneBase.
processor pc: address.
+ [[[singleStep
+ ifTrue:
+ [[processor sp < stackZoneBase ifTrue: [self halt].
+ self recordProcessing.
+ self maybeBreakAt: processor pc] value. "So that the Debugger's Over steps over all this"
+ processor
- [[[singleStep ifTrue:
- [[processor sp < stackZoneBase ifTrue: [self halt].
- self recordProcessing.
- (breakPC isInteger
- ifTrue:
- [processor pc = breakPC
- and: [breakBlock value: self]]
- ifFalse:
- [breakBlock value: self]) ifTrue:
- ["printRegisters := printInstructions := true"
- "self reportLastNInstructions"
- "coInterpreter printExternalHeadFrame"
- "coInterpreter printFrameAndCallers: coInterpreter framePointer SP: coInterpreter stackPointer"
- "coInterpreter shortPrintFrameAndCallers: coInterpreter framePointer"
- "coInterpreter printFrame: processor fp WithSP: processor sp"
- "coInterpreter printFrameAndCallers: processor fp SP: processor sp"
- "coInterpreter shortPrintFrameAndCallers: processor fp"
- "self disassembleMethodFor: processor pc"
- coInterpreter changed: #byteCountText.
- self halt: 'machine code breakpoint at ', processor pc hex]] value]. "So that the Debugger's Over steps over all this"
- singleStep
- ifTrue: [processor
singleStepIn: coInterpreter memory
minimumAddress: guardPageSize
readOnlyBelow: methodZone zoneEnd]
+ ifFalse:
+ [processor
- ifFalse: [processor
runInMemory: coInterpreter memory
minimumAddress: guardPageSize
readOnlyBelow: methodZone zoneEnd].
((printRegisters or: [printInstructions]) and: [clickConfirm]) ifTrue:
[(self confirm: 'continue?') ifFalse:
[self halt]].
true] whileTrue]
on: ProcessorSimulationTrap
do: [:ex| self handleSimulationTrap: ex].
true] whileTrue!
Item was added:
+ ----- Method: Integer>>addBreakpoint: (in category '*VMMaker-interpreter simulator') -----
+ addBreakpoint: address
+ ^{self. address}!
Item was added:
+ ----- Method: Integer>>isActiveBreakpoint (in category '*VMMaker-interpreter simulator') -----
+ isActiveBreakpoint
+ ^true!
Item was added:
+ ----- Method: Integer>>isBreakpointFor: (in category '*VMMaker-interpreter simulator') -----
+ isBreakpointFor: address
+ ^self = address!
Item was added:
+ ----- Method: Integer>>menuPrompt (in category '*VMMaker-interpreter simulator') -----
+ menuPrompt
+ ^' (', self hex, ')'!
Item was added:
+ ----- Method: Integer>>removeBreakpoint: (in category '*VMMaker-interpreter simulator') -----
+ removeBreakpoint: address
+ ^nil!
Item was added:
+ ----- Method: Integer>>singleStepRequiredToTriggerIn: (in category '*VMMaker-interpreter simulator') -----
+ singleStepRequiredToTriggerIn: aCogit
+ ^self between: aCogit cogCodeBase and: aCogit methodZone limitZony!
Item was changed:
----- Method: SimpleStackBasedCogit class>>initializePrimitiveTableForNewsqueak (in category 'class initialization') -----
initializePrimitiveTableForNewsqueak
"Initialize the table of primitive generators. This does not include normal primitives implemented in the coInterpreter.
N.B. primitives that don't have an explicit arg count (the integer following the generator) may be variadic."
"SimpleStackBasedCogit initializePrimitiveTableForSqueakV3"
+ MaxCompiledPrimitiveIndex := self objectRepresentationClass wordSize = 8
+ ifTrue: [555]
+ ifFalse: [222].
- MaxCompiledPrimitiveIndex := 222.
primitiveTable := CArrayAccessor on: (Array new: MaxCompiledPrimitiveIndex + 1).
self table: primitiveTable from:
#( "Integer Primitives (0-19)"
(1 genPrimitiveAdd 1 mclassIsSmallInteger:)
(2 genPrimitiveSubtract 1 mclassIsSmallInteger:)
(3 genPrimitiveLessThan 1 mclassIsSmallInteger:)
(4 genPrimitiveGreaterThan 1 mclassIsSmallInteger:)
(5 genPrimitiveLessOrEqual 1 mclassIsSmallInteger:)
(6 genPrimitiveGreaterOrEqual 1 mclassIsSmallInteger:)
(7 genPrimitiveEqual 1 mclassIsSmallInteger:)
(8 genPrimitiveNotEqual 1 mclassIsSmallInteger:)
(9 genPrimitiveMultiply 1 processorHasMultiplyAndMClassIsSmallInteger:)
(10 genPrimitiveDivide 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(11 genPrimitiveMod 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(12 genPrimitiveDiv 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(13 genPrimitiveQuo 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(14 genPrimitiveBitAnd 1 mclassIsSmallInteger:)
(15 genPrimitiveBitOr 1 mclassIsSmallInteger:)
(16 genPrimitiveBitXor 1 mclassIsSmallInteger:)
(17 genPrimitiveBitShift 1 mclassIsSmallInteger:)
"(18 primitiveMakePoint)"
"(19 primitiveFail)" "Guard primitive for simulation -- *must* fail"
"LargeInteger Primitives (20-39)"
"(20 primitiveFail)"
"(21 primitiveAddLargeIntegers)"
"(22 primitiveSubtractLargeIntegers)"
"(23 primitiveLessThanLargeIntegers)"
"(24 primitiveGreaterThanLargeIntegers)"
"(25 primitiveLessOrEqualLargeIntegers)"
"(26 primitiveGreaterOrEqualLargeIntegers)"
"(27 primitiveEqualLargeIntegers)"
"(28 primitiveNotEqualLargeIntegers)"
"(29 primitiveMultiplyLargeIntegers)"
"(30 primitiveDivideLargeIntegers)"
"(31 primitiveModLargeIntegers)"
"(32 primitiveDivLargeIntegers)"
"(33 primitiveQuoLargeIntegers)"
"(34 primitiveBitAndLargeIntegers)"
"(35 primitiveBitOrLargeIntegers)"
"(36 primitiveBitXorLargeIntegers)"
"(37 primitiveBitShiftLargeIntegers)"
"Float Primitives (38-59)"
"(38 primitiveFloatAt)"
"(39 primitiveFloatAtPut)"
(40 genPrimitiveAsFloat 0 processorHasDoublePrecisionFloatingPointSupport:)
(41 genPrimitiveFloatAdd 1 processorHasDoublePrecisionFloatingPointSupport:)
(42 genPrimitiveFloatSubtract 1 processorHasDoublePrecisionFloatingPointSupport:)
(43 genPrimitiveFloatLessThan 1 processorHasDoublePrecisionFloatingPointSupport:)
(44 genPrimitiveFloatGreaterThan 1 processorHasDoublePrecisionFloatingPointSupport:)
(45 genPrimitiveFloatLessOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(46 genPrimitiveFloatGreaterOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(47 genPrimitiveFloatEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(48 genPrimitiveFloatNotEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(49 genPrimitiveFloatMultiply 1 processorHasDoublePrecisionFloatingPointSupport:)
(50 genPrimitiveFloatDivide 1 processorHasDoublePrecisionFloatingPointSupport:)
"(51 primitiveTruncated)"
"(52 primitiveFractionalPart)"
"(53 primitiveExponent)"
"(54 primitiveTimesTwoPower)"
(55 genPrimitiveFloatSquareRoot 0 processorHasDoublePrecisionFloatingPointSupport:)
"(56 primitiveSine)"
"(57 primitiveArctan)"
"(58 primitiveLogN)"
"(59 primitiveExp)"
"Subscript and Stream Primitives (60-67)"
(60 genPrimitiveAt 1)
(61 genPrimitiveAtPut 2)
(62 genPrimitiveSize 0)
(63 genPrimitiveStringAt 1)
(64 genPrimitiveStringAtPut 2)
"The stream primitives no longer pay their way; normal Smalltalk code is faster."
(65 genFastPrimFail)"was primitiveNext"
(66 genFastPrimFail) "was primitiveNextPut"
(67 genFastPrimFail) "was primitiveAtEnd"
"StorageManagement Primitives (68-79)"
(68 genPrimitiveObjectAt 1) "Good for debugger/InstructionStream performance"
"(69 primitiveObjectAtPut)"
(70 genPrimitiveNew) "For VMMirror support 1 argument instantiateFixedClass: as well as baiscNew"
(71 genPrimitiveNewWithArg) "For VMMirror support 2 argument instantiateVariableClass:withSize: as well as baiscNew:"
"(72 primitiveArrayBecomeOneWay)" "Blue Book: primitiveBecome"
"(73 primitiveInstVarAt)"
"(74 primitiveInstVarAtPut)"
(75 genPrimitiveIdentityHash 0)
"(76 primitiveStoreStackp)" "Blue Book: primitiveAsObject"
"(77 primitiveSomeInstance)"
"(78 primitiveNextInstance)"
(79 genPrimitiveNewMethod 2)
"Control Primitives (80-89)"
"(80 primitiveFail)" "Blue Book: primitiveBlockCopy"
"(81 primitiveFail)" "Blue Book: primitiveValue"
"(82 primitiveFail)" "Blue Book: primitiveValueWithArgs"
(83 genPrimitivePerform)
"(84 primitivePerformWithArgs)"
"(85 primitiveSignal)"
"(86 primitiveWait)"
"(87 primitiveResume)"
"(88 primitiveSuspend)"
"(89 primitiveFlushCache)"
"System Primitives (110-119)"
(110 genPrimitiveIdentical 1)
(111 genPrimitiveClass) "For objectClass: and VMMirror support 1 argument classOf: as well as class"
"(112 primitiveBytesLeft)"
"(113 primitiveQuit)"
"(114 primitiveExitToDebugger)"
"(115 primitiveChangeClass)" "Blue Book: primitiveOopsLeft"
"(116 primitiveFlushCacheByMethod)"
"(117 primitiveExternalCall)"
"(118 primitiveDoPrimitiveWithArgs)"
"(119 primitiveFlushCacheSelective)"
(169 genPrimitiveNotIdentical 1)
(170 genPrimitiveAsCharacter) "SmallInteger>>asCharacter, Character class>>value:"
(171 genPrimitiveCharacterValue 0) "Character>>value"
"(173 primitiveSlotAt 1)"
"(174 primitiveSlotAtPut 2)"
(175 genPrimitiveIdentityHash 0) "Behavior>>identityHash"
"Old closure primitives"
"(186 primitiveFail)" "was primitiveClosureValue"
"(187 primitiveFail)" "was primitiveClosureValueWithArgs"
"Perform method directly"
"(188 primitiveExecuteMethodArgsArray)"
"(189 primitiveExecuteMethod)"
"Unwind primitives"
"(195 primitiveFindNextUnwindContext)"
"(196 primitiveTerminateTo)"
"(197 primitiveFindHandlerContext)"
(198 genFastPrimFail "primitiveMarkUnwindMethod")
(199 genFastPrimFail "primitiveMarkHandlerMethod")
"new closure primitives"
"(200 primitiveClosureCopyWithCopiedValues)"
(201 genPrimitiveClosureValue 0) "value"
(202 genPrimitiveClosureValue 1) "value:"
(203 genPrimitiveClosureValue 2) "value:value:"
(204 genPrimitiveClosureValue 3) "value:value:value:"
(205 genPrimitiveClosureValue 4) "value:value:value:value:"
"(206 genPrimitiveClosureValueWithArgs)" "valueWithArguments:"
"(210 primitiveContextAt)"
"(211 primitiveContextAtPut)"
"(212 primitiveContextSize)"
"(218 primitiveDoNamedPrimitiveWithArgs)"
"(219 primitiveFail)" "reserved for Cog primitives"
"(220 primitiveFail)" "reserved for Cog primitives"
(221 genPrimitiveClosureValue 0) "valueNoContextSwitch"
(222 genPrimitiveClosureValue 1) "valueNoContextSwitch:"
+ "SmallFloat primitives (540-559)"
+ (541 genPrimitiveSmallFloatAdd 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (542 genPrimitiveSmallFloatSubtract 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (543 genPrimitiveSmallFloatLessThan 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (544 genPrimitiveSmallFloatGreaterThan 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (545 genPrimitiveSmallFloatLessOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (546 genPrimitiveSmallFloatGreaterOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (547 genPrimitiveSmallFloatEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (548 genPrimitiveSmallFloatNotEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (549 genPrimitiveSmallFloatMultiply 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (550 genPrimitiveSmallFloatDivide 1 processorHasDoublePrecisionFloatingPointSupport:)
+ "(551 genPrimitiveSmallFloatTruncated 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(552 genPrimitiveSmallFloatFractionalPart 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(553 genPrimitiveSmallFloatExponent 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(554 genPrimitiveSmallFloatTimesTwoPower 1 processorHasDoublePrecisionFloatingPointSupport:)"
+ (555 genPrimitiveSmallFloatSquareRoot 0 processorHasDoublePrecisionFloatingPointSupport:)
+ "(556 genPrimitiveSmallFloatSine 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(557 genPrimitiveSmallFloatArctan 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(558 genPrimitiveSmallFloatLogN 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(559 genPrimitiveSmallFloatExp 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(541 primitiveSmallFloatAdd 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(542 primitiveSmallFloatSubtract 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(543 primitiveSmallFloatLessThan 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(544 primitiveSmallFloatGreaterThan 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(545 primitiveSmallFloatLessOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(546 primitiveSmallFloatGreaterOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(547 primitiveSmallFloatEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(548 primitiveSmallFloatNotEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(549 primitiveSmallFloatMultiply 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(550 primitiveSmallFloatDivide 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(551 primitiveSmallFloatTruncated 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(552 primitiveSmallFloatFractionalPart 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(553 primitiveSmallFloatExponent 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(554 primitiveSmallFloatTimesTwoPower 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(555 primitiveSmallFloatSquareRoot 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(556 primitiveSmallFloatSine 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(557 primitiveSmallFloatArctan 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(558 primitiveSmallFloatLogN 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(559 primitiveSmallFloatExp 0 processorHasDoublePrecisionFloatingPointSupport:)"
)!
Item was changed:
----- Method: SimpleStackBasedCogit class>>initializePrimitiveTableForSqueak (in category 'class initialization') -----
initializePrimitiveTableForSqueak
"Initialize the table of primitive generators. This does not include normal primitives implemented in the coInterpreter.
N.B. primitives that don't have an explicit arg count (the integer following the generator) may be variadic."
"SimpleStackBasedCogit initializePrimitiveTableForSqueak"
+ MaxCompiledPrimitiveIndex := self objectRepresentationClass wordSize = 8
+ ifTrue: [555]
+ ifFalse: [222].
- MaxCompiledPrimitiveIndex := 222.
primitiveTable := CArrayAccessor on: (Array new: MaxCompiledPrimitiveIndex + 1).
self table: primitiveTable from:
#( "Integer Primitives (0-19)"
(1 genPrimitiveAdd 1 mclassIsSmallInteger:)
(2 genPrimitiveSubtract 1 mclassIsSmallInteger:)
(3 genPrimitiveLessThan 1 mclassIsSmallInteger:)
(4 genPrimitiveGreaterThan 1 mclassIsSmallInteger:)
(5 genPrimitiveLessOrEqual 1 mclassIsSmallInteger:)
(6 genPrimitiveGreaterOrEqual 1 mclassIsSmallInteger:)
(7 genPrimitiveEqual 1 mclassIsSmallInteger:)
(8 genPrimitiveNotEqual 1 mclassIsSmallInteger:)
(9 genPrimitiveMultiply 1 processorHasMultiplyAndMClassIsSmallInteger:)
(10 genPrimitiveDivide 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(11 genPrimitiveMod 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(12 genPrimitiveDiv 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(13 genPrimitiveQuo 1 processorHasDivQuoRemAndMClassIsSmallInteger:)
(14 genPrimitiveBitAnd 1 mclassIsSmallInteger:)
(15 genPrimitiveBitOr 1 mclassIsSmallInteger:)
(16 genPrimitiveBitXor 1 mclassIsSmallInteger:)
(17 genPrimitiveBitShift 1 mclassIsSmallInteger:)
"(18 primitiveMakePoint)"
"(19 primitiveFail)" "Guard primitive for simulation -- *must* fail"
"LargeInteger Primitives (20-39)"
"(20 primitiveFail)"
"(21 primitiveAddLargeIntegers)"
"(22 primitiveSubtractLargeIntegers)"
"(23 primitiveLessThanLargeIntegers)"
"(24 primitiveGreaterThanLargeIntegers)"
"(25 primitiveLessOrEqualLargeIntegers)"
"(26 primitiveGreaterOrEqualLargeIntegers)"
"(27 primitiveEqualLargeIntegers)"
"(28 primitiveNotEqualLargeIntegers)"
"(29 primitiveMultiplyLargeIntegers)"
"(30 primitiveDivideLargeIntegers)"
"(31 primitiveModLargeIntegers)"
"(32 primitiveDivLargeIntegers)"
"(33 primitiveQuoLargeIntegers)"
"(34 primitiveBitAndLargeIntegers)"
"(35 primitiveBitOrLargeIntegers)"
"(36 primitiveBitXorLargeIntegers)"
"(37 primitiveBitShiftLargeIntegers)"
"Float Primitives (38-59)"
+ "(38 genPrimitiveFloatAt)"
+ "(39 genPrimitiveFloatAtPut)"
- "(38 primitiveFloatAt)"
- "(39 primitiveFloatAtPut)"
(40 genPrimitiveAsFloat 0 processorHasDoublePrecisionFloatingPointSupport:)
(41 genPrimitiveFloatAdd 1 processorHasDoublePrecisionFloatingPointSupport:)
(42 genPrimitiveFloatSubtract 1 processorHasDoublePrecisionFloatingPointSupport:)
(43 genPrimitiveFloatLessThan 1 processorHasDoublePrecisionFloatingPointSupport:)
(44 genPrimitiveFloatGreaterThan 1 processorHasDoublePrecisionFloatingPointSupport:)
(45 genPrimitiveFloatLessOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(46 genPrimitiveFloatGreaterOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(47 genPrimitiveFloatEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(48 genPrimitiveFloatNotEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
(49 genPrimitiveFloatMultiply 1 processorHasDoublePrecisionFloatingPointSupport:)
(50 genPrimitiveFloatDivide 1 processorHasDoublePrecisionFloatingPointSupport:)
+ "(51 genPrimitiveTruncated)"
+ "(52 genPrimitiveFractionalPart)"
+ "(53 genPrimitiveExponent)"
+ "(54 genPrimitiveTimesTwoPower)"
- "(51 primitiveTruncated)"
- "(52 primitiveFractionalPart)"
- "(53 primitiveExponent)"
- "(54 primitiveTimesTwoPower)"
(55 genPrimitiveFloatSquareRoot 0 processorHasDoublePrecisionFloatingPointSupport:)
+ "(56 genPrimitiveSine)"
+ "(57 genPrimitiveArctan)"
+ "(58 genPrimitiveLogN)"
+ "(59 genPrimitiveExp)"
- "(56 primitiveSine)"
- "(57 primitiveArctan)"
- "(58 primitiveLogN)"
- "(59 primitiveExp)"
"Subscript and Stream Primitives (60-67)"
(60 genPrimitiveAt 1)
(61 genPrimitiveAtPut 2)
(62 genPrimitiveSize 0)
(63 genPrimitiveStringAt 1)
(64 genPrimitiveStringAtPut 2)
"The stream primitives no longer pay their way; normal Smalltalk code is faster."
(65 genFastPrimFail)"was primitiveNext"
(66 genFastPrimFail) "was primitiveNextPut"
(67 genFastPrimFail) "was primitiveAtEnd"
"StorageManagement Primitives (68-79)"
(68 genPrimitiveObjectAt 1) "Good for debugger/InstructionStream performance"
"(69 primitiveObjectAtPut)"
(70 genPrimitiveNew 0)
(71 genPrimitiveNewWithArg 1)
"(72 primitiveArrayBecomeOneWay)" "Blue Book: primitiveBecome"
"(73 primitiveInstVarAt)"
"(74 primitiveInstVarAtPut)"
(75 genPrimitiveIdentityHash 0)
"(76 primitiveStoreStackp)" "Blue Book: primitiveAsObject"
"(77 primitiveSomeInstance)"
"(78 primitiveNextInstance)"
(79 genPrimitiveNewMethod 2)
"Control Primitives (80-89)"
"(80 primitiveFail)" "Blue Book: primitiveBlockCopy"
"(81 primitiveFail)" "Blue Book: primitiveValue"
"(82 primitiveFail)" "Blue Book: primitiveValueWithArgs"
(83 genPrimitivePerform)
"(84 primitivePerformWithArgs)"
"(85 primitiveSignal)"
"(86 primitiveWait)"
"(87 primitiveResume)"
"(88 primitiveSuspend)"
"(89 primitiveFlushCache)"
"System Primitives (110-119)"
(110 genPrimitiveIdentical 1)
(111 genPrimitiveClass) "Support both class and Context>>objectClass:"
"(112 primitiveBytesLeft)"
"(113 primitiveQuit)"
"(114 primitiveExitToDebugger)"
"(115 primitiveChangeClass)" "Blue Book: primitiveOopsLeft"
"(116 primitiveFlushCacheByMethod)"
"(117 primitiveExternalCall)"
"(118 primitiveDoPrimitiveWithArgs)"
"(119 primitiveFlushCacheSelective)"
(169 genPrimitiveNotIdentical 1)
(170 genPrimitiveAsCharacter) "SmallInteger>>asCharacter, Character class>>value:"
(171 genPrimitiveCharacterValue 0) "Character>>value"
"(173 primitiveSlotAt 1)"
"(174 primitiveSlotAtPut 2)"
(175 genPrimitiveIdentityHash 0) "Behavior>>identityHash"
"Old closure primitives"
"(186 primitiveFail)" "was primitiveClosureValue"
"(187 primitiveFail)" "was primitiveClosureValueWithArgs"
"Perform method directly"
"(188 primitiveExecuteMethodArgsArray)"
"(189 primitiveExecuteMethod)"
"Unwind primitives"
"(195 primitiveFindNextUnwindContext)"
"(196 primitiveTerminateTo)"
"(197 primitiveFindHandlerContext)"
(198 genFastPrimFail "primitiveMarkUnwindMethod")
(199 genFastPrimFail "primitiveMarkHandlerMethod")
"new closure primitives"
"(200 primitiveClosureCopyWithCopiedValues)"
(201 genPrimitiveClosureValue 0) "value"
(202 genPrimitiveClosureValue 1) "value:"
(203 genPrimitiveClosureValue 2) "value:value:"
(204 genPrimitiveClosureValue 3) "value:value:value:"
(205 genPrimitiveClosureValue 4) "value:value:value:value:"
"(206 genPrimitiveClosureValueWithArgs)" "valueWithArguments:"
"(210 primitiveContextAt)"
"(211 primitiveContextAtPut)"
"(212 primitiveContextSize)"
"(218 primitiveDoNamedPrimitiveWithArgs)"
"(219 primitiveFail)" "reserved for Cog primitives"
"(220 primitiveFail)" "reserved for Cog primitives"
(221 genPrimitiveClosureValue 0) "valueNoContextSwitch"
(222 genPrimitiveClosureValue 1) "valueNoContextSwitch:"
+ "SmallFloat primitives (540-559)"
+ (541 genPrimitiveSmallFloatAdd 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (542 genPrimitiveSmallFloatSubtract 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (543 genPrimitiveSmallFloatLessThan 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (544 genPrimitiveSmallFloatGreaterThan 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (545 genPrimitiveSmallFloatLessOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (546 genPrimitiveSmallFloatGreaterOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (547 genPrimitiveSmallFloatEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (548 genPrimitiveSmallFloatNotEqual 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (549 genPrimitiveSmallFloatMultiply 1 processorHasDoublePrecisionFloatingPointSupport:)
+ (550 genPrimitiveSmallFloatDivide 1 processorHasDoublePrecisionFloatingPointSupport:)
+ "(551 genPrimitiveSmallFloatTruncated 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(552 genPrimitiveSmallFloatFractionalPart 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(553 genPrimitiveSmallFloatExponent 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(554 genPrimitiveSmallFloatTimesTwoPower 1 processorHasDoublePrecisionFloatingPointSupport:)"
+ (555 genPrimitiveSmallFloatSquareRoot 0 processorHasDoublePrecisionFloatingPointSupport:)
+ "(556 genPrimitiveSmallFloatSine 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(557 genPrimitiveSmallFloatArctan 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(558 genPrimitiveSmallFloatLogN 0 processorHasDoublePrecisionFloatingPointSupport:)"
+ "(559 genPrimitiveSmallFloatExp 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(541 primitiveSmallFloatAdd 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(542 primitiveSmallFloatSubtract 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(543 primitiveSmallFloatLessThan 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(544 primitiveSmallFloatGreaterThan 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(545 primitiveSmallFloatLessOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(546 primitiveSmallFloatGreaterOrEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(547 primitiveSmallFloatEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(548 primitiveSmallFloatNotEqual 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(549 primitiveSmallFloatMultiply 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(550 primitiveSmallFloatDivide 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(551 primitiveSmallFloatTruncated 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(552 primitiveSmallFloatFractionalPart 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(553 primitiveSmallFloatExponent 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(554 primitiveSmallFloatTimesTwoPower 1 processorHasDoublePrecisionFloatingPointSupport:)"
- "(555 primitiveSmallFloatSquareRoot 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(556 primitiveSmallFloatSine 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(557 primitiveSmallFloatArctan 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(558 primitiveSmallFloatLogN 0 processorHasDoublePrecisionFloatingPointSupport:)"
- "(559 primitiveSmallFloatExp 0 processorHasDoublePrecisionFloatingPointSupport:)"
)!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatAdd (in category 'primitive generators') -----
+ genPrimitiveSmallFloatAdd
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatArithmetic: AddRdRd preOpCheck: nil!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatDivide (in category 'primitive generators') -----
+ genPrimitiveSmallFloatDivide
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatArithmetic: DivRdRd preOpCheck: #genDoubleFailIfZeroArgRcvr:arg:!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatEqual (in category 'primitive generators') -----
+ genPrimitiveSmallFloatEqual
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatComparison: #JumpFPEqual: invert: false!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatGreaterOrEqual (in category 'primitive generators') -----
+ genPrimitiveSmallFloatGreaterOrEqual
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatComparison: #JumpFPGreaterOrEqual: invert: false!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatGreaterThan (in category 'primitive generators') -----
+ genPrimitiveSmallFloatGreaterThan
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatComparison: #JumpFPGreater: invert: false!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatLessOrEqual (in category 'primitive generators') -----
+ genPrimitiveSmallFloatLessOrEqual
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatComparison: #JumpFPGreaterOrEqual: invert: true!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatLessThan (in category 'primitive generators') -----
+ genPrimitiveSmallFloatLessThan
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatComparison: #JumpFPGreater: invert: true!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatMultiply (in category 'primitive generators') -----
+ genPrimitiveSmallFloatMultiply
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatArithmetic: MulRdRd preOpCheck: nil!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatNotEqual (in category 'primitive generators') -----
+ genPrimitiveSmallFloatNotEqual
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatComparison: #JumpFPNotEqual: invert: false!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatSquareRoot (in category 'primitive generators') -----
+ genPrimitiveSmallFloatSquareRoot
+ <option: #Spur64BitMemoryManager>
+ "Stack looks like
+ receiver (also in ResultReceiverReg)
+ return address"
+ | jumpFailAlloc |
+ <var: #jumpFailAlloc type: #'AbstractInstruction *'>
+ objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg into: DPFPReg0.
+ self SqrtRd: DPFPReg0.
+ jumpFailAlloc := objectRepresentation
+ genAllocFloatValue: DPFPReg0
+ into: SendNumArgsReg
+ scratchReg: ClassReg
+ scratchReg: TempReg.
+ self MoveR: SendNumArgsReg R: ReceiverResultReg.
+ self RetN: (self primRetNOffsetFor: 0).
+ jumpFailAlloc jmpTarget: self Label.
+ ^self compileFallbackToInterpreterPrimitive: 0!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genPrimitiveSmallFloatSubtract (in category 'primitive generators') -----
+ genPrimitiveSmallFloatSubtract
+ <option: #Spur64BitMemoryManager>
+ ^self genSmallFloatArithmetic: SubRdRd preOpCheck: nil!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genSmallFloatArithmetic:preOpCheck: (in category 'primitive generators') -----
+ genSmallFloatArithmetic: arithmeticOperator preOpCheck: preOpCheckOrNil
+ "Stack looks like
+ receiver (also in ResultReceiverReg)
+ arg
+ return address"
+ <var: #preOpCheckOrNil declareC: 'AbstractInstruction *(*preOpCheckOrNil)(int rcvrReg, int argReg)'>
+ | jumpFailClass jumpFailAlloc jumpFailCheck jumpImmediate jumpNonInt doOp fail |
+ <var: #jumpFailClass type: #'AbstractInstruction *'>
+ <var: #jumpFailAlloc type: #'AbstractInstruction *'>
+ <var: #jumpNonInt type: #'AbstractInstruction *'>
+ <var: #jumpImmediate type: #'AbstractInstruction *'>
+ <var: #jumpFailCheck type: #'AbstractInstruction *'>
+ <var: #doOp type: #'AbstractInstruction *'>
+ <var: #fail type: #'AbstractInstruction *'>
+ self genLoadArgAtDepth: 0 into: ClassReg.
+ objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg scratch: SendNumArgsReg into: DPFPReg0.
+ jumpImmediate := objectRepresentation genJumpImmediate: ClassReg.
+ objectRepresentation genGetCompactClassIndexNonImmOf: ClassReg into: SendNumArgsReg.
+ objectRepresentation genCmpClassFloatCompactIndexR: SendNumArgsReg.
+ jumpFailClass := self JumpNonZero: 0.
+ objectRepresentation genGetDoubleValueOf: ClassReg into: DPFPReg1.
+ doOp := self Label.
+ preOpCheckOrNil ifNotNil:
+ [jumpFailCheck := self perform: preOpCheckOrNil with: DPFPReg0 with: DPFPReg1].
+ self gen: arithmeticOperator operand: DPFPReg1 operand: DPFPReg0.
+ jumpFailAlloc := objectRepresentation
+ genAllocFloatValue: DPFPReg0
+ into: SendNumArgsReg
+ scratchReg: ClassReg
+ scratchReg: TempReg.
+ self MoveR: SendNumArgsReg R: ReceiverResultReg.
+ self RetN: (self primRetNOffsetFor: 1).
+ jumpImmediate jmpTarget: self Label.
+ objectRepresentation maybeGenConvertIfSmallFloatIn: Arg0Reg scratchReg: TempReg into: DPFPReg1 andJumpTo: doOp.
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt := objectRepresentation genJumpNotSmallInteger: ClassReg scratchReg: TempReg].
+ objectRepresentation genConvertSmallIntegerToIntegerInReg: ClassReg.
+ self ConvertR: ClassReg Rd: DPFPReg1.
+ self Jump: doOp.
+ jumpFailAlloc jmpTarget: self Label.
+ self compileFallbackToInterpreterPrimitive: 0.
+ fail := self Label.
+ jumpFailClass jmpTarget: fail.
+ preOpCheckOrNil ifNotNil:
+ [jumpFailCheck jmpTarget: fail].
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt jmpTarget: fail].
+ ^0!
Item was added:
+ ----- Method: SimpleStackBasedCogit>>genSmallFloatComparison:invert: (in category 'primitive generators') -----
+ genSmallFloatComparison: jumpOpcodeGenerator invert: invertComparison
+ "Stack looks like
+ receiver (also in ResultReceiverReg)
+ arg
+ return address"
+ <var: #jumpOpcodeGenerator declareC: 'AbstractInstruction *(*jumpOpcodeGenerator)(void *)'>
+ | jumpFail jumpImmediate jumpNonInt jumpCond compare |
+ <var: #jumpImmediate type: #'AbstractInstruction *'>
+ <var: #jumpNonInt type: #'AbstractInstruction *'>
+ <var: #jumpCond type: #'AbstractInstruction *'>
+ <var: #compare type: #'AbstractInstruction *'>
+ <var: #jumpFail type: #'AbstractInstruction *'>
+
+ self genLoadArgAtDepth: 0 into: ClassReg.
+ objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg scratch: SendNumArgsReg into: DPFPReg0.
+ jumpImmediate := objectRepresentation genJumpImmediate: ClassReg.
+ objectRepresentation genGetCompactClassIndexNonImmOf: ClassReg into: SendNumArgsReg.
+ objectRepresentation genCmpClassFloatCompactIndexR: SendNumArgsReg.
+ jumpFail := self JumpNonZero: 0.
+ objectRepresentation genGetDoubleValueOf: ClassReg into: DPFPReg1.
+ invertComparison "May need to invert for NaNs"
+ ifTrue: [compare := self CmpRd: DPFPReg0 Rd: DPFPReg1]
+ ifFalse: [compare := self CmpRd: DPFPReg1 Rd: DPFPReg0].
+ jumpCond := self perform: jumpOpcodeGenerator with: 0. "FP jumps are a little weird"
+ self genMoveFalseR: ReceiverResultReg.
+ self RetN: (self primRetNOffsetFor: 1).
+ jumpCond jmpTarget: (self genMoveTrueR: ReceiverResultReg).
+ self RetN: (self primRetNOffsetFor: 1).
+ jumpImmediate jmpTarget: self Label.
+ objectRepresentation maybeGenConvertIfSmallFloatIn: ClassReg scratchReg: TempReg into: DPFPReg1 andJumpTo: compare.
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt := objectRepresentation genJumpNotSmallInteger: ClassReg scratchReg: TempReg].
+ objectRepresentation genConvertSmallIntegerToIntegerInReg: ClassReg.
+ self ConvertR: ClassReg Rd: DPFPReg1.
+ self Jump: compare.
+ jumpFail jmpTarget: self Label.
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt jmpTarget: jumpFail getJmpTarget].
+ ^0!
Item was added:
+ ----- Method: SmallInteger>>isBreakpointFor: (in category '*VMMaker-interpreter simulator') -----
+ isBreakpointFor: address
+ <primitive: 7>
+ ^self = address!
Item was added:
+ ----- Method: Spur64BitMemoryManager>>smallFloatExponentBits (in category 'interpreter access') -----
+ smallFloatExponentBits
+ "SmallFloat64's have the same mantissa as IEEE single-precision floating point"
+ <api>
+ <cmacro>
+ ^8!
Item was changed:
----- Method: Spur64BitMemoryManager>>smallFloatMantissaBits (in category 'interpreter access') -----
smallFloatMantissaBits
+ "SmallFloat64's have the same mantissa as IEEE double-precision floating point"
- "SmallFLoat64's have the same mantissa as IEEE double-precision floating point"
<api>
<cmacro>
^52!
Item was changed:
----- Method: StackInterpreter class>>initializePrimitiveTable (in category 'initialization') -----
(excessive size, no diff calculated)
Item was changed:
----- Method: StackInterpreter class>>table:from: (in category 'initialization') -----
table: anArray from: specArray
"SpecArray is an array of one of (index selector) or (index1
index2 selector) or (index nil) or (index1 index2 nil). If selector
then the entry is the selector, but if nil the entry is the index."
| contiguous |
contiguous := 0.
specArray do:
[:spec |
(spec at: 1) = contiguous ifFalse:
[self error: 'Non-contiguous table entry'].
spec size = 2
ifTrue:
[anArray
at: (spec at: 1) + 1
put: ((spec at: 2) ifNil: [spec at: 1] ifNotNil: [:sym| sym]).
contiguous := contiguous + 1]
ifFalse:
[(spec at: 1) to: (spec at: 2) do:
[:i | anArray at: i + 1 put: ((spec at: 3) ifNil: [i] ifNotNil: [:sym| sym])].
contiguous := contiguous + ((spec at: 2) - (spec at: 1)) + 1]].
anArray doWithIndex:
[:entry :index|
entry isSymbol ifTrue:
+ [(self shouldIncludeMethodForSelector: entry) ifFalse:
+ [anArray at: index put: 0]]]!
- [(self whichClassIncludesSelector: entry) ifNotNil:
- [:c| | m |
- m := c >> entry.
- (m pragmaAt: #option:) ifNotNil:
- [:pragma|
- (initializationOptions at: (pragma arguments first) ifAbsent: [true]) ifFalse:
- [anArray at: index put: 0]]]]]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genPrimitiveSmallFloatSquareRoot (in category 'primitive generators') -----
+ genPrimitiveSmallFloatSquareRoot
+ <option: #Spur64BitMemoryManager>
+ | jumpFailAlloc |
+ <var: #jumpFailAlloc type: #'AbstractInstruction *'>
+ objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg into: DPFPReg0.
+ self SqrtRd: DPFPReg0.
+ jumpFailAlloc := objectRepresentation
+ genAllocFloatValue: DPFPReg0
+ into: SendNumArgsReg
+ scratchReg: ClassReg
+ scratchReg: TempReg.
+ self MoveR: SendNumArgsReg R: ReceiverResultReg.
+ self RetN: 0.
+ jumpFailAlloc jmpTarget: self Label.
+ ^self compileFallbackToInterpreterPrimitive: 0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genSmallFloatArithmetic:preOpCheck: (in category 'primitive generators') -----
+ genSmallFloatArithmetic: arithmeticOperator preOpCheck: preOpCheckOrNil
+ "Receiver and arg in registers.
+ Stack looks like
+ return address"
+ <var: #preOpCheckOrNil declareC: 'AbstractInstruction *(*preOpCheckOrNil)(int rcvrReg, int argReg)'>
+ | jumpFailClass jumpFailClass2 jumpFailAlloc jumpFailCheck jumpImmediate jumpNonInt doOp |
+ <var: #jumpFailClass type: #'AbstractInstruction *'>
+ <var: #jumpFailClass2 type: #'AbstractInstruction *'>
+ <var: #jumpFailAlloc type: #'AbstractInstruction *'>
+ <var: #jumpImmediate type: #'AbstractInstruction *'>
+ <var: #jumpNonInt type: #'AbstractInstruction *'>
+ <var: #jumpFailCheck type: #'AbstractInstruction *'>
+ <var: #doOp type: #'AbstractInstruction *'>
+ objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg scratch: SendNumArgsReg into: DPFPReg0.
+ self MoveR: Arg0Reg R: ClassReg.
+ jumpImmediate := objectRepresentation genJumpImmediate: Arg0Reg.
+ objectRepresentation genGetCompactClassIndexNonImmOf: Arg0Reg into: SendNumArgsReg.
+ objectRepresentation genCmpClassFloatCompactIndexR: SendNumArgsReg.
+ jumpFailClass := self JumpNonZero: 0.
+ objectRepresentation genGetDoubleValueOf: Arg0Reg into: DPFPReg1.
+ doOp := self Label.
+ preOpCheckOrNil ifNotNil:
+ [jumpFailCheck := self perform: preOpCheckOrNil with: DPFPReg0 with: DPFPReg1].
+ self gen: arithmeticOperator operand: DPFPReg1 operand: DPFPReg0.
+ jumpFailAlloc := objectRepresentation
+ genAllocFloatValue: DPFPReg0
+ into: SendNumArgsReg
+ scratchReg: ClassReg
+ scratchReg: TempReg.
+ self MoveR: SendNumArgsReg R: ReceiverResultReg.
+ self RetN: 0.
+ jumpImmediate jmpTarget: self Label.
+ objectRepresentation maybeGenConvertIfSmallFloatIn: Arg0Reg scratchReg: TempReg into: DPFPReg1 andJumpTo: doOp.
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt := objectRepresentation genJumpNotSmallInteger: Arg0Reg scratchReg: TempReg].
+ objectRepresentation genConvertSmallIntegerToIntegerInReg: ClassReg.
+ self ConvertR: ClassReg Rd: DPFPReg1.
+ self Jump: doOp.
+ "We need to push the register args on two paths; this one and the interpreter primitive path.
+ But the interpreter primitive path won't unless regArgsHaveBeenPushed is false."
+ self assert: methodOrBlockNumArgs <= self numRegArgs.
+ jumpFailClass jmpTarget: self Label.
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt jmpTarget: jumpFailClass getJmpTarget].
+ preOpCheckOrNil ifNotNil:
+ [jumpFailCheck jmpTarget: jumpFailClass getJmpTarget].
+ backEnd genPushRegisterArgsForNumArgs: methodOrBlockNumArgs scratchReg: SendNumArgsReg.
+ jumpFailClass2 := self Jump: 0.
+ jumpFailAlloc jmpTarget: self Label.
+ self compileFallbackToInterpreterPrimitive: 0.
+ jumpFailClass2 jmpTarget: self Label.
+ ^0!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>genSmallFloatComparison:invert: (in category 'primitive generators') -----
+ genSmallFloatComparison: jumpOpcodeGenerator invert: invertComparison
+ "Receiver and arg in registers.
+ Stack looks like
+ return address"
+ <var: #jumpOpcodeGenerator declareC: 'AbstractInstruction *(*jumpOpcodeGenerator)(void *)'>
+ | jumpFail jumpImmediate jumpNonInt jumpCond compare |
+ <var: #jumpImmediate type: #'AbstractInstruction *'>
+ <var: #jumpNonInt type: #'AbstractInstruction *'>
+ <var: #jumpCond type: #'AbstractInstruction *'>
+ <var: #compare type: #'AbstractInstruction *'>
+ <var: #jumpFail type: #'AbstractInstruction *'>
+ objectRepresentation genGetSmallFloatValueOf: ReceiverResultReg scratch: SendNumArgsReg into: DPFPReg0.
+ jumpImmediate := objectRepresentation genJumpImmediate: Arg0Reg.
+ objectRepresentation genGetCompactClassIndexNonImmOf: Arg0Reg into: SendNumArgsReg.
+ objectRepresentation genCmpClassFloatCompactIndexR: SendNumArgsReg.
+ jumpFail := self JumpNonZero: 0.
+ objectRepresentation genGetDoubleValueOf: Arg0Reg into: DPFPReg1.
+ invertComparison "May need to invert for NaNs"
+ ifTrue: [compare := self CmpRd: DPFPReg0 Rd: DPFPReg1]
+ ifFalse: [compare := self CmpRd: DPFPReg1 Rd: DPFPReg0].
+ jumpCond := self perform: jumpOpcodeGenerator with: 0. "FP jumps are a little weird"
+ self genMoveFalseR: ReceiverResultReg.
+ self RetN: 0.
+ jumpCond jmpTarget: (self genMoveTrueR: ReceiverResultReg).
+ self RetN: 0.
+ jumpImmediate jmpTarget: self Label.
+ objectRepresentation maybeGenConvertIfSmallFloatIn: Arg0Reg scratchReg: TempReg into: DPFPReg1 andJumpTo: compare.
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt := objectRepresentation genJumpNotSmallInteger: Arg0Reg scratchReg: TempReg].
+ objectRepresentation genConvertSmallIntegerToIntegerInReg: Arg0Reg.
+ self ConvertR: Arg0Reg Rd: DPFPReg1.
+ self Jump: compare.
+ jumpFail jmpTarget: self Label.
+ objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ [jumpNonInt jmpTarget: jumpFail getJmpTarget].
+ ^0!
Item was added:
+ ----- Method: UndefinedObject>>addBreakpoint: (in category '*VMMaker-interpreter simulator') -----
+ addBreakpoint: address
+ ^address!
Item was added:
+ ----- Method: UndefinedObject>>isActiveBreakpoint (in category '*VMMaker-interpreter simulator') -----
+ isActiveBreakpoint
+ ^false!
Item was added:
+ ----- Method: UndefinedObject>>isBreakpointFor: (in category '*VMMaker-interpreter simulator') -----
+ isBreakpointFor: address
+ ^false!
Item was added:
+ ----- Method: UndefinedObject>>menuPrompt (in category '*VMMaker-interpreter simulator') -----
+ menuPrompt
+ ^''!
Item was added:
+ ----- Method: UndefinedObject>>shouldStopIfAtPC: (in category '*VMMaker-interpreter simulator') -----
+ shouldStopIfAtPC: address
+ ^true!
Item was added:
+ ----- Method: UndefinedObject>>singleStepRequiredToTriggerIn: (in category '*VMMaker-interpreter simulator') -----
+ singleStepRequiredToTriggerIn: aCogit
+ ^false!
Item was added:
+ ----- Method: VMClass class>>shouldIncludeMethodForSelector: (in category 'translation') -----
+ shouldIncludeMethodForSelector: selector
+ "Answer whether a primitive method shoud be translated. Emit a warning to the transcript if the method doesn't exist."
+ ^(self whichClassIncludesSelector: selector)
+ ifNotNil:
+ [:c|
+ (c >> selector pragmaAt: #option:)
+ ifNotNil:
+ [:pragma|
+ initializationOptions at: (pragma arguments first) ifAbsent: [true]]
+ ifNil: [true]]
+ ifNil:
+ [Transcript nextPutAll: 'Cannot find implementation of '; nextPutAll: selector; nextPutAll: ' in hierarchy of '; print: self; cr; flush.
+ false]!
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Hi Mariano,
> On Dec 22, 2015, at 8:36 PM, Mariano Martinez Peck <marianopeck(a)gmail.com> wrote:
>
>
>
>> On Tue, Dec 22, 2015 at 5:24 PM, tesonep(a)gmail.com <tesonep(a)gmail.com> wrote:
>> Hello Mariano,
>> WNOHANG is a constant is defined in sys/wait.h, after the compilation is not included in the object file.
>>
>> You will have to duplicate its value in the Smalltalk Code. It's value is 1, in linux is defined in bits/waitflags.h as
>>
>> #define WNOHANG 1
>
> mmmmmm but then I would need to take care about its different values in different OS right?
> I am reading for example this thread: https://groups.google.com/forum/#!topic/comp.lang.python/_5rCpfYR_ZE
>
> sunos 4.1.3 : #define WNOHANG 1
> Solaris 2.4 : #define WNOHANG 0100
> OSF1 2.0 : #define WNOHANG 0x1
> Ultrix 4.4 : #define WNOHANG 1
> irix 4.0.5C : #define WNOHANG 0x1
> irix 5.2 : #define WNOHANG 0100
> irix 6.0.1 : #define WNOHANG 0100
>
Exactly. I've discussed this before. Please read
http://lists.pharo.org/pipermail/pharo-dev_lists.pharo.org/2012-May/064382.…
> OK..the thread is from 1995... I thought the POSIX standard would standardize that...
>
> I am now checking at /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.11.sdk/usr/include/sys/wait.h
>
> and it says:
> #define WNOHANG 0x00000001
>
> But again..I wonder how portable is to stick to that...
>
> Ok...maybe I will need to go with a VM primitive as #primGetChildExitStatus: that way I can do the:
>
> self cCode: 'waitpid ( pidToHandle, &exitStatus, WNOHANG )' inSmalltalk: [ exitStatus := -1 ].
>
>
> pd: que groso Pablito verte por aca!!!!
>
>> Cheers,
>> Pablo
>>
>>> On Tue, Dec 22, 2015 at 5:12 PM, Mariano Martinez Peck <marianopeck(a)gmail.com> wrote:
>>> Hi guys,
>>>
>>> Say I want to call to waitpid like this:
>>>
>>> waitpid(childID, &status, WNOHANG);
>>>
>>> How can I do since I don't have access to WNOHANG int value in order to send it via argument .... ???
>>>
>>> Any idea?
>>>
>>> Thanks in advance,
>>>
>>> Mariano
>>> http://marianopeck.wordpress.com
>>
>> Pablo Tesone.
>> tesonep(a)gmail.com
>
> Mariano
> http://marianopeck.wordpress.com
_,,,^..^,,,_ (phone)
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