Hi Ronie, (Hi Clément),
for a while now Clément and I have been unhappy about optStatus
(CogSSOptStatus). Now that the RegisterAllocatingCogit is nearly working
it's clear that a much nicer approach is to give CogSimStackEntry a
liveRegister instance variable and have simSelf take the place of
optStatus, so that what were
optStatus isReceiverResultRegLive
optStatus isReceiverResultRegLive: true
optStatus isReceiverResultRegLive: false
are replaced by
simSelf liveRegister = ReceiverResultReg
simSelf liveRegister: ReceiverResultReg
simSelf liveRegister: NoReg
To this end can you rewrite the Lowcode code generator so that e.g. the
following
genLowcodeAlloca32
<option: #LowcodeVM> "Lowcode instruction generator"
| size |
(size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg
ifTrue:
[self ssAllocateRequiredReg:
(size := optStatus isReceiverResultRegLive
ifTrue: [Arg0Reg]
ifFalse: [ReceiverResultReg])].
size = ReceiverResultReg ifTrue:
[ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
self SubR: size R: TempReg.
self AndCq: -16 R: TempReg.
self MoveR: TempReg R: size.
self MoveR: size Aw: coInterpreter nativeStackPointerAddress.
self ssPushNativeRegister: size.
^ 0
reads something more like
genLowcodeAlloca32
<option: #LowcodeVM> "Lowcode instruction generator"
| size |
self allocateOneRegisterForLowcodeInto: [:reg| size := reg].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
self SubR: size R: TempReg.
self AndCq: -16 R: TempReg.
self MoveR: TempReg R: size.
self MoveR: size Aw: coInterpreter nativeStackPointerAddress.
self ssPushNativeRegister: size.
^ 0
etc? So there are allocateOneRegisterForLowcodeInto: through
allocateThreeRegistersForLowcodeInto:. This way it'll be much easier to
make the above change which I'm making now.
_,,,^..^,,,_
best, Eliot