Vm-dev April 2015

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VM Maker: VMMaker.oscog-eem.1242.mcz
by commits＠source.squeak.org 23 Apr '15

23 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1242.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1242 Author: eem Time: 22 April 2015, 5:53:15.54 pm UUID: 24d3608c-2198-4927-90b4-477af0cca4e7 Ancestors: VMMaker.oscog-eem.1241 Fix the read-before-written initializer to not initialize structs (if the struct types can be identified). Make the allOldMarkedWeakObjectsOnWeaklingStack assert an eassert: (it /is/ extremely expensive) and correct some typos in eassert:. =============== Diff against VMMaker.oscog-eem.1241 =============== Item was changed: ----- Method: SpurMemoryManager>>nilUnmarkedWeaklingSlots (in category 'weakness and ephemerality') ----- nilUnmarkedWeaklingSlots "Nil the unmarked slots in the weaklings on the weakling stack, finalizing those that lost references. Finally, empty the weaklingStack." <inline: #never> "for profiling" self cCode: '' inSmalltalk: [coInterpreter transcript nextPutAll: 'nilling...'; flush]. + self eassert: self allOldMarkedWeakObjectsOnWeaklingStack. - self assert: self allOldMarkedWeakObjectsOnWeaklingStack. weaklingStack = nilObj ifTrue: [^self]. self objStack: weaklingStack from: 0 do: [:weakling| | anyUnmarked | anyUnmarked := self nilUnmarkedWeaklingSlotsIn: weakling. anyUnmarked ifTrue: [coInterpreter signalFinalization: weakling]]. self emptyObjStack: weaklingStack! Item was removed: - ----- Method: TMethod>>findReadBeforeAssignedIn: (in category 'utilities') ----- - findReadBeforeAssignedIn: variables - | readBeforeAssigned | - readBeforeAssigned := Set new. - parseTree - addReadBeforeAssignedIn: variables - to: readBeforeAssigned - assignments: Set new. - ^readBeforeAssigned! Item was added: + ----- Method: TMethod>>findReadBeforeAssignedIn:in: (in category 'utilities') ----- + findReadBeforeAssignedIn: variables in: aCodeGen + | readBeforeAssigned | + readBeforeAssigned := Set new. + parseTree + addReadBeforeAssignedIn: variables + to: readBeforeAssigned + assignments: Set new + in: aCodeGen. + ^readBeforeAssigned! Item was changed: ----- Method: TMethod>>removeUnusedTempsAndNilIfRequiredIn: (in category 'utilities') ----- removeUnusedTempsAndNilIfRequiredIn: aCodeGen "Remove all of the unused temps in this method. Answer a set of the references. As a side-effect introduce explicit temp := nil statements for temps that are tested for nil before necessarily being assigned." | refs readBeforeAssigned | refs := self removeUnusedTempsIn: aCodeGen. "reset the locals to be only those still referred to" locals := locals select: [:e| refs includes: e]. (locals notEmpty + and: [aCodeGen + pushScope: declarations + while: [(readBeforeAssigned := (self findReadBeforeAssignedIn: locals in: aCodeGen)) notEmpty]]) ifTrue: - and: [(readBeforeAssigned := (self findReadBeforeAssignedIn: locals)) notEmpty]) ifTrue: [readBeforeAssigned := readBeforeAssigned reject: [:v| | d | "don't initialize externa and/or arrays" d := self declarationAt: v. (d beginsWith: 'extern') or: [d includes: $[]]. parseTree statements addAllFirst: (readBeforeAssigned asSortedCollection collect: [:var| TAssignmentNode new setVariable: (TVariableNode new setName: var; yourself) expression: (TConstantNode new setValue: 0; yourself)])]. ^refs! Item was removed: - ----- Method: TStmtListNode>>addReadBeforeAssignedIn:to:assignments: (in category 'utilities') ----- - addReadBeforeAssignedIn: variables to: readBeforeAssigned assignments: assigned - "Add any variables in variables that are read before written to readBeforeAssigned. - Add unconditional assignments to assigned. For convenience answer assigned." - self - nodesWithParentsDo: - [:node :parent| - (node isAssignment - and: [variables includes: node variable name]) ifTrue: - [assigned add: node variable name]. - (node isVariable - and: [(variables includes: node name) - and: [(assigned includes: node name) not - and: [(parent notNil and: [parent isAssignment and: [parent variable == node]]) not]]]) ifTrue: - [readBeforeAssigned add: node name]] - unless: - [:node :parent| | conditionalAssignments mayHaveSideEffects | - node isSend - ifTrue: - ["First deal with implicit assignments..." - node isValueExpansion ifTrue: - [assigned addAll: node receiver args]. - (#(mem:cp:y: mem:mo:ve:) includes: node selector) ifTrue: - [assigned add: (node args first detect: [:subnode| subnode isVariable]) name]. - (#(to:do: to:by:do:) includes: node selector) ifTrue: - [assigned addAll: (node args at: node selector numArgs) args. - mayHaveSideEffects := node args size = 4. "See TMethod>>prepareMethodIn:" - mayHaveSideEffects ifTrue: - [assigned add: node args last name]]. - "Then deal with read-before-written in the arms of conditionals..." - (#(ifTrue: ifFalse: ifNil: ifNotNil:) intersection: node selector keywords) notEmpty - ifTrue: - ["First find assignments in the expression..." - (TStmtListNode new setStatements: {node receiver}; yourself) - addReadBeforeAssignedIn: variables - to: readBeforeAssigned - assignments: assigned. - "Now find read-before-written in each arm, and collect the assignments to spot those assigned in both arms" - conditionalAssignments := - node args - collect: - [:block| - block isStmtList ifTrue: - [block - addReadBeforeAssignedIn: variables - to: readBeforeAssigned - assignments: assigned copy]] - thenSelect: [:each| each notNil]. - "add to assigned those variables written to in both arms" - conditionalAssignments size = 2 ifTrue: - [conditionalAssignments := conditionalAssignments collect: [:set| set difference: assigned]. - assigned addAll: (conditionalAssignments first intersection: conditionalAssignments last)]. - true] - ifFalse: - [false]] - ifFalse: - [false]]. - ^assigned! Item was added: + ----- Method: TStmtListNode>>addReadBeforeAssignedIn:to:assignments:in: (in category 'utilities') ----- + addReadBeforeAssignedIn: variables to: readBeforeAssigned assignments: assigned in: aCodeGen + "Add any variables in variables that are read before written to readBeforeAssigned. + Add unconditional assignments to assigned. For convenience answer assigned." + self + nodesWithParentsDo: + [:node :parent| + (node isAssignment + and: [variables includes: node variable name]) ifTrue: + [assigned add: node variable name]. + (node isVariable + and: [(variables includes: node name) + and: [(assigned includes: node name) not + and: [(node structTargetKindIn: aCodeGen) isNil + and: [(parent notNil and: [parent isAssignment and: [parent variable == node]]) not]]]]) ifTrue: + [node name = 'theCalloutState' ifTrue: + [self halt]. + readBeforeAssigned add: node name]] + unless: + [:node :parent| | conditionalAssignments mayHaveSideEffects | + node isSend + ifTrue: + ["First deal with implicit assignments..." + node isValueExpansion ifTrue: + [assigned addAll: node receiver args]. + (#(mem:cp:y: mem:mo:ve:) includes: node selector) ifTrue: + [assigned add: (node args first detect: [:subnode| subnode isVariable]) name]. + (#(to:do: to:by:do:) includes: node selector) ifTrue: + [assigned addAll: (node args at: node selector numArgs) args. + mayHaveSideEffects := node args size = 4. "See TMethod>>prepareMethodIn:" + mayHaveSideEffects ifTrue: + [assigned add: node args last name]]. + "Then deal with read-before-written in the arms of conditionals..." + (#(ifTrue: ifFalse: ifNil: ifNotNil:) intersection: node selector keywords) notEmpty + ifTrue: + ["First find assignments in the expression..." + (TStmtListNode new setStatements: {node receiver}; yourself) + addReadBeforeAssignedIn: variables + to: readBeforeAssigned + assignments: assigned + in: aCodeGen. + "Now find read-before-written in each arm, and collect the assignments to spot those assigned in both arms" + conditionalAssignments := + node args + collect: + [:block| + block isStmtList ifTrue: + [block + addReadBeforeAssignedIn: variables + to: readBeforeAssigned + assignments: assigned copy + in: aCodeGen]] + thenSelect: [:each| each notNil]. + "add to assigned those variables written to in both arms" + conditionalAssignments size = 2 ifTrue: + [conditionalAssignments := conditionalAssignments collect: [:set| set difference: assigned]. + assigned addAll: (conditionalAssignments first intersection: conditionalAssignments last)]. + true] + ifFalse: + [false]] + ifFalse: + [false]]. + ^assigned! Item was changed: ----- Method: VMClass>>eassert: (in category 'debug support') ----- eassert: aBooleanExpressionOrBlock "This is for expensive asserts that we're only interested in checking in extremis. + For example now that Spur objStacks are debugged there's no benefit to + evaluating isValidObjStack: throughout the mark loop because its damn slow." - For exampl,e now that Spur objStacks are debugged there's no benefit to evaluating - isValidObjStack: throguhout the mark loop because its damn slow." <doNotGenerate> ExpensiveAsserts ifTrue: [aBooleanExpressionOrBlock value ifFalse: [AssertionFailure signal: 'Assertion failed']]!

1 0

ARM Cogit
by Eliot Miranda 23 Apr '15

23 Apr '15

Hi All, thanks to hard work by Tim Rowledge and Lars Wasserman we now have a functional JIT for the ARM in the simulator. We're still probably some weeks away from a functional ARM JIT VM; issues like instruction cache flushing on real hardware can be tricky to solve. But we're at least ready to start trying to compile the JIT VM for ARM. Doug, see that I added a build directory for build.linux32ARM/squeak.cog.spur. Hopefully a fast VM for Raspberry Pi and Android is only a few weeks away. -- best, Eliot

4 4

[commit][3313] CogVM source as per VMMaker.oscog-eem.1241
by commits＠squeakvm.org 22 Apr '15

22 Apr '15

Revision: 3313 Author: eliot Date: 2015-04-22 11:36:16 -0700 (Wed, 22 Apr 2015) Log Message: ----------- CogVM source as per VMMaker.oscog-eem.1241 Change source file output for the Cogit so that cogit.c includes cogitARMv5.c or cogitIA32.c as appropriate, using the same style as ThreadedFFIPlugin. Add builds for the ARMv5 Cogit. Changed the names of register allocation methods for more explict names, for instance, allocateOneReg -> allocateRegForStackTop. Cogit: Change map generation and interpretation so that the displacements are in codeGranularity units, and make the codeGranularity 4 on ARM. Comment machineCodeSize and maxSize. Introduce UnfailingPrimitive and use it to avoid generating the interpreter primitive call in Spur the Character>>asInteger primitive. Revise Call/Jump terminology using CallFull/JumpFull for calls/jumps anywhere in the address space. Makes no difference to x86 but is operative on ARM. ARM call/branch ranges use immediate call/jump for all intra-zone transfers, and 5 instruction sequences only for trampoline and interpreter primitive calls. - Change the code generation of == for Spur; only check for forwarders if operands differ. - Change the code generation of == for sistaCogit - change the counter reg to be allocated instead of being a fixed abstract reg - fix a C code gen bug in code gen of #== - fix a bug in #== where the arg was not unforwarded Use new register allocation in #== with V3 in order to limit register moves. Modified Paths: -------------- branches/Cog/build.linux32ARM/makeall branches/Cog/build.linux32ARM/makeproduct branches/Cog/nsspursrc/vm/cogit.c branches/Cog/nsspursrc/vm/cogit.h branches/Cog/nsspursrc/vm/cointerp.c branches/Cog/nsspursrc/vm/cointerp.h branches/Cog/nsspursrc/vm/gcc3x-cointerp.c branches/Cog/spursistasrc/vm/cogit.c branches/Cog/spursistasrc/vm/cogit.h branches/Cog/spursistasrc/vm/cointerp.c branches/Cog/spursistasrc/vm/cointerp.h branches/Cog/spursistasrc/vm/gcc3x-cointerp.c branches/Cog/spursrc/vm/cogit.c branches/Cog/spursrc/vm/cogit.h branches/Cog/spursrc/vm/cointerp.c branches/Cog/spursrc/vm/cointerp.h branches/Cog/spursrc/vm/gcc3x-cointerp.c branches/Cog/spurstack64src/vm/gcc3x-interp.c branches/Cog/spurstack64src/vm/interp.c branches/Cog/spurstacksrc/vm/gcc3x-interp.c branches/Cog/spurstacksrc/vm/interp.c branches/Cog/src/vm/cogit.c branches/Cog/src/vm/cogit.h branches/Cog/src/vm/cointerp.c branches/Cog/src/vm/cointerp.h branches/Cog/src/vm/cointerpmt.c branches/Cog/src/vm/cointerpmt.h branches/Cog/src/vm/gcc3x-cointerp.c branches/Cog/src/vm/gcc3x-cointerpmt.c branches/Cog/stacksrc/vm/gcc3x-interp.c branches/Cog/stacksrc/vm/interp.c Added Paths: ----------- branches/Cog/build.linux32ARM/squeak.cog.spur/ branches/Cog/build.linux32ARM/squeak.cog.spur/build/ branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.ext branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.int branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/ branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.ext branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.int branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/ branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.ext branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.int branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty branches/Cog/nsspursrc/vm/cogitARMv5.c branches/Cog/nsspursrc/vm/cogitIA32.c branches/Cog/spursrc/vm/cogitARMv5.c branches/Cog/spursrc/vm/cogitIA32.c branches/Cog/src/vm/cogitARMv5.c branches/Cog/src/vm/cogitIA32.c Property Changed: ---------------- branches/Cog/platforms/Cross/vm/sqSCCSVersion.h Modified: branches/Cog/build.linux32ARM/makeall =================================================================== --- branches/Cog/build.linux32ARM/makeall 2015-04-17 19:34:25 UTC (rev 3312) +++ branches/Cog/build.linux32ARM/makeall 2015-04-22 18:36:16 UTC (rev 3313) @@ -1,6 +1,6 @@ #!/bin/bash trap 'exit 2' HUP INT PIPE TERM -for d in squeak.*; do +for d in newspeak.* squeak.*; do if test -d "$d"; then (cd $d;./makeallclean "$@") else Modified: branches/Cog/build.linux32ARM/makeproduct =================================================================== --- branches/Cog/build.linux32ARM/makeproduct 2015-04-17 19:34:25 UTC (rev 3312) +++ branches/Cog/build.linux32ARM/makeproduct 2015-04-22 18:36:16 UTC (rev 3313) @@ -1,6 +1,6 @@ #!/bin/bash trap 'exit 2' HUP INT PIPE TERM -for d in newspeak.cog.spur squeak.cog.spur squeak.cog.v3; do +for d in newspeak.cog.spur squeak.cog.spur squeak.cog.v3 squeak.stack.spur squeak.stack.v3; do if test -d "$d"; then (cd $d;./makeallclean "$@") else Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,32 @@ +#!/bin/bash +# Spur VM with VM profiler and threaded heartbeat +INSTALLDIR=cogspurlinuxht +# Some gcc versions create a broken VM using -O2 +case `gcc -v 2>&1 | grep version | sed 's/gcc version *//'` in +3.4.*) OPT="-g -O1 -DNDEBUG -DDEBUGVM=0";; +*) OPT="-g -O2 -DNDEBUG -DDEBUGVM=0";; +esac + +if [ $# -ge 1 ]; then + INSTALLDIR="$1"; shift +fi + +echo -n "clean? " +read a +case $a in +n|no|N|NO) echo "ok but this isn't safe!!";; +*) test -f Makefile && make reallyclean +esac +test -f config.h || ../../../platforms/unix/config/configure --without-npsqueak \ + --with-vmversion=5.0 \ + --with-src=spursrc --with-plugins=src/plugins \ + CC="gcc -m32" \ + CXX="g++ -m32" \ + CFLAGS="$OPT -msse2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DCOGMTVM=0" \ + LIBS="-lpthread -luuid" \ + LDFLAGS=-Wl,-z,now +rm -f vm/sqUnixMain.o # nuke version info +rm -rf ../../../products/$INSTALLDIR +# prefer make install prefix=`readlink -f \`pwd\`/../../../products/$INSTALLDIR` +# but older linux readlinks lack the -f flag +make install-squeak install-plugins prefix=`(cd ../../../;pwd)`/products/$INSTALLDIR 2>&1 | tee LOG Property changes on: branches/Cog/build.linux32ARM/squeak.cog.spur/build/mvm ___________________________________________________________________ Added: svn:executable + * Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.ext =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.ext (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.ext 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,12 @@ +# Copied, perhaps edited, from ../../src/examplePlugins.ext +EXTERNAL_PLUGINS = \ +B3DAcceleratorPlugin \ +BochsIA32Plugin \ +GdbARMPlugin \ +SqueakFFIPrims \ +SqueakSSL \ +LocalePlugin \ +UnicodePlugin \ +UnixOSProcessPlugin \ +UUIDPlugin \ +XDisplayControlPlugin Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.int =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.int (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build/plugins.int 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,37 @@ +# Copied, perhaps edited, from ../../src/examplePlugins.int +INTERNAL_PLUGINS = \ +ADPCMCodecPlugin \ +AioPlugin \ +AsynchFilePlugin \ +B2DPlugin \ +BitBltPlugin \ +BMPReadWriterPlugin \ +CroquetPlugin \ +ZipPlugin \ +DropPlugin \ +DSAPrims \ +FFTPlugin \ +FileCopyPlugin \ +FilePlugin \ +FloatArrayPlugin \ +FloatMathPlugin \ +IA32ABI \ +JoystickTabletPlugin \ +JPEGReaderPlugin \ +JPEGReadWriter2Plugin \ +Klatt \ +LargeIntegers \ +Matrix2x3Plugin \ +MIDIPlugin \ +MiscPrimitivePlugin \ +Mpeg3Plugin \ +RePlugin \ +SecurityPlugin \ +SerialPlugin \ +SocketPlugin \ +SoundCodecPrims \ +SoundGenerationPlugin \ +SoundPlugin \ +StarSqueakPlugin \ +SurfacePlugin \ +VMProfileLinuxSupportPlugin Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,28 @@ +#!/bin/bash +# assert VM with VM profiler and threaded heartbeat +INSTALLDIR=assert/cogspurlinuxht +OPT="-g3 -O1 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -DDEBUGVM=0" + +if [ $# -ge 1 ]; then + INSTALLDIR="$1"; shift +fi + +echo -n "clean? " +read a +case $a in +n|no|N|NO) echo "ok but this isn't safe!!";; +*) test -f Makefile && make reallyclean +esac +test -f config.h || ../../../platforms/unix/config/configure --without-npsqueak \ + --with-vmversion=5.0 \ + --with-src=spursrc --with-plugins=src/plugins \ + CC="gcc -m32" \ + CXX="g++ -m32" \ + CFLAGS="$OPT -msse2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DCOGMTVM=0" \ + LIBS="-lpthread -luuid" \ + LDFLAGS=-Wl,-z,now +rm -f vm/sqUnixMain.o # nuke version info +rm -rf ../../../products/$INSTALLDIR +# prefer make install prefix=`readlink -f \`pwd\`/../../../products/$INSTALLDIR` +# but older linux readlinks lack the -f flag +make install-squeak install-plugins prefix=`(cd ../../../;pwd)`/products/$INSTALLDIR 2>&1 | tee LOG Property changes on: branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/mvm ___________________________________________________________________ Added: svn:executable + * Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.ext =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.ext (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.ext 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,12 @@ +# Copied, perhaps edited, from ../../src/examplePlugins.ext +EXTERNAL_PLUGINS = \ +B3DAcceleratorPlugin \ +BochsIA32Plugin \ +GdbARMPlugin \ +SqueakFFIPrims \ +SqueakSSL \ +LocalePlugin \ +UnicodePlugin \ +UnixOSProcessPlugin \ +UUIDPlugin \ +XDisplayControlPlugin Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.int =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.int (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.assert/plugins.int 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,37 @@ +# Copied, perhaps edited, from ../../src/examplePlugins.int +INTERNAL_PLUGINS = \ +ADPCMCodecPlugin \ +AioPlugin \ +AsynchFilePlugin \ +B2DPlugin \ +BitBltPlugin \ +BMPReadWriterPlugin \ +CroquetPlugin \ +ZipPlugin \ +DropPlugin \ +DSAPrims \ +FFTPlugin \ +FileCopyPlugin \ +FilePlugin \ +FloatArrayPlugin \ +FloatMathPlugin \ +IA32ABI \ +JoystickTabletPlugin \ +JPEGReaderPlugin \ +JPEGReadWriter2Plugin \ +Klatt \ +LargeIntegers \ +Matrix2x3Plugin \ +MIDIPlugin \ +MiscPrimitivePlugin \ +Mpeg3Plugin \ +RePlugin \ +SecurityPlugin \ +SerialPlugin \ +SocketPlugin \ +SoundCodecPrims \ +SoundGenerationPlugin \ +SoundPlugin \ +StarSqueakPlugin \ +SurfacePlugin \ +VMProfileLinuxSupportPlugin Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,28 @@ +#!/bin/bash +# debug Spur VM with VM profiler and threaded heartbeat +INSTALLDIR=debug/cogspurlinuxht +OPT="-g3 -O0 -DDEBUGVM=1" + +if [ $# -ge 1 ]; then + INSTALLDIR="$1"; shift +fi + +echo -n "clean? " +read a +case $a in +n|no|N|NO) echo "ok but this isn't safe!!";; +*) test -f Makefile && make reallyclean +esac +test -f config.h || ../../../platforms/unix/config/configure --without-npsqueak \ + --with-vmversion=5.0 \ + --with-src=spursrc --with-plugins=src/plugins \ + CC="gcc -m32" \ + CXX="g++ -m32" \ + CFLAGS="$OPT -msse2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -DCOGMTVM=0" \ + LIBS="-lpthread -luuid" \ + LDFLAGS=-Wl,-z,now +rm -f vm/sqUnixMain.o # nuke version info +rm -rf ../../../products/$INSTALLDIR +# prefer make install prefix=`readlink -f \`pwd\`/../../../products/$INSTALLDIR` +# but older linux readlinks lack the -f flag +make install-squeak install-plugins prefix=`(cd ../../../;pwd)`/products/$INSTALLDIR 2>&1 | tee LOG Property changes on: branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/mvm ___________________________________________________________________ Added: svn:executable + * Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.ext =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.ext (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.ext 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,12 @@ +# Copied, perhaps edited, from ../../src/examplePlugins.ext +EXTERNAL_PLUGINS = \ +B3DAcceleratorPlugin \ +BochsIA32Plugin \ +GdbARMPlugin \ +SqueakFFIPrims \ +SqueakSSL \ +LocalePlugin \ +UnicodePlugin \ +UnixOSProcessPlugin \ +UUIDPlugin \ +XDisplayControlPlugin Added: branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.int =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.int (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/build.debug/plugins.int 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,37 @@ +# Copied, perhaps edited, from ../../src/examplePlugins.int +INTERNAL_PLUGINS = \ +ADPCMCodecPlugin \ +AioPlugin \ +AsynchFilePlugin \ +B2DPlugin \ +BitBltPlugin \ +BMPReadWriterPlugin \ +CroquetPlugin \ +ZipPlugin \ +DropPlugin \ +DSAPrims \ +FFTPlugin \ +FileCopyPlugin \ +FilePlugin \ +FloatArrayPlugin \ +FloatMathPlugin \ +IA32ABI \ +JoystickTabletPlugin \ +JPEGReaderPlugin \ +JPEGReadWriter2Plugin \ +Klatt \ +LargeIntegers \ +Matrix2x3Plugin \ +MIDIPlugin \ +MiscPrimitivePlugin \ +Mpeg3Plugin \ +RePlugin \ +SecurityPlugin \ +SerialPlugin \ +SocketPlugin \ +SoundCodecPrims \ +SoundGenerationPlugin \ +SoundPlugin \ +StarSqueakPlugin \ +SurfacePlugin \ +VMProfileLinuxSupportPlugin Added: branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,6 @@ +#!/bin/sh +trap 'exit 2' HUP INT PIPE TERM +for d in `dirname $0`/build*; do + (cd $d + echo y | ./mvm "$@") +done Property changes on: branches/Cog/build.linux32ARM/squeak.cog.spur/makeallclean ___________________________________________________________________ Added: svn:executable + * Added: branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty =================================================================== --- branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty (rev 0) +++ branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty 2015-04-22 18:36:16 UTC (rev 3313) @@ -0,0 +1,6 @@ +#!/bin/sh +trap 'exit 2' HUP INT PIPE TERM +for d in `dirname $0`/build*; do + (cd $d + echo n | ./mvm "$@") +done Property changes on: branches/Cog/build.linux32ARM/squeak.cog.spur/makealldirty ___________________________________________________________________ Added: svn:executable + * Modified: branches/Cog/nsspursrc/vm/cogit.c =================================================================== --- branches/Cog/nsspursrc/vm/cogit.c 2015-04-17 19:34:25 UTC (rev 3312) +++ branches/Cog/nsspursrc/vm/cogit.c 2015-04-22 18:36:16 UTC (rev 3313) @@ -1,23954 +1,16 @@ /* Automatically generated by - CCodeGenerator VMMaker.oscog-eem.1207 uuid: 4a338677-029f-42ac-b38d-2bc5ecc213f1 - from - StackToRegisterMappingCogit VMMaker.oscog-eem.1207 uuid: 4a338677-029f-42ac-b38d-2bc5ecc213f1 + Cogit VMMaker.oscog-eem.1237 uuid: 0864d0ce-8b0f-4415-ab43-13e2581488d5 */ -static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.1207 uuid: 4a338677-029f-42ac-b38d-2bc5ecc213f1 " __DATE__ ; -char *__cogitBuildInfo = __buildInfo; +#if defined(__ARM_ARCH__) || defined(__arm__) || defined(__arm32__) || defined(ARM32) +# include "cogitARMv5.c" -#include <stddef.h> -#include "sq.h" -#include "sqCogStackAlignment.h" -#include "dispdbg.h" -#include "cogmethod.h" -#include "nssendcache.h" -#if COGMTVM -#include "cointerpmt.h" -#else -#include "cointerp.h" -#endif -#include "cogit.h" +#elif defined(_M_I386) || defined(_X86_) || defined(i386) || defined(i486) || defined(i586) || defined(i686) || defined(__i386__) || defined(__386__) || defined(X86) || defined(I386) -typedef struct _AbstractInstruction { - unsigned char opcode; - unsigned char machineCodeSize; - unsigned char maxSize; - unsigned long operands [3]; - unsigned long address; - struct _AbstractInstruction *dependent; - unsigned char machineCode [10]; - } AbstractInstruction; +# include "cogitIA32.c" -#define CogIA32Compiler AbstractInstruction - - -typedef struct { - AbstractInstruction *fakeHeader; - AbstractInstruction *fillInstruction; - sqInt numArgs; - sqInt numCopied; - sqInt numInitialNils; - sqInt startpc; - AbstractInstruction *entryLabel; - AbstractInstruction *stackCheckLabel; - sqInt span; - } BlockStart; - -#define CogBlockStart BlockStart - - -typedef struct _BytecodeDescriptor { - sqInt (*generator )(void); - sqInt (*spanFunction )(struct _BytecodeDescriptor *,sqInt,sqInt,sqInt); - sqInt (*needsFrameFunction )(sqInt); - signed char stackDelta; - unsigned char opcode; - unsigned char numBytes; - unsigned isBranchTrue : 1; - unsigned isBranchFalse : 1; - unsigned isReturn : 1; - unsigned isBlockCreation : 1; - unsigned isMapped : 1; - unsigned isMappedInBlock : 1; - unsigned isExtension : 1; - unsigned hasIRC : 1; - } BytecodeDescriptor; - -#define CogBytecodeDescriptor BytecodeDescriptor - - -typedef struct { - sqInt annotation; - AbstractInstruction *instruction; - } InstructionAnnotation; - -#define CogInstructionAnnotation InstructionAnnotation - - -typedef struct { - sqInt (*primitiveGenerator )(void); - sqInt primNumArgs; - sqInt (*enabled )(sqInt); - } PrimitiveDescriptor; - -#define CogPrimitiveDescriptor PrimitiveDescriptor - - -typedef struct { - AbstractInstruction *targetInstruction; - sqInt instructionIndex; - sqInt simStackPtr; - } BytecodeFixup; - -#define CogSSBytecodeFixup BytecodeFixup - - -typedef struct { - char type; - char spilled; - char annotateUse; - sqInt registerr; - sqInt offset; - sqInt constant; - sqInt bcptr; - } CogSimStackEntry; - - -typedef struct { - sqInt isReceiverResultRegLive; - CogSimStackEntry *ssEntry; - } CogSSOptStatus; - - - -/*** Constants ***/ -#define AddCqR 95 -#define AddCwR 102 -#define AddRdRd 110 -#define AddRR 88 -#define AlignmentNops 2 -#define AltBlockCreationBytecodeSize 3 -#define AltFirstSpecialSelector 80 -#define AndCqR 97 -#define AndCqRR 108 -#define AndCwR 104 -#define AndRR 90 -#define AnnotationShift 5 -#define Arg0Reg -7 -#define Arg1Reg -8 -#define ArithmeticShiftRightCqR 81 -#define ArithmeticShiftRightRR 82 -#define BadRegisterSet 1 -#define BlockCreationBytecodeSize 4 -#define BytecodeSetHasDirectedSuperSend 0 -#define Call 9 -#define CallFull 10 -#define CDQ 117 -#define ClassArrayCompactIndex 51 -#define ClassBlockClosureCompactIndex 37 -#define ClassFloatCompactIndex 34 -#define ClassMethodContextCompactIndex 36 -#define ClassReg -5 -#define ClosureFirstCopiedValueIndex 3 -#define ClosureIndex 4 -#define ClosureNumArgsIndex 2 -#define ClosureOuterContextIndex 0 -#define ClosureStartPCIndex 1 -#define CMBlock 3 -#define CMClosedPIC 4 -#define CMFree 1 -#define CMMaxUsageCount 7 -#define CMMethod 2 -#define CMOpenPIC 5 -#define CMPXCHGAwR 125 -#define CMPXCHGMwrR 126 -#define CmpCqR 94 -#define CmpCwR 101 -#define CmpRdRd 109 -#define CmpRR 87 -#define ConstZero 1 -#define ConvertRRd 116 -#define CPUID 120 -#define Debug DEBUGVM -#define DisplacementMask 0x1F -#define DisplacementX2N 0 -#define DivRdRd 113 -#define DPFPReg0 -9 -#define DPFPReg1 -10 -#define DPFPReg2 -11 -#define DPFPReg3 -12 -#define DPFPReg4 -13 -#define DPFPReg5 -14 -#define DPFPReg6 -15 -#define DPFPReg7 -16 -#define EAX 0 -#define EBP 5 -#define EBX 3 -#define ECX 1 -#define EDI 7 -#define EDX 2 -#define EncounteredUnknownBytecode -6 -#define ESI 6 -#define ESP 4 -#define Fill16 5 -#define Fill32 6 -#define FillFromWord 7 -#define FirstAnnotation 64 -#define FirstJump 14 -#define FirstShortJump 18 -#define FirstSpecialSelector 176 -#define FoxCallerSavedIP 4 -#define FoxMethod -4 -#define FoxMFReceiver -12 -#define FoxSavedFP 0 -#define FoxThisContext -8 -#define FPReg -1 -#define GCModeBecome 8 -#define GCModeFull 1 -#define GCModeNewSpace 2 -#define GPRegMax -3 -#define GPRegMin -8 -#define HasBytecodePC 4 -#define HeaderIndex 0 -#define IDIVR 118 -#define IMULRR 119 -#define InstanceSpecificationIndex 2 -#define InstructionPointerIndex 1 -#define InsufficientCodeSpace -2 -#define IsAbsPCReference 3 -#define IsAnnotationExtension 1 -#define IsDirectedSuperSend 9 -#define IsDisplacementX2N 0 -#define IsNSDynamicSuperSend 11 -#define IsNSSelfSend 10 -#define IsNSSendCall 6 -#define IsObjectReference 2 -#define IsRelativeCall 5 -#define IsSendCall 7 -#define IsSuperSend 8 -#define Jump 18 -#define JumpAbove 33 -#define JumpAboveOrEqual 32 -#define JumpBelow 31 -#define JumpBelowOrEqual 34 -#define JumpCarry 25 -#define JumpFPEqual 35 -#define JumpFPGreater 39 -#define JumpFPGreaterOrEqual 40 -#define JumpFPLess 37 -#define JumpFPLessOrEqual 38 -#define JumpFPNotEqual 36 -#define JumpFPOrdered 41 -#define JumpFPUnordered 42 -#define JumpFull 14 -#define JumpGreater 29 -#define JumpGreaterOrEqual 28 -#define JumpLess 27 -#define JumpLessOrEqual 30 -#define JumpLong 15 -#define JumpLongNonZero 17 -#define JumpLongZero 16 -#define JumpNegative 21 -#define JumpNoCarry 26 -#define JumpNonNegative 22 -#define JumpNonZero 20 -#define JumpNoOverflow 24 -#define JumpOverflow 23 -#define JumpR 12 -#define JumpZero 19 -#define Label 1 -#define LargeContextSlots 62 -#define LastJump 42 -#define LFENCE 121 -#define LinkReg -17 -#define LOCK 124 -#define LoadEffectiveAddressMwrR 78 -#define LogicalShiftLeftCqR 85 -#define LogicalShiftLeftRR 86 -#define LogicalShiftRightCqR 83 -#define LogicalShiftRightRR 84 -#define MapEnd 0 -#define MaxCompiledPrimitiveIndex 222 -#define MaxMethodSize 65535 -#define MaxNegativeErrorCode -8 -#define MaxNumArgs 15 -#define MaxStackAllocSize 1572864 -#define MaxStackCheckOffset 0xFFF -#define MaxX2NDisplacement 992 -#define MethodCacheClass 2 -#define MethodCacheMask 0xFFC -#define MethodCacheMethod 3 -#define MethodCacheSelector 1 -#define MethodIndex 3 -#define MethodTooBig -4 -#define MFENCE 122 -#define MFMethodFlagHasContextFlag 1 -#define MFMethodFlagIsBlockFlag 2 -#define ModReg 3 -#define ModRegInd 0 -#define ModRegRegDisp32 2 -#define ModRegRegDisp8 1 -#define MoveAwR 44 -#define MoveCqR 66 -#define MoveCwR 67 -#define MoveM16rR 54 -#define MoveM64rRd 71 -#define MoveMbrR 62 -#define MoveMwrR 48 -#define MoveRAw 45 -#define MoveRdM64r 72 -#define MoveRdRd 70 -#define MoveRMbr 63 -#define MoveRMwr 49 -#define MoveRR 43 -#define MoveRXbrR 65 -#define MoveRXwrR 51 -#define MoveXbrRR 64 -#define MoveXwrRR 50 -#define MULTIPLEBYTECODESETS 1 -#define MulRdRd 112 -#define NegateR 80 -#define NewspeakVM 1 -#define Nop 8 -#define NotFullyInitialized -1 -#define NSCClassTagIndex 0 -#define NSCEnclosingObjectIndex 1 -#define NSCTargetIndex 2 -#define NumObjRefsInRuntime 0 -#define NumOopsPerNSC 6 -#define NumSendTrampolines 4 -#define NumTrampolines 70 -#define OrCqR 98 -#define OrCwR 105 -#define OrRR 91 -#define PCReg -19 -#define PopR 73 -#define PrefetchAw 77 -#define PrimCallCollectsProfileSamples 8 -#define PrimCallDoNotJIT 32 -#define PrimCallMayCallBack 4 -#define PrimCallNeedsNewMethod 1 -#define PrimCallNeedsPrimitiveFunction 2 -#define PrimErrWritePastObject 17 -#define PushCq 75 -#define PushCw 76 -#define PushR 74 -#define ReceiverIndex 5 -#define ReceiverResultReg -3 -#define RetN 11 -#define RISCTempReg -18 -#define SelectorCannotInterpret 34 -#define SelectorDoesNotUnderstand 20 -#define SenderIndex 0 -#define SendNumArgsReg -6 -#define SFENCE 123 -#define ShouldNotJIT -8 -#define SIB1 0 -#define SIB4 2 -#define SistaVM 0 -#define SmallContextSlots 22 -#define SPReg -2 -#define SqrtRd 115 -#define SSBaseOffset 1 -#define SSConstant 2 -#define SSRegister 3 -#define SSSpill 4 -#define StackPointerIndex 2 -#define Stop 13 -#define SubCqR 96 -#define SubCwR 103 -#define SubRdRd 111 -#define SubRR 89 -#define TempReg -4 -#define UnimplementedPrimitive -7 -#define ValueIndex 1 -#define VarBaseReg -20 -#define XCHGAwR 127 -#define XCHGMwrR 128 -#define XCHGRR 129 -#define XMM0L 0 -#define XMM1L 2 -#define XMM2L 4 -#define XMM3L 6 -#define XMM4L 8 -#define XMM5L 10 -#define XMM6L 12 -#define XMM7L 14 -#define XorCwR 106 -#define XorRR 92 -#define YoungSelectorInPIC -5 - - -/*** Function Prototypes ***/ - - -#if !PRODUCTION && defined(__GNUC__) && !defined(NoDbgRegParms) -# define NoDbgRegParms __attribute__ ((regparm (0))) +#else +# error As yet no Cogit implementation appears to exist for your platform. +# error Consider implementing it, starting by adding a subclass of CogAbstractInstruction. #endif - -#if !defined(NoDbgRegParms) -# define NoDbgRegParms /*empty*/ -#endif - - - -#if defined(__GNUC__) && !defined(NeverInline) -# define NeverInline __attribute__ ((noinline)) -#endif - -#if !defined(NeverInline) -# define NeverInline /*empty*/ -#endif - -static sqInt abstractRegisterForConcreteRegister(AbstractInstruction * self_in_abstractRegisterForConcreteRegister, sqInt reg) NoDbgRegParms; -static AbstractInstruction * addDependent(AbstractInstruction * self_in_addDependent, AbstractInstruction *anInstruction) NoDbgRegParms; -static sqInt availableRegisterOrNilFor(AbstractInstruction * self_in_availableRegisterOrNilFor, sqInt liveRegsMask) NoDbgRegParms; -static sqInt genAlignCStackSavingRegistersnumArgswordAlignment(AbstractInstruction * self_in_genAlignCStackSavingRegistersnumArgswordAlignment, sqInt saveRegs, sqInt numArgs, sqInt alignment) NoDbgRegParms; -static AbstractInstruction * generateICacheFlush(AbstractInstruction * self_in_generateICacheFlush) NoDbgRegParms; -static AbstractInstruction * genWriteCResultIntoReg(AbstractInstruction * self_in_genWriteCResultIntoReg, sqInt abstractRegister) NoDbgRegParms; -static AbstractInstruction * getJmpTarget(AbstractInstruction * self_in_getJmpTarget) NoDbgRegParms; -static sqInt isAFixup(AbstractInstruction * self_in_isAFixup, void *fixupOrAddress) NoDbgRegParms; -static sqInt isAnInstruction(AbstractInstruction * self_in_isAnInstruction, AbstractInstruction *addressOrInstruction) NoDbgRegParms; -static sqInt isJump(AbstractInstruction * self_in_isJump) NoDbgRegParms; -static sqInt isLongJump(AbstractInstruction * self_in_isLongJump) NoDbgRegParms; -static unsigned long labelOffset(AbstractInstruction * self_in_labelOffset) NoDbgRegParms; -static sqInt numICacheFlushOpcodes(AbstractInstruction * self_in_numICacheFlushOpcodes) NoDbgRegParms; -static AbstractInstruction * resolveJumpTarget(AbstractInstruction * self_in_resolveJumpTarget) NoDbgRegParms; -static sqInt rewriteCallFullAttarget(AbstractInstruction * self_in_rewriteCallFullAttarget, sqInt callSiteReturnAddress, sqInt callTargetAddress) NoDbgRegParms; -static sqInt rewriteJumpFullAttarget(AbstractInstruction * self_in_rewriteJumpFullAttarget, sqInt callSiteReturnAddress, sqInt callTargetAddress) NoDbgRegParms; -static sqInt setLabelOffset(AbstractInstruction * self_in_setLabelOffset, sqInt aValue) NoDbgRegParms; -static AbstractInstruction * updateLabel(AbstractInstruction * self_in_updateLabel, AbstractInstruction *labelInstruction) NoDbgRegParms; -static sqInt wantsNearAddressFor(AbstractInstruction * self_in_wantsNearAddressFor, sqInt anObject) NoDbgRegParms; -static CogMethod * cmHomeMethod(CogBlockMethod * self_in_cmHomeMethod) NoDbgRegParms; -static sqInt isBranch(BytecodeDescriptor * self_in_isBranch) NoDbgRegParms; -static sqInt isUnconditionalBranch(BytecodeDescriptor * self_in_isUnconditionalBranch) NoDbgRegParms; -static sqInt callerSavedRegisterMask(AbstractInstruction * self_in_callerSavedRegisterMask) NoDbgRegParms; -static sqInt callInstructionByteSize(AbstractInstruction * self_in_callInstructionByteSize) NoDbgRegParms; -static sqInt callTargetFromReturnAddress(AbstractInstruction * self_in_callTargetFromReturnAddress, sqInt callSiteReturnAddress) NoDbgRegParms; -static sqInt computeMaximumSize(AbstractInstruction * self_in_computeMaximumSize) NoDbgRegParms; -static usqInt computeShiftRRSize(AbstractInstruction * self_in_computeShiftRRSize) NoDbgRegParms; -static sqInt concreteDPFPRegister(AbstractInstruction * self_in_concreteDPFPRegister, sqInt registerIndex) NoDbgRegParms; -static sqInt concreteRegister(AbstractInstruction * self_in_concreteRegister, sqInt registerIndex) NoDbgRegParms; -static sqInt concretizeAt(AbstractInstruction * self_in_concretizeAt, sqInt actualAddress) NoDbgRegParms; -static usqInt concretizeFill16(AbstractInstruction * self_in_concretizeFill16) NoDbgRegParms; -static usqInt concretizeFill32(AbstractInstruction * self_in_concretizeFill32) NoDbgRegParms; -static usqInt concretizeFillFromWord(AbstractInstruction * self_in_concretizeFillFromWord) NoDbgRegParms; -static sqInt cResultRegister(AbstractInstruction * self_in_cResultRegister) NoDbgRegParms; -static void dispatchConcretize(AbstractInstruction * self_in_dispatchConcretize) NoDbgRegParms; -static AbstractInstruction * genDivRRQuoRem(AbstractInstruction * self_in_genDivRRQuoRem, sqInt abstractRegDivisor, sqInt abstractRegDividend, sqInt abstractRegQuotient, sqInt abstractRegRemainder) NoDbgRegParms; -static AbstractInstruction * generateCheckFeatures(AbstractInstruction * self_in_generateCheckFeatures) NoDbgRegParms; -static AbstractInstruction * generateLowLevelTryLock(AbstractInstruction * self_in_generateLowLevelTryLock, sqInt vmOwnerLockAddress) NoDbgRegParms; -static AbstractInstruction * generateLowLevelUnlock(AbstractInstruction * self_in_generateLowLevelUnlock, sqInt vmOwnerLockAddress) NoDbgRegParms; -static AbstractInstruction * genGetLeafCallStackPointerFunction(AbstractInstruction * self_in_genGetLeafCallStackPointerFunction) NoDbgRegParms; -static sqInt genLoadCStackPointer(AbstractInstruction * self_in_genLoadCStackPointer) NoDbgRegParms; -static sqInt genLoadCStackPointers(AbstractInstruction * self_in_genLoadCStackPointers) NoDbgRegParms; -static sqInt genLoadStackPointers(AbstractInstruction * self_in_genLoadStackPointers) NoDbgRegParms; -static AbstractInstruction * genMulRR(AbstractInstruction * self_in_genMulRR, sqInt regSource, sqInt regDest) NoDbgRegParms; -static sqInt genPassConstasArgument(AbstractInstruction * self_in_genPassConstasArgument, sqInt constant, sqInt zeroRelativeArgIndex) NoDbgRegParms; -static sqInt genPassRegasArgument(AbstractInstruction * self_in_genPassRegasArgument, sqInt abstractRegister, sqInt zeroRelativeArgIndex) NoDbgRegParms; -static AbstractInstruction * genPushRegisterArgsForAbortMissNumArgs(AbstractInstruction * self_in_genPushRegisterArgsForAbortMissNumArgs, sqInt numArgs) NoDbgRegParms; -static AbstractInstruction * genPushRegisterArgsForNumArgs(AbstractInstruction * self_in_genPushRegisterArgsForNumArgs, sqInt numArgs) NoDbgRegParms; -static sqInt genRemoveNArgsFromStack(AbstractInstruction * self_in_genRemoveNArgsFromStack, sqInt n) NoDbgRegParms; -static sqInt genRestoreRegs(AbstractInstruction * self_in_genRestoreRegs) NoDbgRegParms; -static sqInt genRestoreRegsExcept(AbstractInstruction * self_in_genRestoreRegsExcept, sqInt abstractReg) NoDbgRegParms; -static sqInt genSaveRegisters(AbstractInstruction * self_in_genSaveRegisters) NoDbgRegParms; -static sqInt genSaveStackPointers(AbstractInstruction * self_in_genSaveStackPointers) NoDbgRegParms; -static AbstractInstruction * genSubstituteReturnAddress(AbstractInstruction * self_in_genSubstituteReturnAddress, sqInt retpc) NoDbgRegParms; -static sqInt hasLinkRegister(AbstractInstruction * self_in_hasLinkRegister) NoDbgRegParms; -static sqInt hasSSE2Instructions(AbstractInstruction * self_in_hasSSE2Instructions) NoDbgRegParms; -static sqInt hasSSEInstructions(AbstractInstruction * self_in_hasSSEInstructions) NoDbgRegParms; -static sqInt implicitReceiveCacheAt(AbstractInstruction * self_in_implicitReceiveCacheAt, char *callSiteReturnAddress) NoDbgRegParms; -static sqInt inlineCacheTagAt(AbstractInstruction * self_in_inlineCacheTagAt, sqInt callSiteReturnAddress) NoDbgRegParms; -static sqInt instructionSizeAt(AbstractInstruction * self_in_instructionSizeAt, sqInt pc) NoDbgRegParms; -static sqInt isCallPreceedingReturnPC(AbstractInstruction * self_in_isCallPreceedingReturnPC, sqInt mcpc) NoDbgRegParms; -static sqInt isJumpAt(AbstractInstruction * self_in_isJumpAt, sqInt pc) NoDbgRegParms; -static sqInt isPCDependent(AbstractInstruction * self_in_isPCDependent) NoDbgRegParms; -static sqInt isQuick(AbstractInstruction * self_in_isQuick, unsigned long operand) NoDbgRegParms; -static AbstractInstruction * jmpTarget(AbstractInstruction * self_in_jmpTarget, AbstractInstruction *anAbstractInstruction) NoDbgRegParms; -static sqInt jumpLongByteSize(AbstractInstruction * self_in_jumpLongByteSize) NoDbgRegParms; -static sqInt jumpLongConditionalByteSize(AbstractInstruction * self_in_jumpLongConditionalByteSize) NoDbgRegParms; -static sqInt jumpLongTargetBeforeFollowingAddress(AbstractInstruction * self_in_jumpLongTargetBeforeFollowingAddress, sqInt mcpc) NoDbgRegParms; -static sqInt jumpShortByteSize(AbstractInstruction * self_in_jumpShortByteSize) NoDbgRegParms; -static sqInt jumpTargetPCAt(AbstractInstruction * self_in_jumpTargetPCAt, sqInt pc) NoDbgRegParms; -static sqInt leafCallStackPointerDelta(AbstractInstruction * self_in_leafCallStackPointerDelta) NoDbgRegParms; -static sqInt literalBeforeFollowingAddress(AbstractInstruction * self_in_literalBeforeFollowingAddress, sqInt followingAddress) NoDbgRegParms; -static sqInt literalBeforeInlineCacheTagAt(AbstractInstruction * self_in_literalBeforeInlineCacheTagAt, sqInt callSiteReturnAddress) NoDbgRegParms; -static sqInt loadLiteralByteSize(AbstractInstruction * self_in_loadLiteralByteSize) NoDbgRegParms; -static sqInt machineCodeBytes(AbstractInstruction * self_in_machineCodeBytes) NoDbgRegParms; -static AbstractInstruction * maybeEstablishVarBase(AbstractInstruction * self_in_maybeEstablishVarBase) NoDbgRegParms; -static sqInt modRMRO(AbstractInstruction * self_in_modRMRO, sqInt mod, sqInt regMode, sqInt regOpcode) NoDbgRegParms; -static AbstractInstruction * nopsFromto(AbstractInstruction * self_in_nopsFromto, sqInt startAddr, sqInt endAddr) NoDbgRegParms; -static sqInt numCheckFeaturesOpcodes(AbstractInstruction * self_in_numCheckFeaturesOpcodes) NoDbgRegParms; -static sqInt numLowLevelLockOpcodes(AbstractInstruction * self_in_numLowLevelLockOpcodes) NoDbgRegParms; -static AbstractInstruction * padIfPossibleWithNopsFromto(AbstractInstruction * self_in_padIfPossibleWithNopsFromto, sqInt startAddr, sqInt endAddr) NoDbgRegParms; -static AbstractInstruction * relocateCallBeforeReturnPCby(AbstractInstruction * self_in_relocateCallBeforeReturnPCby, sqInt retpc, sqInt delta) NoDbgRegParms; -static AbstractInstruction * relocateJumpBeforeFollowingAddressby(AbstractInstruction * self_in_relocateJumpBeforeFollowingAddressby, sqInt pc, sqInt delta) NoDbgRegParms; -static AbstractInstruction * relocateMethodReferenceBeforeAddressby(AbstractInstruction * self_in_relocateMethodReferenceBeforeAddressby, sqInt pc, sqInt delta) NoDbgRegParms; -static sqInt rewriteCallAttarget(AbstractInstruction * self_in_rewriteCallAttarget, usqInt callSiteReturnAddress, usqInt callTargetAddress) NoDbgRegParms; -static sqInt rewriteInlineCacheAttagtarget(AbstractInstruction * self_in_rewriteInlineCacheAttagtarget, usqInt callSiteReturnAddress, sqInt cacheTag, usqInt callTargetAddress) NoDbgRegParms; -static AbstractInstruction * rewriteInlineCacheTagat(AbstractInstruction * self_in_rewriteInlineCacheTagat, sqInt cacheTag, sqInt callSiteReturnAddress) NoDbgRegParms; -static sqInt rewriteJumpLongAttarget(AbstractInstruction * self_in_rewriteJumpLongAttarget, sqInt callSiteReturnAddress, sqInt callTargetAddress) NoDbgRegParms; -static sqInt setsConditionCodesFor(AbstractInstruction * self_in_setsConditionCodesFor, sqInt aConditionalJumpOpcode) NoDbgRegParms; -static sqInt shiftSetsConditionCodesFor(AbstractInstruction * self_in_shiftSetsConditionCodesFor, sqInt aConditionalJumpOpcode) NoDbgRegParms; -static sqInt sizeHasModrmat(AbstractInstruction * self_in_sizeHasModrmat, sqInt op, sqInt pc) NoDbgRegParms; -static sqInt sizeImmediateGroup1at(AbstractInstruction * self_in_sizeImmediateGroup1at, sqInt op, sqInt pc) NoDbgRegParms; -static usqInt sizePCDependentInstructionAt(AbstractInstruction * self_in_sizePCDependentInstructionAt, sqInt eventualAbsoluteAddress) NoDbgRegParms; -static sqInt stackBytesForNumArgs(AbstractInstruction * self_in_stackBytesForNumArgs, sqInt numArgs) NoDbgRegParms; -static sqInt stackPageInterruptHeadroomBytes(AbstractInstruction * self_in_stackPageInterruptHeadroomBytes) NoDbgRegParms; -static AbstractInstruction * storeLiteralbeforeFollowingAddress(AbstractInstruction * self_in_storeLiteralbeforeFollowingAddress, sqInt literal, sqInt followingAddress) NoDbgRegParms; -static sqInt sib(AbstractInstruction * self_in_sib, sqInt scale, sqInt indexReg, sqInt baseReg) NoDbgRegParms; -static sqInt twoByteInstructionSizeAt(AbstractInstruction * self_in_twoByteInstructionSizeAt, sqInt pc) NoDbgRegParms; -static sqInt unsignedShortAt(AbstractInstruction * self_in_unsignedShortAt, sqInt byteAddress) NoDbgRegParms; -static AbstractInstruction * gAndCqR(sqInt quickConstant, sqInt reg) NoDbgRegParms; -static AbstractInstruction * gArithmeticShiftRightRR(sqInt reg1, sqInt reg2) NoDbgRegParms; -sqInt abortOffset(void); -static sqInt abstractInstructionfollows(AbstractInstruction *theAbstractInstruction, AbstractInstruction *anAbstractInstruction) NoDbgRegParms; -static void addCleanBlockStarts(void); -void addCogMethodsToHeapMap(void); -static sqInt addressIsInFixups(AbstractInstruction *address) NoDbgRegParms; -static sqInt addressIsInInstructions(AbstractInstruction *address) NoDbgRegParms; -static sqInt addressOfEndOfCaseinCPIC(sqInt n, CogMethod *cPIC) NoDbgRegParms; -static sqInt alignUptoRoutineBoundary(sqInt anAddress) NoDbgRegParms; -static sqInt allMachineCodeObjectReferencesValid(void); -static sqInt allMethodsHaveCorrectHeader(void); -static AbstractInstruction * annotateAbsolutePCRef(AbstractInstruction *abstractInstruction) NoDbgRegParms; -static AbstractInstruction * annotateBytecode(AbstractInstruction *abstractInstruction) NoDbgRegParms; -static AbstractInstruction * annotateobjRef(AbstractInstruction *abstractInstruction, sqInt anOop) NoDbgRegParms; -static AbstractInstruction * annotatewith(AbstractInstruction *abstractInstruction, sqInt annotationFlag) NoDbgRegParms; -static sqInt annotationForMcpcin(sqInt mcpc, CogMethod *cogHomeMethod) NoDbgRegParms; -static void assertSaneJumpTarget(AbstractInstruction *jumpTarget) NoDbgRegParms; -static sqInt blockCreationBytecodeSizeForHeader(sqInt methodHeader) NoDbgRegParms; -static sqInt blockDispatchTargetsForperformarg(CogMethod *cogMethod, usqInt (*binaryFunction)(sqInt mcpc, sqInt arg), sqInt arg) NoDbgRegParms; -sqInt bytecodePCForstartBcpcin(sqInt mcpc, sqInt startbcpc, CogBlockMethod *cogMethod); -static AbstractInstruction * CallNewspeakSend(sqInt callTarget) NoDbgRegParms; -static AbstractInstruction * CallRTregistersToBeSavedMask(sqInt callTarget, sqInt registersToBeSaved) NoDbgRegParms; -static AbstractInstruction * gCall(sqInt callTarget) NoDbgRegParms; -static AbstractInstruction * gCmpCqR(sqInt quickConstant, sqInt reg) NoDbgRegParms; -static AbstractInstruction * gCmpCwR(sqInt wordConstant, sqInt reg) NoDbgRegParms; -static AbstractInstruction * gCmpRR(sqInt reg1, sqInt reg2) NoDbgRegParms; -void callCogCodePopReceiver(void); -void callCogCodePopReceiverAndClassRegs(void); -sqInt ceCPICMissreceiver(CogMethod *cPIC, sqInt receiver); -sqInt ceSICMiss(sqInt receiver); -void checkAssertsEnabledInCogit(void); -static sqInt checkIfValidOopRefAndTargetpccogMethod(sqInt annotation, char *mcpc, sqInt cogMethod) NoDbgRegParms; -static sqInt checkIfValidOopRefpccogMethod(sqInt annotation, char *mcpc, sqInt cogMethod) NoDbgRegParms; -sqInt checkIntegrityOfObjectReferencesInCode(sqInt gcModes); -static sqInt checkMaybeObjRefAt(sqInt mcpc) NoDbgRegParms; -static sqInt checkValidObjectReferencesInClosedPIC(CogMethod *cPIC) NoDbgRegParms; -char * codeEntryFor(char *address); -char * codeEntryNameFor(char *address); -sqInt cogCodeBase(void); -sqInt cogCodeConstituents(void); -static sqInt cogExtendPICCaseNMethodtagisMNUCase(CogMethod *cPIC, sqInt caseNMethod, sqInt caseNTag, sqInt isMNUCase) NoDbgRegParms; -void cogitPostGCAction(sqInt gcMode); -sqInt cogMethodDoesntLookKosher(CogMethod *cogMethod); -CogMethod * cogMNUPICSelectorreceivermethodOperandnumArgs(sqInt selector, sqInt rcvr, sqInt methodOperand, sqInt numArgs); -static CogMethod * cogOpenPICSelectornumArgs(sqInt selector, sqInt numArgs) NoDbgRegParms; -static CogMethod * cogPICSelectornumArgsCase0MethodCase1MethodtagisMNUCase(sqInt selector, sqInt numArgs, CogMethod *case0CogMethod, sqInt case1MethodOrNil, sqInt case1Tag, sqInt isMNUCase) NoDbgRegParms; -CogMethod * cogselector(sqInt aMethodObj, sqInt aSelectorOop); -void compactCogCompiledCode(void); -static AbstractInstruction * compileAbort(void); -static sqInt compileBlockDispatchFromto(sqInt lowBlockStartIndex, sqInt highBlockStartIndex) NoDbgRegParms; -static void compileBlockEntry(BlockStart *blockStart) NoDbgRegParms; -static void compileCallFornumArgsargargargargresultRegsaveRegs(void *aRoutine, sqInt numArgs, sqInt regOrConst0, sqInt regOrConst1, sqInt regOrConst2, sqInt regOrConst3, sqInt resultRegOrNil, sqInt saveRegs) NoDbgRegParms; -static sqInt compileClosedPICPrototype(void); -static AbstractInstruction * compileCPICEntry(void); -static sqInt compileCPICCase0Case1MethodtagisMNUCasenumArgs(CogMethod *cPIC, CogMethod *case0CogMethod, sqInt case1Method, sqInt case1Tag, sqInt isMNUCase, sqInt numArgs) NoDbgRegParms; -static void compileEntry(void); -static sqInt compileMethodBody(void); -static sqInt compileMNUCPICmethodOperandnumArgs(CogMethod *cPIC, sqInt methodOperand, sqInt numArgs) NoDbgRegParms; -static sqInt compilePICAbort(sqInt numArgs) NoDbgRegParms; -static sqInt compilePrimitive(void); -static void compileTrampolineFornumArgsargargargargsaveRegspushLinkRegresultReg(void *aRoutine, sqInt numArgs, sqInt regOrConst0, sqInt regOrConst1, sqInt regOrConst2, sqInt regOrConst3, sqInt saveRegs, sqInt pushLinkReg, sqInt resultRegOrNil) NoDbgRegParms; -static void computeEntryOffsets(void); -static void computeMaximumSizes(void); -static sqInt cPICHasForwardedClass(CogMethod *cPIC) NoDbgRegParms; -static sqInt cPICHasFreedTargets(CogMethod *cPIC) NoDbgRegParms; -static sqInt cPICHasTarget(CogMethod *cPIC, CogMethod *targetMethod) NoDbgRegParms; -static AbstractInstruction * gDivRRQuoRem(sqInt rDivisor, sqInt rDividend, sqInt rQuotient, sqInt rRemainder) NoDbgRegParms; -static sqInt endPCOf(sqInt aMethod) NoDbgRegParms; -void enterCogCodePopReceiver(void); -static sqInt extABytecode(void); -static sqInt extBBytecode(void); -static sqInt fillInBlockHeadersAt(sqInt startAddress) NoDbgRegParms; -static CogMethod * fillInCPICHeadersizenumArgsnumCaseshasMNUCaseselector(CogMethod *pic, sqInt size, sqInt numArgs, sqInt numCases, sqInt hasMNUCase, sqInt selector) NoDbgRegParms; -static CogMethod * fillInMethodHeadersizeselector(CogMethod *method, sqInt size, sqInt selector) NoDbgRegParms; -static CogMethod * fillInOPICHeadersizenumArgsselector(CogMethod *pic, sqInt size, sqInt numArgs, sqInt selector) NoDbgRegParms; -static usqInt findBlockMethodWithEntrystartBcpc(sqInt blockEntryMcpc, sqInt startBcpc) NoDbgRegParms; -static sqInt findMapLocationForMcpcinMethod(sqInt targetMcpc, CogMethod *cogMethod) NoDbgRegParms; -CogBlockMethod * findMethodForStartBcpcinHomeMethod(sqInt startbcpc, CogMethod *cogMethod); -static sqInt findIsBackwardBranchMcpcBcpcMatchingMcpc(BytecodeDescriptor *descriptor, sqInt isBackwardBranch, char *mcpc, sqInt bcpc, void *targetMcpc) NoDbgRegParms; -void followForwardedLiteralsIn(CogMethod *cogMethod); -void followForwardedMethods(void); -static sqInt followMaybeObjRefAt(sqInt mcpc) NoDbgRegParms; -static sqInt followMethodReferencesInClosedPIC(CogMethod *cPIC) NoDbgRegParms; -static void freePICsWithFreedTargets(void); -void freeUnmarkedMachineCode(void); -static sqInt genCheckForInterruptsTrampoline(void); -static void (*genEnilopmartForandandforCallcalled(sqInt regArg1, sqInt regArg2, sqInt regArg3, sqInt forCall, char *trampolineName))(void) NoDbgRegParms; -static void genEnilopmartReturn(sqInt forCall) NoDbgRegParms; -static void generateCaptureCStackPointers(sqInt captureFramePointer) NoDbgRegParms; -static void generateClosedPICPrototype(void); -static CogMethod * generateCogMethod(sqInt selector) NoDbgRegParms; -static sqInt generateInstructionsAt(sqInt eventualAbsoluteAddress) NoDbgRegParms; -static sqInt generateMapAtstart(sqInt addressOrNull, sqInt startAddress) NoDbgRegParms; -static void generateNewspeakRuntime(void); -static void generateOpenPICPrototype(void); -static void generateRunTimeTrampolines(void); -static void generateStackPointerCapture(void); -static void generateTrampolines(void); -static void generateVMOwnerLockFunctions(void); -static sqInt genGetLeafCallStackPointer(void); -static sqInt genInnerPICAbortTrampoline(char *name) NoDbgRegParms; -static sqInt genLoadCStackPointersForPrimCall(void); -static sqInt genNonLocalReturnTrampoline(void); -static sqInt genNSSendTrampolineFornumArgscalled(void *aRoutine, sqInt numArgs, char *aString) NoDbgRegParms; -static sqInt genReturnTrampolineForcalledarg(void *aRoutine, char *aString, sqInt regOrConst0) NoDbgRegParms; -static sqInt genSafeTrampolineForcalled(void *aRoutine, char *aString) NoDbgRegParms; -static sqInt genSafeTrampolineForcalledarg(void *aRoutine, char *aString, sqInt regOrConst0) NoDbgRegParms; -static sqInt genSafeTrampolineForcalledargarg(void *aRoutine, char *aString, sqInt regOrConst0, sqInt regOrConst1) NoDbgRegParms; -static sqInt genSmalltalkToCStackSwitch(void); -static sqInt genTrampolineForcalled(void *aRoutine, char *aString) NoDbgRegParms; -static sqInt genTrampolineForcalledargargargresult(void *aRoutine, char *aString, sqInt regOrConst0, sqInt regOrConst1, sqInt regOrConst2, sqInt resultReg) NoDbgRegParms; -static sqInt genTrampolineForcalledargargresult(void *aRoutine, char *aString, sqInt regOrConst0, sqInt regOrConst1, sqInt resultReg) NoDbgRegParms; -static sqInt genTrampolineForcalledargresult(void *aRoutine, char *aString, sqInt regOrConst0, sqInt resultReg) NoDbgRegParms; -static sqInt genTrampolineForcallednumArgsargargargargsaveRegspushLinkRegresultRegappendOpcodes(void *aRoutine, char *trampolineName, sqInt numArgs, sqInt regOrConst0, sqInt regOrConst1, sqInt regOrConst2, sqInt regOrConst3, sqInt saveRegs, sqInt pushLinkReg, sqInt resultRegOrNil, sqInt appendBoolean) NoDbgRegParms; -static AbstractInstruction * gen(sqInt opcode) NoDbgRegParms; -static AbstractInstruction * genoperand(sqInt opcode, sqInt operand) NoDbgRegParms; -static AbstractInstruction * genoperandoperand(sqInt opcode, sqInt operandOne, sqInt operandTwo) NoDbgRegParms; -static AbstractInstruction * genoperandoperandoperand(sqInt opcode, sqInt operandOne, sqInt operandTwo, sqInt operandThree) NoDbgRegParms; -static sqInt getLiteral(sqInt litIndex) NoDbgRegParms; -static sqInt incrementUsageOfTargetIfLinkedSendmcpcignored(sqInt annotation, char *mcpc, sqInt superfluity) NoDbgRegParms; -static sqInt initialClosedPICUsageCount(void); -static void initializeBackend(void); -void initializeCodeZoneFromupTo(sqInt startAddress, sqInt endAddress); -static sqInt initialMethodUsageCount(void); -static sqInt initialOpenPICUsageCount(void); -static sqInt inverseBranchFor(sqInt opcode) NoDbgRegParms; -static sqInt isBackwardBranchatextsin(BytecodeDescriptor *descriptor, sqInt pc, sqInt nExts, sqInt aMethodObj) NoDbgRegParms; -static sqInt isPCMappedAnnotation(sqInt annotation) NoDbgRegParms; -sqInt isPCWithinMethodZone(void *address); -sqInt isSendReturnPC(sqInt retpc); -static AbstractInstruction * gJumpFPEqual(void *jumpTarget) NoDbgRegParms; -static AbstractInstruction * gJumpFPGreaterOrEqual(void *jumpTarget) NoDbgRegParms; -static AbstractInstruction * gJumpFPGreater(void *jumpTarget) NoDbgRegParms; -static AbstractInstruction * gJumpFPLessOrEqual(void *jumpTarget) NoDbgRegParms; -static AbstractInstruction * gJumpFPLess(void *jumpTarget) NoDbgRegParms; -static AbstractInstruction * gJumpFPNotEqual(void *jumpTarget) NoDbgRegParms; -static AbstractInstruction * gLabel(void); -static AbstractInstruction * gLogicalShiftLeftCqR(sqInt quickConstant, sqInt reg) NoDbgRegParms; -static AbstractInstruction * lastOpcode(void); -void linkNSSendCacheclassTagenclosingObjecttargetcaller(NSSendCache *nsSendCache, sqInt classTag, sqInt enclosingObject, CogMethod *targetMethod, CogMethod *callingMethod); -void linkSendAtintooffsetreceiver(sqInt callSiteReturnAddress, CogMethod *sendingMethod, CogMethod *targetMethod, sqInt theEntryOffset, sqInt receiver); -static void loadSubsequentBytesForDescriptorat(BytecodeDescriptor *descriptor, sqInt pc) NoDbgRegParms; -static AbstractInstruction * gMoveAwR(sqInt address, sqInt reg) NoDbgRegParms; -static AbstractInstruction * gMoveCwR(sqInt wordConstant, sqInt reg) NoDbgRegParms; -static AbstractInstruction * gMoveMwrR(sqInt offset, sqInt baseReg, sqInt destReg) NoDbgRegParms; -static AbstractInstruction * gMoveRMwr(sqInt sourceReg, sqInt offset, sqInt baseReg) NoDbgRegParms; -static AbstractInstruction * gMoveRR(sqInt reg1, sqInt reg2) NoDbgRegParms; -static AbstractInstruction * gMulRR(sqInt reg1, sqInt reg2) NoDbgRegParms; -static sqInt mapEndFor(CogMethod *cogMethod) NoDbgRegParms; -static sqInt mapForperformUntilarg(CogMethod *cogMethod, int (*functionSymbol)(sqInt annotation, char *mcpc, sqInt arg), sqInt arg) NoDbgRegParms; -static sqInt mapObjectReferencesInClosedPIC(CogMethod *cPIC) NoDbgRegParms; -static void mapObjectReferencesInGeneratedRuntime(void); -static void mapObjectReferencesInMachineCodeForBecome(void); -static void mapObjectReferencesInMachineCodeForFullGC(void); -static void mapObjectReferencesInMachineCodeForYoungGC(void); -void mapObjectReferencesInMachineCode(sqInt gcMode); -void markAndTraceMachineCodeOfMarkedMethods(void); -static void markAndTraceObjectReferencesInGeneratedRuntime(void); -static sqInt markLiteralspcmethod(sqInt annotation, char *mcpc, sqInt cogMethod) NoDbgRegParms; -void markMethodAndReferents(CogBlockMethod *aCogMethod); -usqInt maxCogMethodAddress(void); -static sqInt maybeAllocAndInitIRCs(void); -static sqInt maybeFreeCogMethodDoesntLookKosher(CogMethod *cogMethod) NoDbgRegParms; -static sqInt maybeGenerateCheckFeatures(void); -static sqInt maybeGenerateICacheFlush(void); -static void maybeMarkCountersIn(CogMethod *cogMethod) NoDbgRegParms; -static sqInt mclassIsSmallInteger(sqInt ignoredPrimIndex) NoDbgRegParms; -usqInt mcPCForBackwardBranchstartBcpcin(sqInt bcpc, sqInt startbcpc, CogBlockMethod *cogMethod); -static sqInt methodhasSameCodeAscheckPenultimate(sqInt methodA, sqInt methodB, sqInt comparePenultimateLiteral) NoDbgRegParms; -sqInt minCogMethodAddress(void); -sqInt mnuOffset(void); -static AbstractInstruction * gNegateR(sqInt reg) NoDbgRegParms; -static sqInt needsFrameIfInBlock(sqInt stackDelta) NoDbgRegParms; -static sqInt needsFrameNever(sqInt stackDelta) NoDbgRegParms; -static sqInt noAssertMethodClassAssociationOf(sqInt methodPointer) NoDbgRegParms; -static sqInt noCogMethodsMaximallyMarked(void); -static sqInt noTargetsFreeInClosedPIC(CogMethod *cPIC) NoDbgRegParms; -static sqInt outputInstructionsAt(sqInt startAddress) NoDbgRegParms; -static sqInt outputInstructionsForGeneratedRuntimeAt(sqInt startAddress) NoDbgRegParms; -static AbstractInstruction * gPopR(sqInt reg) NoDbgRegParms; -static AbstractInstruction * gPushCw(sqInt wordConstant) NoDbgRegParms; -sqInt patchToOpenPICFornumArgsreceiver(sqInt selector, sqInt numArgs, sqInt receiver); -sqInt pcisWithinMethod(char *address, CogMethod *cogMethod); -static sqInt picAbortDiscriminatorValue(void); -static PrimitiveDescriptor * primitiveGeneratorOrNil(void); -void printCogMethodFor(void *address); -void printTrampolineTable(void); -static sqInt processorHasDivQuoRemAndMClassIsSmallInteger(sqInt ignoredPrimIndex) NoDbgRegParms; -static sqInt processorHasDivQuoRem(sqInt ignoredPrimIndex) NoDbgRegParms; -static sqInt processorHasDoublePrecisionFloatingPointSupport(sqInt ignoredPrimIndex) NoDbgRegParms; -static sqInt processorHasMultiplyAndMClassIsSmallInteger(sqInt ignoredPrimIndex) NoDbgRegParms; -static sqInt processorHasMultiply(sqInt ignoredPrimIndex) NoDbgRegParms; -static AbstractInstruction * gRetN(sqInt offset) NoDbgRegParms; -static void recordGeneratedRunTimeaddress(char *aString, sqInt address) NoDbgRegParms; -sqInt recordPrimTraceFunc(void); -static void recordRunTimeObjectReferences(void); -static sqInt registerMaskFor(sqInt reg) NoDbgRegParms; -static sqInt registerMaskForand(sqInt reg1, sqInt reg2) NoDbgRegParms; -static sqInt registerMaskForandand(sqInt reg1, sqInt reg2, sqInt reg3) NoDbgRegParms; -static void relocateCallsAndSelfReferencesInMethod(CogMethod *cogMethod) NoDbgRegParms; -static void relocateCallsInClosedPIC(CogMethod *cPIC) NoDbgRegParms; -static sqInt relocateIfCallOrMethodReferencemcpcdelta(sqInt annotation, char *mcpc, sqInt delta) NoDbgRegParms; -static sqInt relocateMethodsPreCompaction(void); -static sqInt remapIfObjectRefpchasYoung(sqInt annotation, char *mcpc, sqInt hasYoungPtr) NoDbgRegParms; -static AbstractInstruction * gSubCwR(sqInt wordConstant, sqInt reg) NoDbgRegParms; -static sqInt scanForCleanBlocks(void); -void setBreakMethod(sqInt anObj); -void setPostCompileHook(void (*aFunction)(CogMethod *, void *)); -void setSelectorOfto(CogMethod *cogMethod, sqInt aSelectorOop); @@ Diff output truncated at 50000 characters. @@

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VM Maker: VMMaker.oscog-eem.1241.mcz
by commits＠source.squeak.org 22 Apr '15

22 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1241.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1241 Author: eem Time: 22 April 2015, 10:58:24.214 am UUID: a04410be-4749-4ca7-a350-4788549b0da4 Ancestors: VMMaker.oscog-eem.1240 and fix slips in generateAllSqueakConfigurationsUnderVersionControl =============== Diff against VMMaker.oscog-eem.1240 =============== Item was changed: ----- Method: VMMaker class>>generateAllSqueakConfigurationsUnderVersionControl (in category 'configurations') ----- generateAllSqueakConfigurationsUnderVersionControl + self generateSqueakStackVM; + generateSqueakCogVM; - self generateSqueakCogVM; generateSqueakCogMTVM; + generateSqueakSpurStackVM; + generateSqueakSpurStack64VM; generateSqueakSpurCogVM; + generateSqueakSpurCogSistaVM! - generateSqueakSpurCogSistaVM - !

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VM Maker: VMMaker.oscog-eem.1240.mcz
by commits＠source.squeak.org 22 Apr '15

22 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1240.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1240 Author: eem Time: 22 April 2015, 10:49:33.219 am UUID: b4f0eba3-7350-41a0-a8da-52fbc1568cc8 Ancestors: VMMaker.oscog-eem.1239 Phhh.... =============== Diff against VMMaker.oscog-eem.1239 =============== Item was changed: ----- Method: VMMaker>>generateCogitFileFor: (in category 'generate sources') ----- generateCogitFileFor: cogitClass "Translate the Smalltalk description of the Cogit into C, if required. Ensure that inferTypesForImplicitlyTypedVariablesAndMethods was done, and answer the code generator." | cg | cg := [self buildCodeGeneratorForCogit] on: Notification do: [:ex| ex tag == #getVMMaker ifTrue: [ex resume: self] ifFalse: [(ex respondsTo: #rearmHandlerDuring:) ifTrue: [ex rearmHandlerDuring: [ex pass]] ifFalse: [ex pass]]]. cg inferTypesForImplicitlyTypedVariablesAndMethods. + self needsToRegenerateCogitFile ifFalse: [^cg]. - self needsToRegenerateCogitFile ifFalse: [^nil]. cg vmClass preGenerationHook: cg. cg storeCodeOnFile: (self sourceFilePathFor: cogitClass processorSpecificSourceFileName) doInlining: cogitClass doInlining. ^cg!

1 0

VM Maker: VMMaker.oscog-eem.1239.mcz
by commits＠source.squeak.org 22 Apr '15

22 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1239.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1239 Author: eem Time: 22 April 2015, 10:37:54.358 am UUID: ef1b96fd-5ad1-4f23-84ba-5d5e7a6a3812 Ancestors: VMMaker.oscog-eem.1238 And fix another glitch... =============== Diff against VMMaker.oscog-eem.1238 =============== Item was changed: ----- Method: VMMaker>>generateCogitFileFor: (in category 'generate sources') ----- generateCogitFileFor: cogitClass + "Translate the Smalltalk description of the Cogit into C, if required. Ensure that + inferTypesForImplicitlyTypedVariablesAndMethods was done, and answer the code generator." - "Translate the Smalltalk description of the virtual machine into C. If 'self doInlining' is true, small method bodies are inlined to reduce procedure call overhead. On the PPC, this results in a factor of three speedup with only 30% increase in code size. Subclasses can use specialised versions of CCodeGenerator and interpreterClass." | cg | cg := [self buildCodeGeneratorForCogit] on: Notification do: [:ex| ex tag == #getVMMaker ifTrue: [ex resume: self] ifFalse: [(ex respondsTo: #rearmHandlerDuring:) ifTrue: [ex rearmHandlerDuring: [ex pass]] ifFalse: [ex pass]]]. - self needsToRegenerateCogitFile ifFalse: [^cg]. cg inferTypesForImplicitlyTypedVariablesAndMethods. + self needsToRegenerateCogitFile ifFalse: [^nil]. cg vmClass preGenerationHook: cg. cg storeCodeOnFile: (self sourceFilePathFor: cogitClass processorSpecificSourceFileName) doInlining: cogitClass doInlining. ^cg!

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VM Maker: VMMaker.oscog-eem.1238.mcz
by commits＠source.squeak.org 22 Apr '15

22 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1238.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1238 Author: eem Time: 22 April 2015, 10:25:11.206 am UUID: 6d58bf61-31c3-4ae5-a203-3b154b9cebf6 Ancestors: VMMaker.oscog-eem.1237 Fix some glitches with the new cogit source scheme =============== Diff against VMMaker.oscog-eem.1237 =============== Item was changed: ----- Method: VMMaker>>generateCogitFileFor: (in category 'generate sources') ----- generateCogitFileFor: cogitClass "Translate the Smalltalk description of the virtual machine into C. If 'self doInlining' is true, small method bodies are inlined to reduce procedure call overhead. On the PPC, this results in a factor of three speedup with only 30% increase in code size. Subclasses can use specialised versions of CCodeGenerator and interpreterClass." | cg | cg := [self buildCodeGeneratorForCogit] on: Notification do: [:ex| ex tag == #getVMMaker ifTrue: [ex resume: self] ifFalse: [(ex respondsTo: #rearmHandlerDuring:) ifTrue: [ex rearmHandlerDuring: [ex pass]] ifFalse: [ex pass]]]. + self needsToRegenerateCogitFile ifFalse: [^cg]. - self needsToRegenerateCogitFile ifFalse: [^nil]. cg inferTypesForImplicitlyTypedVariablesAndMethods. cg vmClass preGenerationHook: cg. cg storeCodeOnFile: (self sourceFilePathFor: cogitClass processorSpecificSourceFileName) doInlining: cogitClass doInlining. ^cg! Item was changed: ----- Method: VMMaker>>generateCogitIncludeFileFor: (in category 'generate sources') ----- generateCogitIncludeFileFor: cogitClass "Generate the skeletal cogit.c that includes the processor-specific cogit files." + | code fileName file fileCode | - | code fileName file | code := Cogit generateCodeStringForCogitDotC. fileName := self coreVMDirectory fullNameFor: cogitClass sourceFileName. ((self coreVMDirectory fileExists: cogitClass sourceFileName) + and: [fileCode := (self class oldFileNamed: fileName) contentsOfEntireFile. + (fileCode allButFirst: (fileCode indexOf: $#)) = (code allButFirst: (code indexOf: $#))]) ifFalse: - and: [(self class oldFileNamed: fileName) contents = code]) ifFalse: [file := self class forceNewFileNamed: fileName. [file nextPutAll: code] ensure: [file close]]!

1 0

VM Maker: VMMaker.oscog-eem.1237.mcz
by commits＠source.squeak.org 22 Apr '15

22 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1237.mcz ==================== Summary ==================== Name: VMMaker.oscog-eem.1237 Author: eem Time: 22 April 2015, 10:00:33.801 am UUID: 0864d0ce-8b0f-4415-ab43-13e2581488d5 Ancestors: VMMaker.oscog-cb.1236 Change source file output for the Cogit so that cogit.c includes cogitARMv5.c or cogitIA32.c as appropriate, using the same style as ThreadedFFIPlugin. Fix some generation-time errors and warnings for ARM. =============== Diff against VMMaker.oscog-cb.1236 =============== Item was changed: ----- Method: CCodeGenerator>>generateMinus:on:indent: (in category 'C translation') ----- generateMinus: msgNode on: aStream indent: level "Generate the C code for this message onto the given stream." (self generateAsConstantExpression: msgNode on: aStream) ifFalse: + [msgNode args first constantNumbericValueOrNil ifNotNil: + [:value| + value = 0 ifTrue: + [^self emitCExpression: msgNode receiver on: aStream]]. + self emitCExpression: msgNode receiver on: aStream. - [self emitCExpression: msgNode receiver on: aStream. aStream nextPutAll: ' - '. self emitCExpression: msgNode args first on: aStream]! Item was changed: ----- Method: CCodeGenerator>>generatePlus:on:indent: (in category 'C translation') ----- generatePlus: msgNode on: aStream indent: level "Generate the C code for this message onto the given stream." (self generateAsConstantExpression: msgNode on: aStream) ifFalse: + [msgNode args first constantNumbericValueOrNil ifNotNil: + [:value| + value = 0 ifTrue: + [^self emitCExpression: msgNode receiver on: aStream]]. + self emitCExpression: msgNode receiver on: aStream. - [self emitCExpression: msgNode receiver on: aStream. aStream nextPutAll: ' + '. self emitCExpression: msgNode args first on: aStream]! Item was changed: ----- Method: CCodeGenerator>>generateTimes:on:indent: (in category 'C translation') ----- generateTimes: msgNode on: aStream indent: level "Generate the C code for this message onto the given stream." (self generateAsConstantExpression: msgNode on: aStream) ifFalse: + [msgNode args first constantNumbericValueOrNil ifNotNil: + [:value| + value = 0 ifTrue: + [^self emitCExpression: msgNode args first on: aStream]. + value = 1 ifTrue: + [^self emitCExpression: msgNode receiver on: aStream]]. + self emitCExpression: msgNode receiver on: aStream. - [self emitCExpression: msgNode receiver on: aStream. aStream nextPutAll: ' * '. self emitCExpression: msgNode args first on: aStream]! Item was changed: CogAbstractInstruction subclass: #CogARMCompiler + instanceVariableNames: 'conditionOrNil' - instanceVariableNames: 'cond' classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode ConcreteIPReg ConcreteVarBaseReg EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveNotOpcode MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode' poolDictionaries: '' category: 'VMMaker-JIT'! !CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0! I generate ARM instructions from CogAbstractInstructions. For reference see http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architectur… The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw). This class does not take any special action to flush the instruction cache on instruction-modification.! Item was added: + ----- Method: CogARMCompiler class>>ISA (in category 'translation') ----- + ISA + "Answer the name of the ISA the receiver implements." + ^#ARMv5! Item was changed: ----- Method: CogARMCompiler class>>filteredInstVarNames (in category 'translation') ----- filteredInstVarNames + "Edit such that conditionOrNil is amongst the char size vars opcode machineCodeSize and maxSize." + ^(super filteredInstVarNames copyWithout: 'conditionOrNil') + copyReplaceFrom: 4 to: 3 with: #('conditionOrNil')! - "Edit such that cond is amongst the char size vars opcode machineCodeSize and maxSize." - ^(super filteredInstVarNames copyWithout: 'cond') - copyReplaceFrom: 4 to: 3 with: #('cond')! Item was added: + ----- Method: CogARMCompiler class>>identifyingPredefinedMacros (in category 'translation') ----- + identifyingPredefinedMacros + ^#('__ARM_ARCH__' '__arm__' '__arm32__' 'ARM32')! Item was changed: ----- Method: CogARMCompiler>>concretizeAddCqR (in category 'generate machine code - concretize') ----- concretizeAddCqR "Will get inlined into concretizeAt: switch." "Try whether the quick constant is a small negative number. If it is, optimize." <inline: true> self rotateable8bitImmediate: (operands at: 0) ifTrue: [ :rot :immediate | | reg | reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self adds: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: [ self rotateable8bitImmediate: (operands at: 0) negated ifTrue: [ :rot :immediate | |reg| reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self subs: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] + ifFalse: [^self concretizeDataOperationCwR: 4]]. + ^0 "to keep Slang happy"! - ifFalse: [^self concretizeDataOperationCwR: 4]]! Item was changed: ----- Method: CogARMCompiler>>concretizeAndCqR (in category 'generate machine code - concretize') ----- concretizeAndCqR "Will get inlined into concretizeAt: switch." "AND is very important since it's used to mask all sorts of flags in the jit. We take special care to try to find fast ways to make the masks" <inline: true> |val| val := operands at: 0. self rotateable8bitImmediate: val ifTrue: [ :rot :immediate | | reg | reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self ands: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: [ "see if the constant bit-inverted makes a quick value and if so BIC it instead If the value is -ve, we 2s complement it instead" |invVal| val <0 ifTrue:[invVal := -1 - val] ifFalse:[invVal := val bitInvert32]. self rotateable8bitImmediate: invVal ifTrue: [ :rot :immediate | |reg| reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self bics: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF" |hb reg| reg := self concreteRegister: (operands at: 1). hb := (operands at: 0) highBit. 1 << hb = (val +1) ifTrue: [ "MVN temp reg, 0, making 0xffffffff" self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0). "Then AND reg, temp reg, lsr #(32-hb)" self machineCodeAt: 4 put:(self dataOpType: AndOpcode rd: reg rn: reg rm: ConcreteIPReg lsr: (32-hb )). ^machineCodeSize :=8] + ifFalse: [^self concretizeDataOperationCwR: AndOpcode]]]. + ^0 "to keep Slang happy"! - ifFalse: [^self concretizeDataOperationCwR: AndOpcode]]]! Item was changed: ----- Method: CogARMCompiler>>concretizeAndCqRR (in category 'generate machine code - concretize') ----- concretizeAndCqRR "Will get inlined into concretizeAt: switch." "AND is very important since it's used to mask all sorts of flags in the jit. We take special care to try to find fast ways to make the masks" <inline: true> | val srcReg dstReg | val := operands at: 0. srcReg := self concreteRegister: (operands at: 1). dstReg := self concreteRegister: (operands at: 2). self rotateable8bitImmediate: val ifTrue: [ :rot :immediate | self machineCodeAt: 0 put: (self ands: dstReg rn: srcReg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: ["see if the constant bit-inverted makes a quick value and if so BIC it instead If the value is -ve, we 2s complement it instead" |invVal| invVal := val < 0 ifTrue:[-1 - val] ifFalse:[val bitInvert32]. self rotateable8bitImmediate: invVal ifTrue: [ :rot :immediate | self machineCodeAt: 0 put: (self bics: dstReg rn: srcReg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: "let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF" [| hb | hb := (operands at: 0) highBit. 1 << hb = (val +1) ifTrue: "MVN temp reg, 0, making 0xffffffff" [self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0). "Then AND reg, temp reg, lsr #(32-hb)" self machineCodeAt: 4 put: (self dataOpType: AndOpcode rd: dstReg rn: srcReg rm: ConcreteIPReg lsr: 32 - hb). ^machineCodeSize := 8] ifFalse: + [^self concretizeDataOperationCwR: AndOpcode]]]. + ^0 "to keep Slang happy"! - [^self concretizeDataOperationCwR: AndOpcode]]]! Item was changed: ----- Method: CogARMCompiler>>concretizeConditionalInstruction (in category 'generate machine code') ----- concretizeConditionalInstruction "Concretize the current instruction, but with a condition." <returnTypeC: #void> | savedCond | + self assert: conditionOrNil notNil. + savedCond := conditionOrNil. + conditionOrNil := nil. - self assert: cond notNil. - savedCond := cond. - cond := nil. self dispatchConcretize. + conditionOrNil := savedCond. - cond := savedCond. 0 to: machineCodeSize-1 by: 4 do: [:i| | instr | instr := (self machineCodeAt: i) bitClear: 16rF<<28. + self machineCodeAt: i put: (instr bitOr: (conditionOrNil bitAnd: 16rF)<<28)]! - self machineCodeAt: i put: (instr bitOr: (cond bitAnd: 16rF)<<28)]! Item was changed: ----- Method: CogARMCompiler>>concretizeDataOperationCqR: (in category 'generate machine code - concretize') ----- concretizeDataOperationCqR: armOpcode "Will get inlined into concretizeAt: switch." "4 == Add, 2 == Sub, Xor == 1, And == 0, Or == 12, Bic == 14" <inline: true> |val rd rn | val := operands at: 0. rn := self concreteRegister: (operands at: 1). rd := opcode = CmpOpcode ifTrue: [0] ifFalse:[rn]. self rotateable8bitImmediate: val ifTrue: [:rot :immediate | self machineCodeAt: 0 put: (self type: 1 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: ((rot>>1)"in this usage we have to halve the rot value" << 8 bitOr: immediate)). ^machineCodeSize := 4] ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF" val > 0 ifTrue: [ |hb | hb := val highBit. 1 << hb = (val +1) ifTrue: [ "MVN temp, #0, making 0xffffffff" self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0). "Then armOpcode reg, temp reg, lsr #(32-hb)" self machineCodeAt: 4 put:(self dataOpType: armOpcode rd: rd rn: rn rm: ConcreteIPReg lsr: (32-hb)). ^machineCodeSize :=8]]. ^self concretizeDataOperationCwR: armOpcode]. + ^0 "to keep Slang happy" ! Item was changed: ----- Method: CogARMCompiler>>concretizeLoadEffectiveAddressMwrR (in category 'generate machine code - concretize') ----- concretizeLoadEffectiveAddressMwrR "Will get inlined into concretizeAt: switch." "destReg = srcReg (which contains an address) + offset" <inline: true> | srcReg offset destReg instrOffset | offset := operands at: 0. srcReg := self concreteRegister: (operands at: 1). destReg := self concreteRegister: (operands at: 2). self rotateable8bitImmediate: offset ifTrue: [ :rot :immediate | self machineCodeAt: 0 "add destReg, srcReg, #immediate ROR rot" put: (self add: destReg rn: srcReg imm: immediate ror: rot<<1). + machineCodeSize := 4] - ^machineCodeSize := 4] ifFalse: [instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg. "add destReg, srcReg, ConcreteIPReg" self machineCodeAt: 16 put: (self add: destReg rn: srcReg rm: ConcreteIPReg). + machineCodeSize := instrOffset + 4]. + ^machineCodeSize "to keep Slang happy"! - ^machineCodeSize := instrOffset + 4 ]! Item was changed: ----- Method: CogARMCompiler>>concretizeMoveCqR (in category 'generate machine code - concretize') ----- concretizeMoveCqR "Will get inlined into concretizeAt: switch." "If the quick constant is in fact a shiftable 8bit, generate the apropriate MOV, otherwise do what is necessary for a whole word." <inline: true> |word reg| word := operands at: 0. reg := self concreteRegister: (operands at: 1). self rotateable8bitImmediate: (operands at: 0) ifTrue: [:rot :immediate | self machineCodeAt: 0 put: (self mov: reg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: [|invVal| word <0 ifTrue:[invVal := -1 - word] ifFalse:[invVal := word bitInvert32]. self rotateable8bitImmediate: invVal ifTrue: [ :rot :immediate | self machineCodeAt: 0 put: (self mvn: reg imm: immediate ror: rot). ^machineCodeSize := 4] + ifFalse: [^self concretizeMoveCwR]]. + ^0 "to keep Slang happy"! - ifFalse: [^self concretizeMoveCwR]] - ! Item was changed: ----- Method: CogARMCompiler>>concretizeMoveM16rR (in category 'generate machine code - concretize') ----- concretizeMoveM16rR "Will get inlined into concretizeAt: switch." "ldrh destReg, [srcReg, #immediate], or move offset to ConcreteIPReg ldrh destReg, [srcReg, ConcreteIPReg]" <inline: true> | srcReg offset destReg instrOffset| offset := operands at: 0. srcReg := self concreteRegister: (operands at: 1). destReg := self concreteRegister: (operands at: 2). self is8BitValue: offset ifTrue: [ :u :immediate | self machineCodeAt: 0 "ldrh destReg, [srcReg, #immediate]" put: (self ldrh: destReg rn: srcReg plus: u imm: immediate). ^machineCodeSize := 4] ifFalse: [instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg. "ldrh destReg, [srcReg, ConcreteIPReg]" self machineCodeAt: instrOffset put: (self ldrh: destReg rn: srcReg rm: ConcreteIPReg). + ^machineCodeSize := instrOffset + 4 ]. + ^0 "to keep Slang happy"! - ^machineCodeSize := instrOffset + 4 ]! Item was changed: ----- Method: CogARMCompiler>>concretizeMoveMbrR (in category 'generate machine code - concretize') ----- concretizeMoveMbrR "Will get inlined into concretizeAt: switch." "ldrb destReg, [srcReg, #immediate] or ldrb destReg, [srcReg, ConcreteIPReg]" <inline: true> | srcReg offset destReg instrOffset| offset := operands at: 0. srcReg := self concreteRegister: (operands at: 1). destReg := self concreteRegister: (operands at: 2). self is12BitValue: offset ifTrue: [ :u :immediate | self machineCodeAt: 0 "ldrb destReg, [srcReg, #immediate]" put: (self ldrb: destReg rn: srcReg plus: u imm: immediate). ^machineCodeSize := 4] ifFalse: [(self isAddressRelativeToVarBase: offset) ifTrue: [self machineCodeAt: 0 put: (self adds: ConcreteIPReg rn: ConcreteVarBaseReg imm: offset - cogit varBaseAddress ror: 0). instrOffset := 4] ifFalse: [instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg]. "ldrb destReg, [srcReg, ConcreteIPReg]" self machineCodeAt: instrOffset put: (self ldrb: destReg rn: srcReg rm: ConcreteIPReg). + ^machineCodeSize := instrOffset + 4]. + ^0 "to keep Slang happy"! - ^machineCodeSize := instrOffset + 4]! Item was changed: ----- Method: CogARMCompiler>>concretizeMoveMwrR (in category 'generate machine code - concretize') ----- concretizeMoveMwrR "Will get inlined into concretizeAt: switch." <inline: true> | srcReg offset destReg instrOffset| offset := operands at: 0. srcReg := self concreteRegister: (operands at: 1). destReg := self concreteRegister: (operands at: 2). self is12BitValue: offset ifTrue: [ :u :immediate | self machineCodeAt: 0 "ldr destReg, [srcReg, #immediate]" put: (self ldr: destReg rn: srcReg plus: u imm: immediate). ^machineCodeSize := 4] ifFalse: [instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg. "ldr destReg, [srcReg, ConcreteIPReg]" self machineCodeAt: instrOffset put: (self ldr: destReg rn: srcReg rm: ConcreteIPReg). + ^machineCodeSize := instrOffset + 4]. + ^0 "to keep Slang happy"! - ^machineCodeSize := instrOffset + 4]! Item was changed: ----- Method: CogARMCompiler>>concretizeMoveRMbr (in category 'generate machine code - concretize') ----- concretizeMoveRMbr "Will get inlined into concretizeAt: switch." <inline: true> | srcReg offset baseReg instrOffset| srcReg := self concreteRegister: (operands at: 0). offset := operands at: 1. baseReg := self concreteRegister: (operands at: 2). self is12BitValue: offset ifTrue: [ :u :immediate | self machineCodeAt: 0 "strb srcReg, [baseReg, #immediate]" put: (self strb: srcReg rn: baseReg plus: u imm: immediate). ^machineCodeSize := 4] ifFalse: [(self isAddressRelativeToVarBase: offset) ifTrue: [self machineCodeAt: 0 put: (self adds: ConcreteIPReg rn: ConcreteVarBaseReg imm: offset - cogit varBaseAddress ror: 0). instrOffset := 4] ifFalse: [instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg]. "strb srcReg, [baseReg, ConcreteIPReg]" self machineCodeAt: instrOffset put: (self strb: srcReg rn: baseReg rm: ConcreteIPReg). + ^machineCodeSize := instrOffset + 4 ]. + ^0 "to keep Slang happy"! - ^machineCodeSize := instrOffset + 4 ]! Item was changed: ----- Method: CogARMCompiler>>concretizeMoveRMwr (in category 'generate machine code - concretize') ----- concretizeMoveRMwr "Will get inlined into concretizeAt: switch." <inline: true> | srcReg offset baseReg instrOffset| srcReg := self concreteRegister: (operands at: 0). offset := operands at: 1. baseReg := self concreteRegister: (operands at: 2). self is12BitValue: offset ifTrue: [ :u :immediate | self machineCodeAt: 0 "str srcReg, [baseReg, #immediate]" put: (self str: srcReg rn: baseReg plus: u imm: immediate). ^machineCodeSize := 4] ifFalse: [instrOffset := self at: 0 moveCw: offset intoR: ConcreteIPReg. "str srcReg, [baseReg, ConcreteIPReg]" self machineCodeAt: instrOffset put: (self str: srcReg rn: baseReg rm: ConcreteIPReg). + ^machineCodeSize := instrOffset + 4]. + ^0 "to keep Slang happy"! - ^machineCodeSize := instrOffset + 4]! Item was changed: ----- Method: CogARMCompiler>>concretizeSubCqR (in category 'generate machine code - concretize') ----- concretizeSubCqR "Will get inlined into concretizeAt: switch." "Try whether the quick constant is a small negative number. If it is, optimize." <inline: true> self rotateable8bitImmediate: (operands at: 0) ifTrue: [ :rot :immediate | | reg | reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self subs: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] ifFalse: [ "before building a full load of a big cinstant, see if we can do an add of the constant negated" self rotateable8bitImmediate: (operands at: 0) negated ifTrue: [ :rot :immediate | | reg | reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self adds: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] + ifFalse: [^self concretizeDataOperationCwR: 2]]. + ^0 "to keep Slang happy"! - ifFalse: [^self concretizeDataOperationCwR: 2]]! Item was changed: ----- Method: CogARMCompiler>>concretizeTstCqR (in category 'generate machine code - concretize') ----- concretizeTstCqR "Will get inlined into concretizeAt: switch." <inline: true> self rotateable8bitImmediate: (operands at: 0) ifTrue: [ :rot :immediate | | reg | reg := self concreteRegister: (operands at: 1). self machineCodeAt: 0 put: (self tst: reg rn: reg imm: immediate ror: rot). ^machineCodeSize := 4] + ifFalse: [^self concretizeDataOperationCwR: 8]. + ^0 "to keep Slang happy"! - ifFalse: [^self concretizeDataOperationCwR: 8]! Item was removed: - ----- Method: CogARMCompiler>>cond (in category 'accessing') ----- - cond - ^cond! Item was removed: - ----- Method: CogARMCompiler>>cond: (in category 'accessing') ----- - cond: condCode - ^cond := condCode! Item was added: + ----- Method: CogARMCompiler>>condition (in category 'accessing') ----- + condition + ^conditionOrNil! Item was added: + ----- Method: CogARMCompiler>>condition: (in category 'accessing') ----- + condition: condCode + ^conditionOrNil := condCode! Item was changed: ----- Method: CogARMCompiler>>dataOpType:rd:rn:rm:lsr: (in category 'ARM convenience instructions') ----- + dataOpType: armOpcode rd: destReg rn: srcReg rm: addReg lsr: shft - dataOpType: opcode rd: destReg rn: srcReg rm: addReg lsr: shft "return an {opcode} destReg, srcReg, addReg lsl #shft" "important detail - a 0 shft requires setting the shift-type code to 0 to avoid potential instruction confusion" shft = 0 + ifTrue:[^self type: 0 op: armOpcode set: 1 rn: srcReg rd: destReg shifterOperand: addReg] + ifFalse:[^self type: 0 op: armOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((shft <<7 bitOr: 32) bitOr: addReg)]! - ifTrue:[^self type: 0 op: opcode set: 1 rn: srcReg rd: destReg shifterOperand: addReg] - ifFalse:[^self type: 0 op: opcode set: 1 rn: srcReg rd: destReg shifterOperand: ((shft <<7 bitOr: 32) bitOr: addReg)]! Item was changed: ----- Method: CogARMCompiler>>dispatchConcretize (in category 'generate machine code') ----- dispatchConcretize "Attempt to generate concrete machine code for the instruction at address. This is the inner dispatch of concretizeAt: actualAddress which exists only to get around the branch size limits in the SqueakV3 (blue book derived) bytecode set." <returnTypeC: #void> + conditionOrNil ifNotNil: - cond ifNotNil: [self concretizeConditionalInstruction. ^self]. opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^self concretizeLabel]. [AlignmentNops] -> [^self concretizeAlignmentNops]. [Fill16] -> [^self concretizeFill16]. [Fill32] -> [^self concretizeFill32]. [FillFromWord] -> [^self concretizeFillFromWord]. [Nop] -> [^self concretizeNop]. "ARM Specific Control/Data Movement" [LDMFD] -> [^self concretizeLDMFD]. [STMFD] -> [^self concretizeSTMFD]. [SMULL] -> [^self concretizeSMULL] . [BICCqR] -> [^self concretizeDataOperationCqR: BicOpcode]. "Control" [Call] -> [^self concretizeCall]. "call code within code space" [CallFull] -> [^self concretizeCallFull]. "call code anywhere in address space" [JumpR] -> [^self concretizeJumpR]. [JumpFull] -> [^self concretizeJumpFull]."jump within address space" [JumpLong] -> [^self concretizeConditionalJump: AL]."jumps witihn code space" [JumpLongZero] -> [^self concretizeConditionalJump: EQ]. [JumpLongNonZero] -> [^self concretizeConditionalJump: NE]. [Jump] -> [^self concretizeConditionalJump: AL]. [JumpZero] -> [^self concretizeConditionalJump: EQ]. [JumpNonZero] -> [^self concretizeConditionalJump: NE]. [JumpNegative] -> [^self concretizeConditionalJump: MI]. [JumpNonNegative] -> [^self concretizeConditionalJump: PL]. [JumpOverflow] -> [^self concretizeConditionalJump: VS]. [JumpNoOverflow] -> [^self concretizeConditionalJump: VC]. [JumpCarry] -> [^self concretizeConditionalJump: CS]. [JumpNoCarry] -> [^self concretizeConditionalJump: CC]. [JumpLess] -> [^self concretizeConditionalJump: LT]. [JumpGreaterOrEqual] -> [^self concretizeConditionalJump: GE]. [JumpGreater] -> [^self concretizeConditionalJump: GT]. [JumpLessOrEqual] -> [^self concretizeConditionalJump: LE]. [JumpBelow] -> [^self concretizeConditionalJump: CC]. "unsigned lower" [JumpAboveOrEqual] -> [^self concretizeConditionalJump: CS]. "unsigned greater or equal" [JumpAbove] -> [^self concretizeConditionalJump: HI]. [JumpBelowOrEqual] -> [^self concretizeConditionalJump: LS]. [JumpFPEqual] -> [^self concretizeFPConditionalJump: EQ]. [JumpFPNotEqual] -> [^self concretizeFPConditionalJump: NE]. [JumpFPLess] -> [^self concretizeFPConditionalJump: LT]. [JumpFPGreaterOrEqual] -> [^self concretizeFPConditionalJump: GE]. [JumpFPGreater] -> [^self concretizeFPConditionalJump: GT]. [JumpFPLessOrEqual] -> [^self concretizeFPConditionalJump: LE]. [JumpFPOrdered] -> [^self concretizeFPConditionalJump: VC]. [JumpFPUnordered] -> [^self concretizeFPConditionalJump: VS]. [RetN] -> [^self concretizeRetN]. [Stop] -> [^self concretizeStop]. "Arithmetic" [AddCqR] -> [^self concretizeAddCqR]. [AddCwR] -> [^self concretizeDataOperationCwR: AddOpcode]. [AddRR] -> [^self concretizeDataOperationRR: AddOpcode]. [AddRdRd] -> [^self concretizeAddRdRd]. [AndCqR] -> [^self concretizeAndCqR]. [AndCqRR] -> [^self concretizeAndCqRR]. [AndCwR] -> [^self concretizeDataOperationCwR: AndOpcode]. [AndRR] -> [^self concretizeDataOperationRR: AndOpcode]. [CmpCqR] -> [^self concretizeDataOperationCqR: CmpOpcode]. [CmpCwR] -> [^self concretizeDataOperationCwR: CmpOpcode]. [CmpRR] -> [^self concretizeDataOperationRR: CmpOpcode]. [CmpRdRd] -> [^self concretizeCmpRdRd]. [DivRdRd] -> [^self concretizeDivRdRd]. [MulRdRd] -> [^self concretizeMulRdRd]. [OrCqR] -> [^self concretizeDataOperationCqR: OrOpcode]. [OrCwR] -> [^self concretizeDataOperationCwR: OrOpcode]. [OrRR] -> [^self concretizeDataOperationRR: OrOpcode]. [SubCqR] -> [^self concretizeSubCqR]. [SubCwR] -> [^self concretizeDataOperationCwR: SubOpcode]. [SubRR] -> [^self concretizeDataOperationRR: SubOpcode]. [SubRdRd] -> [^self concretizeSubRdRd]. [SqrtRd] -> [^self concretizeSqrtRd]. [TstCqR] -> [^self concretizeTstCqR]. [XorCqR] -> [^self concretizeDataOperationCqR: XorOpcode]. [XorCwR] -> [^self concretizeDataOperationCwR: XorOpcode]. [XorRR] -> [^self concretizeDataOperationRR: XorOpcode]. [NegateR] -> [^self concretizeNegateR]. [LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR]. [ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR]. [LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR]. [LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR]. [ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR]. [LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR]. [LogicalShiftRightRR] -> [^self concretizeLogicalShiftRightRR]. "Data Movement" [MoveCqR] -> [^self concretizeMoveCqR]. [MoveCwR] -> [^self concretizeMoveCwR]. [MoveRR] -> [^self concretizeMoveRR]. [MoveAwR] -> [^self concretizeMoveAwR]. [MoveRAw] -> [^self concretizeMoveRAw]. [MoveMbrR] -> [^self concretizeMoveMbrR]. [MoveRMbr] -> [^self concretizeMoveRMbr]. [MoveM16rR] -> [^self concretizeMoveM16rR]. [MoveM64rRd] -> [^self concretizeMoveM64rRd]. [MoveMwrR] -> [^self concretizeMoveMwrR]. [MoveXbrRR] -> [^self concretizeMoveXbrRR]. [MoveRXbrR] -> [^self concretizeMoveRXbrR]. [MoveXwrRR] -> [^self concretizeMoveXwrRR]. [MoveRXwrR] -> [^self concretizeMoveRXwrR]. [MoveRMwr] -> [^self concretizeMoveRMwr]. [MoveRdM64r] -> [^self concretizeMoveRdM64r]. [PopR] -> [^self concretizePopR]. [PushR] -> [^self concretizePushR]. [PushCq] -> [^self concretizePushCq]. [PushCw] -> [^self concretizePushCw]. [PrefetchAw] -> [^self concretizePrefetchAw]. "Conversion" [ConvertRRd] -> [^self concretizeConvertRRd]}! Item was changed: ----- Method: CogARMCompiler>>genMulR:R: (in category 'abstract instructions') ----- genMulR: regSource R: regDest "Use SMULL to produce a 64-bit result, implicitly in TempReg,RISCTempReg. Test the top word for 0 or 1 and set oVerflow if not equal. Move result in TempReg into regDest." - <var: #inst type: #AbstractInstruction> cogit gen: SMULL operand: regSource operand: regDest; "result in TempReg,RISCTempReg" gen: AddCqR operand: 1 operand: RISCTempReg; "turn -1,0 into 0,1" gen: AddCqR operand: -1 operand: RISCTempReg; "turn 0,1 into not oVerflow" gen: MoveRR operand: TempReg operand: regDest! Item was changed: ----- Method: CogARMCompiler>>is12BitValue:ifTrue:ifFalse: (in category 'testing') ----- is12BitValue: constant ifTrue: trueAlternativeBlock ifFalse: falseAlternativeBlock "For LDR and STR, there is an instruction allowing for one instruction encoding if the offset is encodable in signed 12 bit form. pass the trueBlock the value and a 1-bit flag to tell it the sign. The falseBlock can do whatever it needs to, typically building the constant as a full 32bit value and then ld/st with that as a register offset" + <inline: true> constant abs <= 4095 "(2 raisedTo: 12)-1" + ifTrue: + [constant >= 0 - ifTrue: [ - constant >= 0 ifTrue: [trueAlternativeBlock value: 1 value: constant] ifFalse: [trueAlternativeBlock value: 0 value: constant abs]] ifFalse: falseAlternativeBlock! Item was changed: ----- Method: CogARMCompiler>>is8BitValue:ifTrue:ifFalse: (in category 'testing') ----- is8BitValue: constant ifTrue: trueAlternativeBlock ifFalse: falseAlternativeBlock "For extended LDR and STR for half & double, there is an instruction allowing for one instruction encoding if the offset is encodable in 8 bit." + <inline: true> constant abs <= 255 "(2 raisedTo: 8)-1" + ifTrue: + [constant >= 0 - ifTrue: [ - constant >= 0 ifTrue: [trueAlternativeBlock value: 1 value: constant] ifFalse: [trueAlternativeBlock value: 0 value: constant abs]] ifFalse: falseAlternativeBlock! Item was added: + ----- Method: CogARMCompiler>>isPCRelativeValueLoad: (in category 'testing') ----- + isPCRelativeValueLoad: instr + <var: 'instr' type: #'unsigned int'> + "add xx, pc, blah or sub xx, pc, blah" + ^(instr >> 16) = 16rE28F or: [instr >> 16 = 16rE24F]! Item was added: + ----- Method: CogAbstractInstruction class>>ISA (in category 'translation') ----- + ISA + "Answer the name of the ISA the receiver's subclass implements." + ^self subclassResponsibility! Item was added: + ----- Method: CogAbstractInstruction class>>identifyingPredefinedMacros (in category 'translation') ----- + identifyingPredefinedMacros + "Answer the predefined macros that identify the processors a subclass handles, if any. + If the subclass isn't yet ready for production (a work in progress) simply answer nil." + ^nil! Item was added: + ----- Method: CogAbstractInstruction class>>moduleName (in category 'translation') ----- + moduleName + "CogAbstractInstruction subclasses collect: [:ea| ea moduleName]" + ^'cogit', self ISA! Item was added: + ----- Method: CogAbstractInstruction class>>translateableSubclasses (in category 'translation') ----- + translateableSubclasses + "CogAbstractInstruction translateableSubclasses" + ^self subclasses select: [:compilerClass| compilerClass identifyingPredefinedMacros notNil]! Item was removed: - ----- Method: CogAbstractInstruction>>isPCRelativeValueLoad: (in category 'testing') ----- - isPCRelativeValueLoad: instr - <var: 'instr' type: #'unsigned int'> - "add xx, pc, blah or sub xx, pc, blah" - ^(instr >> 16) = 16rE28F or: [instr >> 16 = 16rE24F]! Item was changed: ----- Method: CogAbstractInstruction>>outputMachineCodeAt: (in category 'encoding') ----- + outputMachineCodeAt: targetAddress - outputMachineCodeAt: address "By default move machine code a byte at a time Subclasses with coarser granularity can override as desired." <inline: true> 0 to: machineCodeSize - 1 do: [:j| + objectMemory byteAt: targetAddress + j put: (machineCode at: j)]! - objectMemory byteAt: address + j put: (machineCode at: j)]! Item was added: + ----- Method: CogIA32Compiler class>>ISA (in category 'translation') ----- + ISA + "Answer the name of the ISA the receiver implements." + ^#IA32! Item was added: + ----- Method: CogIA32Compiler class>>identifyingPredefinedMacros (in category 'translation') ----- + identifyingPredefinedMacros + ^#('_M_I386' '_X86_' 'i386' 'i486' 'i586' 'i686' '__i386__' '__386__' 'X86' 'I386')! Item was added: + ----- Method: CogMethodZone>>initialize (in category 'initialization') ----- + initialize + "Make youngReferrers arithmetic for addressIsInCodeZone:" + youngReferrers := 0! Item was changed: ----- Method: CogObjectRepresentationFor32BitSpur>>genGetActiveContextLarge:inBlock: (in category 'initialization') ----- genGetActiveContextLarge: isLarge inBlock: isInBlock "Create a trampoline to answer the active context that will answer it if a frame is already married, and create it otherwise. Assume numArgs is in SendNumArgsReg and ClassReg is free." | header slotSize jumpSingle loopHead jumpNeedScavenge continuation exit | <var: #jumpNeedScavenge type: #'AbstractInstruction *'> <var: #continuation type: #'AbstractInstruction *'> <var: #jumpSingle type: #'AbstractInstruction *'> <var: #loopHead type: #'AbstractInstruction *'> <var: #exit type: #'AbstractInstruction *'> cogit "load the flag; stash it in both TempReg & ClassReg; do the compare (a prime candidated for use of AndCq:R:R:)" MoveMw: FoxMethod r: FPReg R: ClassReg; AndCq: MFMethodFlagHasContextFlag R: ClassReg R: TempReg. jumpSingle := cogit JumpZero: 0. "jump if flag bit not set" cogit "since the flag bit was set, get the context in the receiver reg and return" MoveMw: FoxThisContext r: FPReg R: ReceiverResultReg; RetN: 0. jumpSingle jmpTarget: cogit Label. "OK, it doesn't exist; instantiate and initialize it" "set the hasContext flag; See CoInterpreter class>>initializeFrameIndices" cogit OrCq: MFMethodFlagHasContextFlag R: ClassReg; MoveR: ClassReg Mw: FoxMethod r: FPReg. "now get the home CogMethod into ClassReg and save for post-instantiation." isInBlock ifTrue: [cogit SubCq: 3 R: ClassReg; "-3 is -(hasContext+isBlock) flags" MoveM16: 0 r: ClassReg R: TempReg; SubR: TempReg R: ClassReg] ifFalse: [cogit SubCq: 1 R: ClassReg]. "-1 is hasContext flag" "instantiate the context..." slotSize := isLarge ifTrue: [LargeContextSlots] ifFalse: [SmallContextSlots]. header := objectMemory headerForSlots: slotSize format: objectMemory indexablePointersFormat classIndex: ClassMethodContextCompactIndex. self flag: #endianness. cogit MoveAw: objectMemory freeStartAddress R: ReceiverResultReg; MoveCq: (self low32BitsOf: header) R: TempReg; MoveR: TempReg Mw: 0 r: ReceiverResultReg; MoveCq: header >> 32 R: TempReg; MoveR: TempReg Mw: 4 r: ReceiverResultReg; MoveR: ReceiverResultReg R: TempReg; AddCq: (objectMemory smallObjectBytesForSlots: slotSize) R: TempReg; MoveR: TempReg Aw: objectMemory freeStartAddress; CmpCq: objectMemory getScavengeThreshold R: TempReg. jumpNeedScavenge := cogit JumpAboveOrEqual: 0. "Now initialize the fields of the context. See CoInterpreter>>marryFrame:SP:copyTemps:" "sender gets frame pointer as a SmallInteger" continuation := cogit MoveR: FPReg R: TempReg. self genSetSmallIntegerTagsIn: TempReg. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (SenderIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "pc gets frame caller as a SmallInteger" cogit MoveMw: FoxSavedFP r: FPReg R: TempReg. self genSetSmallIntegerTagsIn: TempReg. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (InstructionPointerIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Set the method field, freeing up ClassReg again, and frame's context field," cogit MoveMw: (cogit offset: CogMethod of: #methodObject) r: ClassReg R: TempReg; MoveR: TempReg Mw: objectMemory baseHeaderSize + (MethodIndex * objectMemory wordSize) r: ReceiverResultReg; MoveR: ReceiverResultReg Mw: FoxThisContext r: FPReg. "Now compute stack pointer; this is stackPointer (- 1 for return pc if a CISC) - framePointer - 4 (1 each for saved pc, method, context, receiver) + 1 (1-relative) + numArgs" "TPR note - the code here is actually doing context stackPointer := ((((fp - sp) / 4) - [3|4]) + num args) asSmallInteger" cogit MoveR: FPReg R: TempReg; SubR: SPReg R: TempReg; LogicalShiftRightCq: self log2BytesPerWord R: TempReg; SubCq: (cogit backEnd hasLinkRegister ifTrue: [3] ifFalse: [4]) R: TempReg; AddR: SendNumArgsReg R: TempReg. self genConvertIntegerToSmallIntegerInReg: TempReg. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (StackPointerIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Set closureOrNil to either the stacked receiver or nil" isInBlock ifTrue: [cogit MoveR: SendNumArgsReg R: TempReg; AddCq: 2 R: TempReg; "+2 for saved fp and saved pc" MoveXwr: TempReg R: FPReg R: TempReg] ifFalse: [cogit MoveCw: objectMemory nilObject R: TempReg]. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (ClosureIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Set the receiver" cogit MoveMw: FoxMFReceiver r: FPReg R: TempReg; MoveR: TempReg Mw: objectMemory baseHeaderSize + (ReceiverIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Now copy the arguments. This is tricky because of the shortage of registers,. ClassReg ranges from 1 to numArgs (SendNumArgsReg), and from ReceiverIndex + 1 to ReceiverIndex + numArgs. 1 to: numArgs do: [:i| temp := longAt(FPReg + ((SendNumArgs - i + 2) * BytesPerWord)). +2 for saved pc and savedfp longAtput(FPReg + FoxMFReceiver + (i * BytesPerWord), temp)]" "TPR note: this is a prime candidate for passing off to the backend to do at least faintly optimal code" cogit MoveCq: 1 R: ClassReg. loopHead := cogit CmpR: SendNumArgsReg R: ClassReg. exit := cogit JumpGreater: 0. cogit MoveR: SendNumArgsReg R: TempReg; SubR: ClassReg R: TempReg; AddCq: 2 R: TempReg; "+2 for saved fp and saved pc" MoveXwr: TempReg R: FPReg R: TempReg; AddCq: ReceiverIndex + (objectMemory baseHeaderSize / objectMemory wordSize) R: ClassReg; "Now convert ClassReg from frame index to context index" MoveR: TempReg Xwr: ClassReg R: ReceiverResultReg; SubCq: ReceiverIndex + (objectMemory baseHeaderSize / objectMemory wordSize) - 1 R: ClassReg; "convert back adding 1 ;-)" Jump: loopHead. exit jmpTarget: cogit Label. "Finally nil or copy the non-argument temps. ClassReg := FPReg + FoxMFReceiver. SendNumArgsReg := SendNumArgsReg+ReceiverIndex. [ClassReg := ClassReg - 4. backEnd hasLinkRegister ifTrue: [ClassReg > SPReg] ifFalse: [ClassReg >= SPReg]] whileTrue: [receiver[SendNumArgsReg] := *ClassReg. SendNumArgsReg := SendNumArgsReg + 1]]" coInterpreter marryFrameCopiesTemps ifFalse: [cogit MoveCq: objectMemory nilObject R: TempReg]. cogit MoveR: FPReg R: ClassReg; AddCq: FoxMFReceiver R: ClassReg; AddCq: ReceiverIndex + 1 + (objectMemory baseHeaderSize / objectMemory wordSize) R: SendNumArgsReg. loopHead := cogit SubCq: objectMemory wordSize R: ClassReg. cogit CmpR: SPReg R: ClassReg. "If on a CISC there's a retpc for the trampoline call on top of stack; if on a RISC there isn't." exit := cogit backEnd hasLinkRegister ifTrue: [cogit JumpBelow: 0] ifFalse: [cogit JumpBelowOrEqual: 0]. coInterpreter marryFrameCopiesTemps ifTrue: [cogit MoveMw: 0 r: ClassReg R: TempReg]. cogit MoveR: TempReg Xwr: SendNumArgsReg R: ReceiverResultReg; AddCq: 1 R: SendNumArgsReg; Jump: loopHead. exit jmpTarget: cogit Label. cogit RetN: 0. + jumpNeedScavenge jmpTarget: cogit Label. + cogit backEnd saveAndRestoreLinkRegAround: + [cogit CallRT: ceScheduleScavengeTrampoline]. - jumpNeedScavenge jmpTarget: - (cogit backEnd saveAndRestoreLinkRegAround: [cogit CallRT: ceScheduleScavengeTrampoline]). "We need to push the LR here for ARM, and pop it back after the callRT:" cogit Jump: continuation. ^0! Item was added: + ----- Method: Cogit class>>activeCompilerClass (in category 'translation') ----- + activeCompilerClass + ^CogAbstractInstruction subclasses detect: [:compilerClass| compilerClass ISA == (initializationOptions at: #ISA)]! Item was changed: ----- Method: Cogit class>>ancilliaryClasses: (in category 'translation') ----- ancilliaryClasses: options ProcessorClass ifNil: [Cogit initializeMiscConstants]. ^{ CogMethodZone. CogAbstractInstruction. + self activeCompilerClass. - ProcessorClass basicNew abstractInstructionCompilerClass. CogBlockStart. CogBytecodeDescriptor. CogBytecodeFixup. CogInstructionAnnotation. CogPrimitiveDescriptor. CogBlockMethod. CogMethod }, ((options at: #NewspeakVM ifAbsent: [false]) ifTrue: [{NewspeakCogMethod. NSSendCache}] ifFalse: [#()])! Item was added: + ----- Method: Cogit class>>generateCodeStringForCogitDotC (in category 'translation') ----- + generateCodeStringForCogitDotC + "Generate a skeletal cogit.c that includes the relevant + cogitFOO.c for each subclass of CogAbstractInstruction." + + ^String streamContents: + [:s| + s nextPutAll: '/* Automatically generated by\ ' withCRs. + s nextPutAll: (CCodeGenerator monticelloDescriptionFor: self). + s cr; nextPutAll: ' */'. + s cr; cr; nextPut: $#. + (CogAbstractInstruction subclasses sort: [:a :b| a name < b name]) do: + [:class | + class identifyingPredefinedMacros ifNotNil: + [:predefinedMacros| + s nextPutAll: 'if '. + predefinedMacros + do: [:predefinedMacro| s nextPutAll: 'defined('; nextPutAll: predefinedMacro; nextPut: $)] + separatedBy: [s nextPutAll: ' || ']. + s cr; cr; nextPutAll: '# include "'; nextPutAll: class moduleName; nextPutAll: '.c"'. + s cr; cr; nextPutAll: '#el']]. + s nextPutAll: 'se'. + #( 'As yet no Cogit implementation appears to exist for your platform.' + 'Consider implementing it, starting by adding a subclass of CogAbstractInstruction.') do: + [:msg| s cr; nextPutAll: '# error '; nextPutAll: msg]. + s cr; nextPutAll: '#endif'; cr]! Item was changed: ----- Method: Cogit class>>initializeMiscConstants (in category 'class initialization') ----- initializeMiscConstants super initializeMiscConstants. Debug := initializationOptions at: #Debug ifAbsent: [false]. (initializationOptions includesKey: #EagerInstructionDecoration) ifTrue: [EagerInstructionDecoration := initializationOptions at: #EagerInstructionDecoration] ifFalse: [EagerInstructionDecoration isNil ifTrue: [EagerInstructionDecoration := false]]. "speeds up single stepping but could lose fidelity" + ProcessorClass := (initializationOptions at: #ISA ifAbsentPut: [#IA32]) caseOf: { - ProcessorClass := (initializationOptions at: #ISA ifAbsent: [#IA32]) caseOf: { [#IA32] -> [BochsIA32Alien]. [#ARMv5] -> [GdbARMAlien]. }. "Our criterion for which methods to JIT is literal count. The default value is 60 literals or less." MaxLiteralCountForCompile := initializationOptions at: #MaxLiteralCountForCompile ifAbsent: [60]. "we special-case 0, 1 & 2 argument sends, N is numArgs >= 3" NumSendTrampolines := 4. "Currently not even the ceImplicitReceiverTrampoline contains object references." NumObjRefsInRuntime := 0. NSCSelectorIndex := (NSSendCache instVarNames indexOf: #selector) - 1. NSCNumArgsIndex := (NSSendCache instVarNames indexOf: #numArgs) - 1. NSCClassTagIndex := (NSSendCache instVarNames indexOf: #classTag) - 1. NSCEnclosingObjectIndex := (NSSendCache instVarNames indexOf: #enclosingObject) - 1. NSCTargetIndex := (NSSendCache instVarNames indexOf: #target) - 1. NumOopsPerNSC := NSSendCache instVarNames size. "Max size to alloca when compiling. Mac OS X 10.6.8 segfaults approaching 8Mb. Linux 2.6.9 segfaults above 11Mb. WIndows XP segfaults approaching 2Mb." MaxStackAllocSize := 1024 * 1024 * 3 / 2 ! Item was added: + ----- Method: Cogit class>>processorSpecificSourceFileName (in category 'translation') ----- + processorSpecificSourceFileName + ^self activeCompilerClass moduleName, '.c'! Item was changed: ----- Method: Cogit>>addressIsInCodeZone: (in category 'testing') ----- addressIsInCodeZone: address "N.B. We /don't/ write this as address between: codeBase and: methodZone limitZony in case we're testing an address in a method whose code has yet to be allocated and is hence >= methodZone limitZony" ^address asUnsignedInteger >= codeBase + and: [address < methodZone youngReferrers]! - and: [address < (methodZone youngReferrers ifNil: [0])]! Item was changed: ----- Method: VMMaker class>>generateEitherSqueakCogVM (in category 'configurations') ----- generateEitherSqueakCogVM | coInterpreterClass | coInterpreterClass := self chooseCoInterpreterClassIfAbsent: [^self]. ^self generateSqueakCogVMWithInterpreterClass: coInterpreterClass + options: ((coInterpreterClass includesBehavior: CoInterpreterMT) - options: #( ISA IA32), - ((coInterpreterClass includesBehavior: CoInterpreterMT) ifTrue: [#(COGMTVM true)] ifFalse: [#()])! Item was changed: ----- Method: VMMaker class>>generateNewspeakSpurCogVM (in category 'configurations') ----- generateNewspeakSpurCogVM "No primitives since we can use those for the Cog Newspeak VM" ^VMMaker generate: CoInterpreter and: StackToRegisterMappingCogit with: #( ObjectMemory Spur32BitCoMemoryManager MULTIPLEBYTECODESETS true + NewspeakVM true) - NewspeakVM true - ISA IA32) to: (FileDirectory default pathFromURI: self sourceTree, '/nsspursrc') platformDir: (FileDirectory default pathFromURI: self sourceTree, '/platforms') including:#( AsynchFilePlugin BMPReadWriterPlugin BalloonEnginePlugin BitBltSimulation DeflatePlugin DSAPlugin DropPlugin FileCopyPlugin FilePlugin FloatArrayPlugin FloatMathPlugin ImmX11Plugin JPEGReadWriter2Plugin JPEGReaderPlugin LargeIntegersPlugin Matrix2x3Plugin MiscPrimitivePlugin NewsqueakIA32ABIPlugin RePlugin SecurityPlugin SocketPlugin SoundPlugin SqueakSSLPlugin SurfacePlugin UUIDPlugin UnixOSProcessPlugin UnixAioPlugin VMProfileLinuxSupportPlugin VMProfileMacSupportPlugin Win32OSProcessPlugin) ! Item was changed: ----- Method: VMMaker class>>generateSqueakSpurCogSistaVM (in category 'configurations') ----- generateSqueakSpurCogSistaVM "No primitives since we can use those for the Cog VM" ^VMMaker generate: CoInterpreter and: SistaStackToRegisterMappingCogit with: #( SistaVM true ObjectMemory Spur32BitCoMemoryManager MULTIPLEBYTECODESETS true - ISA IA32 bytecodeTableInitializer initializeBytecodeTableForSqueakV3PlusClosuresSistaV1Hybrid) to: (FileDirectory default pathFromURI: self sourceTree, '/spursistasrc') platformDir: (FileDirectory default pathFromURI: self sourceTree, '/platforms') including:#()! Item was changed: ----- Method: VMMaker class>>generateSqueakSpurCogVM (in category 'configurations') ----- generateSqueakSpurCogVM "No primitives since we can use those for the Cog VM" ^VMMaker generate: CoInterpreter and: StackToRegisterMappingCogit + with: #(ObjectMemory Spur32BitCoMemoryManager) - with: #( ObjectMemory Spur32BitCoMemoryManager - ISA IA32) to: (FileDirectory default pathFromURI: self sourceTree, '/spursrc') platformDir: (FileDirectory default pathFromURI: self sourceTree, '/platforms') including:#()! Item was added: + ----- Method: VMMaker class>>oldFileNamed: (in category 'utilities') ----- + oldFileNamed: aFilename + "Always output files in unix lf format. + A single format is friendlier to e.g. external version control systems. + The Microsoft and old MacOS classic C compilers all accept lf format files." + + ^(MultiByteFileStream oldFileNamed: aFilename) + lineEndConvention: #lf; + yourself! Item was removed: - ----- Method: VMMaker>>generateCogitFile (in category 'generate sources') ----- - generateCogitFile - "Translate the Smalltalk description of the virtual machine into C. If 'self doInlining' is true, small method bodies are inlined to reduce procedure call overhead. On the PPC, this results in a factor of three speedup with only 30% increase in code size. Subclasses can use specialised versions of CCodeGenerator and interpreterClass." - - | cg cogitClass | - (cogitClass := self interpreterClass cogitClass) ifNil: [^nil]. - cg := [self buildCodeGeneratorForCogit] - on: Notification - do: [:ex| - ex tag == #getVMMaker - ifTrue: [ex resume: self] - ifFalse: [(ex respondsTo: #rearmHandlerDuring:) - ifTrue: [ex rearmHandlerDuring: [ex pass]] - ifFalse: [ex pass]]]. - self needsToRegenerateCogitFile ifFalse: [^nil]. - - cg inferTypesForImplicitlyTypedVariablesAndMethods. - - cg vmClass preGenerationHook: cg. - cg storeCodeOnFile: (self sourceFilePathFor: cogitClass sourceFileName) doInlining: cogitClass doInlining. - cg vmClass additionalHeadersDo: - [:headerName :headerContents| | filePath | - filePath := self coreVMDirectory fullNameFor: headerName. - (cg needToGenerateHeader: headerName file: filePath contents: headerContents) ifTrue: - [cg storeHeaderOnFile: filePath contents: headerContents]]. - cogitClass apiExportHeaderName ifNotNil: - [cg storeAPIExportHeader: cogitClass apiExportHeaderName - OnFile: (self sourceFilePathFor: cogitClass apiExportHeaderName)]! Item was added: + ----- Method: VMMaker>>generateCogitFileFor: (in category 'generate sources') ----- + generateCogitFileFor: cogitClass + "Translate the Smalltalk description of the virtual machine into C. If 'self doInlining' is true, small method bodies are inlined to reduce procedure call overhead. On the PPC, this results in a factor of three speedup with only 30% increase in code size. Subclasses can use specialised versions of CCodeGenerator and interpreterClass." + + | cg | + cg := [self buildCodeGeneratorForCogit] + on: Notification + do: [:ex| + ex tag == #getVMMaker + ifTrue: [ex resume: self] + ifFalse: [(ex respondsTo: #rearmHandlerDuring:) + ifTrue: [ex rearmHandlerDuring: [ex pass]] + ifFalse: [ex pass]]]. + self needsToRegenerateCogitFile ifFalse: [^nil]. + + cg inferTypesForImplicitlyTypedVariablesAndMethods. + + cg vmClass preGenerationHook: cg. + cg storeCodeOnFile: (self sourceFilePathFor: cogitClass processorSpecificSourceFileName) doInlining: cogitClass doInlining. + ^cg! Item was added: + ----- Method: VMMaker>>generateCogitFiles (in category 'generate sources') ----- + generateCogitFiles + "Translate the Smalltalk description of the virtual machine into C. If 'self doInlining' is true, small method bodies are inlined to reduce procedure call overhead. On the PPC, this results in a factor of three speedup with only 30% increase in code size. Subclasses can use specialised versions of CCodeGenerator and interpreterClass." + + | cogitClass cg | + (cogitClass := self interpreterClass cogitClass) ifNil: [^nil]. + self generateCogitIncludeFileFor: cogitClass. + CogAbstractInstruction translateableSubclasses do: + [:compilerClass| + optionsDictionary at: #ISA put: compilerClass ISA. + cg := self generateCogitFileFor: cogitClass]. + cg vmClass additionalHeadersDo: + [:headerName :headerContents| | filePath | + filePath := self coreVMDirectory fullNameFor: headerName. + (cg needToGenerateHeader: headerName file: filePath contents: headerContents) ifTrue: + [cg storeHeaderOnFile: filePath contents: headerContents]]. + cogitClass apiExportHeaderName ifNotNil: + [cg storeAPIExportHeader: cogitClass apiExportHeaderName + OnFile: (self sourceFilePathFor: cogitClass apiExportHeaderName)]! Item was added: + ----- Method: VMMaker>>generateCogitIncludeFileFor: (in category 'generate sources') ----- + generateCogitIncludeFileFor: cogitClass + "Generate the skeletal cogit.c that includes the processor-specific cogit files." + + | code fileName file | + code := Cogit generateCodeStringForCogitDotC. + fileName := self coreVMDirectory fullNameFor: cogitClass sourceFileName. + ((self coreVMDirectory fileExists: cogitClass sourceFileName) + and: [(self class oldFileNamed: fileName) contents = code]) ifFalse: + [file := self class forceNewFileNamed: fileName. + [file nextPutAll: code] ensure: + [file close]]! Item was changed: ----- Method: VMMaker>>generateMainVM (in category 'generate sources') ----- generateMainVM "Generate the interp (and optionally the cogit), internal plugins and exports. N.B. generateInterpreterFile *must* preceed generateCogitFile so that the objectMemory and interpreter classes are initialized before the Cogit code is generated." self generateInterpreterFile; + generateCogitFiles; - generateCogitFile; processFilesForCoreVM; generateInternalPlugins; generateExportsFile! Item was changed: ----- Method: VMMaker>>needsToRegenerateCogitFile (in category 'generate sources') ----- needsToRegenerateCogitFile "Check the timestamp for the relevant classes and then the timestamp for the main source file (e.g. interp.c) file if it already exists. Answer if the file needs regenerating." | cogitClass cogitClasses tStamp | cogitClasses := (cogitClass := self interpreterClass cogitClass) withAllSuperclasses copyUpThrough: Cogit. cogitClasses addAllLast: (cogitClass ancilliaryClasses: self options). tStamp := cogitClasses inject: 0 into: [:tS :cl| tS max: cl timeStamp]. "don't translate if the file is newer than my timeStamp" + (self coreVMDirectory entryAt: cogitClass processorSpecificSourceFileName ifAbsent: [nil]) ifNotNil: - (self coreVMDirectory entryAt: cogitClass sourceFileName ifAbsent: [nil]) ifNotNil: [:fstat| tStamp < fstat modificationTime ifTrue: + [^self confirm: ('The ', self configurationNameIfAny, cogitClass printString, + ', ', cogitClass activeCompilerClass, '\classes have not been modified since the ', + cogitClass processorSpecificSourceFileName, + ' source file\was last generated. Do you still want to regenerate it?') withCRs]]. + ^true! - [^self confirm: 'The ', self configurationNameIfAny, cogitClass printString, ' classes have not been modified since\ the source file was last generated.\Do you still want to regenerate it?' withCRs]]. - ^true - !

1 0

[FIXED] SqueakSSL for Windows :)
by Marcel Taeumel 22 Apr '15

22 Apr '15

Hi, there! :) Tobias and I fixed the SqueakSSL implementation for Windows. Please find the modified source code attached and add it to the VM code repository. sqWin32SSL.c <http://forum.world.st/file/n4820813/sqWin32SSL.c> The fixes are: - SNI support - setting an Int property via sqSetIntPropertySSL(...) - Unicode problems when extracting the correct peerName in sqExtractPeerName Tobias will send around builds for the shared libraries ASAP. :) Best, Marcel -- View this message in context: http://forum.world.st/FIXED-SqueakSSL-for-Windows-tp4820813.html Sent from the Squeak VM mailing list archive at Nabble.com.

5 6

VM Maker: VMMaker.oscog-cb.1236.mcz
by commits＠source.squeak.org 22 Apr '15

22 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1236.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1236 Author: cb Time: 22 April 2015, 10:07:41.028 am UUID: cf4af270-9dfa-4f2a-b84c-0cdb3c5f4913 Ancestors: VMMaker.oscog-tpr.1235 changed the names of register allocation methods for more explict names, for instance, allocateOneReg -> allocateRegForStackTop Fixed a bug where not the best register was allocated in #== (was allocating a reg based on stackTop value instead of ssValue: 1) =============== Diff against VMMaker.oscog-tpr.1235 =============== Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode (in category 'bytecode generators') ----- genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode "SistaV1: * 254 11111110 kkkkkkkk jjjjjjjj branch If Not Instance Of Behavior/Array Of Behavior kkkkkkkk (+ Extend A * 256, where Extend A >= 0) distance jjjjjjjj (+ Extend B * 256, where Extend B >= 0)" | reg literal distance targetFixUp | + reg := self allocateRegForStackTopEntry. - reg := self allocateOneRegister. self ssTop popToReg: reg. literal := self getLiteral: (extA * 256 + byte1). extA := 0. distance := extB * 256 + byte2. extB := 0. targetFixUp := (self ensureFixupAt: bytecodePC + 3 + distance - initialPC) asUnsignedInteger. (objectMemory isArrayNonImm: literal) ifTrue: [objectRepresentation branchIf: reg notInstanceOfBehaviors: literal target: targetFixUp] ifFalse: [objectRepresentation branchIf: reg notInstanceOfBehavior: literal target: targetFixUp]. self genPopStackBytecode. ^0! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genJumpIf:to: (in category 'bytecode generator support') ----- genJumpIf: boolean to: targetBytecodePC "The heart of performance counting in Sista. Conditional branches are 6 times less frequent than sends and can provide basic block frequencies (send counters can't). Each conditional has a 32-bit counter split into an upper 16 bits counting executions and a lower half counting untaken executions of the branch. Executing the branch decrements the upper half, tripping if the count goes negative. Not taking the branch decrements the lower half. N.B. We *do not* eliminate dead branches (true ifTrue:/true ifFalse:) so that scanning for send and branch data is simplified and that branch data is correct." <inline: false> | desc ok counterAddress countTripped retry counterReg | <var: #ok type: #'AbstractInstruction *'> <var: #desc type: #'CogSimStackEntry *'> <var: #retry type: #'AbstractInstruction *'> <var: #countTripped type: #'AbstractInstruction *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super genJumpIf: boolean to: targetBytecodePC ]. self ssFlushTo: simStackPtr - 1. desc := self ssTop. self ssPop: 1. desc popToReg: TempReg. + counterReg := self allocateAnyReg. - counterReg := self allocateRegisterNotConflictingWith: 0. counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). counterIndex := counterIndex + 1. self flag: 'will need to use MoveAw32:R: if 64 bits'. self assert: objectMemory wordSize = CounterBytes. retry := self MoveAw: counterAddress R: counterReg. self SubCq: 16r10000 R: counterReg. "Count executed" "Don't write back if we trip; avoids wrapping count back to initial value, and if we trip we don't execute." countTripped := self JumpCarry: 0. self MoveR: counterReg Aw: counterAddress. "write back" "Cunning trick by LPD. If true and false are contiguous subtract the smaller. Correct result is either 0 or the distance between them. If result is not 0 or their distance send mustBeBoolean." self assert: (objectMemory objectAfter: objectMemory falseObject) = objectMemory trueObject. self annotate: (self SubCw: boolean R: TempReg) objRef: boolean. self JumpZero: (self ensureFixupAt: targetBytecodePC - initialPC). self SubCq: 1 R: counterReg. "Count untaken" self MoveR: counterReg Aw: counterAddress. "write back" self CmpCq: (boolean == objectMemory falseObject ifTrue: [objectMemory trueObject - objectMemory falseObject] ifFalse: [objectMemory falseObject - objectMemory trueObject]) R: TempReg. ok := self JumpZero: 0. self MoveCq: 0 R: counterReg. "if counterReg is 0 this is a mustBeBoolean, not a counter trip." countTripped jmpTarget: (self CallRT: (boolean == objectMemory falseObject ifTrue: [ceSendMustBeBooleanAddFalseTrampoline] ifFalse: [ceSendMustBeBooleanAddTrueTrampoline])). "If we're in an image which hasn't got the Sista code loaded then the ceCounterTripped: trampoline will return directly to machine code, returning the boolean. So the code should jump back to the retry point. The trampoline makes sure that TempReg has been reloaded." self annotateBytecode: self Label. self Jump: retry. ok jmpTarget: self Label. ^0! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor nExts rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts inlineCAB annotateInst counterAddress countTripped counterReg | <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super genSpecialSelectorComparison ]. self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]. "short-cut the jump if operands are SmallInteger constants." (argIsInt and: [rcvrIsInt]) ifTrue: [self cCode: '' inSmalltalk: "In Simulator ints are unsigned..." [rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt]. primDescriptor opcode caseOf: { [JumpLess] -> [result := rcvrInt < argInt]. [JumpLessOrEqual] -> [result := rcvrInt <= argInt]. [JumpGreater] -> [result := rcvrInt > argInt]. [JumpGreaterOrEqual] -> [result := rcvrInt >= argInt]. [JumpZero] -> [result := rcvrInt = argInt]. [JumpNonZero] -> [result := rcvrInt ~= argInt] }. "Must enter any annotatedConstants into the map" self annotateBytecodeIfAnnotated: (self ssValue: 1). self annotateBytecodeIfAnnotated: self ssTop. "Must annotate the bytecode for correct pc mapping." self ssPop: 2. ^self ssPushAnnotatedConstant: (result ifTrue: [objectMemory trueObject] ifFalse: [objectMemory falseObject])]. nextPC := bytecodePC + primDescriptor numBytes. nExts := 0. [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + (byte0 bitAnd: 256). branchDescriptor isExtension] whileTrue: [nExts := nExts + 1. nextPC := nextPC + branchDescriptor numBytes]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. targetBytecodePC := nextPC + branchDescriptor numBytes + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). postBranchPC := nextPC + branchDescriptor numBytes. argIsInt ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. annotateInst := self ssTop annotateUse. self ssPop: 2. self MoveR: ReceiverResultReg R: TempReg] ifFalse: [self marshallSendArguments: 1. self MoveR: Arg0Reg R: TempReg. rcvrIsInt ifFalse: [objectRepresentation isSmallIntegerTagNonZero ifTrue: [self AndR: ReceiverResultReg R: TempReg] ifFalse: [self OrR: ReceiverResultReg R: TempReg]]]. jumpNotSmallInts := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. + counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg). "Use this as the count reg, can't conflict with the registers for the arg and the receiver" - counterReg := self allocateRegisterNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg). "Use this as the count reg, can't conflict with the registers for the arg and the receiver" self ssAllocateRequiredReg: counterReg. "Use this as the count reg." counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). self flag: 'will need to use MoveAw32:R: if 64 bits'. self assert: objectMemory wordSize = CounterBytes. self MoveAw: counterAddress R: counterReg. self SubCq: 16r10000 R: counterReg. "Count executed" "If counter trips simply abort the inlined comparison and send continuing to the following branch *without* writing back. A double decrement will not trip the second time." countTripped := self JumpCarry: 0. self MoveR: counterReg Aw: counterAddress. "write back" argIsInt ifTrue: [annotateInst ifTrue: [self annotateBytecode: (self CmpCq: argInt R: ReceiverResultReg)] ifFalse: [self CmpCq: argInt R: ReceiverResultReg]] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self gen: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self SubCq: 1 R: counterReg. "Count untaken" self MoveR: counterReg Aw: counterAddress. "write back" self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). countTripped jmpTarget: (jumpNotSmallInts jmpTarget: self Label). argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg]. ^self genMarshalledSend: (coInterpreter specialSelector: byte0 - self firstSpecialSelectorBytecodeOffset) numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders (in category 'bytecode generators') ----- genSpecialSelectorEqualsEqualsWithForwarders "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor nExts label counterReg fixup counterAddress countTripped unforwardArg unforwardRcvr argReg rcvrReg regMask | <var: #fixup type: #'BytecodeFixup *'> <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> ((coInterpreter isOptimizedMethod: methodObj) or: [needsFrame not]) ifTrue: [ ^ super genSpecialSelectorEqualsEquals ]. primDescriptor := self generatorAt: byte0. regMask := 0. nextPC := bytecodePC + primDescriptor numBytes. nExts := 0. [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + (byte0 bitAnd: 256). branchDescriptor isExtension] whileTrue: [nExts := nExts + 1. nextPC := nextPC + branchDescriptor numBytes]. (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifTrue: [self ssFlushTo: simStackPtr - 2]. unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. "if the rcvr or the arg is an annotable constant, we need to push it to a register else the forwarder check can't jump back to the comparison after unforwarding the constant" unforwardArg ifTrue: [unforwardRcvr ifTrue: + [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. - [self allocateTwoRegistersInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue:1) popToReg: rcvrReg] ifFalse: + [argReg := self allocateRegForStackTopEntry. - [argReg := self allocateOneRegister. self ssTop popToReg: argReg]] ifFalse: [self assert: unforwardRcvr. + rcvrReg := self allocateRegForStackEntryAt: 1. - rcvrReg := self allocateOneRegister. (self ssValue:1) popToReg: rcvrReg]. argReg ifNotNil: [ regMask := self registerMaskFor: regMask ]. rcvrReg ifNotNil: [ regMask := regMask bitOr: (self registerMaskFor: rcvrReg) ]. "Here we can use Cq because the constant does not need to be annotated" self assert: (unforwardArg not or: [argReg notNil]). self assert: (unforwardRcvr not or: [rcvrReg notNil]). "Only interested in inlining if followed by a conditional branch." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genDirectEqualsEqualsArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg]. targetBytecodePC := nextPC + branchDescriptor numBytes + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). postBranchPC := nextPC + branchDescriptor numBytes. + counterReg := self allocateRegNotConflictingWith: regMask. "Use this as the count reg, can't conflict with the registers for the arg and the receiver of #==." - counterReg := self allocateRegisterNotConflictingWith: regMask. "Use this as the count reg, can't conflict with the registers for the arg and the receiver of #==." counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). self flag: 'will need to use MoveAw32:R: if 64 bits'. self assert: objectMemory wordSize = CounterBytes. self MoveAw: counterAddress R: counterReg. self SubCq: 16r10000 R: counterReg. "Count executed" "If counter trips simply abort the inlined comparison and send continuing to the following branch *without* writing back. A double decrement will not trip the second time." countTripped := self JumpCarry: 0. self MoveR: counterReg Aw: counterAddress. "write back" self assert: (unforwardArg or: [ unforwardRcvr ]). label := self Label. unforwardArg ifFalse: [ self CmpCq: self ssTop constant R: rcvrReg ] ifTrue: [ unforwardRcvr ifFalse: [ self CmpCq: (self ssValue: 1) constant R: argReg ] ifTrue: [ self CmpR: argReg R: rcvrReg ] ]. self ssPop: 2. branchDescriptor isBranchTrue ifTrue: [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. unforwardArg ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ] ]. branchDescriptor isBranchFalse ifTrue: [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. unforwardArg ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ] ]. self ssPop: -2. "the jump has not been taken and forwarders have been followed." self SubCq: 1 R: counterReg. "Count untaken" self MoveR: counterReg Aw: counterAddress. "write back" self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). countTripped jmpTarget: self Label. "inlined version of #== ignoring the branchDescriptor if the counter trips to have normal state for the optimizer" ^ self genDirectEqualsEqualsArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateAnyReg (in category 'simulation stack') ----- + allocateAnyReg + < inline: true > + ^ self allocateRegNotConflictingWith: 0! Item was removed: - ----- Method: StackToRegisterMappingCogit>>allocateOneRegister (in category 'simulation stack') ----- - allocateOneRegister - - self ssTop type = SSRegister ifTrue: [ ^ self ssTop register]. - - ^ self allocateRegisterNotConflictingWith: 0 - ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegForStackEntryAt: (in category 'simulation stack') ----- + allocateRegForStackEntryAt: index + <inline: true> + <var: #stackEntry type: #'CogSimStackEntry *'> + | stackEntry | + stackEntry := self ssValue: index. + stackEntry type = SSRegister ifTrue: [ ^ stackEntry register]. + ^ self allocateAnyReg + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegForStackTopEntry (in category 'simulation stack') ----- + allocateRegForStackTopEntry + ^ self allocateRegForStackEntryAt: 0 + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegForStackTopThreeEntriesInto:thirdIsReceiver: (in category 'simulation stack') ----- + allocateRegForStackTopThreeEntriesInto: trinaryBlock thirdIsReceiver: thirdIsReceiver + <inline: true> + | topRegistersMask rTop rNext rThird | + + topRegistersMask := 0. + + (self ssTop type = SSRegister and: [ thirdIsReceiver not or: [ self ssTop register ~= ReceiverResultReg ] ]) ifTrue: + [ topRegistersMask := self registerMaskFor: (rTop := self ssTop register)]. + ((self ssValue: 1) type = SSRegister and: [ thirdIsReceiver not or: [ (self ssValue: 1) register ~= ReceiverResultReg ] ]) ifTrue: + [ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rNext := (self ssValue: 1) register))]. + ((self ssValue: 2) type = SSRegister and: [thirdIsReceiver not or: [ (self ssValue: 2) register = ReceiverResultReg ] ]) ifTrue: + [ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rThird := (self ssValue: 2) register))]. + + rThird ifNil: + [ thirdIsReceiver + ifTrue: + [ rThird := ReceiverResultReg. "Free ReceiverResultReg if it was not free" + (self register: ReceiverResultReg isInMask: self liveRegisters) ifTrue: + [ self ssAllocateRequiredReg: ReceiverResultReg ]. + optStatus isReceiverResultRegLive: false ] + ifFalse: [ rThird := self allocateRegNotConflictingWith: topRegistersMask ]. + topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: rThird) ]. + + rTop ifNil: [ + rTop := self allocateRegNotConflictingWith: topRegistersMask. + topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: rTop) ]. + + rNext ifNil: [ rNext := self allocateRegNotConflictingWith: topRegistersMask ]. + + ^ trinaryBlock value: rTop value: rNext value: rThird + + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegForStackTopTwoEntriesInto: (in category 'simulation stack') ----- + allocateRegForStackTopTwoEntriesInto: binaryBlock + <inline: true> + | topRegistersMask rTop rNext | + + topRegistersMask := 0. + + self ssTop type = SSRegister ifTrue: + [ topRegistersMask := self registerMaskFor: (rTop := self ssTop register)]. + (self ssValue: 1) type = SSRegister ifTrue: + [ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rNext := (self ssValue: 1) register))]. + + rTop ifNil: [ rTop := self allocateRegNotConflictingWith: topRegistersMask ]. + + rNext ifNil: [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ]. + + ^ binaryBlock value: rTop value: rNext + + ! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateRegNotConflictingWith: (in category 'simulation stack') ----- + allocateRegNotConflictingWith: regMask + | reg | + "if there's a free register, use it" + reg := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: regMask). + reg ifNil: "No free register, choose one that does not conflict with regMask" + [reg := self freeAnyRegNotConflictingWith: regMask]. + reg = ReceiverResultReg ifTrue: "If we've allocated RcvrResultReg, it's not live anymore" + [ optStatus isReceiverResultRegLive: false ]. + ^ reg! Item was removed: - ----- Method: StackToRegisterMappingCogit>>allocateRegisterNotConflictingWith: (in category 'simulation stack') ----- - allocateRegisterNotConflictingWith: regMask - | reg | - "if there's a free register, use it" - reg := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: regMask). - reg ifNil: "No free register, choose one that does not conflict with regMask" - [reg := self freeRegisterNotConflictingWith: regMask]. - reg = ReceiverResultReg ifTrue: "If we've allocated RcvrResultReg, it's not live anymore" - [ optStatus isReceiverResultRegLive: false ]. - ^ reg! Item was removed: - ----- Method: StackToRegisterMappingCogit>>allocateThreeRegistersInto:thirdIsReceiver: (in category 'simulation stack') ----- - allocateThreeRegistersInto: trinaryBlock thirdIsReceiver: thirdIsReceiver - <inline: true> - | topRegistersMask rTop rNext rThird | - - topRegistersMask := 0. - - (self ssTop type = SSRegister and: [ thirdIsReceiver not or: [ self ssTop register ~= ReceiverResultReg ] ]) ifTrue: - [ topRegistersMask := self registerMaskFor: (rTop := self ssTop register)]. - ((self ssValue: 1) type = SSRegister and: [ thirdIsReceiver not or: [ (self ssValue: 1) register ~= ReceiverResultReg ] ]) ifTrue: - [ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rNext := (self ssValue: 1) register))]. - ((self ssValue: 2) type = SSRegister and: [thirdIsReceiver not or: [ (self ssValue: 2) register = ReceiverResultReg ] ]) ifTrue: - [ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rThird := (self ssValue: 2) register))]. - - rThird ifNil: - [ thirdIsReceiver - ifTrue: - [ rThird := ReceiverResultReg. "Free ReceiverResultReg if it was not free" - (self register: ReceiverResultReg isInMask: self liveRegisters) ifTrue: - [ self ssAllocateRequiredReg: ReceiverResultReg ]. - optStatus isReceiverResultRegLive: false ] - ifFalse: [ rThird := self allocateRegisterNotConflictingWith: topRegistersMask ]. - topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: rThird) ]. - - rTop ifNil: [ - rTop := self allocateRegisterNotConflictingWith: topRegistersMask. - topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: rTop) ]. - - rNext ifNil: [ rNext := self allocateRegisterNotConflictingWith: topRegistersMask ]. - - ^ trinaryBlock value: rTop value: rNext value: rThird - - ! Item was removed: - ----- Method: StackToRegisterMappingCogit>>allocateTwoRegistersInto: (in category 'simulation stack') ----- - allocateTwoRegistersInto: binaryBlock - <inline: true> - | topRegistersMask rTop rNext | - - topRegistersMask := 0. - - self ssTop type = SSRegister ifTrue: - [ topRegistersMask := self registerMaskFor: (rTop := self ssTop register)]. - (self ssValue: 1) type = SSRegister ifTrue: - [ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rNext := (self ssValue: 1) register))]. - - rTop ifNil: [ rTop := self allocateRegisterNotConflictingWith: topRegistersMask ]. - - rNext ifNil: [ rNext := self allocateRegisterNotConflictingWith: (self registerMaskFor: rTop) ]. - - ^ binaryBlock value: rTop value: rNext - - ! Item was removed: - ----- Method: StackToRegisterMappingCogit>>availableRegister (in category 'simulation stack') ----- - availableRegister - | reg | - reg := self availableRegisterOrNil. - reg ifNil: [self error: 'no available register']. - ^reg! Item was removed: - ----- Method: StackToRegisterMappingCogit>>availableRegisterOrNil (in category 'simulation stack') ----- - availableRegisterOrNil - ^backEnd availableRegisterOrNilFor: self liveRegisters! Item was added: + ----- Method: StackToRegisterMappingCogit>>freeAnyRegNotConflictingWith: (in category 'simulation stack') ----- + freeAnyRegNotConflictingWith: regMask + "Spill the closest register on stack not conflicting with regMask. + Assertion Failure if regMask has already all the registers" + <var: #desc type: #'CogSimStackEntry *'> + | reg index | + index := simSpillBase max: 0. + [reg isNil and: [index < simStackPtr] ] whileTrue: + [ | desc | + desc := self simStackAt: index. + desc type = SSRegister ifTrue: + [ (regMask anyMask: (self registerMaskFor: desc register)) ifFalse: + [ reg := desc register ] ]. + index := index + 1]. + self assert: reg notNil. + self ssAllocateRequiredReg: reg. + ^reg! Item was removed: - ----- Method: StackToRegisterMappingCogit>>freeRegisterNotConflictingWith: (in category 'simulation stack') ----- - freeRegisterNotConflictingWith: regMask - "Spill the closest register on stack not conflicting with regMask. - Assertion Failure if regMask has already all the registers" - <var: #desc type: #'CogSimStackEntry *'> - | reg index | - index := simSpillBase max: 0. - [reg isNil and: [index < simStackPtr] ] whileTrue: - [ | desc | - desc := self simStackAt: index. - desc type = SSRegister ifTrue: - [ (regMask anyMask: (self registerMaskFor: desc register)) ifFalse: - [ reg := desc register ] ]. - index := index + 1]. - self assert: reg notNil. - self ssAllocateRequiredReg: reg. - ^reg! Item was changed: ----- Method: StackToRegisterMappingCogit>>genBinaryConstOpVarInlinePrimitive: (in category 'inline primitive generators') ----- genBinaryConstOpVarInlinePrimitive: prim "Const op var version of binary inline primitives." "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution. See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:" | ra val untaggedVal adjust | + ra := self allocateRegForStackTopEntry. - ra := self allocateOneRegister. self ssTop popToReg: ra. self ssPop: 1. val := self ssTop constant. self ssPop: 1. untaggedVal := val - objectMemory smallIntegerTag. prim caseOf: { "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow" [0] -> [self AddCq: untaggedVal R: ra]. [1] -> [self MoveCq: val R: TempReg. self SubR: ra R: TempReg. objectRepresentation genAddSmallIntegerTagsTo: TempReg. self MoveR: TempReg R: ra]. [2] -> [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ra. self MoveCq: (objectMemory integerValueOf: val) R: TempReg. self MulR: TempReg R: ra. objectRepresentation genAddSmallIntegerTagsTo: ra]. "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow" "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)" "CmpCqR is SubRCq so everything is reversed, but because no CmpRCq things are reversed again and we invert the sense of the jumps." [32] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpLess opFalse: JumpGreaterOrEqual destReg: ra ]. [33] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpGreater opFalse: JumpLessOrEqual destReg: ra ]. [34] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpLessOrEqual opFalse: JumpGreater destReg: ra ]. [35] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpGreaterOrEqual opFalse: JumpLess destReg: ra ]. [36] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpZero opFalse: JumpNonZero destReg: ra ]. [37] -> [ self CmpCq: val R: ra. self genBinaryInlineComparison: JumpNonZero opFalse: JumpZero destReg: ra ]. "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop" [64] -> [objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. adjust := (objectMemory baseHeaderSize >> objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" adjust ~= 0 ifTrue: [ self AddCq: adjust R: ra. ]. self genMoveConstant: val R: TempReg. self MoveXwr: ra R: TempReg R: ra]. [65] -> [objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. adjust := objectMemory baseHeaderSize - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" self AddCq: adjust R: ra. self genMoveConstant: val R: TempReg. self MoveXbr: ra R: TempReg R: ra. objectRepresentation genConvertIntegerToSmallIntegerInReg: ra] } otherwise: [^EncounteredUnknownBytecode]. self ssPushRegister: ra. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genBinaryVarOpConstInlinePrimitive: (in category 'inline primitive generators') ----- genBinaryVarOpConstInlinePrimitive: prim "Var op const version of inline binary inline primitives." "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution. See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:" | rr val untaggedVal | val := self ssTop constant. self ssPop: 1. + rr := self allocateRegForStackTopEntry. - rr := self allocateOneRegister. self ssTop popToReg: rr. self ssPop: 1. untaggedVal := val - objectMemory smallIntegerTag. prim caseOf: { "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow" [0] -> [self AddCq: untaggedVal R: rr]. [1] -> [self SubCq: untaggedVal R: rr ]. [2] -> [self flag: 'could use MulCq:R'. objectRepresentation genShiftAwaySmallIntegerTagsInScratchReg: rr. self MoveCq: (objectMemory integerValueOf: val) R: TempReg. self MulR: TempReg R: rr. objectRepresentation genAddSmallIntegerTagsTo: rr]. "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow" "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)" "CmpCqR is SubRCq so everything is reversed." [32] -> [ self CmpCq: val R: rr. self genBinaryInlineComparison: JumpGreater opFalse: JumpLessOrEqual destReg: rr ]. [33] -> [ self CmpCq: val R: rr. self genBinaryInlineComparison: JumpLess opFalse: JumpGreaterOrEqual destReg: rr ]. [34] -> [ self CmpCq: val R: rr. self genBinaryInlineComparison: JumpGreaterOrEqual opFalse: JumpLess destReg: rr ]. [35] -> [ self CmpCq: val R: rr. self genBinaryInlineComparison: JumpLessOrEqual opFalse: JumpGreater destReg: rr ]. [36] -> [ self CmpCq: val R: rr. self genBinaryInlineComparison: JumpZero opFalse: JumpNonZero destReg: rr ]. [37] -> [ self CmpCq: val R: rr. self genBinaryInlineComparison: JumpNonZero opFalse: JumpZero destReg: rr ]. "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop" [64] -> [objectRepresentation genLoadSlot: (objectMemory integerValueOf: val) - 1 sourceReg: rr destReg: rr]. [65] -> [self MoveCq: (objectMemory integerValueOf: val) + objectMemory baseHeaderSize - 1 R: TempReg. self MoveXbr: TempReg R: rr R: rr. objectRepresentation genConvertIntegerToSmallIntegerInReg: rr] } otherwise: [^EncounteredUnknownBytecode]. self ssPushRegister: rr. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genBinaryVarOpVarInlinePrimitive: (in category 'inline primitive generators') ----- genBinaryVarOpVarInlinePrimitive: prim "Var op var version of binary inline primitives." "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution. See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:" | ra rr adjust | + self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext | ra := rTop. rr := rNext ]. - self allocateTwoRegistersInto: [:rTop :rNext | ra := rTop. rr := rNext ]. self ssTop popToReg: ra. self ssPop: 1. self ssTop popToReg: rr. self ssPop: 1. prim caseOf: { "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow" [0] -> [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ra. self AddR: ra R: rr]. [1] -> [self SubR: ra R: rr. objectRepresentation genAddSmallIntegerTagsTo: rr]. [2] -> [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: rr. objectRepresentation genShiftAwaySmallIntegerTagsInScratchReg: ra. self MulR: ra R: rr. objectRepresentation genAddSmallIntegerTagsTo: rr]. "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow" "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)" "CmpCqR is SubRCq so everything is reversed." [32] -> [ self CmpR: ra R: rr. self genBinaryInlineComparison: JumpGreater opFalse: JumpLessOrEqual destReg: rr ]. [33] -> [ self CmpR: ra R: rr. self genBinaryInlineComparison: JumpLess opFalse: JumpGreaterOrEqual destReg: rr ]. [34] -> [ self CmpR: ra R: rr. self genBinaryInlineComparison: JumpGreaterOrEqual opFalse: JumpLess destReg: rr ]. [35] -> [ self CmpR: ra R: rr. self genBinaryInlineComparison: JumpLessOrEqual opFalse: JumpGreater destReg: rr ]. [36] -> [ self CmpR: ra R: rr. self genBinaryInlineComparison: JumpZero opFalse: JumpNonZero destReg: rr ]. [37] -> [ self CmpR: ra R: rr. self genBinaryInlineComparison: JumpNonZero opFalse: JumpZero destReg: rr ]. "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop" [64] -> [objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. adjust := (objectMemory baseHeaderSize >> objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" adjust ~= 0 ifTrue: [ self AddCq: adjust R: ra. ]. self MoveXwr: ra R: rr R: rr ]. [65] -> [objectRepresentation genConvertSmallIntegerToIntegerInReg: ra. adjust := objectMemory baseHeaderSize - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" self AddCq: adjust R: ra. self MoveXbr: ra R: rr R: rr. objectRepresentation genConvertIntegerToSmallIntegerInReg: rr] } otherwise: [^EncounteredUnknownBytecode]. self ssPushRegister: rr. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genPushLiteralVariable: (in category 'bytecode generator support') ----- genPushLiteralVariable: literalIndex <inline: false> | association freeReg | + freeReg := self allocateAnyReg. - freeReg := self ssAllocatePreferredReg: ClassReg. association := self getLiteral: literalIndex. "N.B. Do _not_ use ReceiverResultReg to avoid overwriting receiver in assignment in frameless methods." "So far descriptors are not rich enough to describe the entire dereference so generate the register load but don't push the result. There is an order-of-evaluation issue if we defer the dereference." self genMoveConstant: association R: TempReg. objectRepresentation genEnsureObjInRegNotForwarded: TempReg scratchReg: freeReg. objectRepresentation genLoadSlot: ValueIndex sourceReg: TempReg destReg: freeReg. self ssPushRegister: freeReg. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders (in category 'bytecode generators') ----- genSpecialSelectorEqualsEqualsWithForwarders | primDescriptor nextPC nExts branchDescriptor unforwardRcvr argReg targetBytecodePC unforwardArg rcvrReg jumpNotEqual jumpEqual postBranchPC label fixup | <var: #fixup type: #'BytecodeFixup *'> <var: #jumpEqual type: #'AbstractInstruction *'> <var: #jumpNotEqual type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> primDescriptor := self generatorAt: byte0. nextPC := bytecodePC + primDescriptor numBytes. nExts := 0. [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + bytecodeSetOffset. branchDescriptor isExtension] whileTrue: [nExts := nExts + 1. nextPC := nextPC + branchDescriptor numBytes]. "If branching the stack must be flushed for the merge" (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifTrue: [self ssFlushTo: simStackPtr - 2]. unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. "if the rcvr or the arg is an annotable constant, we need to push it to a register else the forwarder check can't jump back to the comparison after unforwarding the constant" unforwardArg ifTrue: [unforwardRcvr ifTrue: + [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. - [self allocateTwoRegistersInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue:1) popToReg: rcvrReg] ifFalse: + [argReg := self allocateRegForStackTopEntry. - [argReg := self allocateOneRegister. self ssTop popToReg: argReg]] ifFalse: [self assert: unforwardRcvr. + rcvrReg := self allocateRegForStackEntryAt: 1. - rcvrReg := self allocateOneRegister. (self ssValue:1) popToReg: rcvrReg]. label := self Label. "Here we can use Cq because the constant does not need to be annotated" self assert: (unforwardArg not or: [argReg notNil]). self assert: (unforwardRcvr not or: [rcvrReg notNil]). unforwardArg ifFalse: [ self CmpCq: self ssTop constant R: rcvrReg ] ifTrue: [ unforwardRcvr ifFalse: [ self CmpCq: (self ssValue: 1) constant R: argReg ] ifTrue: [ self CmpR: argReg R: rcvrReg ] ]. self ssPop: 2. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [jumpEqual := self JumpZero: 0. unforwardArg ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ]. self genMoveFalseR: rcvrReg. jumpNotEqual := self Jump: 0. jumpEqual jmpTarget: (self genMoveTrueR: rcvrReg). jumpNotEqual jmpTarget: self Label. self ssPushRegister: rcvrReg. ^0]. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." targetBytecodePC := nextPC + branchDescriptor numBytes + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). postBranchPC := nextPC + branchDescriptor numBytes. (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" self assert: (unforwardArg or: [ unforwardRcvr ]). branchDescriptor isBranchTrue ifTrue: [ deadCode ifFalse: [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC ]. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. unforwardArg ifTrue: [ (deadCode or: [ unforwardRcvr ]) ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] ifFalse: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ] ]. unforwardRcvr ifTrue: [ deadCode ifTrue: [objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ] ifFalse: [objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ] ] ]. branchDescriptor isBranchFalse ifTrue: [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. unforwardArg ifTrue: [ unforwardRcvr ifFalse: [objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ] ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ]. "Not reached"]. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genTrinaryInlinePrimitive: (in category 'inline primitive generators') ----- genTrinaryInlinePrimitive: prim "Unary inline primitives." "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution. See EncoderForSistaV1's class comment and StackInterpreter>>#trinaryInlinePrimitive:" | ra1 ra2 rr adjust | "The store check requires rr to be ReceiverResultReg" + self + allocateRegForStackTopThreeEntriesInto: [:rTop :rNext :rThird | ra2 := rTop. ra1 := rNext. rr := rThird ] + thirdIsReceiver: prim = 0. - self allocateThreeRegistersInto: [:rTop :rNext :rThird | ra2 := rTop. ra1 := rNext. rr := rThird ] thirdIsReceiver: prim = 0. self assert: (rr ~= ra1 and: [rr ~= ra2 and: [ra1 ~= ra2]]). self ssTop popToReg: ra2. self ssPop: 1. self ssTop popToReg: ra1. self ssPop: 1. self ssTop popToReg: rr. self ssPop: 1. objectRepresentation genConvertSmallIntegerToIntegerInReg: ra1. "Now: ra is the variable object, rr is long, TempReg holds the value to store." prim caseOf: { "0 - 1 pointerAt:put: and byteAt:Put:" [0] -> [ adjust := (objectMemory baseHeaderSize >> objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" adjust ~= 0 ifTrue: [ self AddCq: adjust R: ra1. ]. self MoveR: ra2 Xwr: ra1 R: rr. objectRepresentation genStoreCheckReceiverReg: rr valueReg: ra2 scratchReg: TempReg inFrame: true]. [1] -> [ objectRepresentation genConvertSmallIntegerToIntegerInReg: ra2. adjust := objectMemory baseHeaderSize - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative" self AddCq: adjust R: ra1. self MoveR: ra2 Xbr: ra1 R: rr. objectRepresentation genConvertIntegerToSmallIntegerInReg: ra2. ] } otherwise: [^EncounteredUnknownBytecode]. self ssPushRegister: ra2. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genUnaryInlinePrimitive: (in category 'inline primitive generators') ----- genUnaryInlinePrimitive: prim "Unary inline primitives." "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution. See EncoderForSistaV1's class comment and StackInterpreter>>#unaryInlinePrimitive:" | rcvrReg resultReg | + rcvrReg := self allocateRegForStackTopEntry. + resultReg := self allocateRegNotConflictingWith: (self registerMaskFor: rcvrReg). - rcvrReg := self allocateOneRegister. - resultReg := self allocateRegisterNotConflictingWith: (self registerMaskFor: rcvrReg). self ssTop popToReg: rcvrReg. self ssPop: 1. prim caseOf: { "00 unchecked class" [1] -> "01 unchecked pointer numSlots" [objectRepresentation genGetNumSlotsOf: rcvrReg into: resultReg; genConvertIntegerToSmallIntegerInReg: resultReg]. "02 unchecked pointer basicSize" [3] -> "03 unchecked byte numBytes" [objectRepresentation genGetNumBytesOf: rcvrReg into: resultReg; genConvertIntegerToSmallIntegerInReg: resultReg]. "04 unchecked short16Type format numShorts" "05 unchecked word32Type format numWords" "06 unchecked doubleWord64Type format numDoubleWords" } otherwise: [^EncounteredUnknownBytecode].. self ssPushRegister: resultReg. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genVanillaSpecialSelectorEqualsEquals (in category 'bytecode generators') ----- genVanillaSpecialSelectorEqualsEquals | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor nExts jumpEqual jumpNotEqual rcvrReg argReg argIsConstant rcvrIsConstant | <var: #jumpEqual type: #'AbstractInstruction *'> <var: #jumpNotEqual type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> primDescriptor := self generatorAt: byte0. nextPC := bytecodePC + primDescriptor numBytes. nExts := 0. [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + bytecodeSetOffset. branchDescriptor isExtension] whileTrue: [nExts := nExts + 1. nextPC := nextPC + branchDescriptor numBytes]. "If branching the stack must be flushed for the merge" (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifTrue: [self ssFlushTo: simStackPtr - 2]. "Don't use ReceiverResultReg for receiver to keep ReceiverResultReg live. Optimize e.g. rcvr == nil, the common case for ifNil: et al." argIsConstant := self ssTop type = SSConstant. rcvrIsConstant := argIsConstant and: [ (self ssValue:1) type = SSConstant ]. argIsConstant ifFalse: [rcvrIsConstant ifFalse: + [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. - [self allocateTwoRegistersInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. self ssTop popToReg: argReg. (self ssValue:1) popToReg: rcvrReg] ifTrue: + [argReg := self allocateRegForStackTopEntry. - [argReg := self allocateOneRegister. self ssTop popToReg: argReg]] ifTrue: [self assert: rcvrIsConstant not. + rcvrReg := self allocateRegForStackEntryAt: 1. - rcvrReg := self allocateOneRegister. (self ssValue:1) popToReg: rcvrReg]. argIsConstant ifTrue: [ self genCompConstant: self ssTop constant R: rcvrReg ] ifFalse: [ rcvrIsConstant ifTrue: [ self genCompConstant: (self ssValue: 1) constant R: argReg ] ifFalse: [ self CmpR: argReg R: rcvrReg ] ]. self ssPop: 2. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [jumpNotEqual := self JumpNonZero: 0. self genMoveTrueR: rcvrReg. jumpEqual := self Jump: 0. jumpNotEqual jmpTarget: (self genMoveFalseR: rcvrReg). jumpEqual jmpTarget: self Label. self ssPushRegister: rcvrReg. ^0]. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." targetBytecodePC := nextPC + branchDescriptor numBytes + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). postBranchPC := nextPC + branchDescriptor numBytes. (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" self gen: (branchDescriptor isBranchTrue ifTrue: [JumpZero] ifFalse: [JumpNonZero]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. deadCode ifFalse: [self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC)]. ^0! Item was removed: - ----- Method: StackToRegisterMappingCogit>>ssAllocatePreferredReg: (in category 'simulation stack') ----- - ssAllocatePreferredReg: preferredReg - | preferredMask lastPreferred liveRegs | - lastPreferred := -1. - "compute live regs while noting the last occurrence of preferredReg. - If there are none free we must spill from simSpillBase to last occurrence." - preferredMask := (self registerMaskFor: preferredReg). - liveRegs := self registerMaskFor: TempReg and: FPReg and: SPReg. - (simSpillBase max: 0) to: simStackPtr do: - [:i| - liveRegs := liveRegs bitOr: (self simStackAt: i) registerMask. - (liveRegs bitAnd: preferredMask) ~= 0 ifTrue: - [lastPreferred := i]]. - "If preferredReg is not live we can allocate it." - (self register: preferredReg isInMask: liveRegs) ifFalse: - [^preferredReg]. - "If any other is not live we can allocate it." - GPRegMin to: GPRegMax do: - [:reg| - (self register: reg isInMask: liveRegs) ifFalse: - [^reg]]. - "All live, must spill" - self ssFlushTo: lastPreferred. - self assert: (self liveRegisters bitAnd: preferredMask) = 0. - ^preferredReg!

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Vm-dev April 2015