Vm-dev April 2015

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Re: [Vm-dev] VM Maker: VMMaker.oscog-cb.1236.mcz
by Clément Bera 25 Apr '15

25 Apr '15

Eliot here's a good example to stress the register allocation: Integer>>#regStress | t t2 | t := self yourself. t2 := self + 1. ^ { t == t2 . t == t2 . t == t2 . t == t2 . t == t2 . t == t2 . t == t2 } I think the resulting machine code method is beautiful, it needs to spill only when it runs out of registers :-). Of course it makes sense mainly when you use inlined bytecodes instead of only #==. Some extra register moves are done because the JIT does remember if a temporary value is currently in a register (It moves each time the temp t to the same register whereas the register value is not changed). Maybe we should add a feature that remembers if temporaries are currently in a register, and if so, when doing push temp, only push the register directly in the simStack, and in case of temporary store or stack flush the register associated with a temp is not valid anymore somehow... 2015-04-22 10:08 GMT+02:00 <commits(a)source.squeak.org>: > > Eliot Miranda uploaded a new version of VMMaker to project VM Maker: > http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1236.mcz > > ==================== Summary ==================== > > Name: VMMaker.oscog-cb.1236 > Author: cb > Time: 22 April 2015, 10:07:41.028 am > UUID: cf4af270-9dfa-4f2a-b84c-0cdb3c5f4913 > Ancestors: VMMaker.oscog-tpr.1235 > > changed the names of register allocation methods for more explict names, > for instance, allocateOneReg -> allocateRegForStackTop > > Fixed a bug where not the best register was allocated in #== (was > allocating a reg based on stackTop value instead of ssValue: 1) > > =============== Diff against VMMaker.oscog-tpr.1235 =============== > > Item was changed: > ----- Method: > SistaStackToRegisterMappingCogit>>genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode > (in category 'bytecode generators') ----- > genExtJumpIfNotInstanceOfBehaviorsOrPopBytecode > "SistaV1: * 254 11111110 kkkkkkkk > jjjjjjjj branch If Not Instance Of Behavior/Array Of > Behavior kkkkkkkk (+ Extend A * 256, where Extend A >= 0) distance jjjjjjjj > (+ Extend B * 256, where Extend B >= 0)" > > | reg literal distance targetFixUp | > > + reg := self allocateRegForStackTopEntry. > - reg := self allocateOneRegister. > self ssTop popToReg: reg. > > literal := self getLiteral: (extA * 256 + byte1). > extA := 0. > distance := extB * 256 + byte2. > extB := 0. > > targetFixUp := (self ensureFixupAt: bytecodePC + 3 + distance - > initialPC) asUnsignedInteger. > > (objectMemory isArrayNonImm: literal) > ifTrue: [objectRepresentation branchIf: reg > notInstanceOfBehaviors: literal target: targetFixUp] > ifFalse: [objectRepresentation branchIf: reg > notInstanceOfBehavior: literal target: targetFixUp]. > > self genPopStackBytecode. > > ^0! > > Item was changed: > ----- Method: SistaStackToRegisterMappingCogit>>genJumpIf:to: (in > category 'bytecode generator support') ----- > genJumpIf: boolean to: targetBytecodePC > "The heart of performance counting in Sista. Conditional branches > are 6 times less > frequent than sends and can provide basic block frequencies (send > counters can't). > Each conditional has a 32-bit counter split into an upper 16 bits > counting executions > and a lower half counting untaken executions of the branch. > Executing the branch > decrements the upper half, tripping if the count goes negative. > Not taking the branch > decrements the lower half. N.B. We *do not* eliminate dead > branches (true ifTrue:/true ifFalse:) > so that scanning for send and branch data is simplified and that > branch data is correct." > <inline: false> > | desc ok counterAddress countTripped retry counterReg | > <var: #ok type: #'AbstractInstruction *'> > <var: #desc type: #'CogSimStackEntry *'> > <var: #retry type: #'AbstractInstruction *'> > <var: #countTripped type: #'AbstractInstruction *'> > > (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super > genJumpIf: boolean to: targetBytecodePC ]. > > self ssFlushTo: simStackPtr - 1. > desc := self ssTop. > self ssPop: 1. > desc popToReg: TempReg. > > + counterReg := self allocateAnyReg. > - counterReg := self allocateRegisterNotConflictingWith: 0. > counterAddress := counters + ((self sizeof: #sqInt) * > counterIndex). > counterIndex := counterIndex + 1. > self flag: 'will need to use MoveAw32:R: if 64 bits'. > self assert: objectMemory wordSize = CounterBytes. > retry := self MoveAw: counterAddress R: counterReg. > self SubCq: 16r10000 R: counterReg. "Count executed" > "Don't write back if we trip; avoids wrapping count back to > initial value, and if we trip we don't execute." > countTripped := self JumpCarry: 0. > self MoveR: counterReg Aw: counterAddress. "write back" > > "Cunning trick by LPD. If true and false are contiguous subtract > the smaller. > Correct result is either 0 or the distance between them. If > result is not 0 or > their distance send mustBeBoolean." > self assert: (objectMemory objectAfter: objectMemory falseObject) > = objectMemory trueObject. > self annotate: (self SubCw: boolean R: TempReg) objRef: boolean. > self JumpZero: (self ensureFixupAt: targetBytecodePC - initialPC). > > self SubCq: 1 R: counterReg. "Count untaken" > self MoveR: counterReg Aw: counterAddress. "write back" > > self CmpCq: (boolean == objectMemory falseObject > ifTrue: [objectMemory trueObject - > objectMemory falseObject] > ifFalse: [objectMemory falseObject > - objectMemory trueObject]) > R: TempReg. > ok := self JumpZero: 0. > self MoveCq: 0 R: counterReg. "if counterReg is 0 this is a > mustBeBoolean, not a counter trip." > countTripped jmpTarget: > (self CallRT: (boolean == objectMemory falseObject > ifTrue: > [ceSendMustBeBooleanAddFalseTrampoline] > ifFalse: > [ceSendMustBeBooleanAddTrueTrampoline])). > "If we're in an image which hasn't got the Sista code loaded then > the ceCounterTripped: > trampoline will return directly to machine code, returning the > boolean. So the code should > jump back to the retry point. The trampoline makes sure that > TempReg has been reloaded." > self annotateBytecode: self Label. > self Jump: retry. > ok jmpTarget: self Label. > ^0! > > Item was changed: > ----- Method: > SistaStackToRegisterMappingCogit>>genSpecialSelectorComparison (in category > 'bytecode generators') ----- > genSpecialSelectorComparison > "Override to count inlined branches if followed by a conditional > branch. > We borrow the following conditional branch's counter and when > about to > inline the comparison we decrement the counter (without writing > it back) > and if it trips simply abort the inlining, falling back to the > normal send which > will then continue to the conditional branch which will trip and > enter the abort." > | nextPC postBranchPC targetBytecodePC primDescriptor > branchDescriptor nExts > rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts > inlineCAB annotateInst > counterAddress countTripped counterReg | > <var: #countTripped type: #'AbstractInstruction *'> > <var: #primDescriptor type: #'BytecodeDescriptor *'> > <var: #jumpNotSmallInts type: #'AbstractInstruction *'> > <var: #branchDescriptor type: #'BytecodeDescriptor *'> > > (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super > genSpecialSelectorComparison ]. > > self ssFlushTo: simStackPtr - 2. > primDescriptor := self generatorAt: byte0. > argIsInt := self ssTop type = SSConstant > and: [objectMemory isIntegerObject: > (argInt := self ssTop constant)]. > rcvrIsInt := (self ssValue: 1) type = SSConstant > and: [objectMemory isIntegerObject: > (rcvrInt := (self ssValue: 1) constant)]. > > "short-cut the jump if operands are SmallInteger constants." > (argIsInt and: [rcvrIsInt]) ifTrue: > [self cCode: '' inSmalltalk: "In Simulator ints are > unsigned..." > [rcvrInt := objectMemory integerValueOf: > rcvrInt. > argInt := objectMemory integerValueOf: > argInt]. > primDescriptor opcode caseOf: { > [JumpLess] -> [result > := rcvrInt < argInt]. > [JumpLessOrEqual] -> [result := > rcvrInt <= argInt]. > [JumpGreater] -> [result := > rcvrInt > argInt]. > [JumpGreaterOrEqual] -> [result := rcvrInt >= > argInt]. > [JumpZero] -> [result > := rcvrInt = argInt]. > [JumpNonZero] -> [result := > rcvrInt ~= argInt] }. > "Must enter any annotatedConstants into the map" > self annotateBytecodeIfAnnotated: (self ssValue: 1). > self annotateBytecodeIfAnnotated: self ssTop. > "Must annotate the bytecode for correct pc mapping." > self ssPop: 2. > ^self ssPushAnnotatedConstant: (result > > ifTrue: [objectMemory trueObject] > > ifFalse: [objectMemory falseObject])]. > > nextPC := bytecodePC + primDescriptor numBytes. > nExts := 0. > [branchDescriptor := self generatorAt: (objectMemory fetchByte: > nextPC ofObject: methodObj) + (byte0 bitAnd: 256). > branchDescriptor isExtension] whileTrue: > [nExts := nExts + 1. > nextPC := nextPC + branchDescriptor numBytes]. > "Only interested in inlining if followed by a conditional branch." > inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor > isBranchFalse]. > "Further, only interested in inlining = and ~= if there's a > SmallInteger constant involved. > The relational operators successfully statically predict > SmallIntegers; the equality operators do not." > (inlineCAB and: [primDescriptor opcode = JumpZero or: > [primDescriptor opcode = JumpNonZero]]) ifTrue: > [inlineCAB := argIsInt or: [rcvrIsInt]]. > inlineCAB ifFalse: > [^self genSpecialSelectorSend]. > > targetBytecodePC := nextPC > + branchDescriptor > numBytes > + (self spanFor: > branchDescriptor at: nextPC exts: nExts in: methodObj). > postBranchPC := nextPC + branchDescriptor numBytes. > argIsInt > ifTrue: > [(self ssValue: 1) popToReg: ReceiverResultReg. > annotateInst := self ssTop annotateUse. > self ssPop: 2. > self MoveR: ReceiverResultReg R: TempReg] > ifFalse: > [self marshallSendArguments: 1. > self MoveR: Arg0Reg R: TempReg. > rcvrIsInt ifFalse: > [objectRepresentation > isSmallIntegerTagNonZero > ifTrue: [self AndR: > ReceiverResultReg R: TempReg] > ifFalse: [self OrR: > ReceiverResultReg R: TempReg]]]. > jumpNotSmallInts := objectRepresentation > genJumpNotSmallIntegerInScratchReg: TempReg. > > + counterReg := self allocateRegNotConflictingWith: (self > registerMaskFor: ReceiverResultReg and: Arg0Reg). "Use this as the count > reg, can't conflict with the registers for the arg and the receiver" > - counterReg := self allocateRegisterNotConflictingWith: (self > registerMaskFor: ReceiverResultReg and: Arg0Reg). "Use this as the count > reg, can't conflict with the registers for the arg and the receiver" > self ssAllocateRequiredReg: counterReg. "Use this as the count > reg." > counterAddress := counters + ((self sizeof: #sqInt) * > counterIndex). > self flag: 'will need to use MoveAw32:R: if 64 bits'. > self assert: objectMemory wordSize = CounterBytes. > self MoveAw: counterAddress R: counterReg. > self SubCq: 16r10000 R: counterReg. "Count executed" > "If counter trips simply abort the inlined comparison and send > continuing to the following > branch *without* writing back. A double decrement will not trip > the second time." > countTripped := self JumpCarry: 0. > self MoveR: counterReg Aw: counterAddress. "write back" > > argIsInt > ifTrue: [annotateInst > ifTrue: [self annotateBytecode: > (self CmpCq: argInt R: ReceiverResultReg)] > ifFalse: [self CmpCq: argInt R: > ReceiverResultReg]] > ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. > "Cmp is weird/backwards so invert the comparison. Further since > there is a following conditional > jump bytecode define non-merge fixups and leave the cond bytecode > to set the mergeness." > self gen: (branchDescriptor isBranchTrue > ifTrue: [primDescriptor opcode] > ifFalse: [self inverseBranchFor: > primDescriptor opcode]) > operand: (self ensureNonMergeFixupAt: targetBytecodePC - > initialPC) asUnsignedInteger. > self SubCq: 1 R: counterReg. "Count untaken" > self MoveR: counterReg Aw: counterAddress. "write back" > self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). > countTripped jmpTarget: (jumpNotSmallInts jmpTarget: self Label). > argIsInt ifTrue: > [self MoveCq: argInt R: Arg0Reg]. > ^self genMarshalledSend: (coInterpreter specialSelector: byte0 - > self firstSpecialSelectorBytecodeOffset) > numArgs: 1 > sendTable: ordinarySendTrampolines! > > Item was changed: > ----- Method: > SistaStackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders > (in category 'bytecode generators') ----- > genSpecialSelectorEqualsEqualsWithForwarders > "Override to count inlined branches if followed by a conditional > branch. > We borrow the following conditional branch's counter and when > about to > inline the comparison we decrement the counter (without writing > it back) > and if it trips simply abort the inlining, falling back to the > normal send which > will then continue to the conditional branch which will trip and > enter the abort." > | nextPC postBranchPC targetBytecodePC primDescriptor > branchDescriptor nExts label counterReg fixup > counterAddress countTripped unforwardArg unforwardRcvr argReg > rcvrReg regMask | > <var: #fixup type: #'BytecodeFixup *'> > <var: #countTripped type: #'AbstractInstruction *'> > <var: #primDescriptor type: #'BytecodeDescriptor *'> > <var: #branchDescriptor type: #'BytecodeDescriptor *'> > > ((coInterpreter isOptimizedMethod: methodObj) or: [needsFrame > not]) ifTrue: [ ^ super genSpecialSelectorEqualsEquals ]. > > primDescriptor := self generatorAt: byte0. > regMask := 0. > > nextPC := bytecodePC + primDescriptor numBytes. > nExts := 0. > [branchDescriptor := self generatorAt: (objectMemory fetchByte: > nextPC ofObject: methodObj) + (byte0 bitAnd: 256). > branchDescriptor isExtension] whileTrue: > [nExts := nExts + 1. > nextPC := nextPC + branchDescriptor numBytes]. > > (branchDescriptor isBranchTrue or: [branchDescriptor > isBranchFalse]) ifTrue: > [self ssFlushTo: simStackPtr - 2]. > > unforwardRcvr := (objectRepresentation isUnannotatableConstant: > (self ssValue: 1)) not. > unforwardArg := (objectRepresentation isUnannotatableConstant: > self ssTop) not. > > "if the rcvr or the arg is an annotable constant, we need to push > it to a register > else the forwarder check can't jump back to the comparison after > unforwarding the constant" > unforwardArg > ifTrue: > [unforwardRcvr > ifTrue: > + [self > allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. > rcvrReg := rNext]. > - [self allocateTwoRegistersInto: > [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. > self ssTop popToReg: argReg. > (self ssValue:1) popToReg: > rcvrReg] > ifFalse: > + [argReg := self > allocateRegForStackTopEntry. > - [argReg := self > allocateOneRegister. > self ssTop popToReg: argReg]] > ifFalse: > [self assert: unforwardRcvr. > + rcvrReg := self allocateRegForStackEntryAt: 1. > - rcvrReg := self allocateOneRegister. > (self ssValue:1) popToReg: rcvrReg]. > > argReg ifNotNil: [ regMask := self registerMaskFor: regMask ]. > rcvrReg ifNotNil: [ regMask := regMask bitOr: (self > registerMaskFor: rcvrReg) ]. > > "Here we can use Cq because the constant does not need to be > annotated" > self assert: (unforwardArg not or: [argReg notNil]). > self assert: (unforwardRcvr not or: [rcvrReg notNil]). > > "Only interested in inlining if followed by a conditional branch." > (branchDescriptor isBranchTrue or: [branchDescriptor > isBranchFalse]) ifFalse: > [^ self genDirectEqualsEqualsArg: unforwardArg rcvr: > unforwardRcvr argReg: argReg rcvrReg: rcvrReg]. > > targetBytecodePC := nextPC > + branchDescriptor > numBytes > + (self spanFor: > branchDescriptor at: nextPC exts: nExts in: methodObj). > postBranchPC := nextPC + branchDescriptor numBytes. > > + counterReg := self allocateRegNotConflictingWith: regMask. "Use > this as the count reg, can't conflict with the registers for the arg and > the receiver of #==." > - counterReg := self allocateRegisterNotConflictingWith: regMask. > "Use this as the count reg, can't conflict with the registers for the arg > and the receiver of #==." > counterAddress := counters + ((self sizeof: #sqInt) * > counterIndex). > self flag: 'will need to use MoveAw32:R: if 64 bits'. > self assert: objectMemory wordSize = CounterBytes. > self MoveAw: counterAddress R: counterReg. > self SubCq: 16r10000 R: counterReg. "Count executed" > "If counter trips simply abort the inlined comparison and send > continuing to the following > branch *without* writing back. A double decrement will not trip > the second time." > countTripped := self JumpCarry: 0. > self MoveR: counterReg Aw: counterAddress. "write back" > > self assert: (unforwardArg or: [ unforwardRcvr ]). > > label := self Label. > > unforwardArg > ifFalse: [ self CmpCq: self ssTop constant R: rcvrReg ] > ifTrue: [ unforwardRcvr > ifFalse: [ self CmpCq: (self ssValue: 1) constant > R: argReg ] > ifTrue: [ self CmpR: argReg R: rcvrReg ] ]. > > self ssPop: 2. > branchDescriptor isBranchTrue ifTrue: > [ fixup := self ensureNonMergeFixupAt: postBranchPC - > initialPC. > self JumpZero: (self ensureNonMergeFixupAt: > targetBytecodePC - initialPC) asUnsignedInteger. > unforwardArg ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: > label ]. > unforwardRcvr ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: > label ] ]. > branchDescriptor isBranchFalse ifTrue: > [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - > initialPC. > self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - > initialPC) asUnsignedInteger. > unforwardArg ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label > ]. > unforwardRcvr ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: > label ] ]. > self ssPop: -2. > > "the jump has not been taken and forwarders have been followed." > self SubCq: 1 R: counterReg. "Count untaken" > self MoveR: counterReg Aw: counterAddress. "write back" > self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). > > countTripped jmpTarget: self Label. > > "inlined version of #== ignoring the branchDescriptor if the > counter trips to have normal state for the optimizer" > ^ self genDirectEqualsEqualsArg: unforwardArg rcvr: unforwardRcvr > argReg: argReg rcvrReg: rcvrReg! > > Item was added: > + ----- Method: StackToRegisterMappingCogit>>allocateAnyReg (in category > 'simulation stack') ----- > + allocateAnyReg > + < inline: true > > + ^ self allocateRegNotConflictingWith: 0! > > Item was removed: > - ----- Method: StackToRegisterMappingCogit>>allocateOneRegister (in > category 'simulation stack') ----- > - allocateOneRegister > - > - self ssTop type = SSRegister ifTrue: [ ^ self ssTop register]. > - > - ^ self allocateRegisterNotConflictingWith: 0 > - ! > > Item was added: > + ----- Method: StackToRegisterMappingCogit>>allocateRegForStackEntryAt: > (in category 'simulation stack') ----- > + allocateRegForStackEntryAt: index > + <inline: true> > + <var: #stackEntry type: #'CogSimStackEntry *'> > + | stackEntry | > + stackEntry := self ssValue: index. > + stackEntry type = SSRegister ifTrue: [ ^ stackEntry register]. > + ^ self allocateAnyReg > + ! > > Item was added: > + ----- Method: StackToRegisterMappingCogit>>allocateRegForStackTopEntry > (in category 'simulation stack') ----- > + allocateRegForStackTopEntry > + ^ self allocateRegForStackEntryAt: 0 > + ! > > Item was added: > + ----- Method: > StackToRegisterMappingCogit>>allocateRegForStackTopThreeEntriesInto:thirdIsReceiver: > (in category 'simulation stack') ----- > + allocateRegForStackTopThreeEntriesInto: trinaryBlock thirdIsReceiver: > thirdIsReceiver > + <inline: true> > + | topRegistersMask rTop rNext rThird | > + > + topRegistersMask := 0. > + > + (self ssTop type = SSRegister and: [ thirdIsReceiver not or: [ > self ssTop register ~= ReceiverResultReg ] ]) ifTrue: > + [ topRegistersMask := self registerMaskFor: (rTop := self > ssTop register)]. > + ((self ssValue: 1) type = SSRegister and: [ thirdIsReceiver not > or: [ (self ssValue: 1) register ~= ReceiverResultReg ] ]) ifTrue: > + [ topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: (rNext := (self ssValue: 1) register))]. > + ((self ssValue: 2) type = SSRegister and: [thirdIsReceiver not or: > [ (self ssValue: 2) register = ReceiverResultReg ] ]) ifTrue: > + [ topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: (rThird := (self ssValue: 2) register))]. > + > + rThird ifNil: > + [ thirdIsReceiver > + ifTrue: > + [ rThird := ReceiverResultReg. "Free > ReceiverResultReg if it was not free" > + (self register: ReceiverResultReg > isInMask: self liveRegisters) ifTrue: > + [ self ssAllocateRequiredReg: > ReceiverResultReg ]. > + optStatus isReceiverResultRegLive: false ] > + ifFalse: [ rThird := self > allocateRegNotConflictingWith: topRegistersMask ]. > + topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: rThird) ]. > + > + rTop ifNil: [ > + rTop := self allocateRegNotConflictingWith: > topRegistersMask. > + topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: rTop) ]. > + > + rNext ifNil: [ rNext := self allocateRegNotConflictingWith: > topRegistersMask ]. > + > + ^ trinaryBlock value: rTop value: rNext value: rThird > + > + ! > > Item was added: > + ----- Method: > StackToRegisterMappingCogit>>allocateRegForStackTopTwoEntriesInto: (in > category 'simulation stack') ----- > + allocateRegForStackTopTwoEntriesInto: binaryBlock > + <inline: true> > + | topRegistersMask rTop rNext | > + > + topRegistersMask := 0. > + > + self ssTop type = SSRegister ifTrue: > + [ topRegistersMask := self registerMaskFor: (rTop := self > ssTop register)]. > + (self ssValue: 1) type = SSRegister ifTrue: > + [ topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: (rNext := (self ssValue: 1) register))]. > + > + rTop ifNil: [ rTop := self allocateRegNotConflictingWith: > topRegistersMask ]. > + > + rNext ifNil: [ rNext := self allocateRegNotConflictingWith: (self > registerMaskFor: rTop) ]. > + > + ^ binaryBlock value: rTop value: rNext > + > + ! > > Item was added: > + ----- Method: > StackToRegisterMappingCogit>>allocateRegNotConflictingWith: (in category > 'simulation stack') ----- > + allocateRegNotConflictingWith: regMask > + | reg | > + "if there's a free register, use it" > + reg := backEnd availableRegisterOrNilFor: (self liveRegisters > bitOr: regMask). > + reg ifNil: "No free register, choose one that does not conflict > with regMask" > + [reg := self freeAnyRegNotConflictingWith: regMask]. > + reg = ReceiverResultReg ifTrue: "If we've allocated RcvrResultReg, > it's not live anymore" > + [ optStatus isReceiverResultRegLive: false ]. > + ^ reg! > > Item was removed: > - ----- Method: > StackToRegisterMappingCogit>>allocateRegisterNotConflictingWith: (in > category 'simulation stack') ----- > - allocateRegisterNotConflictingWith: regMask > - | reg | > - "if there's a free register, use it" > - reg := backEnd availableRegisterOrNilFor: (self liveRegisters > bitOr: regMask). > - reg ifNil: "No free register, choose one that does not conflict > with regMask" > - [reg := self freeRegisterNotConflictingWith: regMask]. > - reg = ReceiverResultReg ifTrue: "If we've allocated RcvrResultReg, > it's not live anymore" > - [ optStatus isReceiverResultRegLive: false ]. > - ^ reg! > > Item was removed: > - ----- Method: > StackToRegisterMappingCogit>>allocateThreeRegistersInto:thirdIsReceiver: > (in category 'simulation stack') ----- > - allocateThreeRegistersInto: trinaryBlock thirdIsReceiver: thirdIsReceiver > - <inline: true> > - | topRegistersMask rTop rNext rThird | > - > - topRegistersMask := 0. > - > - (self ssTop type = SSRegister and: [ thirdIsReceiver not or: [ > self ssTop register ~= ReceiverResultReg ] ]) ifTrue: > - [ topRegistersMask := self registerMaskFor: (rTop := self > ssTop register)]. > - ((self ssValue: 1) type = SSRegister and: [ thirdIsReceiver not > or: [ (self ssValue: 1) register ~= ReceiverResultReg ] ]) ifTrue: > - [ topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: (rNext := (self ssValue: 1) register))]. > - ((self ssValue: 2) type = SSRegister and: [thirdIsReceiver not or: > [ (self ssValue: 2) register = ReceiverResultReg ] ]) ifTrue: > - [ topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: (rThird := (self ssValue: 2) register))]. > - > - rThird ifNil: > - [ thirdIsReceiver > - ifTrue: > - [ rThird := ReceiverResultReg. "Free > ReceiverResultReg if it was not free" > - (self register: ReceiverResultReg > isInMask: self liveRegisters) ifTrue: > - [ self ssAllocateRequiredReg: > ReceiverResultReg ]. > - optStatus isReceiverResultRegLive: false ] > - ifFalse: [ rThird := self > allocateRegisterNotConflictingWith: topRegistersMask ]. > - topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: rThird) ]. > - > - rTop ifNil: [ > - rTop := self allocateRegisterNotConflictingWith: > topRegistersMask. > - topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: rTop) ]. > - > - rNext ifNil: [ rNext := self allocateRegisterNotConflictingWith: > topRegistersMask ]. > - > - ^ trinaryBlock value: rTop value: rNext value: rThird > - > - ! > > Item was removed: > - ----- Method: StackToRegisterMappingCogit>>allocateTwoRegistersInto: (in > category 'simulation stack') ----- > - allocateTwoRegistersInto: binaryBlock > - <inline: true> > - | topRegistersMask rTop rNext | > - > - topRegistersMask := 0. > - > - self ssTop type = SSRegister ifTrue: > - [ topRegistersMask := self registerMaskFor: (rTop := self > ssTop register)]. > - (self ssValue: 1) type = SSRegister ifTrue: > - [ topRegistersMask := topRegistersMask bitOr: (self > registerMaskFor: (rNext := (self ssValue: 1) register))]. > - > - rTop ifNil: [ rTop := self allocateRegisterNotConflictingWith: > topRegistersMask ]. > - > - rNext ifNil: [ rNext := self allocateRegisterNotConflictingWith: > (self registerMaskFor: rTop) ]. > - > - ^ binaryBlock value: rTop value: rNext > - > - ! > > Item was removed: > - ----- Method: StackToRegisterMappingCogit>>availableRegister (in > category 'simulation stack') ----- > - availableRegister > - | reg | > - reg := self availableRegisterOrNil. > - reg ifNil: [self error: 'no available register']. > - ^reg! > > Item was removed: > - ----- Method: StackToRegisterMappingCogit>>availableRegisterOrNil (in > category 'simulation stack') ----- > - availableRegisterOrNil > - ^backEnd availableRegisterOrNilFor: self liveRegisters! > > Item was added: > + ----- Method: StackToRegisterMappingCogit>>freeAnyRegNotConflictingWith: > (in category 'simulation stack') ----- > + freeAnyRegNotConflictingWith: regMask > + "Spill the closest register on stack not conflicting with regMask. > + Assertion Failure if regMask has already all the registers" > + <var: #desc type: #'CogSimStackEntry *'> > + | reg index | > + index := simSpillBase max: 0. > + [reg isNil and: [index < simStackPtr] ] whileTrue: > + [ | desc | > + desc := self simStackAt: index. > + desc type = SSRegister ifTrue: > + [ (regMask anyMask: (self registerMaskFor: desc > register)) ifFalse: > + [ reg := desc register ] ]. > + index := index + 1]. > + self assert: reg notNil. > + self ssAllocateRequiredReg: reg. > + ^reg! > > Item was removed: > - ----- Method: > StackToRegisterMappingCogit>>freeRegisterNotConflictingWith: (in category > 'simulation stack') ----- > - freeRegisterNotConflictingWith: regMask > - "Spill the closest register on stack not conflicting with regMask. > - Assertion Failure if regMask has already all the registers" > - <var: #desc type: #'CogSimStackEntry *'> > - | reg index | > - index := simSpillBase max: 0. > - [reg isNil and: [index < simStackPtr] ] whileTrue: > - [ | desc | > - desc := self simStackAt: index. > - desc type = SSRegister ifTrue: > - [ (regMask anyMask: (self registerMaskFor: desc > register)) ifFalse: > - [ reg := desc register ] ]. > - index := index + 1]. > - self assert: reg notNil. > - self ssAllocateRequiredReg: reg. > - ^reg! > > Item was changed: > ----- Method: > StackToRegisterMappingCogit>>genBinaryConstOpVarInlinePrimitive: (in > category 'inline primitive generators') ----- > genBinaryConstOpVarInlinePrimitive: prim > "Const op var version of binary inline primitives." > "SistaV1: 248 11111000 iiiiiiii > mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 > means inlined primitive, no hard return after execution. > See EncoderForSistaV1's class comment and > StackInterpreter>>#binaryInlinePrimitive:" > | ra val untaggedVal adjust | > + ra := self allocateRegForStackTopEntry. > - ra := self allocateOneRegister. > self ssTop popToReg: ra. > self ssPop: 1. > val := self ssTop constant. > self ssPop: 1. > untaggedVal := val - objectMemory smallIntegerTag. > prim caseOf: { > "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op > SmallInteger => SmallInteger, no overflow" > [0] -> [self AddCq: untaggedVal R: ra]. > [1] -> [self MoveCq: val R: TempReg. > self SubR: ra R: TempReg. > objectRepresentation > genAddSmallIntegerTagsTo: TempReg. > self MoveR: TempReg R: ra]. > [2] -> [objectRepresentation > genRemoveSmallIntegerTagsInScratchReg: ra. > self MoveCq: (objectMemory > integerValueOf: val) R: TempReg. > self MulR: TempReg R: ra. > objectRepresentation > genAddSmallIntegerTagsTo: ra]. > > "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, > SmallInteger op SmallInteger => SmallInteger, no overflow" > > "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op > SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags > value, just generate the instruction!!!!)" > "CmpCqR is SubRCq so everything is reversed, but because > no CmpRCq things are reversed again and we invert the sense of the jumps." > [32] -> [ self CmpCq: val R: ra. > self genBinaryInlineComparison: JumpLess > opFalse: JumpGreaterOrEqual destReg: ra ]. > [33] -> [ self CmpCq: val R: ra. > self genBinaryInlineComparison: > JumpGreater opFalse: JumpLessOrEqual destReg: ra ]. > [34] -> [ self CmpCq: val R: ra. > self genBinaryInlineComparison: > JumpLessOrEqual opFalse: JumpGreater destReg: ra ]. > [35] -> [ self CmpCq: val R: ra. > self genBinaryInlineComparison: > JumpGreaterOrEqual opFalse: JumpLess destReg: ra ]. > [36] -> [ self CmpCq: val R: ra. > self genBinaryInlineComparison: JumpZero > opFalse: JumpNonZero destReg: ra ]. > [37] -> [ self CmpCq: val R: ra. > self genBinaryInlineComparison: > JumpNonZero opFalse: JumpZero destReg: ra ]. > > "2064 through 2068, Pointer Object>>at:, Byte > Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word > Object>>at:. obj op 0-rel SmallInteger => oop" > [64] -> [objectRepresentation > genConvertSmallIntegerToIntegerInReg: ra. > adjust := (objectMemory baseHeaderSize >> > objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from > 1 relative to zero relative" > adjust ~= 0 ifTrue: [ self AddCq: adjust > R: ra. ]. > self genMoveConstant: val R: TempReg. > self MoveXwr: ra R: TempReg R: ra]. > [65] -> [objectRepresentation > genConvertSmallIntegerToIntegerInReg: ra. > adjust := objectMemory baseHeaderSize - 1. > "shift by baseHeaderSize and then move from 1 relative to zero relative" > self AddCq: adjust R: ra. > self genMoveConstant: val R: TempReg. > self MoveXbr: ra R: TempReg R: ra. > objectRepresentation > genConvertIntegerToSmallIntegerInReg: ra] > } > otherwise: [^EncounteredUnknownBytecode]. > self ssPushRegister: ra. > ^0! > > Item was changed: > ----- Method: > StackToRegisterMappingCogit>>genBinaryVarOpConstInlinePrimitive: (in > category 'inline primitive generators') ----- > genBinaryVarOpConstInlinePrimitive: prim > "Var op const version of inline binary inline primitives." > "SistaV1: 248 11111000 iiiiiiii > mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 > means inlined primitive, no hard return after execution. > See EncoderForSistaV1's class comment and > StackInterpreter>>#binaryInlinePrimitive:" > | rr val untaggedVal | > val := self ssTop constant. > self ssPop: 1. > + rr := self allocateRegForStackTopEntry. > - rr := self allocateOneRegister. > self ssTop popToReg: rr. > self ssPop: 1. > untaggedVal := val - objectMemory smallIntegerTag. > prim caseOf: { > "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op > SmallInteger => SmallInteger, no overflow" > [0] -> [self AddCq: untaggedVal R: rr]. > [1] -> [self SubCq: untaggedVal R: rr ]. > [2] -> [self flag: 'could use MulCq:R'. > objectRepresentation > genShiftAwaySmallIntegerTagsInScratchReg: rr. > self MoveCq: (objectMemory > integerValueOf: val) R: TempReg. > self MulR: TempReg R: rr. > objectRepresentation > genAddSmallIntegerTagsTo: rr]. > > "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, > SmallInteger op SmallInteger => SmallInteger, no overflow" > > "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op > SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags > value, just generate the instruction!!!!)" > "CmpCqR is SubRCq so everything is reversed." > [32] -> [ self CmpCq: val R: rr. > self genBinaryInlineComparison: > JumpGreater opFalse: JumpLessOrEqual destReg: rr ]. > [33] -> [ self CmpCq: val R: rr. > self genBinaryInlineComparison: JumpLess > opFalse: JumpGreaterOrEqual destReg: rr ]. > [34] -> [ self CmpCq: val R: rr. > self genBinaryInlineComparison: > JumpGreaterOrEqual opFalse: JumpLess destReg: rr ]. > [35] -> [ self CmpCq: val R: rr. > self genBinaryInlineComparison: > JumpLessOrEqual opFalse: JumpGreater destReg: rr ]. > [36] -> [ self CmpCq: val R: rr. > self genBinaryInlineComparison: JumpZero > opFalse: JumpNonZero destReg: rr ]. > [37] -> [ self CmpCq: val R: rr. > self genBinaryInlineComparison: > JumpNonZero opFalse: JumpZero destReg: rr ]. > > "2064 through 2068, Pointer Object>>at:, Byte > Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word > Object>>at:. obj op 0-rel SmallInteger => oop" > [64] -> [objectRepresentation genLoadSlot: (objectMemory > integerValueOf: val) - 1 sourceReg: rr destReg: rr]. > [65] -> [self MoveCq: (objectMemory integerValueOf: val) + > objectMemory baseHeaderSize - 1 R: TempReg. > self MoveXbr: TempReg R: rr R: rr. > objectRepresentation > genConvertIntegerToSmallIntegerInReg: rr] > > } > otherwise: [^EncounteredUnknownBytecode]. > self ssPushRegister: rr. > ^0! > > Item was changed: > ----- Method: > StackToRegisterMappingCogit>>genBinaryVarOpVarInlinePrimitive: (in category > 'inline primitive generators') ----- > genBinaryVarOpVarInlinePrimitive: prim > "Var op var version of binary inline primitives." > "SistaV1: 248 11111000 iiiiiiii > mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 > means inlined primitive, no hard return after execution. > See EncoderForSistaV1's class comment and > StackInterpreter>>#binaryInlinePrimitive:" > | ra rr adjust | > + self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext | ra := > rTop. rr := rNext ]. > - self allocateTwoRegistersInto: [:rTop :rNext | ra := rTop. rr := > rNext ]. > self ssTop popToReg: ra. > self ssPop: 1. > self ssTop popToReg: rr. > self ssPop: 1. > prim caseOf: { > "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op > SmallInteger => SmallInteger, no overflow" > [0] -> [objectRepresentation > genRemoveSmallIntegerTagsInScratchReg: ra. > self AddR: ra R: rr]. > [1] -> [self SubR: ra R: rr. > objectRepresentation > genAddSmallIntegerTagsTo: rr]. > [2] -> [objectRepresentation > genRemoveSmallIntegerTagsInScratchReg: rr. > objectRepresentation > genShiftAwaySmallIntegerTagsInScratchReg: ra. > self MulR: ra R: rr. > objectRepresentation > genAddSmallIntegerTagsTo: rr]. > > "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, > SmallInteger op SmallInteger => SmallInteger, no overflow" > > "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op > SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags > value, just generate the instruction!!!!)" > "CmpCqR is SubRCq so everything is reversed." > [32] -> [ self CmpR: ra R: rr. > self genBinaryInlineComparison: > JumpGreater opFalse: JumpLessOrEqual destReg: rr ]. > [33] -> [ self CmpR: ra R: rr. > self genBinaryInlineComparison: JumpLess > opFalse: JumpGreaterOrEqual destReg: rr ]. > [34] -> [ self CmpR: ra R: rr. > self genBinaryInlineComparison: > JumpGreaterOrEqual opFalse: JumpLess destReg: rr ]. > [35] -> [ self CmpR: ra R: rr. > self genBinaryInlineComparison: > JumpLessOrEqual opFalse: JumpGreater destReg: rr ]. > [36] -> [ self CmpR: ra R: rr. > self genBinaryInlineComparison: JumpZero > opFalse: JumpNonZero destReg: rr ]. > [37] -> [ self CmpR: ra R: rr. > self genBinaryInlineComparison: > JumpNonZero opFalse: JumpZero destReg: rr ]. > > "2064 through 2068, Pointer Object>>at:, Byte > Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word > Object>>at:. obj op 0-rel SmallInteger => oop" > [64] -> [objectRepresentation > genConvertSmallIntegerToIntegerInReg: ra. > adjust := (objectMemory baseHeaderSize >> > objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from > 1 relative to zero relative" > adjust ~= 0 ifTrue: [ self AddCq: adjust > R: ra. ]. > self MoveXwr: ra R: rr R: rr ]. > [65] -> [objectRepresentation > genConvertSmallIntegerToIntegerInReg: ra. > adjust := objectMemory baseHeaderSize - 1. > "shift by baseHeaderSize and then move from 1 relative to zero relative" > self AddCq: adjust R: ra. > self MoveXbr: ra R: rr R: rr. > objectRepresentation > genConvertIntegerToSmallIntegerInReg: rr] > > } > otherwise: [^EncounteredUnknownBytecode]. > self ssPushRegister: rr. > ^0! > > Item was changed: > ----- Method: StackToRegisterMappingCogit>>genPushLiteralVariable: (in > category 'bytecode generator support') ----- > genPushLiteralVariable: literalIndex > <inline: false> > | association freeReg | > + freeReg := self allocateAnyReg. > - freeReg := self ssAllocatePreferredReg: ClassReg. > association := self getLiteral: literalIndex. > "N.B. Do _not_ use ReceiverResultReg to avoid overwriting receiver > in assignment in frameless methods." > "So far descriptors are not rich enough to describe the entire > dereference so generate the register > load but don't push the result. There is an order-of-evaluation > issue if we defer the dereference." > self genMoveConstant: association R: TempReg. > objectRepresentation > genEnsureObjInRegNotForwarded: TempReg > scratchReg: freeReg. > objectRepresentation > genLoadSlot: ValueIndex > sourceReg: TempReg > destReg: freeReg. > self ssPushRegister: freeReg. > ^0! > > Item was changed: > ----- Method: > StackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders > (in category 'bytecode generators') ----- > genSpecialSelectorEqualsEqualsWithForwarders > | primDescriptor nextPC nExts branchDescriptor unforwardRcvr > argReg targetBytecodePC > unforwardArg rcvrReg jumpNotEqual jumpEqual postBranchPC label > fixup | > <var: #fixup type: #'BytecodeFixup *'> > <var: #jumpEqual type: #'AbstractInstruction *'> > <var: #jumpNotEqual type: #'AbstractInstruction *'> > <var: #primDescriptor type: #'BytecodeDescriptor *'> > <var: #branchDescriptor type: #'BytecodeDescriptor *'> > > primDescriptor := self generatorAt: byte0. > > nextPC := bytecodePC + primDescriptor numBytes. > nExts := 0. > [branchDescriptor := self generatorAt: (objectMemory fetchByte: > nextPC ofObject: methodObj) + bytecodeSetOffset. > branchDescriptor isExtension] whileTrue: > [nExts := nExts + 1. > nextPC := nextPC + branchDescriptor numBytes]. > "If branching the stack must be flushed for the merge" > (branchDescriptor isBranchTrue or: [branchDescriptor > isBranchFalse]) ifTrue: > [self ssFlushTo: simStackPtr - 2]. > > unforwardRcvr := (objectRepresentation isUnannotatableConstant: > (self ssValue: 1)) not. > unforwardArg := (objectRepresentation isUnannotatableConstant: > self ssTop) not. > > "if the rcvr or the arg is an annotable constant, we need to push > it to a register > else the forwarder check can't jump back to the comparison after > unforwarding the constant" > unforwardArg > ifTrue: > [unforwardRcvr > ifTrue: > + [self > allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. > rcvrReg := rNext]. > - [self allocateTwoRegistersInto: > [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. > self ssTop popToReg: argReg. > (self ssValue:1) popToReg: > rcvrReg] > ifFalse: > + [argReg := self > allocateRegForStackTopEntry. > - [argReg := self > allocateOneRegister. > self ssTop popToReg: argReg]] > ifFalse: > [self assert: unforwardRcvr. > + rcvrReg := self allocateRegForStackEntryAt: 1. > - rcvrReg := self allocateOneRegister. > (self ssValue:1) popToReg: rcvrReg]. > > label := self Label. > > "Here we can use Cq because the constant does not need to be > annotated" > self assert: (unforwardArg not or: [argReg notNil]). > self assert: (unforwardRcvr not or: [rcvrReg notNil]). > unforwardArg > ifFalse: [ self CmpCq: self ssTop constant R: rcvrReg ] > ifTrue: [ unforwardRcvr > ifFalse: [ self CmpCq: (self ssValue: 1) constant > R: argReg ] > ifTrue: [ self CmpR: argReg R: rcvrReg ] ]. > > self ssPop: 2. > > "If not followed by a branch, resolve to true or false." > (branchDescriptor isBranchTrue or: [branchDescriptor > isBranchFalse]) ifFalse: > [jumpEqual := self JumpZero: 0. > unforwardArg ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label > ]. > unforwardRcvr ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: > label ]. > self genMoveFalseR: rcvrReg. > jumpNotEqual := self Jump: 0. > jumpEqual jmpTarget: (self genMoveTrueR: rcvrReg). > jumpNotEqual jmpTarget: self Label. > self ssPushRegister: rcvrReg. > ^0]. > > "Further since there is a following conditional jump bytecode, > define > non-merge fixups and leave the cond bytecode to set the > mergeness." > targetBytecodePC := nextPC > + branchDescriptor > numBytes > + (self spanFor: > branchDescriptor at: nextPC exts: nExts in: methodObj). > postBranchPC := nextPC + branchDescriptor numBytes. > (self fixupAt: nextPC - initialPC) targetInstruction = 0 > ifTrue: "The next instruction is dead. we can skip it." > [deadCode := true. > self ensureFixupAt: targetBytecodePC - initialPC. > self ensureFixupAt: postBranchPC - initialPC] > ifFalse: > [self ssPushConstant: objectMemory trueObject]. > "dummy value" > > self assert: (unforwardArg or: [ unforwardRcvr ]). > branchDescriptor isBranchTrue ifTrue: > [ deadCode ifFalse: [ fixup := self ensureNonMergeFixupAt: > postBranchPC - initialPC ]. > self JumpZero: (self ensureNonMergeFixupAt: > targetBytecodePC - initialPC) asUnsignedInteger. > unforwardArg ifTrue: [ (deadCode or: [ unforwardRcvr ]) > ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label > ] > ifFalse: [ objectRepresentation > genEnsureOopInRegNotForwarded: argReg > scratchReg: TempReg > ifForwarder: label > ifNotForwarder: fixup ] ]. > unforwardRcvr ifTrue: [ deadCode > ifTrue: [objectRepresentation > genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: > label ] > ifFalse: [objectRepresentation > genEnsureOopInRegNotForwarded: rcvrReg > scratchReg: TempReg > ifForwarder: label > ifNotForwarder: fixup ] ] ]. > branchDescriptor isBranchFalse ifTrue: > [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - > initialPC. > self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - > initialPC) asUnsignedInteger. > unforwardArg ifTrue: [ unforwardRcvr > ifFalse: [objectRepresentation > genEnsureOopInRegNotForwarded: argReg > scratchReg: TempReg > ifForwarder: label > ifNotForwarder: fixup ] > ifTrue: [ objectRepresentation > genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label > ] ]. > unforwardRcvr ifTrue: > [ objectRepresentation > genEnsureOopInRegNotForwarded: rcvrReg > scratchReg: TempReg > ifForwarder: label > ifNotForwarder: fixup ]. > "Not reached"]. > ^0! > > Item was changed: > ----- Method: StackToRegisterMappingCogit>>genTrinaryInlinePrimitive: > (in category 'inline primitive generators') ----- > genTrinaryInlinePrimitive: prim > "Unary inline primitives." > "SistaV1: 248 11111000 iiiiiiii > mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 > means inlined primitive, no hard return after execution. > See EncoderForSistaV1's class comment and > StackInterpreter>>#trinaryInlinePrimitive:" > > | ra1 ra2 rr adjust | > "The store check requires rr to be ReceiverResultReg" > + self > + allocateRegForStackTopThreeEntriesInto: [:rTop :rNext > :rThird | ra2 := rTop. ra1 := rNext. rr := rThird ] > + thirdIsReceiver: prim = 0. > - self allocateThreeRegistersInto: [:rTop :rNext :rThird | ra2 := > rTop. ra1 := rNext. rr := rThird ] thirdIsReceiver: prim = 0. > self assert: (rr ~= ra1 and: [rr ~= ra2 and: [ra1 ~= ra2]]). > self ssTop popToReg: ra2. > self ssPop: 1. > self ssTop popToReg: ra1. > self ssPop: 1. > self ssTop popToReg: rr. > self ssPop: 1. > objectRepresentation genConvertSmallIntegerToIntegerInReg: ra1. > "Now: ra is the variable object, rr is long, TempReg holds the > value to store." > prim caseOf: { > "0 - 1 pointerAt:put: and byteAt:Put:" > [0] -> [ adjust := (objectMemory baseHeaderSize >> > objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from > 1 relative to zero relative" > adjust ~= 0 ifTrue: [ self AddCq: adjust > R: ra1. ]. > self MoveR: ra2 Xwr: ra1 R: rr. > objectRepresentation > genStoreCheckReceiverReg: rr valueReg: ra2 scratchReg: TempReg inFrame: > true]. > [1] -> [ objectRepresentation > genConvertSmallIntegerToIntegerInReg: ra2. > adjust := objectMemory baseHeaderSize - 1. > "shift by baseHeaderSize and then move from 1 relative to zero relative" > self AddCq: adjust R: ra1. > self MoveR: ra2 Xbr: ra1 R: rr. > objectRepresentation > genConvertIntegerToSmallIntegerInReg: ra2. ] > } > otherwise: [^EncounteredUnknownBytecode]. > self ssPushRegister: ra2. > ^0! > > Item was changed: > ----- Method: StackToRegisterMappingCogit>>genUnaryInlinePrimitive: (in > category 'inline primitive generators') ----- > genUnaryInlinePrimitive: prim > "Unary inline primitives." > "SistaV1: 248 11111000 iiiiiiii > mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 > means inlined primitive, no hard return after execution. > See EncoderForSistaV1's class comment and > StackInterpreter>>#unaryInlinePrimitive:" > | rcvrReg resultReg | > + rcvrReg := self allocateRegForStackTopEntry. > + resultReg := self allocateRegNotConflictingWith: (self > registerMaskFor: rcvrReg). > - rcvrReg := self allocateOneRegister. > - resultReg := self allocateRegisterNotConflictingWith: (self > registerMaskFor: rcvrReg). > self ssTop popToReg: rcvrReg. > self ssPop: 1. > prim > caseOf: { > "00 unchecked class" > [1] -> "01 unchecked pointer numSlots" > [objectRepresentation > genGetNumSlotsOf: rcvrReg into: > resultReg; > > genConvertIntegerToSmallIntegerInReg: resultReg]. > "02 unchecked pointer > basicSize" > [3] -> "03 unchecked byte numBytes" > [objectRepresentation > genGetNumBytesOf: rcvrReg into: > resultReg; > > genConvertIntegerToSmallIntegerInReg: resultReg]. > "04 unchecked > short16Type format numShorts" > "05 unchecked > word32Type format numWords" > "06 unchecked > doubleWord64Type format numDoubleWords" > } > otherwise: > [^EncounteredUnknownBytecode].. > self ssPushRegister: resultReg. > ^0! > > Item was changed: > ----- Method: > StackToRegisterMappingCogit>>genVanillaSpecialSelectorEqualsEquals (in > category 'bytecode generators') ----- > genVanillaSpecialSelectorEqualsEquals > | nextPC postBranchPC targetBytecodePC primDescriptor > branchDescriptor nExts > jumpEqual jumpNotEqual rcvrReg argReg argIsConstant > rcvrIsConstant | > <var: #jumpEqual type: #'AbstractInstruction *'> > <var: #jumpNotEqual type: #'AbstractInstruction *'> > <var: #primDescriptor type: #'BytecodeDescriptor *'> > <var: #branchDescriptor type: #'BytecodeDescriptor *'> > primDescriptor := self generatorAt: byte0. > > nextPC := bytecodePC + primDescriptor numBytes. > nExts := 0. > [branchDescriptor := self generatorAt: (objectMemory fetchByte: > nextPC ofObject: methodObj) + bytecodeSetOffset. > branchDescriptor isExtension] whileTrue: > [nExts := nExts + 1. > nextPC := nextPC + branchDescriptor numBytes]. > "If branching the stack must be flushed for the merge" > (branchDescriptor isBranchTrue or: [branchDescriptor > isBranchFalse]) ifTrue: > [self ssFlushTo: simStackPtr - 2]. > > "Don't use ReceiverResultReg for receiver to keep > ReceiverResultReg live. > Optimize e.g. rcvr == nil, the common case for ifNil: et al." > > argIsConstant := self ssTop type = SSConstant. > rcvrIsConstant := argIsConstant and: [ (self ssValue:1) type = > SSConstant ]. > > argIsConstant > ifFalse: > [rcvrIsConstant > ifFalse: > + [self > allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. > rcvrReg := rNext]. > - [self allocateTwoRegistersInto: > [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. > self ssTop popToReg: argReg. > (self ssValue:1) popToReg: > rcvrReg] > ifTrue: > + [argReg := self > allocateRegForStackTopEntry. > - [argReg := self > allocateOneRegister. > self ssTop popToReg: argReg]] > ifTrue: > [self assert: rcvrIsConstant not. > + rcvrReg := self allocateRegForStackEntryAt: 1. > - rcvrReg := self allocateOneRegister. > (self ssValue:1) popToReg: rcvrReg]. > > argIsConstant > ifTrue: [ self genCompConstant: self ssTop constant R: > rcvrReg ] > ifFalse: [ rcvrIsConstant > ifTrue: [ self genCompConstant: (self ssValue: 1) > constant R: argReg ] > ifFalse: [ self CmpR: argReg R: rcvrReg ] ]. > > self ssPop: 2. > > "If not followed by a branch, resolve to true or false." > (branchDescriptor isBranchTrue or: [branchDescriptor > isBranchFalse]) ifFalse: > [jumpNotEqual := self JumpNonZero: 0. > self genMoveTrueR: rcvrReg. > jumpEqual := self Jump: 0. > jumpNotEqual jmpTarget: (self genMoveFalseR: rcvrReg). > jumpEqual jmpTarget: self Label. > self ssPushRegister: rcvrReg. > ^0]. > > "Further since there is a following conditional jump bytecode, > define > non-merge fixups and leave the cond bytecode to set the > mergeness." > targetBytecodePC := nextPC > + branchDescriptor > numBytes > + (self spanFor: > branchDescriptor at: nextPC exts: nExts in: methodObj). > postBranchPC := nextPC + branchDescriptor numBytes. > (self fixupAt: nextPC - initialPC) targetInstruction = 0 > ifTrue: "The next instruction is dead. we can skip it." > [deadCode := true. > self ensureFixupAt: targetBytecodePC - initialPC. > self ensureFixupAt: postBranchPC - initialPC] > ifFalse: > [self ssPushConstant: objectMemory trueObject]. > "dummy value" > self gen: (branchDescriptor isBranchTrue ifTrue: [JumpZero] > ifFalse: [JumpNonZero]) > operand: (self ensureNonMergeFixupAt: targetBytecodePC - > initialPC) asUnsignedInteger. > deadCode ifFalse: [self Jump: (self ensureNonMergeFixupAt: > postBranchPC - initialPC)]. > ^0! > > Item was removed: > - ----- Method: StackToRegisterMappingCogit>>ssAllocatePreferredReg: (in > category 'simulation stack') ----- > - ssAllocatePreferredReg: preferredReg > - | preferredMask lastPreferred liveRegs | > - lastPreferred := -1. > - "compute live regs while noting the last occurrence of > preferredReg. > - If there are none free we must spill from simSpillBase to last > occurrence." > - preferredMask := (self registerMaskFor: preferredReg). > - liveRegs := self registerMaskFor: TempReg and: FPReg and: SPReg. > - (simSpillBase max: 0) to: simStackPtr do: > - [:i| > - liveRegs := liveRegs bitOr: (self simStackAt: i) > registerMask. > - (liveRegs bitAnd: preferredMask) ~= 0 ifTrue: > - [lastPreferred := i]]. > - "If preferredReg is not live we can allocate it." > - (self register: preferredReg isInMask: liveRegs) ifFalse: > - [^preferredReg]. > - "If any other is not live we can allocate it." > - GPRegMin to: GPRegMax do: > - [:reg| > - (self register: reg isInMask: liveRegs) ifFalse: > - [^reg]]. > - "All live, must spill" > - self ssFlushTo: lastPreferred. > - self assert: (self liveRegisters bitAnd: preferredMask) = 0. > - ^preferredReg! > >

2 7

frameless instance initialization
by Eliot Miranda 25 Apr '15

25 Apr '15

Hi All, here's a challenge. Currently the JIT is naive about a sequence of inst var assignments. It treats assignment separately, each getting its own copy of the store check. For example when initializing an Interval via: setFrom: startInteger to: stopInteger by: stepInteger start := startInteger. stop := stopInteger. step := stepInteger it generates the following assembly on ARM: A0D0 objhdr: 8000000A000035 nArgs: 3 type: 2 blksiz: 140 method: C03C10 mthhdr: 6180005 selctr: 6B71A0=#setFrom:to:by: blkentry: 0 stackCheckOffset: 0 cmRefersToYoung: no 0000a0ec: mov r7, #0 0000a0f0: push {lr} 0000a0f4: bl 0x000009f8 = 16r9F8 = ceMethodAbortNArgs 0000a0f8: ands r0, r0, #1 0000a0fc: b 0x0000a114 = 16rA114 = setFrom:to:by:@44 entry: 0000a100: ands r0, r7, #3 0000a104: bne 0x0000a0f8 = 16rA0F8 = setFrom:to:by:@28 0000a108: ldr r0, [r7] 0000a10c: mvn ip, #0 0000a110: ands r0, r0, ip, lsr #10 0000a114: cmp r0, r8 0000a118: bne 0x0000a0f0 = 16rA0F0 = setFrom:to:by:@20 noCheckEntry: 0000a11c: ldr r5, [sp, #8] startInteger 0000a120: str r5, [r7, #8] start 0000a124: mov r0, r5 0000a128: ands r0, r0, #3 startInteger immediate? 0000a12c: bne 0x0000a168 = 16rA168 = setFrom:to:by:@98 0000a130: mov r0, #0, 8 0000a134: orr r0, r0, #5308416 ; 0x510000 0000a138: orr r0, r0, #50944 ; 0xc700 0000a13c: orr r0, r0, #136 ; 0x88 = 16r51C788 = nil 0000a140: cmp r7, r0 self in oldSpace? (self >= nil) 0000a144: bcc 0x0000a168 = 16rA168 = setFrom:to:by:@98 0000a148: cmp r5, r0 startInteger young? (startInteger < nil) 0000a14c: bcs 0x0000a168 = 16rA168 = setFrom:to:by:@98 0000a150: ldrb r0, [r7, #3] self in remembered table? 0000a154: ands r0, r0, #32 0000a158: bne 0x0000a168 = 16rA168 = setFrom:to:by:@98 0000a15c: push {lr} add self to remembered table 0000a160: bl 0x00000f88 = 16rF88 = ceStoreCheckTrampoline IsRelativeCall: 0000a164: pop {lr} 0000a168: ldr r5, [sp, #4] stopInteger 0000a16c: str r5, [r7, #12] 0000a170: mov r0, r5 0000a174: ands r0, r0, #3 0000a178: bne 0x0000a1b4 = 16rA1B4 = setFrom:to:by:@E4 0000a17c: mov r0, #0, 8 0000a180: orr r0, r0, #5308416 ; 0x510000 0000a184: orr r0, r0, #50944 ; 0xc700 0000a188: orr r0, r0, #136 ; 0x88 = 16r51C788 = nil 0000a18c: cmp r7, r0 0000a190: bcc 0x0000a1b4 = 16rA1B4 = setFrom:to:by:@E4 0000a194: cmp r5, r0 0000a198: bcs 0x0000a1b4 = 16rA1B4 = setFrom:to:by:@E4 0000a19c: ldrb r0, [r7, #3] 0000a1a0: ands r0, r0, #32 0000a1a4: bne 0x0000a1b4 = 16rA1B4 = setFrom:to:by:@E4 0000a1a8: push {lr} 0000a1ac: bl 0x00000f88 = 16rF88 = ceStoreCheckTrampoline IsRelativeCall: 0000a1b0: pop {lr} 0000a1b4: ldr r5, [sp] stepInteger 0000a1b8: str r5, [r7, #16] 0000a1bc: mov r0, r5 0000a1c0: ands r0, r0, #3 0000a1c4: bne 0x0000a200 = 16rA200 = setFrom:to:by:@130 0000a1c8: mov r0, #0, 8 0000a1cc: orr r0, r0, #5308416 ; 0x510000 0000a1d0: orr r0, r0, #50944 ; 0xc700 0000a1d4: orr r0, r0, #136 ; 0x88 = 16r51C788 = nil 0000a1d8: cmp r7, r0 0000a1dc: bcc 0x0000a200 = 16rA200 = setFrom:to:by:@130 0000a1e0: cmp r5, r0 0000a1e4: bcs 0x0000a200 = 16rA200 = setFrom:to:by:@130 0000a1e8: ldrb r0, [r7, #3] 0000a1ec: ands r0, r0, #32 0000a1f0: bne 0x0000a200 = 16rA200 = setFrom:to:by:@130 0000a1f4: push {lr} 0000a1f8: bl 0x00000f88 = 16rF88 = ceStoreCheckTrampoline IsRelativeCall: 0000a1fc: pop {lr} 0000a200: add sp, sp, #16 ADD 16 to SP 0000a204: mov pc, lr 0000a208: nop ; (mov r0, r0) startpc: 12 16rA164 IsRelativeCall (16rA20F) 16rA1B0 IsRelativeCall (16rA20E) 16rA1FC IsRelativeCall (16rA20D) If the Cogit were smart enough to identify methods that contained only instance initialization code (push arg or push constant, storePop inst var, and return self) we could generate much more compact code, e.g. noCheckEntry: ldr r5, [sp, #8] startInteger str r5, [r7, #8] ldr r5, [sp, #4] stopInteger str r5, [r7, #12] ldr r5, [sp] stepInteger str r5, [r7, #16] mov r0, #0, 8 orr r0, r0, #5308416 ; 0x510000 orr r0, r0, #50944 ; 0xc700 orr r0, r0, #136 ; 0x88 = 16r51C788 = nil cmp r7, r0 self young? if so, jump to return bcc L4 ldr r5, [sp, #8] startInteger immediate? tests r5, r5, #3 bne L1 cmp r5, r0 startInteger old? bcs L1 L2: ldrb r0, [r7, #3] self in remembered table? ands r0, r0, #32 bne L1 push {lr} bl ceStoreCheckTrampoline IsRelativeCall: pop {lr} add sp, sp, #16 ADD 16 to SP mov pc, lr L1: ldr r5, [sp, #4] stopInteger tests r5, r5, #3 bne L3 cmp r5, r0 bcs L3 ldrb r0, [r7, #3] ands r0, r0, #32 beq L2 L3: ldr r5, [sp] stepInteger tests r5, r5, #3 bne L4 cmp r5, r0 bcs L4 ldrb r0, [r7, #3] ands r0, r0, #32 beq L2 L4: add sp, sp, #16 ADD 16 to SP mov pc, lr That's 5 times shorter, including method header, and does far less work in common cases (self is compared with nil, which is also the old/new boundary only once, not once for every inst var) but in the case of an Interval using SmallIntegers may be slower because each variable is read from the stack twice. Interesting choices. But I think the code density would win. Of course, this may make no difference to overall speed but it would be nice to now :-). If you're up for this, let me know. -- best, Eliot

3 3

VM Maker: VMMaker.oscog-cb.1257.mcz
by commits＠source.squeak.org 25 Apr '15

25 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1257.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1257 Author: cb Time: 25 April 2015, 4:23:00.043 pm UUID: 2ad6cc71-391b-4b83-b2b6-ccb90ceb6d00 Ancestors: VMMaker.oscog-cb.1256 Extracted the count logic in SistaCogit to be in one method called by the 3 methods generating branches to avoid duplication. I believe there's a bug in JumpIf:, if the couterReg is callerSaved then I think it is not saved correctly. That was probably not an issue before I introduced the better register allocation because Eliot most probably carefully picked a register for counterReg which was callee saved in x86. Added a few comments and indentation fix in StackToRegisterMappingCogit. =============== Diff against VMMaker.oscog-cb.1256 =============== Item was added: + ----- Method: SistaStackToRegisterMappingCogit>>genExecutionCountLogicInto:counterRegNotConflictingWith: (in category 'bytecode generator support') ----- + genExecutionCountLogicInto: trinaryBlock counterRegNotConflictingWith: regMask + <var: #countTripped type: #'AbstractInstruction *'> + <inline: true> + | counterReg counterAddress countTripped | + counterReg := self allocateRegNotConflictingWith: regMask. + counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). + self flag: 'will need to use MoveAw32:R: if 64 bits'. + self assert: objectMemory wordSize = CounterBytes. + self MoveAw: counterAddress R: counterReg. + self SubCq: 16r10000 R: counterReg. "Count executed" + "If counter trips simply abort the comparison continuing to the following + branch *without* writing back. A double decrement will not trip the second time." + countTripped := self JumpCarry: 0. + self MoveR: counterReg Aw: counterAddress. "write back" + trinaryBlock value: counterReg value: counterAddress value: countTripped! Item was added: + ----- Method: SistaStackToRegisterMappingCogit>>genFallsThroughCountLogicCounterReg:counterAddress: (in category 'bytecode generator support') ----- + genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress + <inline: true> + "Gen this when the branch has not been taken and forwarders have been followed." + self SubCq: 1 R: counterReg. "Count untaken" + self MoveR: counterReg Aw: counterAddress. "write back"! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genJumpIf:to: (in category 'bytecode generator support') ----- genJumpIf: boolean to: targetBytecodePC "The heart of performance counting in Sista. Conditional branches are 6 times less frequent than sends and can provide basic block frequencies (send counters can't). Each conditional has a 32-bit counter split into an upper 16 bits counting executions and a lower half counting untaken executions of the branch. Executing the branch decrements the upper half, tripping if the count goes negative. Not taking the branch decrements the lower half. N.B. We *do not* eliminate dead branches (true ifTrue:/true ifFalse:) so that scanning for send and branch data is simplified and that branch data is correct." <inline: false> | desc ok counterAddress countTripped retry counterReg | <var: #ok type: #'AbstractInstruction *'> <var: #desc type: #'CogSimStackEntry *'> <var: #retry type: #'AbstractInstruction *'> <var: #countTripped type: #'AbstractInstruction *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super genJumpIf: boolean to: targetBytecodePC ]. self ssFlushTo: simStackPtr - 1. desc := self ssTop. self ssPop: 1. desc popToReg: TempReg. + + self + genExecutionCountLogicInto: [ :cReg :cAddress :countTripBranch | + counterReg := cReg. + counterAddress := cAddress. + countTripped := countTripBranch ] + counterRegNotConflictingWith: 0. - - counterReg := self allocateAnyReg. - counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). counterIndex := counterIndex + 1. + + retry := self Label. - self flag: 'will need to use MoveAw32:R: if 64 bits'. - self assert: objectMemory wordSize = CounterBytes. - retry := self MoveAw: counterAddress R: counterReg. - self SubCq: 16r10000 R: counterReg. "Count executed" - "Don't write back if we trip; avoids wrapping count back to initial value, and if we trip we don't execute." - countTripped := self JumpCarry: 0. - self MoveR: counterReg Aw: counterAddress. "write back" "Cunning trick by LPD. If true and false are contiguous subtract the smaller. Correct result is either 0 or the distance between them. If result is not 0 or their distance send mustBeBoolean." self assert: (objectMemory objectAfter: objectMemory falseObject) = objectMemory trueObject. self annotate: (self SubCw: boolean R: TempReg) objRef: boolean. self JumpZero: (self ensureFixupAt: targetBytecodePC - initialPC). + self genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress. - self SubCq: 1 R: counterReg. "Count untaken" - self MoveR: counterReg Aw: counterAddress. "write back" self CmpCq: (boolean == objectMemory falseObject ifTrue: [objectMemory trueObject - objectMemory falseObject] ifFalse: [objectMemory falseObject - objectMemory trueObject]) R: TempReg. ok := self JumpZero: 0. self MoveCq: 0 R: counterReg. "if counterReg is 0 this is a mustBeBoolean, not a counter trip." countTripped jmpTarget: (self CallRT: (boolean == objectMemory falseObject ifTrue: [ceSendMustBeBooleanAddFalseTrampoline] ifFalse: [ceSendMustBeBooleanAddTrueTrampoline])). "If we're in an image which hasn't got the Sista code loaded then the ceCounterTripped: trampoline will return directly to machine code, returning the boolean. So the code should jump back to the retry point. The trampoline makes sure that TempReg has been reloaded." self annotateBytecode: self Label. self Jump: retry. ok jmpTarget: self Label. ^0! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts inlineCAB annotateInst counterAddress countTripped counterReg | <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super genSpecialSelectorComparison ]. self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]. "short-cut the jump if operands are SmallInteger constants." (argIsInt and: [rcvrIsInt]) ifTrue: [self cCode: '' inSmalltalk: "In Simulator ints are unsigned..." [rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt]. primDescriptor opcode caseOf: { [JumpLess] -> [result := rcvrInt < argInt]. [JumpLessOrEqual] -> [result := rcvrInt <= argInt]. [JumpGreater] -> [result := rcvrInt > argInt]. [JumpGreaterOrEqual] -> [result := rcvrInt >= argInt]. [JumpZero] -> [result := rcvrInt = argInt]. [JumpNonZero] -> [result := rcvrInt ~= argInt] }. "Must enter any annotatedConstants into the map" self annotateBytecodeIfAnnotated: (self ssValue: 1). self annotateBytecodeIfAnnotated: self ssTop. "Must annotate the bytecode for correct pc mapping." self ssPop: 2. ^self ssPushAnnotatedConstant: (result ifTrue: [objectMemory trueObject] ifFalse: [objectMemory falseObject])]. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. argIsInt ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. annotateInst := self ssTop annotateUse. self ssPop: 2. self MoveR: ReceiverResultReg R: TempReg] ifFalse: [self marshallSendArguments: 1. self MoveR: Arg0Reg R: TempReg. rcvrIsInt ifFalse: [objectRepresentation isSmallIntegerTagNonZero ifTrue: [self AndR: ReceiverResultReg R: TempReg] ifFalse: [self OrR: ReceiverResultReg R: TempReg]]]. jumpNotSmallInts := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. + self + genExecutionCountLogicInto: [ :cReg :cAddress :countTripBranch | + counterReg := cReg. + counterAddress := cAddress. + countTripped := countTripBranch ] + counterRegNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg). - counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg). "Use this as the count reg, can't conflict with the registers for the arg and the receiver" - counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). - self flag: 'will need to use MoveAw32:R: if 64 bits'. - self assert: objectMemory wordSize = CounterBytes. - self MoveAw: counterAddress R: counterReg. - self SubCq: 16r10000 R: counterReg. "Count executed" - "If counter trips simply abort the inlined comparison and send continuing to the following - branch *without* writing back. A double decrement will not trip the second time." - countTripped := self JumpCarry: 0. - self MoveR: counterReg Aw: counterAddress. "write back" argIsInt ifTrue: [annotateInst ifTrue: [self annotateBytecode: (self CmpCq: argInt R: ReceiverResultReg)] ifFalse: [self CmpCq: argInt R: ReceiverResultReg]] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self gen: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. + + self genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress. + - self SubCq: 1 R: counterReg. "Count untaken" - self MoveR: counterReg Aw: counterAddress. "write back" self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). countTripped jmpTarget: (jumpNotSmallInts jmpTarget: self Label). + argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg]. ^self genMarshalledSend: (coInterpreter specialSelector: byte0 - self firstSpecialSelectorBytecodeOffset) numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders (in category 'bytecode generators') ----- genSpecialSelectorEqualsEqualsWithForwarders "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." | nextPC postBranchPC targetBytecodePC branchDescriptor label counterReg fixup counterAddress countTripped unforwardArg unforwardRcvr argReg rcvrReg regMask | <var: #fixup type: #'BytecodeFixup *'> <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> ((coInterpreter isOptimizedMethod: methodObj) or: [needsFrame not]) ifTrue: [ ^ super genSpecialSelectorEqualsEquals ]. regMask := 0. self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. "If an operand is an annotable constant, it may be forwarded, so we need to store it into a register so the forwarder check can jump back to the comparison after unforwarding the constant. However, if one of the operand is an unnanotable constant, does not allocate a register for it (machine code will use operations on constants)." self allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg rcvrNeedsReg: unforwardRcvr into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. argReg ifNotNil: [ regMask := self registerMaskFor: argReg ]. rcvrReg ifNotNil: [ regMask := regMask bitOr: (self registerMaskFor: rcvrReg) ]. "Only interested in inlining if followed by a conditional branch." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genEqualsEqualsNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg]. - - counterReg := self allocateRegNotConflictingWith: regMask. "Use this as the count reg, can't conflict with the registers for the arg and the receiver of #==." - counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). - self flag: 'will need to use MoveAw32:R: if 64 bits'. - self assert: objectMemory wordSize = CounterBytes. - self MoveAw: counterAddress R: counterReg. - self SubCq: 16r10000 R: counterReg. "Count executed" - "If counter trips simply abort the inlined comparison and send continuing to the following - branch *without* writing back. A double decrement will not trip the second time." - countTripped := self JumpCarry: 0. - self MoveR: counterReg Aw: counterAddress. "write back" + self + genExecutionCountLogicInto: [ :cReg :cAddress :countTripBranch | + counterReg := cReg. + counterAddress := cAddress. + countTripped := countTripBranch ] + counterRegNotConflictingWith: regMask. + self assert: (unforwardArg or: [ unforwardRcvr ]). "If branching the stack must be flushed for the merge" self ssFlushTo: simStackPtr - 2. label := self Label. self genEqualsEqualsComparisonArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "pop by 2 temporarily for the fixups" branchDescriptor isBranchTrue ifTrue: [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. ] ifFalse: [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. ]. unforwardArg ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ]. self ssPop: -2. + self genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress. - "the jump has not been taken and forwarders have been followed." - self SubCq: 1 R: counterReg. "Count untaken" - self MoveR: counterReg Aw: counterAddress. "write back" self Jump: fixup. - countTripped jmpTarget: self Label. "inlined version of #== ignoring the branchDescriptor if the counter trips to have normal state for the optimizer" self genEqualsEqualsNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. ^ 0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders (in category 'bytecode generators') ----- genSpecialSelectorEqualsEqualsWithForwarders | nextPC branchDescriptor unforwardRcvr argReg targetBytecodePC unforwardArg rcvrReg postBranchPC label fixup | <var: #fixup type: #'BytecodeFixup *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "If an operand is an annotable constant, it may be forwarded, so we need to store it into a register so the forwarder check can jump back to the comparison after unforwarding the constant. However, if one of the operand is an unnanotable constant, does not allocate a register for it (machine code will use operations on constants) and does not generate forwarder checks." unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. self allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg rcvrNeedsReg: unforwardRcvr into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genEqualsEqualsNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg]. "If branching the stack must be flushed for the merge" self ssFlushTo: simStackPtr - 2. label := self Label. self genEqualsEqualsComparisonArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" self assert: (unforwardArg or: [ unforwardRcvr ]). branchDescriptor isBranchTrue ifTrue: [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger ] ifFalse: "branchDescriptor is branchFalse" [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger ]. + "The forwarders checks need to jump back to the comparison (label) if a forwarder is found, else jump forward either to the next forwarder check or to the postBranch or branch target (fixup)." unforwardArg ifTrue: [ unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] ifFalse: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ] ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg ifForwarder: label ifNotForwarder: fixup ]. + + "Not reached, execution flow have jumped to fixup" + ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genVanillaSpecialSelectorEqualsEquals (in category 'bytecode generators') ----- genVanillaSpecialSelectorEqualsEquals | nextPC postBranchPC targetBytecodePC branchDescriptor rcvrReg argReg argIsConstant rcvrIsConstant | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. argIsConstant := self ssTop type = SSConstant. "they can't be both constants because we do not have instructions manipulating two constants, if this is the case, which can happen due to annotable constants that can be moved in memory with become and therefore can't resolve #== at compilation time, still write the rcvr into a register as if it was not a constant. It's uncommon anyway." rcvrIsConstant := argIsConstant not and: [(self ssValue: 1) type = SSConstant]. self allocateEqualsEqualsRegistersArgNeedsReg: argIsConstant not rcvrNeedsReg: rcvrIsConstant not into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [ ^ self genEqualsEqualsNoBranchArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg]. "If branching the stack must be flushed for the merge" self ssFlushTo: simStackPtr - 2. self genEqualsEqualsComparisonArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" + self gen: (branchDescriptor isBranchTrue ifTrue: [JumpZero] ifFalse: [JumpNonZero]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. + + "If the branch is dead, then we can just fall through postBranchPC (only a nop in-between), else + we need to jump over the code of the branch" + deadCode ifFalse: [self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC)]. - deadCode ifFalse: [self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC)]. ^0!

1 0

VM Maker: VMMaker.oscog-cb.1256.mcz
by commits＠source.squeak.org 25 Apr '15

25 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1256.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1256 Author: cb Time: 25 April 2015, 3:39:56.845 pm UUID: 3f901fb1-b9ab-4c74-8a9a-b9483fbd9830 Ancestors: VMMaker.oscog-cb.1255 After spending yet another hour on the SistaCogit to figure out what is not working, I realized that I could simplify a lot the #== code generation code in StackToRegisterMappingCogit. The code is now simpler to read. The only difference in the generated machine code is that 2 branches now jump to the instruction after a Nop instead of jumping directly to the Nop, but though I enjoy stepping over Nops while simulating machine code, it does not change anything. =============== Diff against VMMaker.oscog-cb.1255 =============== Item was removed: - ----- Method: StackToRegisterMappingCogit>>genEqualsEqualsForwarderChecksArg:rcvr:argReg:rcvrReg:label:fixup:canBeDead: (in category 'bytecode generator support') ----- - genEqualsEqualsForwarderChecksArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg label: label fixup: fixup canBeDead: canBeDead - "This code generates the forwarders checks if #== is followed by a branch. The forwarders checks need to jump back to the comparison (label) if - a forwarder is found, else jump forward to the correct place, the postBranch or branch target (fixup), if this is the last forwarder check, or jump to - the next forwarder checkif there are 2, or just fall through if it needs to jump to the postBranch and that the branch is dead code" - <inline: true> - unforwardArg ifTrue: [ (canBeDead or: [ unforwardRcvr ]) - ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] - ifFalse: [ objectRepresentation - genEnsureOopInRegNotForwarded: argReg - scratchReg: TempReg - ifForwarder: label - ifNotForwarder: fixup ] ]. - unforwardRcvr ifTrue: [ canBeDead - ifTrue: [objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ] - ifFalse: [objectRepresentation - genEnsureOopInRegNotForwarded: rcvrReg - scratchReg: TempReg - ifForwarder: label - ifNotForwarder: fixup ] ]! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders (in category 'bytecode generators') ----- genSpecialSelectorEqualsEqualsWithForwarders | nextPC branchDescriptor unforwardRcvr argReg targetBytecodePC unforwardArg rcvrReg postBranchPC label fixup | <var: #fixup type: #'BytecodeFixup *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. "If an operand is an annotable constant, it may be forwarded, so we need to store it into a register so the forwarder check can jump back to the comparison after unforwarding the constant. However, if one of the operand is an unnanotable constant, does not allocate a register for it (machine code will use operations on constants) and does not generate forwarder checks." unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. self allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg rcvrNeedsReg: unforwardRcvr into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: [^ self genEqualsEqualsNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg]. "If branching the stack must be flushed for the merge" self ssFlushTo: simStackPtr - 2. label := self Label. self genEqualsEqualsComparisonArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" self assert: (unforwardArg or: [ unforwardRcvr ]). + branchDescriptor isBranchTrue + ifTrue: + [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC. + self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger ] + ifFalse: "branchDescriptor is branchFalse" + [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. + self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger ]. + "The forwarders checks need to jump back to the comparison (label) if a forwarder is found, else + jump forward either to the next forwarder check or to the postBranch or branch target (fixup)." + unforwardArg ifTrue: + [ unforwardRcvr + ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] + ifFalse: [ objectRepresentation + genEnsureOopInRegNotForwarded: argReg + scratchReg: TempReg + ifForwarder: label + ifNotForwarder: fixup ] ]. + unforwardRcvr ifTrue: + [ objectRepresentation + genEnsureOopInRegNotForwarded: rcvrReg + scratchReg: TempReg + ifForwarder: label + ifNotForwarder: fixup ]. - branchDescriptor isBranchTrue ifTrue: - [ deadCode ifFalse: [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC ]. - self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. - self - genEqualsEqualsForwarderChecksArg: unforwardArg - rcvr: unforwardRcvr - argReg: argReg - rcvrReg: rcvrReg - label: label - fixup: fixup - canBeDead: deadCode ]. - branchDescriptor isBranchFalse ifTrue: - [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. - self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. - self - genEqualsEqualsForwarderChecksArg: unforwardArg - rcvr: unforwardRcvr - argReg: argReg - rcvrReg: rcvrReg - label: label - fixup: fixup - canBeDead: false]. ^0!

1 0

VM Maker: VMMaker.oscog-cb.1255.mcz
by commits＠source.squeak.org 25 Apr '15

25 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1255.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1255 Author: cb Time: 25 April 2015, 3:17:57.287 pm UUID: 939d4856-6309-444c-9ed9-32caf51a7001 Ancestors: VMMaker.oscog-cb.1254 Improved readability by using even more #genMoveConstant:R: instead of: (objectRepresentation shouldAnnotateObjectReference: constant) ifTrue: [ (self annotate: (self MoveCw: constant R: reg) objRef: constant) ] ifFalse: [ self MoveCq: constant R: reg ] =============== Diff against VMMaker.oscog-cb.1254 =============== Item was changed: ----- Method: CogObjectRepresentationFor32BitSpur>>genGetActiveContextLarge:inBlock: (in category 'initialization') ----- genGetActiveContextLarge: isLarge inBlock: isInBlock "Create a trampoline to answer the active context that will answer it if a frame is already married, and create it otherwise. Assume numArgs is in SendNumArgsReg and ClassReg is free." | header slotSize jumpSingle loopHead jumpNeedScavenge continuation exit | <var: #jumpNeedScavenge type: #'AbstractInstruction *'> <var: #continuation type: #'AbstractInstruction *'> <var: #jumpSingle type: #'AbstractInstruction *'> <var: #loopHead type: #'AbstractInstruction *'> <var: #exit type: #'AbstractInstruction *'> cogit "load the flag; stash it in both TempReg & ClassReg; do the compare (a prime candidated for use of AndCq:R:R:)" MoveMw: FoxMethod r: FPReg R: ClassReg; AndCq: MFMethodFlagHasContextFlag R: ClassReg R: TempReg. jumpSingle := cogit JumpZero: 0. "jump if flag bit not set" cogit "since the flag bit was set, get the context in the receiver reg and return" MoveMw: FoxThisContext r: FPReg R: ReceiverResultReg; RetN: 0. jumpSingle jmpTarget: cogit Label. "OK, it doesn't exist; instantiate and initialize it" "set the hasContext flag; See CoInterpreter class>>initializeFrameIndices" cogit OrCq: MFMethodFlagHasContextFlag R: ClassReg; MoveR: ClassReg Mw: FoxMethod r: FPReg. "now get the home CogMethod into ClassReg and save for post-instantiation." isInBlock ifTrue: [cogit SubCq: 3 R: ClassReg; "-3 is -(hasContext+isBlock) flags" MoveM16: 0 r: ClassReg R: TempReg; SubR: TempReg R: ClassReg] ifFalse: [cogit SubCq: 1 R: ClassReg]. "-1 is hasContext flag" "instantiate the context..." slotSize := isLarge ifTrue: [LargeContextSlots] ifFalse: [SmallContextSlots]. header := objectMemory headerForSlots: slotSize format: objectMemory indexablePointersFormat classIndex: ClassMethodContextCompactIndex. self flag: #endianness. cogit MoveAw: objectMemory freeStartAddress R: ReceiverResultReg; MoveCq: (self low32BitsOf: header) R: TempReg; MoveR: TempReg Mw: 0 r: ReceiverResultReg; MoveCq: header >> 32 R: TempReg; MoveR: TempReg Mw: 4 r: ReceiverResultReg; MoveR: ReceiverResultReg R: TempReg; AddCq: (objectMemory smallObjectBytesForSlots: slotSize) R: TempReg; MoveR: TempReg Aw: objectMemory freeStartAddress; CmpCq: objectMemory getScavengeThreshold R: TempReg. jumpNeedScavenge := cogit JumpAboveOrEqual: 0. "Now initialize the fields of the context. See CoInterpreter>>marryFrame:SP:copyTemps:" "sender gets frame pointer as a SmallInteger" continuation := cogit MoveR: FPReg R: TempReg. self genSetSmallIntegerTagsIn: TempReg. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (SenderIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "pc gets frame caller as a SmallInteger" cogit MoveMw: FoxSavedFP r: FPReg R: TempReg. self genSetSmallIntegerTagsIn: TempReg. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (InstructionPointerIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Set the method field, freeing up ClassReg again, and frame's context field," cogit MoveMw: (cogit offset: CogMethod of: #methodObject) r: ClassReg R: TempReg; MoveR: TempReg Mw: objectMemory baseHeaderSize + (MethodIndex * objectMemory wordSize) r: ReceiverResultReg; MoveR: ReceiverResultReg Mw: FoxThisContext r: FPReg. "Now compute stack pointer; this is stackPointer (- 1 for return pc if a CISC) - framePointer - 4 (1 each for saved pc, method, context, receiver) + 1 (1-relative) + numArgs" "TPR note - the code here is actually doing context stackPointer := ((((fp - sp) / 4) - [3|4]) + num args) asSmallInteger" cogit MoveR: FPReg R: TempReg; SubR: SPReg R: TempReg; LogicalShiftRightCq: self log2BytesPerWord R: TempReg; SubCq: (cogit backEnd hasLinkRegister ifTrue: [3] ifFalse: [4]) R: TempReg; AddR: SendNumArgsReg R: TempReg. self genConvertIntegerToSmallIntegerInReg: TempReg. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (StackPointerIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Set closureOrNil to either the stacked receiver or nil" isInBlock ifTrue: [cogit MoveR: SendNumArgsReg R: TempReg; AddCq: 2 R: TempReg; "+2 for saved fp and saved pc" MoveXwr: TempReg R: FPReg R: TempReg] ifFalse: + [cogit genMoveConstant: objectMemory nilObject R: TempReg]. - [cogit MoveCw: objectMemory nilObject R: TempReg]. cogit MoveR: TempReg Mw: objectMemory baseHeaderSize + (ClosureIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Set the receiver" cogit MoveMw: FoxMFReceiver r: FPReg R: TempReg; MoveR: TempReg Mw: objectMemory baseHeaderSize + (ReceiverIndex * objectMemory bytesPerOop) r: ReceiverResultReg. "Now copy the arguments. This is tricky because of the shortage of registers,. ClassReg ranges from 1 to numArgs (SendNumArgsReg), and from ReceiverIndex + 1 to ReceiverIndex + numArgs. 1 to: numArgs do: [:i| temp := longAt(FPReg + ((SendNumArgs - i + 2) * BytesPerWord)). +2 for saved pc and savedfp longAtput(FPReg + FoxMFReceiver + (i * BytesPerWord), temp)]" "TPR note: this is a prime candidate for passing off to the backend to do at least faintly optimal code" cogit MoveCq: 1 R: ClassReg. loopHead := cogit CmpR: SendNumArgsReg R: ClassReg. exit := cogit JumpGreater: 0. cogit MoveR: SendNumArgsReg R: TempReg; SubR: ClassReg R: TempReg; AddCq: 2 R: TempReg; "+2 for saved fp and saved pc" MoveXwr: TempReg R: FPReg R: TempReg; AddCq: ReceiverIndex + (objectMemory baseHeaderSize / objectMemory wordSize) R: ClassReg; "Now convert ClassReg from frame index to context index" MoveR: TempReg Xwr: ClassReg R: ReceiverResultReg; SubCq: ReceiverIndex + (objectMemory baseHeaderSize / objectMemory wordSize) - 1 R: ClassReg; "convert back adding 1 ;-)" Jump: loopHead. exit jmpTarget: cogit Label. "Finally nil or copy the non-argument temps. ClassReg := FPReg + FoxMFReceiver. SendNumArgsReg := SendNumArgsReg+ReceiverIndex. [ClassReg := ClassReg - 4. backEnd hasLinkRegister ifTrue: [ClassReg > SPReg] ifFalse: [ClassReg >= SPReg]] whileTrue: [receiver[SendNumArgsReg] := *ClassReg. SendNumArgsReg := SendNumArgsReg + 1]]" coInterpreter marryFrameCopiesTemps ifFalse: [cogit MoveCq: objectMemory nilObject R: TempReg]. cogit MoveR: FPReg R: ClassReg; AddCq: FoxMFReceiver R: ClassReg; AddCq: ReceiverIndex + 1 + (objectMemory baseHeaderSize / objectMemory wordSize) R: SendNumArgsReg. loopHead := cogit SubCq: objectMemory wordSize R: ClassReg. cogit CmpR: SPReg R: ClassReg. "If on a CISC there's a retpc for the trampoline call on top of stack; if on a RISC there isn't." exit := cogit backEnd hasLinkRegister ifTrue: [cogit JumpBelow: 0] ifFalse: [cogit JumpBelowOrEqual: 0]. coInterpreter marryFrameCopiesTemps ifTrue: [cogit MoveMw: 0 r: ClassReg R: TempReg]. cogit MoveR: TempReg Xwr: SendNumArgsReg R: ReceiverResultReg; AddCq: 1 R: SendNumArgsReg; Jump: loopHead. exit jmpTarget: cogit Label. cogit RetN: 0. jumpNeedScavenge jmpTarget: cogit Label. cogit backEnd saveAndRestoreLinkRegAround: [cogit CallRT: ceScheduleScavengeTrampoline]. cogit Jump: continuation. ^0! Item was changed: ----- Method: CogObjectRepresentationFor32BitSpur>>genNewArrayOfSize:initialized: (in category 'bytecode generator support') ----- genNewArrayOfSize: size initialized: initialized "Generate a call to code that allocates a new Array of size. The Array should be initialized with nils iff initialized is true. The size arg is passed in SendNumArgsReg, the result must come back in ReceiverResultReg." | header skip | <var: #skip type: #'AbstractInstruction *'> self assert: size < objectMemory numSlotsMask. header := objectMemory headerForSlots: size format: objectMemory arrayFormat classIndex: ClassArrayCompactIndex. self flag: #endianness. cogit MoveAw: objectMemory freeStartAddress R: ReceiverResultReg; MoveCq: (self low32BitsOf: header) R: TempReg; MoveR: TempReg Mw: 0 r: ReceiverResultReg; MoveCq: header >> 32 R: TempReg; MoveR: TempReg Mw: 4 r: ReceiverResultReg. (initialized and: [size > 0]) ifTrue: + [cogit genMoveConstant: objectMemory nilObject R: TempReg. - [cogit MoveCw: objectMemory nilObject R: TempReg. 1 to: size do: [:i| cogit MoveR: TempReg Mw: i * 4 + 4 r: ReceiverResultReg]]. cogit MoveR: ReceiverResultReg R: TempReg; AddCq: (objectMemory smallObjectBytesForSlots: size) R: TempReg; MoveR: TempReg Aw: objectMemory freeStartAddress; CmpCq: objectMemory getScavengeThreshold R: TempReg. skip := cogit JumpBelow: 0. cogit CallRT: ceScheduleScavengeTrampoline. skip jmpTarget: cogit Label. ^0! Item was changed: ----- Method: SimpleStackBasedCogit>>compileFrameBuild (in category 'compile abstract instructions') ----- compileFrameBuild "Build a frame for a CogMethod activation. See CoInterpreter class>>initializeFrameIndices. receiver (in ReceiverResultReg) arg0 ... argN caller's saved ip/this stackPage (for a base frame) fp-> saved fp method context (uninitialized?) receiver first temp ... sp-> Nth temp If there is a primitive and an error code the Nth temp is the error code. Ensure SendNumArgsReg is set early on (incidentally to nilObj) because it is the flag determining whether context switch is allowed on stack-overflow." | methodHeader jumpSkip | <inline: false> <var: #jumpSkip type: #'AbstractInstruction *'> needsFrame ifFalse: [^0]. methodHeader := objectMemory methodHeaderOf: methodObj. backEnd hasLinkRegister ifTrue: [self PushR: LinkReg]. self PushR: FPReg. self MoveR: SPReg R: FPReg. methodLabel addDependent: (self annotateAbsolutePCRef: (self PushCw: methodLabel asInteger)). "method" + self genMoveConstant: objectMemory nilObject R: SendNumArgsReg. - self annotate: (self MoveCw: objectMemory nilObject R: SendNumArgsReg) - objRef: objectMemory nilObject. self PushR: SendNumArgsReg. "context" self PushR: ReceiverResultReg. methodOrBlockNumArgs + 1 to: (coInterpreter temporaryCountOfMethodHeader: methodHeader) do: [:i| self PushR: SendNumArgsReg]. (primitiveIndex > 0 and: [(coInterpreter longStoreBytecodeForHeader: methodHeader) = (objectMemory fetchByte: initialPC + (coInterpreter sizeOfCallPrimitiveBytecode: methodHeader) ofObject: methodObj)]) ifTrue: [self compileGetErrorCode. initialPC := initialPC + (coInterpreter sizeOfCallPrimitiveBytecode: methodHeader) + (coInterpreter sizeOfLongStoreTempBytecode: methodHeader)]. self MoveAw: coInterpreter stackLimitAddress R: TempReg. self CmpR: TempReg R: SPReg. "N.B. FLAGS := SPReg - TempReg" "If we can't context switch for this method, use a slightly slower overflow check that clears SendNumArgsReg." (coInterpreter canContextSwitchIfActivating: methodObj header: methodHeader) ifTrue: [self JumpBelow: stackOverflowCall. stackCheckLabel := self Label] ifFalse: [jumpSkip := self JumpAboveOrEqual: 0. self MoveCq: 0 R: SendNumArgsReg. self Jump: stackOverflowCall. jumpSkip jmpTarget: (stackCheckLabel := self Label)]. self annotateBytecode: stackCheckLabel. self cppIf: #NewspeakVM ifTrue: [numIRCs > 0 ifTrue: [self PrefetchAw: theIRCs]]! Item was changed: ----- Method: SimpleStackBasedCogit>>genDoubleComparison:invert: (in category 'primitive generators') ----- genDoubleComparison: jumpOpcodeGenerator invert: invertComparison "Stack looks like receiver (also in ResultReceiverReg) arg return address" <var: #jumpOpcodeGenerator declareC: 'AbstractInstruction *(*jumpOpcodeGenerator)(void *)'> | jumpFail jumpImmediate jumpNonInt jumpCond compare | <var: #jumpImmediate type: #'AbstractInstruction *'> <var: #jumpNonInt type: #'AbstractInstruction *'> <var: #jumpCond type: #'AbstractInstruction *'> <var: #compare type: #'AbstractInstruction *'> <var: #jumpFail type: #'AbstractInstruction *'> self MoveMw: objectMemory wordSize r: SPReg R: TempReg. objectRepresentation genGetDoubleValueOf: ReceiverResultReg into: DPFPReg0. self MoveR: TempReg R: ClassReg. jumpImmediate := objectRepresentation genJumpImmediateInScratchReg: TempReg. objectRepresentation genGetCompactClassIndexNonImmOf: ClassReg into: SendNumArgsReg. objectRepresentation genCmpClassFloatCompactIndexR: SendNumArgsReg. jumpFail := self JumpNonZero: 0. objectRepresentation genGetDoubleValueOf: ClassReg into: DPFPReg1. invertComparison "May need to invert for NaNs" ifTrue: [compare := self CmpRd: DPFPReg0 Rd: DPFPReg1] ifFalse: [compare := self CmpRd: DPFPReg1 Rd: DPFPReg0]. jumpCond := self perform: jumpOpcodeGenerator with: 0. "FP jumps are a little weird" + self genMoveFalseR: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory falseObject R: ReceiverResultReg) - objRef: objectMemory falseObject. self flag: 'currently caller pushes result'. self RetN: objectMemory wordSize * 2. + jumpCond jmpTarget: (self genMoveTrueR: ReceiverResultReg). - jumpCond jmpTarget: (self annotate: (self MoveCw: objectMemory trueObject R: ReceiverResultReg) - objRef: objectMemory trueObject). self RetN: objectMemory wordSize * 2. jumpImmediate jmpTarget: self Label. objectRepresentation smallIntegerIsOnlyImmediateType ifFalse: [jumpNonInt := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg]. objectRepresentation genConvertSmallIntegerToIntegerInReg: ClassReg. self ConvertR: ClassReg Rd: DPFPReg1. self Jump: compare. jumpFail jmpTarget: self Label. objectRepresentation smallIntegerIsOnlyImmediateType ifFalse: [jumpNonInt jmpTarget: jumpFail getJmpTarget]. ^0! Item was added: + ----- Method: SimpleStackBasedCogit>>genMoveConstant:R: (in category 'bytecode generator support') ----- + genMoveConstant: constant R: reg + <inline: true> + ^ (objectRepresentation shouldAnnotateObjectReference: constant) + ifTrue: [ (self annotate: (self MoveCw: constant R: reg) objRef: constant) ] + ifFalse: [ self MoveCq: constant R: reg ] + + ! Item was added: + ----- Method: SimpleStackBasedCogit>>genMoveFalseR: (in category 'bytecode generator support') ----- + genMoveFalseR: reg + <inline: true> + ^ self genMoveConstant: objectMemory falseObject R: reg + ! Item was added: + ----- Method: SimpleStackBasedCogit>>genMoveTrueR: (in category 'bytecode generator support') ----- + genMoveTrueR: reg + <inline: true> + ^ self genMoveConstant: objectMemory trueObject R: reg + ! Item was changed: ----- Method: SimpleStackBasedCogit>>genPushLiteralVariable: (in category 'bytecode generator support') ----- genPushLiteralVariable: literalIndex <inline: false> | association | association := self getLiteral: literalIndex. "N.B. Do _not_ use ReceiverResultReg to avoid overwriting receiver in assignment in frameless methods." + self genMoveConstant: association R: ClassReg. - self annotate: (self MoveCw: association R: ClassReg) objRef: association. objectRepresentation genEnsureObjInRegNotForwarded: ClassReg scratchReg: TempReg. objectRepresentation genLoadSlot: ValueIndex sourceReg: ClassReg destReg: TempReg. self PushR: TempReg. ^0! Item was changed: ----- Method: SimpleStackBasedCogit>>genReturnFalse (in category 'bytecode generators') ----- genReturnFalse + self genMoveFalseR: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory falseObject R: ReceiverResultReg) - objRef: objectMemory falseObject. ^self genUpArrowReturn! Item was changed: ----- Method: SimpleStackBasedCogit>>genReturnNil (in category 'bytecode generators') ----- genReturnNil + self genMoveConstant: objectMemory nilObject R: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory nilObject R: ReceiverResultReg) - objRef: objectMemory nilObject. ^self genUpArrowReturn! Item was changed: ----- Method: SimpleStackBasedCogit>>genReturnNilFromBlock (in category 'bytecode generators') ----- genReturnNilFromBlock self assert: inBlock. self flag: 'currently caller pushes result'. + self genMoveConstant: objectMemory nilObject R: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory nilObject R: ReceiverResultReg) - objRef: objectMemory nilObject. ^self genBlockReturn! Item was changed: ----- Method: SimpleStackBasedCogit>>genReturnTrue (in category 'bytecode generators') ----- genReturnTrue + self genMoveTrueR: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory trueObject R: ReceiverResultReg) - objRef: objectMemory trueObject. ^self genUpArrowReturn! Item was changed: ----- Method: SimpleStackBasedCogit>>genSend:numArgs:sendTable: (in category 'bytecode generator support') ----- genSend: selector numArgs: numArgs sendTable: sendTable <inline: false> <var: #sendTable type: #'sqInt *'> | annotation | (objectMemory isYoung: selector) ifTrue: [hasYoungReferent := true]. self assert: needsFrame. annotation := self annotationForSendTable: sendTable. self assert: (numArgs between: 0 and: 255). "say" self assert: (objectMemory addressCouldBeOop: selector). self MoveMw: numArgs * objectMemory wordSize r: SPReg R: ReceiverResultReg. "Deal with stale super sends; see SpurMemoryManager's class comment." (self annotationIsForUncheckedEntryPoint: annotation) ifTrue: [objectRepresentation genEnsureOopInRegNotForwarded: ReceiverResultReg scratchReg: TempReg]. numArgs > 2 ifTrue: [self MoveCq: numArgs R: SendNumArgsReg]. (BytecodeSetHasDirectedSuperSend and: [annotation = IsDirectedSuperSend]) ifTrue: + [self genMoveConstant: tempOop R: TempReg]. - [self annotate: (self MoveCw: tempOop R: TempReg) objRef: tempOop]. self MoveCw: selector R: ClassReg. self annotate: (self Call: (sendTable at: (numArgs min: NumSendTrampolines - 1))) with: annotation. self flag: 'currently caller pushes result'. self PushR: ReceiverResultReg. ^0! Item was changed: ----- Method: SimpleStackBasedCogit>>genSmallIntegerComparison: (in category 'primitive generators') ----- genSmallIntegerComparison: jumpOpcode "Stack looks like receiver (also in ResultReceiverReg) arg return address" | jumpFail jumpTrue | <var: #jumpFail type: #'AbstractInstruction *'> <var: #jumpTrue type: #'AbstractInstruction *'> self MoveMw: objectMemory wordSize r: SPReg R: TempReg. self MoveR: TempReg R: ClassReg. jumpFail := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. self CmpR: ClassReg R: ReceiverResultReg. "N.B. FLAGS := RRReg - ClassReg" jumpTrue := self gen: jumpOpcode. + self genMoveFalseR: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory falseObject R: ReceiverResultReg) - objRef: objectMemory falseObject. self flag: 'currently caller pushes result'. self RetN: objectMemory wordSize * 2. + jumpTrue jmpTarget: (self genMoveTrueR: ReceiverResultReg). - jumpTrue jmpTarget: (self annotate: (self MoveCw: objectMemory trueObject R: ReceiverResultReg) - objRef: objectMemory trueObject). self RetN: objectMemory wordSize * 2. jumpFail jmpTarget: self Label. ^0! Item was changed: ----- Method: SimpleStackBasedCogit>>genSmallIntegerComparison:orDoubleComparison: (in category 'primitive generators') ----- genSmallIntegerComparison: jumpOpcode orDoubleComparison: jumpFPOpcodeGenerator "Stack looks like receiver (also in ResultReceiverReg) arg return address" | jumpDouble jumpNonInt jumpFail jumpTrue jumpCond | <var: #jumpFPOpcodeGenerator declareC: 'AbstractInstruction *(*jumpFPOpcodeGenerator)(void *)'> <var: #jumpDouble type: #'AbstractInstruction *'> <var: #jumpNonInt type: #'AbstractInstruction *'> <var: #jumpCond type: #'AbstractInstruction *'> <var: #jumpTrue type: #'AbstractInstruction *'> <var: #jumpFail type: #'AbstractInstruction *'> backEnd hasDoublePrecisionFloatingPointSupport ifFalse: [^self genSmallIntegerComparison: jumpOpcode]. self MoveMw: objectMemory wordSize r: SPReg R: TempReg. self MoveR: TempReg R: ClassReg. jumpDouble := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. self CmpR: ClassReg R: ReceiverResultReg. "N.B. FLAGS := RRReg - ClassReg" jumpTrue := self gen: jumpOpcode. + self genMoveFalseR: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory falseObject R: ReceiverResultReg) - objRef: objectMemory falseObject. self flag: 'currently caller pushes result'. self RetN: objectMemory wordSize * 2. + jumpTrue jmpTarget: (self genMoveTrueR: ReceiverResultReg). - jumpTrue jmpTarget: (self annotate: (self MoveCw: objectMemory trueObject R: ReceiverResultReg) - objRef: objectMemory trueObject). self RetN: objectMemory wordSize * 2. "Argument may be a Float : let us check or fail" jumpDouble jmpTarget: self Label. objectRepresentation smallIntegerIsOnlyImmediateType ifFalse: [self MoveR: ClassReg R: TempReg. jumpNonInt := objectRepresentation genJumpImmediateInScratchReg: TempReg]. objectRepresentation genGetCompactClassIndexNonImmOf: ClassReg into: SendNumArgsReg. objectRepresentation genCmpClassFloatCompactIndexR: SendNumArgsReg. jumpFail := self JumpNonZero: 0. "It was a Float, so convert the receiver to double and perform the operation" self MoveR: ReceiverResultReg R: TempReg. objectRepresentation genConvertSmallIntegerToIntegerInReg: TempReg. self ConvertR: TempReg Rd: DPFPReg0. objectRepresentation genGetDoubleValueOf: ClassReg into: DPFPReg1. self CmpRd: DPFPReg1 Rd: DPFPReg0. jumpCond := self perform: jumpFPOpcodeGenerator with: 0. "FP jumps are a little weird" + self genMoveFalseR: ReceiverResultReg. - self annotate: (self MoveCw: objectMemory falseObject R: ReceiverResultReg) - objRef: objectMemory falseObject. self flag: 'currently caller pushes result'. self RetN: objectMemory wordSize * 2. + jumpCond jmpTarget: (self genMoveTrueR: ReceiverResultReg). - jumpCond jmpTarget: (self annotate: (self MoveCw: objectMemory trueObject R: ReceiverResultReg) - objRef: objectMemory trueObject). self RetN: objectMemory wordSize * 2. objectRepresentation smallIntegerIsOnlyImmediateType ifTrue: [jumpFail jmpTarget: self Label] ifFalse: [jumpNonInt jmpTarget: (jumpFail jmpTarget: self Label)]. ^0! Item was changed: ----- Method: SimpleStackBasedCogit>>genSpecialSelectorEqualsEquals (in category 'bytecode generators') ----- genSpecialSelectorEqualsEquals | jumpNotEqual jumpPush | <var: #jumpNotEqual type: #'AbstractInstruction *'> <var: #jumpPush type: #'AbstractInstruction *'> self PopR: Arg0Reg. objectRepresentation genEnsureObjInRegNotForwarded: Arg0Reg scratchReg: TempReg. self MoveMw: 0 r: SPReg R: ClassReg. objectRepresentation genEnsureObjInRegNotForwarded: ClassReg scratchReg: TempReg. self CmpR: Arg0Reg R: ClassReg. jumpNotEqual := self JumpNonZero: 0. + self annotate: (self genMoveTrueR: Arg0Reg) - self annotate: (self MoveCw: objectMemory trueObject R: Arg0Reg) objRef: objectMemory trueObject. jumpPush := self Jump: 0. + jumpNotEqual jmpTarget: (self genMoveFalseR: Arg0Reg). - jumpNotEqual jmpTarget: (self annotate: (self MoveCw: objectMemory falseObject R: Arg0Reg) - objRef: objectMemory falseObject). jumpPush jmpTarget: (self MoveR: Arg0Reg Mw: 0 r: SPReg). ^0! Item was changed: ----- Method: SimpleStackBasedCogit>>genStorePop:LiteralVariable: (in category 'bytecode generator support') ----- genStorePop: popBoolean LiteralVariable: litVarIndex <inline: false> | association | "The only reason we assert needsFrame here is that in a frameless method ReceiverResultReg must and does contain only self, but the ceStoreCheck trampoline expects the target of the store to be in ReceiverResultReg. So in a frameless method we would have a conflict between the receiver and the literal store, unless we we smart enough to realise that ReceiverResultReg was unused after the literal variable store, unlikely given that methods return self by default." self assert: needsFrame. association := self getLiteral: litVarIndex. + self genMoveConstant: association R: ReceiverResultReg. - self annotate: (self MoveCw: association R: ReceiverResultReg) objRef: association. objectRepresentation genEnsureObjInRegNotForwarded: ReceiverResultReg scratchReg: TempReg. popBoolean ifTrue: [self PopR: ClassReg] ifFalse: [self MoveMw: 0 r: SPReg R: ClassReg]. traceStores > 0 ifTrue: [self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreSourceReg: ClassReg slotIndex: ValueIndex destReg: ReceiverResultReg scratchReg: TempReg inFrame: needsFrame! Item was removed: - ----- Method: StackToRegisterMappingCogit>>genMoveConstant:R: (in category 'bytecode generator support') ----- - genMoveConstant: constant R: reg - <inline: true> - ^ (objectRepresentation shouldAnnotateObjectReference: constant) - ifTrue: [ (self annotate: (self MoveCw: constant R: reg) objRef: constant) ] - ifFalse: [ self MoveCq: constant R: reg ] - - ! Item was removed: - ----- Method: StackToRegisterMappingCogit>>genMoveFalseR: (in category 'bytecode generator support') ----- - genMoveFalseR: reg - <inline: true> - ^ self genMoveConstant: objectMemory falseObject R: reg - ! Item was removed: - ----- Method: StackToRegisterMappingCogit>>genMoveTrueR: (in category 'bytecode generator support') ----- - genMoveTrueR: reg - <inline: true> - ^ self genMoveConstant: objectMemory trueObject R: reg - !

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VM Maker: VMMaker.oscog-cb.1254.mcz
by commits＠source.squeak.org 25 Apr '15

25 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1254.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1254 Author: cb Time: 25 April 2015, 2:53:23.172 pm UUID: 97025480-a775-439d-b087-6a5f4be3e7c7 Ancestors: VMMaker.oscog-tpr.1253 In genStorePop: popBoolean LiteralVariable: litVarIndex ; use allocateRequiredReg instead of allocateCallReg as the ceStoreCheckTrampoline generation takes already care of saving the register, including ReceiverResultReg, better. In genStorePop: popBoolean MaybeContextReceiverVariable: slotIndex, fixed a comment In genStorePop: popBoolean RemoteTemp: slotIndex At: remoteTempIndex, still need to allocate ReceiverResultReg (one of my recent fix remove allocateCallReg: instead of replacing it with allocateRequiredReg:) and move optStatus isReceiverResultRegLive: false in the branch where ReceiverReg is allocated only. =============== Diff against VMMaker.oscog-tpr.1253 =============== Item was changed: ----- Method: StackToRegisterMappingCogit>>genStorePop:LiteralVariable: (in category 'bytecode generator support') ----- genStorePop: popBoolean LiteralVariable: litVarIndex <inline: false> | topReg assocReg association | "The only reason we assert needsFrame here is that in a frameless method ReceiverResultReg must and does contain only self, but the ceStoreCheck trampoline expects the target of the store to be in ReceiverResultReg. So in a frameless method we would have a conflict between the receiver and the literal store, unless we we smart enough to realise that ReceiverResultReg was unused after the literal variable store, unlikely given that methods return self by default." self assert: needsFrame. "N.B. No need to check the stack for references because we generate code for literal variable loads that stores the result in a register, deferring only the register push." association := self getLiteral: litVarIndex. "Avoid store check for immediate values" (objectRepresentation isUnannotatableConstant: self ssTop) ifTrue: [ assocReg := self allocateAnyReg. self genMoveConstant: association R: assocReg. objectRepresentation genEnsureObjInRegNotForwarded: assocReg scratchReg: TempReg. self ssStorePop: popBoolean toReg: TempReg. traceStores > 0 ifTrue: [ assocReg = ReceiverResultReg ifFalse: [ self ssAllocateRequiredReg: ReceiverResultReg. optStatus isReceiverResultRegLive: false. self MoveR: assocReg R: ReceiverResultReg ]. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreImmediateInSourceReg: TempReg slotIndex: ValueIndex destReg: assocReg ]. topReg := self allocateRegForStackTopEntryNotConflictingWith: (self registerMaskFor: ReceiverResultReg). self ssStorePop: popBoolean toReg: topReg. optStatus isReceiverResultRegLive: false. + self ssAllocateRequiredReg: ReceiverResultReg. "for ceStoreCheck call in genStoreSourceReg: has to be ReceiverResultReg" - self ssAllocateCallReg: ReceiverResultReg. "for ceStoreCheck call in genStoreSourceReg: has to be ReceiverResultReg" self genMoveConstant: association R: ReceiverResultReg. objectRepresentation genEnsureObjInRegNotForwarded: ReceiverResultReg scratchReg: TempReg. traceStores > 0 ifTrue: [self MoveR: topReg R: TempReg. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreSourceReg: topReg slotIndex: ValueIndex destReg: ReceiverResultReg scratchReg: TempReg inFrame: needsFrame! Item was changed: ----- Method: StackToRegisterMappingCogit>>genStorePop:MaybeContextReceiverVariable: (in category 'bytecode generator support') ----- genStorePop: popBoolean MaybeContextReceiverVariable: slotIndex <inline: false> | jmpSingle jmpDone valueReg | <var: #jmpSingle type: #'AbstractInstruction *'> <var: #jmpDone type: #'AbstractInstruction *'> "The reason we need a frame here is that assigning to an inst var of a context may involve wholesale reorganization of stack pages, and the only way to preserve the execution state of an activation in that case is if it has a frame." self assert: needsFrame. self ssFlushUpThroughReceiverVariable: slotIndex. "Note that ReceiverResultReg remains live after both ceStoreContextInstVarTrampoline and ceStoreCheckTrampoline." self ensureReceiverResultRegContainsSelf. self ssPop: 1. + self ssAllocateCallReg: ClassReg and: SendNumArgsReg. "for ceStoreContextInstVarTrampoline" - self ssAllocateCallReg: ClassReg and: SendNumArgsReg. "for the ceStoreCheck call in genStoreSourceReg:... below" self ssPush: 1. objectRepresentation genLoadSlot: SenderIndex sourceReg: ReceiverResultReg destReg: TempReg. valueReg := self ssStorePop: popBoolean toPreferredReg: ClassReg. valueReg ~= ClassReg ifTrue: [self MoveR: valueReg R: ClassReg]. jmpSingle := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. self MoveCq: slotIndex R: SendNumArgsReg. self CallRT: ceStoreContextInstVarTrampoline. jmpDone := self Jump: 0. jmpSingle jmpTarget: self Label. traceStores > 0 ifTrue: [self MoveR: ClassReg R: TempReg. self CallRT: ceTraceStoreTrampoline]. objectRepresentation genStoreSourceReg: ClassReg slotIndex: slotIndex destReg: ReceiverResultReg scratchReg: TempReg inFrame: true. jmpDone jmpTarget: self Label. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genStorePop:RemoteTemp:At: (in category 'bytecode generator support') ----- genStorePop: popBoolean RemoteTemp: slotIndex At: remoteTempIndex <inline: false> | topReg topSpilled tempVectReg | "The only reason we assert needsFrame here is that in a frameless method ReceiverResultReg must and does contain only self, but the ceStoreCheck trampoline expects the target of the store to be in ReceiverResultReg. So in a frameless method we would have a conflict between the receiver and the temote temp store, unless we we smart enough to realise that ReceiverResultReg was unused after the literal variable store, unlikely given that methods return self by default." self assert: needsFrame. - optStatus isReceiverResultRegLive: false. "N.B. No need to check the stack for references because we generate code for remote temp loads that stores the result in a register, deferring only the register push." "Avoid store check for immediate values" (objectRepresentation isUnannotatableConstant: self ssTop) ifTrue: [ tempVectReg := self allocateAnyReg. self MoveMw: (self frameOffsetOfTemporary: remoteTempIndex) r: FPReg R: tempVectReg. self ssStorePop: popBoolean toReg: TempReg. traceStores > 0 ifTrue: [ tempVectReg = ReceiverResultReg ifFalse: [ self ssAllocateRequiredReg: ReceiverResultReg. optStatus isReceiverResultRegLive: false. self MoveR: tempVectReg R: ReceiverResultReg ]. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreImmediateInSourceReg: TempReg slotIndex: slotIndex destReg: tempVectReg]. topReg := self allocateRegForStackTopEntryNotConflictingWith: (self registerMaskFor: ReceiverResultReg). topSpilled := self ssTop spilled. self ssStorePop: (popBoolean or: [topSpilled]) toReg: topReg. popBoolean ifFalse: [topSpilled ifFalse: [self ssPop: 1]. self ssPushRegister: topReg]. + self ssAllocateRequiredReg: ReceiverResultReg. + optStatus isReceiverResultRegLive: false. self MoveMw: (self frameOffsetOfTemporary: remoteTempIndex) r: FPReg R: ReceiverResultReg. traceStores > 0 ifTrue: [self MoveR: topReg R: TempReg. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreSourceReg: topReg slotIndex: slotIndex destReg: ReceiverResultReg scratchReg: TempReg inFrame: needsFrame!

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Re: [Vm-dev] VM Maker: VMMaker.oscog-tpr.1253.mcz
by David T. Lewis 25 Apr '15

25 Apr '15

On Fri, Apr 24, 2015 at 10:35:15PM +0000, commits(a)source.squeak.org wrote: > > We can now sim the trunk46-spur image up to where Balloon does something > the simulator code can't handle. 130 million bytecodes or so and a full > scale gc, compaction, pig compact and code compact. > Bravo! Dave

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VM Maker: VMMaker.oscog-tpr.1253.mcz
by commits＠source.squeak.org 25 Apr '15

25 Apr '15

tim Rowledge uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1253.mcz ==================== Summary ==================== Name: VMMaker.oscog-tpr.1253 Author: tpr Time: 24 April 2015, 3:34:54.257 pm UUID: 8f8f4942-2558-4a50-a21a-80d513acf9f0 Ancestors: VMMaker.oscog-cb.1252 Add ARM opcodes for MSR (status register updating) and CMPSMULL (a virtual instruction that actually uses a CMP but brings in an ASR 31 of one arg; this is only for use in the genMulR:R:) Since fixing the mulitply breaks things - we think because the sim code does not handle it correctly though cannot be sure yet - turn off usage of it by setting canMulRR to false. Add a crucial rewriteInlineCacheTag:at: for ARM. We can now sim the trunk46-spur image up to where Balloon does something the simulator code can't handle. 130 million bytecodes or so and a full scale gc, compaction, pig compact and code compact. =============== Diff against VMMaker.oscog-cb.1252 =============== Item was changed: CogAbstractInstruction subclass: #CogARMCompiler instanceVariableNames: 'conditionOrNil' + classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CMPSMULL CPSRReg CS CmpOpcode ConcreteIPReg ConcreteVarBaseReg EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveNotOpcode MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode' - classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode ConcreteIPReg ConcreteVarBaseReg EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveNotOpcode MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode' poolDictionaries: '' category: 'VMMaker-JIT'! !CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0! I generate ARM instructions from CogAbstractInstructions. For reference see http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architectur… The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw). This class does not take any special action to flush the instruction cache on instruction-modification.! Item was changed: ----- Method: CogARMCompiler class>>initialize (in category 'class initialization') ----- initialize "Initialize various ARM instruction-related constants." "CogARMCompiler initialize" | specificOpcodes refs | super initialize. self ~~ CogARMCompiler ifTrue: [^self]. R0 := 0. R1 := 1. R2 := 2. R3 := 3. R4 := 4. R5 := 5. R6 := 6. R7 := 7. R8 := 8. R9 := 9. R10 := 10. R11 := 11. R12 := 12. SP := 13. LR := 14. PC := 15. CArg0Reg := 0. CArg1Reg := 1. CArg2Reg := 2. CArg3Reg := 3. ConcreteVarBaseReg := 10. ConcreteIPReg := 12. "IP, The Intra-Procedure-call scratch register." "Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1" EQ := 0. NE := 1. CS := 2. CC := 3. MI := 4. PL := 5. VS := 6. VC := 7. HI := 8. LS := 9. GE := 10. LT := 11. GT := 12. LE := 13. AL := 14. AddOpcode := 4. AndOpcode := 0. BicOpcode := 14. CmpOpcode := 10. MoveOpcode := 13. MoveNotOpcode := 15. OrOpcode := 12. RsbOpcode := 3. SubOpcode := 2. XorOpcode := 1. SMLALOpcode := 7. CPSRReg := 16. OverflowFlag := 1 << 28. "Specific instructions" LastRTLCode isNil ifTrue: [CogRTLOpcodes initialize]. + specificOpcodes := #(SMULL MSR MRS LDMFD STMFD BICCqR CMPSMULL). - specificOpcodes := #(SMULL MSR MRS LDMFD STMFD BICCqR). refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect: [:ea| ea key]. (classPool keys reject: [:k| (specificOpcodes includes: k) or: [refs includes: k]]) do: [:k| Undeclared declare: k from: classPool]. specificOpcodes withIndexDo: [:classVarName :value| self classPool declare: classVarName from: Undeclared; at: classVarName put: value + LastRTLCode - 1]! Item was changed: ----- Method: CogARMCompiler>>canMulRR (in category 'testing') ----- canMulRR <inline: true> + ^false! - ^true! Item was changed: ----- Method: CogARMCompiler>>computeMaximumSize (in category 'generate machine code') ----- computeMaximumSize "Because we don't use Thumb, each ARM instruction has 4 bytes. Some abstract opcodes need more than one instruction. We only handle those in this caseOf: and let the default return 4" opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^maxSize := 0]. [AlignmentNops] -> [^maxSize := (operands at: 0) - 4]. [Fill16] -> [^maxSize := 4]. [Fill32] -> [^maxSize := 4]. [FillFromWord] -> [^maxSize := 4]. [Nop] -> [^maxSize := 4]. "ARM Specific Control/Data Movement" [BICCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [TstCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [SMULL] -> [^maxSize := 4]. + [MSR] -> [^maxSize := 4]. + [CMPSMULL] -> [^maxSize := 4]. "special compare for genMulR:R: usage" "Control" [Call] -> [^maxSize := 4]. [CallFull] -> [^maxSize := 20]. [JumpR] -> [^maxSize := 4]. [Jump] -> [^maxSize := 4]. [JumpFull] -> [^maxSize := 20]. [JumpLong] -> [^maxSize := 4]. [JumpZero] -> [^maxSize := 4]. [JumpNonZero] -> [^maxSize := 4]. [JumpNegative] -> [^maxSize := 4]. [JumpNonNegative] -> [^maxSize := 4]. [JumpOverflow] -> [^maxSize := 4]. [JumpNoOverflow] -> [^maxSize := 4]. [JumpCarry] -> [^maxSize := 4]. [JumpNoCarry] -> [^maxSize := 4]. [JumpLess] -> [^maxSize := 4]. [JumpGreaterOrEqual] -> [^maxSize := 4]. [JumpGreater] -> [^maxSize := 4]. [JumpLessOrEqual] -> [^maxSize := 4]. [JumpBelow] -> [^maxSize := 4]. [JumpAboveOrEqual] -> [^maxSize := 4]. [JumpAbove] -> [^maxSize := 4]. [JumpBelowOrEqual] -> [^maxSize := 4]. [JumpLongZero] -> [^maxSize := 4]. [JumpLongNonZero] -> [^maxSize := 4]. [JumpFPEqual] -> [^maxSize := 8]. [JumpFPNotEqual] -> [^maxSize := 8]. [JumpFPLess] -> [^maxSize := 8]. [JumpFPGreaterOrEqual]-> [^maxSize := 8]. [JumpFPGreater] -> [^maxSize := 8]. [JumpFPLessOrEqual] -> [^maxSize := 8]. [JumpFPOrdered] -> [^maxSize := 8]. [JumpFPUnordered] -> [^maxSize := 8]. [RetN] -> [^(operands at: 0) = 0 ifTrue: [maxSize := 4] ifFalse: [maxSize := 8]]. [Stop] -> [^maxSize := 4]. "Arithmetic" [AddCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [AndCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [AndCqRR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [CmpCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [OrCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [SubCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [XorCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [AddCwR] -> [^maxSize := 20]. [AndCwR] -> [^maxSize := 20]. [CmpCwR] -> [^maxSize := 20]. [OrCwR] -> [^maxSize := 20]. [SubCwR] -> [^maxSize := 20]. [XorCwR] -> [^maxSize := 20]. [AddRR] -> [^maxSize := 4]. [AndRR] -> [^maxSize := 4]. [CmpRR] -> [^maxSize := 4]. [OrRR] -> [^maxSize := 4]. [XorRR] -> [^maxSize := 4]. [SubRR] -> [^maxSize := 4]. [NegateR] -> [^maxSize := 4]. [LoadEffectiveAddressMwrR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [LogicalShiftLeftCqR] -> [^maxSize := 4]. [LogicalShiftRightCqR] -> [^maxSize := 4]. [ArithmeticShiftRightCqR] -> [^maxSize := 4]. [LogicalShiftLeftRR] -> [^maxSize := 4]. [LogicalShiftRightRR] -> [^maxSize := 4]. [ArithmeticShiftRightRR] -> [^maxSize := 4]. [AddRdRd] -> [^maxSize := 4]. [CmpRdRd] -> [^maxSize := 4]. [SubRdRd] -> [^maxSize := 4]. [MulRdRd] -> [^maxSize := 4]. [DivRdRd] -> [^maxSize := 4]. [SqrtRd] -> [^maxSize := 4]. "Data Movement" [MoveCqR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 16]]. [MoveCwR] -> [^maxSize := 16]. [MoveRR] -> [^maxSize := 4]. [MoveRdRd] -> [^maxSize := 4]. [MoveAwR] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 0)) ifTrue: [4] ifFalse: [20]]. [MoveRAw] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 1)) ifTrue: [4] ifFalse: [20]]. [MoveRMwr] -> [self is12BitValue: (operands at: 1) ifTrue: [ :u :i | ^maxSize := 4] ifFalse: [ ^maxSize := 20 ]]. [MoveRdM64r] -> [^maxSize := 20]. [MoveMbrR] -> [self is12BitValue: (operands at: 0) ifTrue: [ :u :i | ^maxSize := 4] ifFalse: [ ^maxSize := 20 ]]. [MoveRMbr] -> [self is12BitValue: (operands at: 1) ifTrue: [ :u :i | ^maxSize := 4] ifFalse: [ ^maxSize := 20 ]]. [MoveM16rR] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 4] ifFalse: [maxSize := 20]]. [MoveM64rRd] -> [^maxSize := 20]. [MoveMwrR] -> [self is12BitValue: (operands at: 0) ifTrue: [ :u :i | ^maxSize := 4] ifFalse: [ ^maxSize := 20 ]]. [MoveXbrRR] -> [^maxSize := 4]. [MoveRXbrR] -> [^maxSize := 4]. [MoveXwrRR] -> [^maxSize := 4]. [MoveRXwrR] -> [^maxSize := 4]. [PopR] -> [^maxSize := 4]. [PushR] -> [^maxSize := 4]. [PushCw] -> [^maxSize := 20]. [PushCq] -> [^self rotateable8bitImmediate: (operands at: 0) ifTrue: [:r :i| maxSize := 8] ifFalse: [maxSize := 20]]. [PrefetchAw] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 1)) ifTrue: [4] ifFalse: [20]]. "Conversion" [ConvertRRd] -> [^maxSize := 4]. }. ^0 "to keep C compiler quiet" ! Item was added: + ----- Method: CogARMCompiler>>concretizeCMPSMULL (in category 'generate machine code - concretize') ----- + concretizeCMPSMULL + "Generate a CMP a, b, ASR #31 instruction, specifically for comparing the resutls of SMULLs in genMulR:R:" + | hiReg loReg | + hiReg := self concreteRegister: (operands at: 0). + loReg := self concreteRegister: (operands at: 1). + self machineCodeAt: 0 + put: (self type: 0 op: CmpOpcode set: 1 rn: hiReg rd: 0) + + (31<<7) "the shift amount" + + (2<<5) "the shift type - ASR" + + loReg. + ^machineCodeSize := 4! Item was changed: ----- Method: CogARMCompiler>>concretizeDataOperationCqR: (in category 'generate machine code - concretize') ----- concretizeDataOperationCqR: armOpcode "Will get inlined into concretizeAt: switch." "4 == Add, 2 == Sub, Xor == 1, And == 0, Or == 12, Bic == 14" <inline: true> |val rd rn | val := operands at: 0. rn := self concreteRegister: (operands at: 1). + rd := opcode = CmpOpcode ifTrue: [0] ifFalse:[rn]. "Extra note - if ever a version of this code wants to NOT set the Set flag - Cmp must always have it set or it will pretend to be a SMALALBT and Very Bad Things might happen" - rd := opcode = CmpOpcode ifTrue: [0] ifFalse:[rn]. self rotateable8bitImmediate: val ifTrue: [:rot :immediate | self machineCodeAt: 0 put: (self type: 1 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: ((rot>>1)"in this usage we have to halve the rot value" << 8 bitOr: immediate)). ^machineCodeSize := 4] ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF" val > 0 ifTrue: [ |hb | hb := val highBit. 1 << hb = (val +1) ifTrue: [ "MVN temp, #0, making 0xffffffff" self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0). "Then armOpcode reg, temp reg, lsr #(32-hb)" self machineCodeAt: 4 put:(self dataOpType: armOpcode rd: rd rn: rn rm: ConcreteIPReg lsr: (32-hb)). ^machineCodeSize :=8]]. ^self concretizeDataOperationCwR: armOpcode]. ^0 "to keep Slang happy" ! Item was added: + ----- Method: CogARMCompiler>>concretizeMSR (in category 'generate machine code - concretize') ----- + concretizeMSR + "Generate an MSR CPSR_f, #flags instruction. + Note that we only have business with the NZCV flags so we use + N -> 8 + Z -> 4 + C -> 2 + V -> 1. + You don't want to mess with this too much." + | flags | + flags := self concreteRegister: (operands at: 0). + self machineCodeAt: 0 put: (self msr: flags). + ^machineCodeSize := 4! Item was changed: ----- Method: CogARMCompiler>>concretizeSMULL (in category 'generate machine code - concretize') ----- concretizeSMULL + | srcA srcB hiResultReg loResultReg | + "Generate an SMULL loResultReg, hiResultReg, srcA, srcB instruction" + srcA := self concreteRegister: (operands at: 0). + "NOTE: srcB contains the other mutiplicand at this point. It is OK to use it as the destination for the low part of the result and in fact this saves us moving it later" + loResultReg := srcB := self concreteRegister: (operands at: 1). + hiResultReg := self concreteRegister: RISCTempReg. - | srcReg destReg hiReg loReg | - srcReg := self concreteRegister: (operands at: 0). - destReg := self concreteRegister: (operands at: 1). - hiReg := self concreteRegister: RISCTempReg. - loReg := self concreteRegister: TempReg. self machineCodeAt: 0 + put: (self type: 0 op: 6 set: 0 rn: hiResultReg rd: loResultReg) + + (srcA << 8) - put: (self type: 0 op: 6 set: 0 rn: hiReg rd: loReg) - + (srcReg << 8) + (9 << 4) + + srcB. - + destReg. ^machineCodeSize := 4! Item was changed: ----- Method: CogARMCompiler>>dispatchConcretize (in category 'generate machine code') ----- dispatchConcretize "Attempt to generate concrete machine code for the instruction at address. This is the inner dispatch of concretizeAt: actualAddress which exists only to get around the branch size limits in the SqueakV3 (blue book derived) bytecode set." <returnTypeC: #void> conditionOrNil ifNotNil: [self concretizeConditionalInstruction. ^self]. opcode caseOf: { "Noops & Pseudo Ops" [Label] -> [^self concretizeLabel]. [AlignmentNops] -> [^self concretizeAlignmentNops]. [Fill16] -> [^self concretizeFill16]. [Fill32] -> [^self concretizeFill32]. [FillFromWord] -> [^self concretizeFillFromWord]. [Nop] -> [^self concretizeNop]. "ARM Specific Control/Data Movement" [LDMFD] -> [^self concretizeLDMFD]. [STMFD] -> [^self concretizeSTMFD]. [SMULL] -> [^self concretizeSMULL] . + [CMPSMULL] -> [^self concretizeCMPSMULL]. + [MSR] -> [^self concretizeMSR]. [BICCqR] -> [^self concretizeDataOperationCqR: BicOpcode]. "Control" [Call] -> [^self concretizeCall]. "call code within code space" [CallFull] -> [^self concretizeCallFull]. "call code anywhere in address space" [JumpR] -> [^self concretizeJumpR]. [JumpFull] -> [^self concretizeJumpFull]."jump within address space" [JumpLong] -> [^self concretizeConditionalJump: AL]."jumps witihn code space" [JumpLongZero] -> [^self concretizeConditionalJump: EQ]. [JumpLongNonZero] -> [^self concretizeConditionalJump: NE]. [Jump] -> [^self concretizeConditionalJump: AL]. [JumpZero] -> [^self concretizeConditionalJump: EQ]. [JumpNonZero] -> [^self concretizeConditionalJump: NE]. [JumpNegative] -> [^self concretizeConditionalJump: MI]. [JumpNonNegative] -> [^self concretizeConditionalJump: PL]. [JumpOverflow] -> [^self concretizeConditionalJump: VS]. [JumpNoOverflow] -> [^self concretizeConditionalJump: VC]. [JumpCarry] -> [^self concretizeConditionalJump: CS]. [JumpNoCarry] -> [^self concretizeConditionalJump: CC]. [JumpLess] -> [^self concretizeConditionalJump: LT]. [JumpGreaterOrEqual] -> [^self concretizeConditionalJump: GE]. [JumpGreater] -> [^self concretizeConditionalJump: GT]. [JumpLessOrEqual] -> [^self concretizeConditionalJump: LE]. [JumpBelow] -> [^self concretizeConditionalJump: CC]. "unsigned lower" [JumpAboveOrEqual] -> [^self concretizeConditionalJump: CS]. "unsigned greater or equal" [JumpAbove] -> [^self concretizeConditionalJump: HI]. [JumpBelowOrEqual] -> [^self concretizeConditionalJump: LS]. [JumpFPEqual] -> [^self concretizeFPConditionalJump: EQ]. [JumpFPNotEqual] -> [^self concretizeFPConditionalJump: NE]. [JumpFPLess] -> [^self concretizeFPConditionalJump: LT]. [JumpFPGreaterOrEqual] -> [^self concretizeFPConditionalJump: GE]. [JumpFPGreater] -> [^self concretizeFPConditionalJump: GT]. [JumpFPLessOrEqual] -> [^self concretizeFPConditionalJump: LE]. [JumpFPOrdered] -> [^self concretizeFPConditionalJump: VC]. [JumpFPUnordered] -> [^self concretizeFPConditionalJump: VS]. [RetN] -> [^self concretizeRetN]. [Stop] -> [^self concretizeStop]. "Arithmetic" [AddCqR] -> [^self concretizeAddCqR]. [AddCwR] -> [^self concretizeDataOperationCwR: AddOpcode]. [AddRR] -> [^self concretizeDataOperationRR: AddOpcode]. [AddRdRd] -> [^self concretizeAddRdRd]. [AndCqR] -> [^self concretizeAndCqR]. [AndCqRR] -> [^self concretizeAndCqRR]. [AndCwR] -> [^self concretizeDataOperationCwR: AndOpcode]. [AndRR] -> [^self concretizeDataOperationRR: AndOpcode]. [CmpCqR] -> [^self concretizeDataOperationCqR: CmpOpcode]. [CmpCwR] -> [^self concretizeDataOperationCwR: CmpOpcode]. [CmpRR] -> [^self concretizeDataOperationRR: CmpOpcode]. [CmpRdRd] -> [^self concretizeCmpRdRd]. [DivRdRd] -> [^self concretizeDivRdRd]. [MulRdRd] -> [^self concretizeMulRdRd]. [OrCqR] -> [^self concretizeDataOperationCqR: OrOpcode]. [OrCwR] -> [^self concretizeDataOperationCwR: OrOpcode]. [OrRR] -> [^self concretizeDataOperationRR: OrOpcode]. [SubCqR] -> [^self concretizeSubCqR]. [SubCwR] -> [^self concretizeDataOperationCwR: SubOpcode]. [SubRR] -> [^self concretizeDataOperationRR: SubOpcode]. [SubRdRd] -> [^self concretizeSubRdRd]. [SqrtRd] -> [^self concretizeSqrtRd]. [TstCqR] -> [^self concretizeTstCqR]. [XorCqR] -> [^self concretizeDataOperationCqR: XorOpcode]. [XorCwR] -> [^self concretizeDataOperationCwR: XorOpcode]. [XorRR] -> [^self concretizeDataOperationRR: XorOpcode]. [NegateR] -> [^self concretizeNegateR]. [LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR]. [ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR]. [LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR]. [LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR]. [ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR]. [LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR]. [LogicalShiftRightRR] -> [^self concretizeLogicalShiftRightRR]. "Data Movement" [MoveCqR] -> [^self concretizeMoveCqR]. [MoveCwR] -> [^self concretizeMoveCwR]. [MoveRR] -> [^self concretizeMoveRR]. [MoveAwR] -> [^self concretizeMoveAwR]. [MoveRAw] -> [^self concretizeMoveRAw]. [MoveMbrR] -> [^self concretizeMoveMbrR]. [MoveRMbr] -> [^self concretizeMoveRMbr]. [MoveM16rR] -> [^self concretizeMoveM16rR]. [MoveM64rRd] -> [^self concretizeMoveM64rRd]. [MoveMwrR] -> [^self concretizeMoveMwrR]. [MoveXbrRR] -> [^self concretizeMoveXbrRR]. [MoveRXbrR] -> [^self concretizeMoveRXbrR]. [MoveXwrRR] -> [^self concretizeMoveXwrRR]. [MoveRXwrR] -> [^self concretizeMoveRXwrR]. [MoveRMwr] -> [^self concretizeMoveRMwr]. [MoveRdM64r] -> [^self concretizeMoveRdM64r]. [PopR] -> [^self concretizePopR]. [PushR] -> [^self concretizePushR]. [PushCq] -> [^self concretizePushCq]. [PushCw] -> [^self concretizePushCw]. [PrefetchAw] -> [^self concretizePrefetchAw]. "Conversion" [ConvertRRd] -> [^self concretizeConvertRRd]}! Item was changed: ----- Method: CogARMCompiler>>genMulR:R: (in category 'abstract instructions') ----- genMulR: regSource R: regDest + "Use SMULL to produce a 64-bit result, explicitly in RISCTempReg,regDest. + By comparing RISCTempReg with regDest ASR 31(which effectively makes it 0 or -1) we know that the result being EQ means the hi reg and the top bit of the lo reg are the same - ie no overflow. The condition code can then be forced to oVerflow by use of MSR APSR_nzcvq, #1, lsl 28" - "Use SMULL to produce a 64-bit result, implicitly in TempReg,RISCTempReg. - Test the top word for 0 or 1 and set oVerflow if not equal. Move result in - TempReg into regDest." cogit + gen: SMULL operand: regSource operand: regDest; "result in RISCTempReg,regDest" + gen: CMPSMULL operand: RISCTempReg operand: regDest; + gen: MSR operand: 1! - gen: SMULL operand: regSource operand: regDest; "result in TempReg,RISCTempReg" - gen: AddCqR operand: 1 operand: RISCTempReg; "turn -1,0 into 0,1" - gen: AddCqR operand: -1 operand: RISCTempReg; "turn 0,1 into not oVerflow" - gen: MoveRR operand: TempReg operand: regDest! Item was added: + ----- Method: CogARMCompiler>>msr: (in category 'encoding') ----- + msr: flags + "Generate an MSR CPSR_f, #flags instruction. + Note that + a) CPSR_f is equivalent to APSR_nzcvq (ARM ARM DDI0406A p A8-209 & A2-14) + b) We only have business with the NZCV flags so the generated instruction shifts the flags value <<28 - which is a ROR 4" + + ^16r1328F000 + + (2 "rotate rights are in units of 2, remember" << 8) + + (flags bitAnd: 16rF) " to make sure we don't have silly values here"! Item was added: + ----- Method: CogARMCompiler>>rewriteInlineCacheTag:at: (in category 'inline cacheing') ----- + rewriteInlineCacheTag: cacheTag at: callSiteReturnAddress + "Rewrite an inline cache with a new tag. This variant is used + by the garbage collector." + self insert32BitOperand: cacheTag into4InstructionsPreceeding: callSiteReturnAddress -4!

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Re: [Pharo-dev] running the vm from within a dll
by Clément Bera 24 Apr '15

24 Apr '15

Hello, In short this is possible but there are several things to do before we are able to compile the VM as a dynamic library. No one is currently working on it right now because there are limited resources in the VM development and the focus is on other topics (x86_64 and ARM port as well as JIT optimizations). The android VM is working and it may be a good start. If you're interested in doing it, I cc vm-dev were people can detail you what has exactly to be done. Best, Clement 2015-04-24 18:06 GMT+02:00 Stefan Krecher <stefan.krecher(a)googlemail.com>: > Hi all, > i know this topic was discussed from time to time but I'm not sure if > there is a simple answer. > Can the VM be compiled to a windows dll, so pharo could get started from > another dll and would exchange events? > It is probably a similar approach to the one Andreas Raab did for the > android/ squeak port back in 2010. > He compiled squeak as a shared library and started it on Android via a > Java wrapper. > I had a short conversation on that with Andreas on this years ago and it > sounded very easy. I had the impression that he did this on one evening and > it just worked. The code looked simple too. > But maybe it was that easy because Andreas was a super-smart guy ... > Anyway - would this architecture fit with a dll-scario (having a dll that > starts pharo, which itself runs in a dll)? > Regards > Stefan >

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VM Maker: VMMaker.oscog-cb.1252.mcz
by commits＠source.squeak.org 24 Apr '15

24 Apr '15

Eliot Miranda uploaded a new version of VMMaker to project VM Maker: http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1252.mcz ==================== Summary ==================== Name: VMMaker.oscog-cb.1252 Author: cb Time: 24 April 2015, 11:59:54.377 am UUID: 020130de-cdca-49ec-8f3f-2fa2d3d110d2 Ancestors: VMMaker.oscog-eem.1251 In order to fix the SistaCogit (still crashing somehow), I refactored the #== code which was duplicated three times between the Stack v3 / Stack Spur / Sista Spur cogits, mainly by creating 2 smaller methods which are now called by the 3 duplicated methods. I introduced: #extractMaybeBranchDescriptorInto: so I don't need to duplicate the code that fetch the branch descriptor in #== and comparison. Removed a useless allocateCallReg in genStorePop:RemoteTemp:At: because the call reg are saved in the trampoline. Removed a duplicated self assert: needsFrame in genStorePop: popBoolean LiteralVariable: litVarIndex (Eliot moved it to the beginning of the method). =============== Diff against VMMaker.oscog-eem.1251 =============== Item was added: + ----- Method: CogObjectRepresentation>>genEnsureOopInRegNotForwarded:scratchReg:jumpBackTo: (in category 'compile abstract instructions') ----- + genEnsureOopInRegNotForwarded: reg scratchReg: scratch jumpBackTo: instruction + "Make sure that the oop in reg is not forwarded. By default there is + nothing to do. Subclasses for memory managers that forward will override." + ^0! Item was removed: - ----- Method: SistaStackToRegisterMappingCogit>>genDirectEqualsEqualsNoBranchArg:rcvr:argReg:rcvrReg: (in category 'bytecode generators') ----- - genDirectEqualsEqualsNoBranchArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg - <inline: true> - | label jumpEqual jumpNotEqual | - label := self Label. - self genEqualsEqualsComparisonArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg. - self ssPop: 2. - jumpEqual := self JumpZero: 0. - unforwardArg ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. - unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ]. - self genMoveFalseR: rcvrReg. - jumpNotEqual := self Jump: 0. - jumpEqual jmpTarget: (self genMoveTrueR: rcvrReg). - jumpNotEqual jmpTarget: self Label. - self ssPushRegister: rcvrReg. - ^0! Item was removed: - ----- Method: SistaStackToRegisterMappingCogit>>genEqualsEqualsComparisonArg:rcvr:argReg:rcvrReg: (in category 'bytecode generators') ----- - genEqualsEqualsComparisonArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg - <inline: true> - unforwardArg - ifFalse: [ self CmpCq: self ssTop constant R: rcvrReg ] - ifTrue: [ unforwardRcvr - ifFalse: [ self CmpCq: (self ssValue: 1) constant R: argReg ] - ifTrue: [ self CmpR: argReg R: rcvrReg ] ]. ! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." + | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor - | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor nExts rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts inlineCAB annotateInst counterAddress countTripped counterReg | <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> (coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super genSpecialSelectorComparison ]. self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]. "short-cut the jump if operands are SmallInteger constants." (argIsInt and: [rcvrIsInt]) ifTrue: [self cCode: '' inSmalltalk: "In Simulator ints are unsigned..." [rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt]. primDescriptor opcode caseOf: { [JumpLess] -> [result := rcvrInt < argInt]. [JumpLessOrEqual] -> [result := rcvrInt <= argInt]. [JumpGreater] -> [result := rcvrInt > argInt]. [JumpGreaterOrEqual] -> [result := rcvrInt >= argInt]. [JumpZero] -> [result := rcvrInt = argInt]. [JumpNonZero] -> [result := rcvrInt ~= argInt] }. "Must enter any annotatedConstants into the map" self annotateBytecodeIfAnnotated: (self ssValue: 1). self annotateBytecodeIfAnnotated: self ssTop. "Must annotate the bytecode for correct pc mapping." self ssPop: 2. ^self ssPushAnnotatedConstant: (result ifTrue: [objectMemory trueObject] ifFalse: [objectMemory falseObject])]. + self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | + branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. + - nextPC := bytecodePC + primDescriptor numBytes. - nExts := 0. - [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + (byte0 bitAnd: 256). - branchDescriptor isExtension] whileTrue: - [nExts := nExts + 1. - nextPC := nextPC + branchDescriptor numBytes]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. - targetBytecodePC := nextPC - + branchDescriptor numBytes - + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). - postBranchPC := nextPC + branchDescriptor numBytes. argIsInt ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. annotateInst := self ssTop annotateUse. self ssPop: 2. self MoveR: ReceiverResultReg R: TempReg] ifFalse: [self marshallSendArguments: 1. self MoveR: Arg0Reg R: TempReg. rcvrIsInt ifFalse: [objectRepresentation isSmallIntegerTagNonZero ifTrue: [self AndR: ReceiverResultReg R: TempReg] ifFalse: [self OrR: ReceiverResultReg R: TempReg]]]. jumpNotSmallInts := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. counterReg := self allocateRegNotConflictingWith: (self registerMaskFor: ReceiverResultReg and: Arg0Reg). "Use this as the count reg, can't conflict with the registers for the arg and the receiver" counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). self flag: 'will need to use MoveAw32:R: if 64 bits'. self assert: objectMemory wordSize = CounterBytes. self MoveAw: counterAddress R: counterReg. self SubCq: 16r10000 R: counterReg. "Count executed" "If counter trips simply abort the inlined comparison and send continuing to the following branch *without* writing back. A double decrement will not trip the second time." countTripped := self JumpCarry: 0. self MoveR: counterReg Aw: counterAddress. "write back" argIsInt ifTrue: [annotateInst ifTrue: [self annotateBytecode: (self CmpCq: argInt R: ReceiverResultReg)] ifFalse: [self CmpCq: argInt R: ReceiverResultReg]] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self gen: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self SubCq: 1 R: counterReg. "Count untaken" self MoveR: counterReg Aw: counterAddress. "write back" self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). countTripped jmpTarget: (jumpNotSmallInts jmpTarget: self Label). argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg]. ^self genMarshalledSend: (coInterpreter specialSelector: byte0 - self firstSpecialSelectorBytecodeOffset) numArgs: 1 sendTable: ordinarySendTrampolines! Item was changed: ----- Method: SistaStackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders (in category 'bytecode generators') ----- genSpecialSelectorEqualsEqualsWithForwarders "Override to count inlined branches if followed by a conditional branch. We borrow the following conditional branch's counter and when about to inline the comparison we decrement the counter (without writing it back) and if it trips simply abort the inlining, falling back to the normal send which will then continue to the conditional branch which will trip and enter the abort." + | nextPC postBranchPC targetBytecodePC branchDescriptor label counterReg fixup - | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor nExts label counterReg fixup counterAddress countTripped unforwardArg unforwardRcvr argReg rcvrReg regMask | <var: #fixup type: #'BytecodeFixup *'> <var: #countTripped type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> ((coInterpreter isOptimizedMethod: methodObj) or: [needsFrame not]) ifTrue: [ ^ super genSpecialSelectorEqualsEquals ]. - primDescriptor := self generatorAt: byte0. regMask := 0. - - nextPC := bytecodePC + primDescriptor numBytes. - nExts := 0. - [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + (byte0 bitAnd: 256). - branchDescriptor isExtension] whileTrue: - [nExts := nExts + 1. - nextPC := nextPC + branchDescriptor numBytes]. + self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | + branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. - (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifTrue: - [self ssFlushTo: simStackPtr - 2]. unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. + "If an operand is an annotable constant, it may be forwarded, so we need to store it into a + register so the forwarder check can jump back to the comparison after unforwarding the constant. + However, if one of the operand is an unnanotable constant, does not allocate a register for it + (machine code will use operations on constants)." + self + allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg + rcvrNeedsReg: unforwardRcvr + into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. - "if the rcvr or the arg is an annotable constant, we need to push it to a register - else the forwarder check can't jump back to the comparison after unforwarding the constant" - unforwardArg - ifTrue: - [unforwardRcvr - ifTrue: - [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. - self ssTop popToReg: argReg. - (self ssValue:1) popToReg: rcvrReg] - ifFalse: - [argReg := self allocateRegForStackTopEntry. - self ssTop popToReg: argReg]] - ifFalse: - [self assert: unforwardRcvr. - rcvrReg := self allocateRegForStackEntryAt: 1. - (self ssValue:1) popToReg: rcvrReg]. argReg ifNotNil: [ regMask := self registerMaskFor: argReg ]. rcvrReg ifNotNil: [ regMask := regMask bitOr: (self registerMaskFor: rcvrReg) ]. - self assert: (unforwardArg not or: [argReg notNil]). - self assert: (unforwardRcvr not or: [rcvrReg notNil]). - "Only interested in inlining if followed by a conditional branch." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: + [^ self genEqualsEqualsNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg]. - [^ self genDirectEqualsEqualsNoBranchArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg]. - targetBytecodePC := nextPC - + branchDescriptor numBytes - + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). - postBranchPC := nextPC + branchDescriptor numBytes. counterReg := self allocateRegNotConflictingWith: regMask. "Use this as the count reg, can't conflict with the registers for the arg and the receiver of #==." counterAddress := counters + ((self sizeof: #sqInt) * counterIndex). self flag: 'will need to use MoveAw32:R: if 64 bits'. self assert: objectMemory wordSize = CounterBytes. self MoveAw: counterAddress R: counterReg. self SubCq: 16r10000 R: counterReg. "Count executed" "If counter trips simply abort the inlined comparison and send continuing to the following branch *without* writing back. A double decrement will not trip the second time." countTripped := self JumpCarry: 0. self MoveR: counterReg Aw: counterAddress. "write back" self assert: (unforwardArg or: [ unforwardRcvr ]). + "If branching the stack must be flushed for the merge" + self ssFlushTo: simStackPtr - 2. + label := self Label. + self genEqualsEqualsComparisonArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. - self genEqualsEqualsComparisonArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg. self ssPop: 2. "pop by 2 temporarily for the fixups" branchDescriptor isBranchTrue ifTrue: [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. ] ifFalse: [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. ]. unforwardArg ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ]. self ssPop: -2. "the jump has not been taken and forwarders have been followed." self SubCq: 1 R: counterReg. "Count untaken" self MoveR: counterReg Aw: counterAddress. "write back" self Jump: fixup. countTripped jmpTarget: self Label. "inlined version of #== ignoring the branchDescriptor if the counter trips to have normal state for the optimizer" + self genEqualsEqualsNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. - self genDirectEqualsEqualsNoBranchArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg. ^ 0! Item was added: + ----- Method: StackToRegisterMappingCogit>>allocateEqualsEqualsRegistersArgNeedsReg:rcvrNeedsReg:into: (in category 'bytecode generator support') ----- + allocateEqualsEqualsRegistersArgNeedsReg: argNeedsReg rcvrNeedsReg: rcvrNeedsReg into: binaryBlock + <inline: true> + | argReg rcvrReg | + self assert: (argNeedsReg or: [rcvrNeedsReg]). + argNeedsReg + ifTrue: + [rcvrNeedsReg + ifTrue: + [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. + self ssTop popToReg: argReg. + (self ssValue: 1) popToReg: rcvrReg] + ifFalse: + [argReg := self allocateRegForStackTopEntry. + self ssTop popToReg: argReg]] + ifFalse: + [self assert: rcvrNeedsReg. + rcvrReg := self allocateRegForStackEntryAt: 1. + (self ssValue:1) popToReg: rcvrReg]. + + self assert: (argNeedsReg not or: [argReg notNil]). + self assert: (rcvrNeedsReg not or: [rcvrReg notNil]). + + binaryBlock value: rcvrReg value: argReg.! Item was added: + ----- Method: StackToRegisterMappingCogit>>extractMaybeBranchDescriptorInto: (in category 'bytecode generator support') ----- + extractMaybeBranchDescriptorInto: fourArgBlock + "Looks one instruction ahead of the current bytecodePC and answers its bytecode descriptor and its pc. + If the instruction found is a branch, also answers the pc after the branch and the pc targetted by the branch" + | primDescriptor nextPC nExts branchDescriptor targetBytecodePC postBranchPC | + <var: #primDescriptor type: #'BytecodeDescriptor *'> + <var: #branchDescriptor type: #'BytecodeDescriptor *'> + + primDescriptor := self generatorAt: byte0. + + nextPC := bytecodePC + primDescriptor numBytes. + nExts := 0. + [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + bytecodeSetOffset. + branchDescriptor isExtension] whileTrue: + [nExts := nExts + 1. + nextPC := nextPC + branchDescriptor numBytes]. + + (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: + [ ^ fourArgBlock value: branchDescriptor value: nextPC value: 0 value: 0 ]. + + targetBytecodePC := nextPC + + branchDescriptor numBytes + + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). + postBranchPC := nextPC + branchDescriptor numBytes. + + fourArgBlock value: branchDescriptor value: nextPC value: postBranchPC value: targetBytecodePC! Item was changed: ----- Method: StackToRegisterMappingCogit>>genBinaryInlineComparison:opFalse:destReg: (in category 'inline primitive generators') ----- genBinaryInlineComparison: opTrue opFalse: opFalse destReg: destReg "Inlined comparison. opTrue = jump for true and opFalse = jump for false" + | nextPC branchDescriptor targetBytecodePC postBranchPC | + + self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | + branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. + - | nextPC branchDescriptor nExts | - nextPC := bytecodePC + 3. - nExts := 0. - [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + bytecodeSetOffset. - branchDescriptor isExtension] whileTrue: - [nExts := nExts + 1. - nextPC := nextPC + branchDescriptor numBytes]. (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifTrue: "This is the path where the inlined comparison is followed immediately by a branch" + [ (self fixupAt: nextPC - initialPC) targetInstruction = 0 - [| targetBytecodePC postBranchPC | - targetBytecodePC := nextPC - + branchDescriptor numBytes - + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). - postBranchPC := nextPC + branchDescriptor numBytes. - (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC ] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" self gen: (branchDescriptor isBranchTrue ifTrue: [opTrue] ifFalse: [opFalse]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. deadCode ifFalse: [ self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC) ] ] ifFalse: "This is the path where the inlined comparison is *not* followed immediately by a branch" [| condJump jump | condJump := self gen: opTrue operand: 0. self genMoveFalseR: destReg. jump := self Jump: 0. condJump jmpTarget: (self genMoveTrueR: destReg). jump jmpTarget: self Label]. ^ 0! Item was added: + ----- Method: StackToRegisterMappingCogit>>genEqualsEqualsComparisonArgIsConstant:rcvrIsConstant:argReg:rcvrReg: (in category 'bytecode generator support') ----- + genEqualsEqualsComparisonArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg + "Generates the Cmp instruction for #==. The instruction is different if one of the operands is a constant. + In the case of the v3 memory manager, the constant could be annotable." + <inline: true> + argIsConstant + ifTrue: [ self genCompConstant: self ssTop constant R: rcvrReg ] + ifFalse: [ rcvrIsConstant + ifTrue: [ self genCompConstant: (self ssValue: 1) constant R: argReg ] + ifFalse: [ self CmpR: argReg R: rcvrReg ] ].! Item was added: + ----- Method: StackToRegisterMappingCogit>>genEqualsEqualsForwarderChecksArg:rcvr:argReg:rcvrReg:label:fixup:canBeDead: (in category 'bytecode generator support') ----- + genEqualsEqualsForwarderChecksArg: unforwardArg rcvr: unforwardRcvr argReg: argReg rcvrReg: rcvrReg label: label fixup: fixup canBeDead: canBeDead + "This code generates the forwarders checks if #== is followed by a branch. The forwarders checks need to jump back to the comparison (label) if + a forwarder is found, else jump forward to the correct place, the postBranch or branch target (fixup), if this is the last forwarder check, or jump to + the next forwarder checkif there are 2, or just fall through if it needs to jump to the postBranch and that the branch is dead code" + <inline: true> + unforwardArg ifTrue: [ (canBeDead or: [ unforwardRcvr ]) + ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] + ifFalse: [ objectRepresentation + genEnsureOopInRegNotForwarded: argReg + scratchReg: TempReg + ifForwarder: label + ifNotForwarder: fixup ] ]. + unforwardRcvr ifTrue: [ canBeDead + ifTrue: [objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ] + ifFalse: [objectRepresentation + genEnsureOopInRegNotForwarded: rcvrReg + scratchReg: TempReg + ifForwarder: label + ifNotForwarder: fixup ] ]! Item was added: + ----- Method: StackToRegisterMappingCogit>>genEqualsEqualsNoBranchArgIsConstant:rcvrIsConstant:argReg:rcvrReg: (in category 'bytecode generator support') ----- + genEqualsEqualsNoBranchArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg + "Generates the machine code for #== in the case where the instruction is not followed by a branch" + <var: #jumpEqual type: #'AbstractInstruction *'> + <var: #jumpNotEqual type: #'AbstractInstruction *'> + | label jumpEqual jumpNotEqual | + label := self Label. + self genEqualsEqualsComparisonArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg. + self ssPop: 2. + jumpEqual := self JumpZero: 0. + argIsConstant ifFalse: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. + rcvrIsConstant ifFalse: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ]. + self genMoveFalseR: rcvrReg. + jumpNotEqual := self Jump: 0. + jumpEqual jmpTarget: (self genMoveTrueR: rcvrReg). + jumpNotEqual jmpTarget: self Label. + self ssPushRegister: rcvrReg. + ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorComparison (in category 'bytecode generators') ----- genSpecialSelectorComparison + | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor - | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor nExts rcvrIsInt argIsInt rcvrInt argInt result jumpNotSmallInts inlineCAB annotateInst | <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> <var: #jumpNotSmallInts type: #'AbstractInstruction *'> self ssFlushTo: simStackPtr - 2. primDescriptor := self generatorAt: byte0. argIsInt := self ssTop type = SSConstant and: [objectMemory isIntegerObject: (argInt := self ssTop constant)]. rcvrIsInt := (self ssValue: 1) type = SSConstant and: [objectMemory isIntegerObject: (rcvrInt := (self ssValue: 1) constant)]. (argIsInt and: [rcvrIsInt]) ifTrue: [self cCode: '' inSmalltalk: "In Simulator ints are unsigned..." [rcvrInt := objectMemory integerValueOf: rcvrInt. argInt := objectMemory integerValueOf: argInt]. primDescriptor opcode caseOf: { [JumpLess] -> [result := rcvrInt < argInt]. [JumpLessOrEqual] -> [result := rcvrInt <= argInt]. [JumpGreater] -> [result := rcvrInt > argInt]. [JumpGreaterOrEqual] -> [result := rcvrInt >= argInt]. [JumpZero] -> [result := rcvrInt = argInt]. [JumpNonZero] -> [result := rcvrInt ~= argInt] }. "Must enter any annotatedConstants into the map" self annotateBytecodeIfAnnotated: (self ssValue: 1). self annotateBytecodeIfAnnotated: self ssTop. "Must annotate the bytecode for correct pc mapping." self ssPop: 2. ^self ssPushAnnotatedConstant: (result ifTrue: [objectMemory trueObject] ifFalse: [objectMemory falseObject])]. + self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | + branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. + - nextPC := bytecodePC + primDescriptor numBytes. - nExts := 0. - [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + (byte0 bitAnd: 256). - branchDescriptor isExtension] whileTrue: - [nExts := nExts + 1. - nextPC := nextPC + branchDescriptor numBytes]. "Only interested in inlining if followed by a conditional branch." inlineCAB := branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]. "Further, only interested in inlining = and ~= if there's a SmallInteger constant involved. The relational operators successfully statically predict SmallIntegers; the equality operators do not." (inlineCAB and: [primDescriptor opcode = JumpZero or: [primDescriptor opcode = JumpNonZero]]) ifTrue: [inlineCAB := argIsInt or: [rcvrIsInt]]. inlineCAB ifFalse: [^self genSpecialSelectorSend]. - targetBytecodePC := nextPC - + branchDescriptor numBytes - + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). - postBranchPC := nextPC + branchDescriptor numBytes. argIsInt ifTrue: [(self ssValue: 1) popToReg: ReceiverResultReg. annotateInst := self ssTop annotateUse. self ssPop: 2. self MoveR: ReceiverResultReg R: TempReg] ifFalse: [self marshallSendArguments: 1. self MoveR: Arg0Reg R: TempReg. rcvrIsInt ifFalse: [objectRepresentation isSmallIntegerTagNonZero ifTrue: [self AndR: ReceiverResultReg R: TempReg] ifFalse: [self OrR: ReceiverResultReg R: TempReg]]]. jumpNotSmallInts := objectRepresentation genJumpNotSmallIntegerInScratchReg: TempReg. argIsInt ifTrue: [annotateInst ifTrue: [self annotateBytecode: (self CmpCq: argInt R: ReceiverResultReg)] ifFalse: [self CmpCq: argInt R: ReceiverResultReg]] ifFalse: [self CmpR: Arg0Reg R: ReceiverResultReg]. "Cmp is weird/backwards so invert the comparison. Further since there is a following conditional jump bytecode define non-merge fixups and leave the cond bytecode to set the mergeness." self gen: (branchDescriptor isBranchTrue ifTrue: [primDescriptor opcode] ifFalse: [self inverseBranchFor: primDescriptor opcode]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC). jumpNotSmallInts jmpTarget: self Label. argIsInt ifTrue: [self MoveCq: argInt R: Arg0Reg]. ^self genMarshalledSend: (coInterpreter specialSelector: byte0 - self firstSpecialSelectorBytecodeOffset) numArgs: 1 sendTable: ordinarySendTrampolines.! Item was changed: ----- Method: StackToRegisterMappingCogit>>genSpecialSelectorEqualsEqualsWithForwarders (in category 'bytecode generators') ----- genSpecialSelectorEqualsEqualsWithForwarders + | nextPC branchDescriptor unforwardRcvr argReg targetBytecodePC + unforwardArg rcvrReg postBranchPC label fixup | - | primDescriptor nextPC nExts branchDescriptor unforwardRcvr argReg targetBytecodePC - unforwardArg rcvrReg jumpNotEqual jumpEqual postBranchPC label fixup | <var: #fixup type: #'BytecodeFixup *'> - <var: #jumpEqual type: #'AbstractInstruction *'> - <var: #jumpNotEqual type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> + self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | + branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. - primDescriptor := self generatorAt: byte0. + "If an operand is an annotable constant, it may be forwarded, so we need to store it into a + register so the forwarder check can jump back to the comparison after unforwarding the constant. + However, if one of the operand is an unnanotable constant, does not allocate a register for it + (machine code will use operations on constants) and does not generate forwarder checks." - nextPC := bytecodePC + primDescriptor numBytes. - nExts := 0. - [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + bytecodeSetOffset. - branchDescriptor isExtension] whileTrue: - [nExts := nExts + 1. - nextPC := nextPC + branchDescriptor numBytes]. - "If branching the stack must be flushed for the merge" - (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifTrue: - [self ssFlushTo: simStackPtr - 2]. - unforwardRcvr := (objectRepresentation isUnannotatableConstant: (self ssValue: 1)) not. unforwardArg := (objectRepresentation isUnannotatableConstant: self ssTop) not. + self + allocateEqualsEqualsRegistersArgNeedsReg: unforwardArg + rcvrNeedsReg: unforwardRcvr + into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. - "if the rcvr or the arg is an annotable constant, we need to push it to a register - else the forwarder check can't jump back to the comparison after unforwarding the constant" - unforwardArg - ifTrue: - [unforwardRcvr - ifTrue: - [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. - self ssTop popToReg: argReg. - (self ssValue:1) popToReg: rcvrReg] - ifFalse: - [argReg := self allocateRegForStackTopEntry. - self ssTop popToReg: argReg]] - ifFalse: - [self assert: unforwardRcvr. - rcvrReg := self allocateRegForStackEntryAt: 1. - (self ssValue:1) popToReg: rcvrReg]. + "If not followed by a branch, resolve to true or false." + (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: + [^ self genEqualsEqualsNoBranchArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg]. - label := self Label. + "If branching the stack must be flushed for the merge" + self ssFlushTo: simStackPtr - 2. + + label := self Label. + self genEqualsEqualsComparisonArgIsConstant: unforwardArg not rcvrIsConstant: unforwardRcvr not argReg: argReg rcvrReg: rcvrReg. - "Here we can use Cq because the constant does not need to be annotated" - self assert: (unforwardArg not or: [argReg notNil]). - self assert: (unforwardRcvr not or: [rcvrReg notNil]). - unforwardArg - ifFalse: [ self CmpCq: self ssTop constant R: rcvrReg ] - ifTrue: [ unforwardRcvr - ifFalse: [ self CmpCq: (self ssValue: 1) constant R: argReg ] - ifTrue: [ self CmpR: argReg R: rcvrReg ] ]. - self ssPop: 2. - "If not followed by a branch, resolve to true or false." - (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: - [jumpEqual := self JumpZero: 0. - unforwardArg ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ]. - unforwardRcvr ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ]. - self genMoveFalseR: rcvrReg. - jumpNotEqual := self Jump: 0. - jumpEqual jmpTarget: (self genMoveTrueR: rcvrReg). - jumpNotEqual jmpTarget: self Label. - self ssPushRegister: rcvrReg. - ^0]. - "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." - targetBytecodePC := nextPC - + branchDescriptor numBytes - + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). - postBranchPC := nextPC + branchDescriptor numBytes. (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" self assert: (unforwardArg or: [ unforwardRcvr ]). branchDescriptor isBranchTrue ifTrue: [ deadCode ifFalse: [ fixup := self ensureNonMergeFixupAt: postBranchPC - initialPC ]. self JumpZero: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. + self + genEqualsEqualsForwarderChecksArg: unforwardArg + rcvr: unforwardRcvr + argReg: argReg + rcvrReg: rcvrReg + label: label + fixup: fixup + canBeDead: deadCode ]. - unforwardArg ifTrue: [ (deadCode or: [ unforwardRcvr ]) - ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] - ifFalse: [ objectRepresentation - genEnsureOopInRegNotForwarded: argReg - scratchReg: TempReg - ifForwarder: label - ifNotForwarder: fixup ] ]. - unforwardRcvr ifTrue: [ deadCode - ifTrue: [objectRepresentation genEnsureOopInRegNotForwarded: rcvrReg scratchReg: TempReg jumpBackTo: label ] - ifFalse: [objectRepresentation - genEnsureOopInRegNotForwarded: rcvrReg - scratchReg: TempReg - ifForwarder: label - ifNotForwarder: fixup ] ] ]. branchDescriptor isBranchFalse ifTrue: [ fixup := self ensureNonMergeFixupAt: targetBytecodePC - initialPC. self JumpZero: (self ensureNonMergeFixupAt: postBranchPC - initialPC) asUnsignedInteger. + self + genEqualsEqualsForwarderChecksArg: unforwardArg + rcvr: unforwardRcvr + argReg: argReg + rcvrReg: rcvrReg + label: label + fixup: fixup + canBeDead: false]. - unforwardArg ifTrue: [ unforwardRcvr - ifFalse: [objectRepresentation - genEnsureOopInRegNotForwarded: argReg - scratchReg: TempReg - ifForwarder: label - ifNotForwarder: fixup ] - ifTrue: [ objectRepresentation genEnsureOopInRegNotForwarded: argReg scratchReg: TempReg jumpBackTo: label ] ]. - unforwardRcvr ifTrue: - [ objectRepresentation - genEnsureOopInRegNotForwarded: rcvrReg - scratchReg: TempReg - ifForwarder: label - ifNotForwarder: fixup ]. - "Not reached"]. ^0! Item was changed: ----- Method: StackToRegisterMappingCogit>>genStorePop:LiteralVariable: (in category 'bytecode generator support') ----- genStorePop: popBoolean LiteralVariable: litVarIndex <inline: false> | topReg assocReg association | "The only reason we assert needsFrame here is that in a frameless method ReceiverResultReg must and does contain only self, but the ceStoreCheck trampoline expects the target of the store to be in ReceiverResultReg. So in a frameless method we would have a conflict between the receiver and the literal store, unless we we smart enough to realise that ReceiverResultReg was unused after the literal variable store, unlikely given that methods return self by default." self assert: needsFrame. "N.B. No need to check the stack for references because we generate code for literal variable loads that stores the result in a register, deferring only the register push." association := self getLiteral: litVarIndex. "Avoid store check for immediate values" + (objectRepresentation isUnannotatableConstant: self ssTop) ifTrue: - (objectRepresentation isUnannotatableConstant: self ssTop) - ifTrue: [ assocReg := self allocateAnyReg. self genMoveConstant: association R: assocReg. objectRepresentation genEnsureObjInRegNotForwarded: assocReg scratchReg: TempReg. self ssStorePop: popBoolean toReg: TempReg. traceStores > 0 ifTrue: [ assocReg = ReceiverResultReg ifFalse: [ self ssAllocateRequiredReg: ReceiverResultReg. optStatus isReceiverResultRegLive: false. self MoveR: assocReg R: ReceiverResultReg ]. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreImmediateInSourceReg: TempReg slotIndex: ValueIndex + destReg: assocReg ]. - destReg: assocReg ] - ifFalse: [ self assert: needsFrame. "because ReceiverResult reg is used for storeCheckTrampoline" ]. - topReg := self allocateRegForStackTopEntryNotConflictingWith: (self registerMaskFor: ReceiverResultReg). self ssStorePop: popBoolean toReg: topReg. optStatus isReceiverResultRegLive: false. self ssAllocateCallReg: ReceiverResultReg. "for ceStoreCheck call in genStoreSourceReg: has to be ReceiverResultReg" self genMoveConstant: association R: ReceiverResultReg. objectRepresentation genEnsureObjInRegNotForwarded: ReceiverResultReg scratchReg: TempReg. traceStores > 0 ifTrue: [self MoveR: topReg R: TempReg. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreSourceReg: topReg slotIndex: ValueIndex destReg: ReceiverResultReg scratchReg: TempReg inFrame: needsFrame! Item was changed: ----- Method: StackToRegisterMappingCogit>>genStorePop:RemoteTemp:At: (in category 'bytecode generator support') ----- genStorePop: popBoolean RemoteTemp: slotIndex At: remoteTempIndex <inline: false> | topReg topSpilled tempVectReg | "The only reason we assert needsFrame here is that in a frameless method ReceiverResultReg must and does contain only self, but the ceStoreCheck trampoline expects the target of the store to be in ReceiverResultReg. So in a frameless method we would have a conflict between the receiver and the temote temp store, unless we we smart enough to realise that ReceiverResultReg was unused after the literal variable store, unlikely given that methods return self by default." self assert: needsFrame. optStatus isReceiverResultRegLive: false. "N.B. No need to check the stack for references because we generate code for remote temp loads that stores the result in a register, deferring only the register push." "Avoid store check for immediate values" (objectRepresentation isUnannotatableConstant: self ssTop) ifTrue: [ tempVectReg := self allocateAnyReg. self MoveMw: (self frameOffsetOfTemporary: remoteTempIndex) r: FPReg R: tempVectReg. self ssStorePop: popBoolean toReg: TempReg. traceStores > 0 ifTrue: [ tempVectReg = ReceiverResultReg ifFalse: [ self ssAllocateRequiredReg: ReceiverResultReg. optStatus isReceiverResultRegLive: false. self MoveR: tempVectReg R: ReceiverResultReg ]. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreImmediateInSourceReg: TempReg slotIndex: slotIndex destReg: tempVectReg]. topReg := self allocateRegForStackTopEntryNotConflictingWith: (self registerMaskFor: ReceiverResultReg). - self ssPop: 1. - "for the ceStoreCheck call in genStoreSourceReg:... below" - self ssAllocateCallReg: topReg and: ReceiverResultReg. - self ssPush: 1. topSpilled := self ssTop spilled. self ssStorePop: (popBoolean or: [topSpilled]) toReg: topReg. popBoolean ifFalse: [topSpilled ifFalse: [self ssPop: 1]. self ssPushRegister: topReg]. self MoveMw: (self frameOffsetOfTemporary: remoteTempIndex) r: FPReg R: ReceiverResultReg. traceStores > 0 ifTrue: [self MoveR: topReg R: TempReg. self CallRT: ceTraceStoreTrampoline]. ^objectRepresentation genStoreSourceReg: topReg slotIndex: slotIndex destReg: ReceiverResultReg scratchReg: TempReg inFrame: needsFrame! Item was changed: ----- Method: StackToRegisterMappingCogit>>genVanillaSpecialSelectorEqualsEquals (in category 'bytecode generators') ----- genVanillaSpecialSelectorEqualsEquals + | nextPC postBranchPC targetBytecodePC branchDescriptor + rcvrReg argReg argIsConstant rcvrIsConstant | - | nextPC postBranchPC targetBytecodePC primDescriptor branchDescriptor nExts - jumpEqual jumpNotEqual rcvrReg argReg argIsConstant rcvrIsConstant | - <var: #jumpEqual type: #'AbstractInstruction *'> - <var: #jumpNotEqual type: #'AbstractInstruction *'> <var: #primDescriptor type: #'BytecodeDescriptor *'> <var: #branchDescriptor type: #'BytecodeDescriptor *'> - primDescriptor := self generatorAt: byte0. - - nextPC := bytecodePC + primDescriptor numBytes. - nExts := 0. - [branchDescriptor := self generatorAt: (objectMemory fetchByte: nextPC ofObject: methodObj) + bytecodeSetOffset. - branchDescriptor isExtension] whileTrue: - [nExts := nExts + 1. - nextPC := nextPC + branchDescriptor numBytes]. - "If branching the stack must be flushed for the merge" - (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifTrue: - [self ssFlushTo: simStackPtr - 2]. - - "Don't use ReceiverResultReg for receiver to keep ReceiverResultReg live. - Optimize e.g. rcvr == nil, the common case for ifNil: et al." + self extractMaybeBranchDescriptorInto: [ :descr :next :postBranch :target | + branchDescriptor := descr. nextPC := next. postBranchPC := postBranch. targetBytecodePC := target ]. + argIsConstant := self ssTop type = SSConstant. + "they can't be both constants because we do not have instructions manipulating two constants, + if this is the case, which can happen due to annotable constants that can be moved in memory + with become and therefore can't resolve #== at compilation time, still write the rcvr into a + register as if it was not a constant. It's uncommon anyway." + rcvrIsConstant := argIsConstant not and: [(self ssValue: 1) type = SSConstant]. - rcvrIsConstant := argIsConstant and: [ (self ssValue:1) type = SSConstant ]. + self + allocateEqualsEqualsRegistersArgNeedsReg: argIsConstant not + rcvrNeedsReg: rcvrIsConstant not + into: [ :rcvr :arg | rcvrReg:= rcvr. argReg := arg ]. - argIsConstant - ifFalse: - [rcvrIsConstant - ifFalse: - [self allocateRegForStackTopTwoEntriesInto: [:rTop :rNext| argReg := rTop. rcvrReg := rNext]. - self ssTop popToReg: argReg. - (self ssValue:1) popToReg: rcvrReg] - ifTrue: - [argReg := self allocateRegForStackTopEntry. - self ssTop popToReg: argReg]] - ifTrue: - [self assert: rcvrIsConstant not. - rcvrReg := self allocateRegForStackEntryAt: 1. - (self ssValue:1) popToReg: rcvrReg]. - argIsConstant - ifTrue: [ self genCompConstant: self ssTop constant R: rcvrReg ] - ifFalse: [ rcvrIsConstant - ifTrue: [ self genCompConstant: (self ssValue: 1) constant R: argReg ] - ifFalse: [ self CmpR: argReg R: rcvrReg ] ]. - - self ssPop: 2. - "If not followed by a branch, resolve to true or false." (branchDescriptor isBranchTrue or: [branchDescriptor isBranchFalse]) ifFalse: + [ ^ self genEqualsEqualsNoBranchArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg]. + + "If branching the stack must be flushed for the merge" + self ssFlushTo: simStackPtr - 2. + + self genEqualsEqualsComparisonArgIsConstant: argIsConstant rcvrIsConstant: rcvrIsConstant argReg: argReg rcvrReg: rcvrReg. + self ssPop: 2. - [jumpNotEqual := self JumpNonZero: 0. - self genMoveTrueR: rcvrReg. - jumpEqual := self Jump: 0. - jumpNotEqual jmpTarget: (self genMoveFalseR: rcvrReg). - jumpEqual jmpTarget: self Label. - self ssPushRegister: rcvrReg. - ^0]. "Further since there is a following conditional jump bytecode, define non-merge fixups and leave the cond bytecode to set the mergeness." - targetBytecodePC := nextPC - + branchDescriptor numBytes - + (self spanFor: branchDescriptor at: nextPC exts: nExts in: methodObj). - postBranchPC := nextPC + branchDescriptor numBytes. (self fixupAt: nextPC - initialPC) targetInstruction = 0 ifTrue: "The next instruction is dead. we can skip it." [deadCode := true. self ensureFixupAt: targetBytecodePC - initialPC. self ensureFixupAt: postBranchPC - initialPC] ifFalse: [self ssPushConstant: objectMemory trueObject]. "dummy value" self gen: (branchDescriptor isBranchTrue ifTrue: [JumpZero] ifFalse: [JumpNonZero]) operand: (self ensureNonMergeFixupAt: targetBytecodePC - initialPC) asUnsignedInteger. deadCode ifFalse: [self Jump: (self ensureNonMergeFixupAt: postBranchPC - initialPC)]. ^0!

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Vm-dev April 2015